1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2012-2014, 2018-2023 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_fw_api_rx_h__ 8 #define __iwl_fw_api_rx_h__ 9 10 /* API for pre-9000 hardware */ 11 12 #define IWL_RX_INFO_PHY_CNT 8 13 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1 14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0 17 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8 18 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16 19 20 enum iwl_mac_context_info { 21 MAC_CONTEXT_INFO_NONE, 22 MAC_CONTEXT_INFO_GSCAN, 23 }; 24 25 /** 26 * struct iwl_rx_phy_info - phy info 27 * (REPLY_RX_PHY_CMD = 0xc0) 28 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 29 * @cfg_phy_cnt: configurable DSP phy data byte count 30 * @stat_id: configurable DSP phy data set ID 31 * @reserved1: reserved 32 * @system_timestamp: GP2 at on air rise 33 * @timestamp: TSF at on air rise 34 * @beacon_time_stamp: beacon at on-air rise 35 * @phy_flags: general phy flags: band, modulation, ... 36 * @channel: channel number 37 * @non_cfg_phy: for various implementations of non_cfg_phy 38 * @rate_n_flags: RATE_MCS_* 39 * @byte_count: frame's byte-count 40 * @frame_time: frame's time on the air, based on byte count and frame rate 41 * calculation 42 * @mac_active_msk: what MACs were active when the frame was received 43 * @mac_context_info: additional info on the context in which the frame was 44 * received as defined in &enum iwl_mac_context_info 45 * 46 * Before each Rx, the device sends this data. It contains PHY information 47 * about the reception of the packet. 48 */ 49 struct iwl_rx_phy_info { 50 u8 non_cfg_phy_cnt; 51 u8 cfg_phy_cnt; 52 u8 stat_id; 53 u8 reserved1; 54 __le32 system_timestamp; 55 __le64 timestamp; 56 __le32 beacon_time_stamp; 57 __le16 phy_flags; 58 __le16 channel; 59 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; 60 __le32 rate_n_flags; 61 __le32 byte_count; 62 u8 mac_active_msk; 63 u8 mac_context_info; 64 __le16 frame_time; 65 } __packed; 66 67 /* 68 * TCP offload Rx assist info 69 * 70 * bits 0:3 - reserved 71 * bits 4:7 - MIC CRC length 72 * bits 8:12 - MAC header length 73 * bit 13 - Padding indication 74 * bit 14 - A-AMSDU indication 75 * bit 15 - Offload enabled 76 */ 77 enum iwl_csum_rx_assist_info { 78 CSUM_RXA_RESERVED_MASK = 0x000f, 79 CSUM_RXA_MICSIZE_MASK = 0x00f0, 80 CSUM_RXA_HEADERLEN_MASK = 0x1f00, 81 CSUM_RXA_PADD = BIT(13), 82 CSUM_RXA_AMSDU = BIT(14), 83 CSUM_RXA_ENA = BIT(15) 84 }; 85 86 /** 87 * struct iwl_rx_mpdu_res_start - phy info 88 * @byte_count: byte count of the frame 89 * @assist: see &enum iwl_csum_rx_assist_info 90 */ 91 struct iwl_rx_mpdu_res_start { 92 __le16 byte_count; 93 __le16 assist; 94 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */ 95 96 /** 97 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags 98 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 99 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK 100 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 101 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive 102 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 103 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position 104 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 105 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 106 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 107 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 108 */ 109 enum iwl_rx_phy_flags { 110 RX_RES_PHY_FLAGS_BAND_24 = BIT(0), 111 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), 112 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), 113 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), 114 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 115 RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 116 RX_RES_PHY_FLAGS_AGG = BIT(7), 117 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), 118 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), 119 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), 120 }; 121 122 /** 123 * enum iwl_mvm_rx_status - written by fw for each Rx packet 124 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 125 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 126 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found 127 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid 128 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 129 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 130 * in the driver. 131 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 132 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 133 * alg = CCM only. Checks replay attack for 11w frames. 134 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 135 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 136 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 137 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 138 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension 139 * algorithm 140 * @RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC: this frame is protected using 141 * CMAC or GMAC 142 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 143 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 144 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 145 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw 146 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors 147 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask 148 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift 149 */ 150 enum iwl_mvm_rx_status { 151 RX_MPDU_RES_STATUS_CRC_OK = BIT(0), 152 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), 153 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), 154 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), 155 RX_MPDU_RES_STATUS_ICV_OK = BIT(5), 156 RX_MPDU_RES_STATUS_MIC_OK = BIT(6), 157 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 158 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), 159 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 160 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 161 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 162 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 163 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 164 RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC = (6 << 8), 165 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 166 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 167 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), 168 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), 169 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), 170 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24, 171 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT, 172 }; 173 174 /* 9000 series API */ 175 enum iwl_rx_mpdu_mac_flags1 { 176 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03, 177 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0, 178 /* shift should be 4, but the length is measured in 2-byte 179 * words, so shifting only by 3 gives a byte result 180 */ 181 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3, 182 }; 183 184 enum iwl_rx_mpdu_mac_flags2 { 185 /* in 2-byte words */ 186 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f, 187 IWL_RX_MPDU_MFLG2_PAD = 0x20, 188 IWL_RX_MPDU_MFLG2_AMSDU = 0x40, 189 }; 190 191 enum iwl_rx_mpdu_amsdu_info { 192 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f, 193 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80, 194 }; 195 196 #define RX_MPDU_BAND_POS 6 197 #define RX_MPDU_BAND_MASK 0xC0 198 #define BAND_IN_RX_STATUS(_val) \ 199 (((_val) & RX_MPDU_BAND_MASK) >> RX_MPDU_BAND_POS) 200 201 enum iwl_rx_l3_proto_values { 202 IWL_RX_L3_TYPE_NONE, 203 IWL_RX_L3_TYPE_IPV4, 204 IWL_RX_L3_TYPE_IPV4_FRAG, 205 IWL_RX_L3_TYPE_IPV6_FRAG, 206 IWL_RX_L3_TYPE_IPV6, 207 IWL_RX_L3_TYPE_IPV6_IN_IPV4, 208 IWL_RX_L3_TYPE_ARP, 209 IWL_RX_L3_TYPE_EAPOL, 210 }; 211 212 #define IWL_RX_L3_PROTO_POS 4 213 214 enum iwl_rx_l3l4_flags { 215 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), 216 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), 217 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), 218 IWL_RX_L3L4_TCP_ACK = BIT(3), 219 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS, 220 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8, 221 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12, 222 }; 223 224 enum iwl_rx_mpdu_status { 225 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), 226 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), 227 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), 228 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), 229 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), 230 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), 231 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 232 /* overlayed since IWL_UCODE_TLV_API_DEPRECATE_TTAK */ 233 IWL_RX_MPDU_STATUS_REPLAY_ERROR = BIT(7), 234 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8, 235 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK, 236 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8, 237 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8, 238 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8, 239 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8, 240 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8, 241 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8, 242 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), 243 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), 244 245 IWL_RX_MPDU_STATUS_DUPLICATE = BIT(22), 246 247 IWL_RX_MPDU_STATUS_STA_ID = 0x1f000000, 248 }; 249 250 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f 251 252 enum iwl_rx_mpdu_reorder_data { 253 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff, 254 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000, 255 IWL_RX_MPDU_REORDER_SN_SHIFT = 12, 256 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000, 257 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24, 258 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000, 259 }; 260 261 enum iwl_rx_mpdu_phy_info { 262 IWL_RX_MPDU_PHY_AMPDU = BIT(5), 263 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), 264 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), 265 /* short preamble is only for CCK, for non-CCK overridden by this */ 266 IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY = BIT(7), 267 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), 268 }; 269 270 enum iwl_rx_mpdu_mac_info { 271 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f, 272 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0, 273 }; 274 275 /* TSF overload low dword */ 276 enum iwl_rx_phy_he_data0 { 277 /* info type: HE any */ 278 IWL_RX_PHY_DATA0_HE_BEAM_CHNG = 0x00000001, 279 IWL_RX_PHY_DATA0_HE_UPLINK = 0x00000002, 280 IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK = 0x000000fc, 281 IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK = 0x00000f00, 282 /* 1 bit reserved */ 283 IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK = 0x000fe000, 284 IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM = 0x00100000, 285 IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK = 0x00600000, 286 IWL_RX_PHY_DATA0_HE_PE_DISAMBIG = 0x00800000, 287 IWL_RX_PHY_DATA0_HE_DOPPLER = 0x01000000, 288 /* 6 bits reserved */ 289 IWL_RX_PHY_DATA0_HE_DELIM_EOF = 0x80000000, 290 }; 291 292 /* TSF overload low dword */ 293 enum iwl_rx_phy_eht_data0 { 294 /* info type: EHT any */ 295 IWL_RX_PHY_DATA0_EHT_VALIDATE = BIT(0), 296 IWL_RX_PHY_DATA0_EHT_UPLINK = BIT(1), 297 IWL_RX_PHY_DATA0_EHT_BSS_COLOR_MASK = 0x000000fc, 298 IWL_RX_PHY_DATA0_ETH_SPATIAL_REUSE_MASK = 0x00000f00, 299 IWL_RX_PHY_DATA0_EHT_PS160 = BIT(12), 300 IWL_RX_PHY_DATA0_EHT_TXOP_DUR_MASK = 0x000fe000, 301 IWL_RX_PHY_DATA0_EHT_LDPC_EXT_SYM = BIT(20), 302 IWL_RX_PHY_DATA0_EHT_PRE_FEC_PAD_MASK = 0x00600000, 303 IWL_RX_PHY_DATA0_EHT_PE_DISAMBIG = BIT(23), 304 IWL_RX_PHY_DATA0_EHT_BW320_SLOT = BIT(24), 305 IWL_RX_PHY_DATA0_EHT_SIGA_CRC_OK = BIT(25), 306 IWL_RX_PHY_DATA0_EHT_PHY_VER = 0x1c000000, 307 /* 2 bits reserved */ 308 IWL_RX_PHY_DATA0_EHT_DELIM_EOF = BIT(31), 309 }; 310 311 enum iwl_rx_phy_info_type { 312 IWL_RX_PHY_INFO_TYPE_NONE = 0, 313 IWL_RX_PHY_INFO_TYPE_CCK = 1, 314 IWL_RX_PHY_INFO_TYPE_OFDM_LGCY = 2, 315 IWL_RX_PHY_INFO_TYPE_HT = 3, 316 IWL_RX_PHY_INFO_TYPE_VHT_SU = 4, 317 IWL_RX_PHY_INFO_TYPE_VHT_MU = 5, 318 IWL_RX_PHY_INFO_TYPE_HE_SU = 6, 319 IWL_RX_PHY_INFO_TYPE_HE_MU = 7, 320 IWL_RX_PHY_INFO_TYPE_HE_TB = 8, 321 IWL_RX_PHY_INFO_TYPE_HE_MU_EXT = 9, 322 IWL_RX_PHY_INFO_TYPE_HE_TB_EXT = 10, 323 IWL_RX_PHY_INFO_TYPE_EHT_MU = 11, 324 IWL_RX_PHY_INFO_TYPE_EHT_TB = 12, 325 IWL_RX_PHY_INFO_TYPE_EHT_MU_EXT = 13, 326 IWL_RX_PHY_INFO_TYPE_EHT_TB_EXT = 14, 327 }; 328 329 /* TSF overload high dword */ 330 enum iwl_rx_phy_common_data1 { 331 /* 332 * check this first - if TSF overload is set, 333 * see &enum iwl_rx_phy_info_type 334 */ 335 IWL_RX_PHY_DATA1_INFO_TYPE_MASK = 0xf0000000, 336 337 /* info type: HT/VHT/HE/EHT any */ 338 IWL_RX_PHY_DATA1_LSIG_LEN_MASK = 0x0fff0000, 339 }; 340 341 /* TSF overload high dword For HE rates*/ 342 enum iwl_rx_phy_he_data1 { 343 /* info type: HE MU/MU-EXT */ 344 IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION = 0x00000001, 345 IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK = 0x0000001e, 346 347 /* info type: HE any */ 348 IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK = 0x000000e0, 349 IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80 = 0x00000100, 350 /* trigger encoded */ 351 IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK = 0x0000fe00, 352 353 /* info type: HE TB/TX-EXT */ 354 IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE = 0x00000001, 355 IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK = 0x0000000e, 356 }; 357 358 /* TSF overload high dword For EHT-MU/TB rates*/ 359 enum iwl_rx_phy_eht_data1 { 360 /* info type: EHT-MU */ 361 IWL_RX_PHY_DATA1_EHT_MU_NUM_SIG_SYM_USIGA2 = 0x0000001f, 362 /* info type: EHT-TB */ 363 IWL_RX_PHY_DATA1_EHT_TB_PILOT_TYPE = BIT(0), 364 IWL_RX_PHY_DATA1_EHT_TB_LOW_SS = 0x0000001e, 365 366 /* info type: EHT any */ 367 /* number of EHT-LTF symbols 0 - 1 EHT-LTF, 1 - 2 EHT-LTFs, 2 - 4 EHT-LTFs, 368 * 3 - 6 EHT-LTFs, 4 - 8 EHT-LTFs */ 369 IWL_RX_PHY_DATA1_EHT_SIG_LTF_NUM = 0x000000e0, 370 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B0 = 0x00000100, 371 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B1_B7 = 0x0000fe00, 372 }; 373 374 /* goes into Metadata DW 7 (Qu) or 8 (So or higher) */ 375 enum iwl_rx_phy_he_data2 { 376 /* info type: HE MU-EXT */ 377 /* the a1/a2/... is what the PHY/firmware calls the values */ 378 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0 = 0x000000ff, /* a1 */ 379 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2 = 0x0000ff00, /* a2 */ 380 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0 = 0x00ff0000, /* b1 */ 381 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2 = 0xff000000, /* b2 */ 382 383 /* info type: HE TB-EXT */ 384 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1 = 0x0000000f, 385 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2 = 0x000000f0, 386 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3 = 0x00000f00, 387 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4 = 0x0000f000, 388 }; 389 390 /* goes into Metadata DW 8 (Qu) or 7 (So or higher) */ 391 enum iwl_rx_phy_he_data3 { 392 /* info type: HE MU-EXT */ 393 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1 = 0x000000ff, /* c1 */ 394 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3 = 0x0000ff00, /* c2 */ 395 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1 = 0x00ff0000, /* d1 */ 396 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3 = 0xff000000, /* d2 */ 397 }; 398 399 /* goes into Metadata DW 4 high 16 bits */ 400 enum iwl_rx_phy_he_he_data4 { 401 /* info type: HE MU-EXT */ 402 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU = 0x0001, 403 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU = 0x0002, 404 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK = 0x0004, 405 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK = 0x0008, 406 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK = 0x00f0, 407 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM = 0x0100, 408 IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK = 0x0600, 409 }; 410 411 /* goes into Metadata DW 8 (Qu has no EHT) */ 412 enum iwl_rx_phy_eht_data2 { 413 /* info type: EHT-MU-EXT */ 414 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A1 = 0x000001ff, 415 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A2 = 0x0003fe00, 416 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_B1 = 0x07fc0000, 417 418 /* info type: EHT-TB-EXT */ 419 IWL_RX_PHY_DATA2_EHT_TB_EXT_TRIG_SIGA1 = 0xffffffff, 420 }; 421 422 /* goes into Metadata DW 7 (Qu has no EHT) */ 423 enum iwl_rx_phy_eht_data3 { 424 /* note: low 8 bits cannot be used */ 425 /* info type: EHT-MU-EXT */ 426 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C1 = 0x0003fe00, 427 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C2 = 0x07fc0000, 428 }; 429 430 /* goes into Metadata DW 4 */ 431 enum iwl_rx_phy_eht_data4 { 432 /* info type: EHT-MU-EXT */ 433 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D1 = 0x000001ff, 434 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D2 = 0x0003fe00, 435 IWL_RX_PHY_DATA4_EHT_MU_EXT_SIGB_MCS = 0x000c0000, 436 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_B2 = 0x1ff00000, 437 }; 438 439 /* goes into Metadata DW 16 */ 440 enum iwl_rx_phy_data5 { 441 /* info type: EHT any */ 442 IWL_RX_PHY_DATA5_EHT_TYPE_AND_COMP = 0x00000003, 443 /* info type: EHT-TB */ 444 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE1 = 0x0000003c, 445 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE2 = 0x000003c0, 446 /* info type: EHT-MU */ 447 IWL_RX_PHY_DATA5_EHT_MU_PUNC_CH_CODE = 0x0000007c, 448 IWL_RX_PHY_DATA5_EHT_MU_STA_ID_USR = 0x0003ff80, 449 IWL_RX_PHY_DATA5_EHT_MU_NUM_USR_NON_OFDMA = 0x001c0000, 450 IWL_RX_PHY_DATA5_EHT_MU_SPATIAL_CONF_USR_FIELD = 0x0fe00000, 451 }; 452 453 /** 454 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor 455 */ 456 struct iwl_rx_mpdu_desc_v1 { 457 /* DW7 - carries rss_hash only when rpa_en == 1 */ 458 union { 459 /** 460 * @rss_hash: RSS hash value 461 */ 462 __le32 rss_hash; 463 464 /** 465 * @phy_data2: depends on info type (see @phy_data1) 466 */ 467 __le32 phy_data2; 468 }; 469 470 /* DW8 - carries filter_match only when rpa_en == 1 */ 471 union { 472 /** 473 * @filter_match: filter match value 474 */ 475 __le32 filter_match; 476 477 /** 478 * @phy_data3: depends on info type (see @phy_data1) 479 */ 480 __le32 phy_data3; 481 }; 482 483 /* DW9 */ 484 /** 485 * @rate_n_flags: RX rate/flags encoding 486 */ 487 __le32 rate_n_flags; 488 /* DW10 */ 489 /** 490 * @energy_a: energy chain A 491 */ 492 u8 energy_a; 493 /** 494 * @energy_b: energy chain B 495 */ 496 u8 energy_b; 497 /** 498 * @channel: channel number 499 */ 500 u8 channel; 501 /** 502 * @mac_context: MAC context mask 503 */ 504 u8 mac_context; 505 /* DW11 */ 506 /** 507 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 508 */ 509 __le32 gp2_on_air_rise; 510 /* DW12 & DW13 */ 511 union { 512 /** 513 * @tsf_on_air_rise: 514 * TSF value on air rise (INA), only valid if 515 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 516 */ 517 __le64 tsf_on_air_rise; 518 519 struct { 520 /** 521 * @phy_data0: depends on info_type, see @phy_data1 522 */ 523 __le32 phy_data0; 524 /** 525 * @phy_data1: valid only if 526 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 527 * see &enum iwl_rx_phy_common_data1 or 528 * &enum iwl_rx_phy_he_data1 or 529 * &enum iwl_rx_phy_eht_data1. 530 */ 531 __le32 phy_data1; 532 }; 533 }; 534 } __packed; /* RX_MPDU_RES_START_API_S_VER_4 */ 535 536 /** 537 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor 538 */ 539 struct iwl_rx_mpdu_desc_v3 { 540 /* DW7 - carries filter_match only when rpa_en == 1 */ 541 union { 542 /** 543 * @filter_match: filter match value 544 */ 545 __le32 filter_match; 546 547 /** 548 * @phy_data3: depends on info type (see @phy_data1) 549 */ 550 __le32 phy_data3; 551 }; 552 553 /* DW8 - carries rss_hash only when rpa_en == 1 */ 554 union { 555 /** 556 * @rss_hash: RSS hash value 557 */ 558 __le32 rss_hash; 559 560 /** 561 * @phy_data2: depends on info type (see @phy_data1) 562 */ 563 __le32 phy_data2; 564 }; 565 /* DW9 */ 566 /** 567 * @partial_hash: 31:0 ip/tcp header hash 568 * w/o some fields (such as IP SRC addr) 569 */ 570 __le32 partial_hash; 571 /* DW10 */ 572 /** 573 * @raw_xsum: raw xsum value 574 */ 575 __be16 raw_xsum; 576 /** 577 * @reserved_xsum: reserved high bits in the raw checksum 578 */ 579 __le16 reserved_xsum; 580 /* DW11 */ 581 /** 582 * @rate_n_flags: RX rate/flags encoding 583 */ 584 __le32 rate_n_flags; 585 /* DW12 */ 586 /** 587 * @energy_a: energy chain A 588 */ 589 u8 energy_a; 590 /** 591 * @energy_b: energy chain B 592 */ 593 u8 energy_b; 594 /** 595 * @channel: channel number 596 */ 597 u8 channel; 598 /** 599 * @mac_context: MAC context mask 600 */ 601 u8 mac_context; 602 /* DW13 */ 603 /** 604 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 605 */ 606 __le32 gp2_on_air_rise; 607 /* DW14 & DW15 */ 608 union { 609 /** 610 * @tsf_on_air_rise: 611 * TSF value on air rise (INA), only valid if 612 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 613 */ 614 __le64 tsf_on_air_rise; 615 616 struct { 617 /** 618 * @phy_data0: depends on info_type, see @phy_data1 619 */ 620 __le32 phy_data0; 621 /** 622 * @phy_data1: valid only if 623 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 624 * see &enum iwl_rx_phy_data1. 625 */ 626 __le32 phy_data1; 627 }; 628 }; 629 /* DW16 */ 630 /** 631 * @phy_data5: valid only if 632 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 633 * see &enum iwl_rx_phy_data5. 634 */ 635 __le32 phy_data5; 636 /* DW17 */ 637 /** 638 * @reserved: reserved 639 */ 640 __le32 reserved[1]; 641 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 642 RX_MPDU_RES_START_API_S_VER_5 */ 643 644 /** 645 * struct iwl_rx_mpdu_desc - RX MPDU descriptor 646 */ 647 struct iwl_rx_mpdu_desc { 648 /* DW2 */ 649 /** 650 * @mpdu_len: MPDU length 651 */ 652 __le16 mpdu_len; 653 /** 654 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1 655 */ 656 u8 mac_flags1; 657 /** 658 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2 659 */ 660 u8 mac_flags2; 661 /* DW3 */ 662 /** 663 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info 664 */ 665 u8 amsdu_info; 666 /** 667 * @phy_info: &enum iwl_rx_mpdu_phy_info 668 */ 669 __le16 phy_info; 670 /** 671 * @mac_phy_idx: MAC/PHY index 672 */ 673 u8 mac_phy_idx; 674 /* DW4 */ 675 union { 676 struct { 677 /* carries csum data only when rpa_en == 1 */ 678 /** 679 * @raw_csum: raw checksum (alledgedly unreliable) 680 */ 681 __le16 raw_csum; 682 683 union { 684 /** 685 * @l3l4_flags: &enum iwl_rx_l3l4_flags 686 */ 687 __le16 l3l4_flags; 688 689 /** 690 * @phy_data4: depends on info type, see phy_data1 691 */ 692 __le16 phy_data4; 693 }; 694 }; 695 /** 696 * @phy_eht_data4: depends on info type, see phy_data1 697 */ 698 __le32 phy_eht_data4; 699 }; 700 /* DW5 */ 701 /** 702 * @status: &enum iwl_rx_mpdu_status 703 */ 704 __le32 status; 705 706 /* DW6 */ 707 /** 708 * @reorder_data: &enum iwl_rx_mpdu_reorder_data 709 */ 710 __le32 reorder_data; 711 712 union { 713 struct iwl_rx_mpdu_desc_v1 v1; 714 struct iwl_rx_mpdu_desc_v3 v3; 715 }; 716 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 717 RX_MPDU_RES_START_API_S_VER_4, 718 RX_MPDU_RES_START_API_S_VER_5 */ 719 720 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1) 721 722 #define RX_NO_DATA_CHAIN_A_POS 0 723 #define RX_NO_DATA_CHAIN_A_MSK (0xff << RX_NO_DATA_CHAIN_A_POS) 724 #define RX_NO_DATA_CHAIN_B_POS 8 725 #define RX_NO_DATA_CHAIN_B_MSK (0xff << RX_NO_DATA_CHAIN_B_POS) 726 #define RX_NO_DATA_CHANNEL_POS 16 727 #define RX_NO_DATA_CHANNEL_MSK (0xff << RX_NO_DATA_CHANNEL_POS) 728 729 #define RX_NO_DATA_INFO_TYPE_POS 0 730 #define RX_NO_DATA_INFO_TYPE_MSK (0xff << RX_NO_DATA_INFO_TYPE_POS) 731 #define RX_NO_DATA_INFO_TYPE_NONE 0 732 #define RX_NO_DATA_INFO_TYPE_RX_ERR 1 733 #define RX_NO_DATA_INFO_TYPE_NDP 2 734 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED 3 735 #define RX_NO_DATA_INFO_TYPE_TB_UNMATCHED 4 736 737 #define RX_NO_DATA_INFO_ERR_POS 8 738 #define RX_NO_DATA_INFO_ERR_MSK (0xff << RX_NO_DATA_INFO_ERR_POS) 739 #define RX_NO_DATA_INFO_ERR_NONE 0 740 #define RX_NO_DATA_INFO_ERR_BAD_PLCP 1 741 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE 2 742 #define RX_NO_DATA_INFO_ERR_NO_DELIM 3 743 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR 4 744 #define RX_NO_DATA_INFO_LOW_ENERGY 5 745 746 #define RX_NO_DATA_FRAME_TIME_POS 0 747 #define RX_NO_DATA_FRAME_TIME_MSK (0xfffff << RX_NO_DATA_FRAME_TIME_POS) 748 749 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK 0x03800000 750 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK 0x38000000 751 #define RX_NO_DATA_RX_VEC2_EHT_NSTS_MSK 0x00f00000 752 753 /* content of OFDM_RX_VECTOR_USIG_A1_OUT */ 754 enum iwl_rx_usig_a1 { 755 IWL_RX_USIG_A1_ENHANCED_WIFI_VER_ID = 0x00000007, 756 IWL_RX_USIG_A1_BANDWIDTH = 0x00000038, 757 IWL_RX_USIG_A1_UL_FLAG = 0x00000040, 758 IWL_RX_USIG_A1_BSS_COLOR = 0x00001f80, 759 IWL_RX_USIG_A1_TXOP_DURATION = 0x000fe000, 760 IWL_RX_USIG_A1_DISREGARD = 0x01f00000, 761 IWL_RX_USIG_A1_VALIDATE = 0x02000000, 762 IWL_RX_USIG_A1_EHT_BW320_SLOT = 0x04000000, 763 IWL_RX_USIG_A1_EHT_TYPE = 0x18000000, 764 IWL_RX_USIG_A1_RDY = 0x80000000, 765 }; 766 767 /* content of OFDM_RX_VECTOR_USIG_A2_EHT_OUT */ 768 enum iwl_rx_usig_a2_eht { 769 IWL_RX_USIG_A2_EHT_PPDU_TYPE = 0x00000003, 770 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B2 = 0x00000004, 771 IWL_RX_USIG_A2_EHT_PUNC_CHANNEL = 0x000000f8, 772 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B8 = 0x00000100, 773 IWL_RX_USIG_A2_EHT_SIG_MCS = 0x00000600, 774 IWL_RX_USIG_A2_EHT_SIG_SYM_NUM = 0x0000f800, 775 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_1 = 0x000f0000, 776 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_2 = 0x00f00000, 777 IWL_RX_USIG_A2_EHT_TRIG_USIG2_DISREGARD = 0x1f000000, 778 IWL_RX_USIG_A2_EHT_CRC_OK = 0x40000000, 779 IWL_RX_USIG_A2_EHT_RDY = 0x80000000, 780 }; 781 782 /** 783 * struct iwl_rx_no_data - RX no data descriptor 784 * @info: 7:0 frame type, 15:8 RX error type 785 * @rssi: 7:0 energy chain-A, 786 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 787 * @on_air_rise_time: GP2 during on air rise 788 * @fr_time: frame time 789 * @rate: rate/mcs of frame 790 * @phy_info: &enum iwl_rx_phy_he_data0 or &enum iwl_rx_phy_eht_data0 791 * based on &enum iwl_rx_phy_info_type 792 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 793 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 794 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 795 */ 796 struct iwl_rx_no_data { 797 __le32 info; 798 __le32 rssi; 799 __le32 on_air_rise_time; 800 __le32 fr_time; 801 __le32 rate; 802 __le32 phy_info[2]; 803 __le32 rx_vec[2]; 804 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1, 805 RX_NO_DATA_NTFY_API_S_VER_2 */ 806 807 /** 808 * struct iwl_rx_no_data_ver_3 - RX no data descriptor 809 * @info: 7:0 frame type, 15:8 RX error type 810 * @rssi: 7:0 energy chain-A, 811 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 812 * @on_air_rise_time: GP2 during on air rise 813 * @fr_time: frame time 814 * @rate: rate/mcs of frame 815 * @phy_info: &enum iwl_rx_phy_eht_data0 and &enum iwl_rx_phy_info_type 816 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 817 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 818 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 819 * for EHT: OFDM_RX_VECTOR_USIG_A1_OUT, OFDM_RX_VECTOR_USIG_A2_EHT_OUT, 820 * OFDM_RX_VECTOR_EHT_OUT, OFDM_RX_VECTOR_EHT_USER_FIELD_OUT 821 */ 822 struct iwl_rx_no_data_ver_3 { 823 __le32 info; 824 __le32 rssi; 825 __le32 on_air_rise_time; 826 __le32 fr_time; 827 __le32 rate; 828 __le32 phy_info[2]; 829 __le32 rx_vec[4]; 830 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1, 831 RX_NO_DATA_NTFY_API_S_VER_2 832 RX_NO_DATA_NTFY_API_S_VER_3 */ 833 834 struct iwl_frame_release { 835 u8 baid; 836 u8 reserved; 837 __le16 nssn; 838 }; 839 840 /** 841 * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release 842 * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask 843 * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask 844 */ 845 enum iwl_bar_frame_release_sta_tid { 846 IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f, 847 IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0, 848 }; 849 850 /** 851 * enum iwl_bar_frame_release_ba_info - BA information for BAR release 852 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask 853 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver) 854 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask 855 */ 856 enum iwl_bar_frame_release_ba_info { 857 IWL_BAR_FRAME_RELEASE_NSSN_MASK = 0x00000fff, 858 IWL_BAR_FRAME_RELEASE_SN_MASK = 0x00fff000, 859 IWL_BAR_FRAME_RELEASE_BAID_MASK = 0x3f000000, 860 }; 861 862 /** 863 * struct iwl_bar_frame_release - frame release from BAR info 864 * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid. 865 * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info. 866 */ 867 struct iwl_bar_frame_release { 868 __le32 sta_tid; 869 __le32 ba_info; 870 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */ 871 872 enum iwl_rss_hash_func_en { 873 IWL_RSS_HASH_TYPE_IPV4_TCP, 874 IWL_RSS_HASH_TYPE_IPV4_UDP, 875 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD, 876 IWL_RSS_HASH_TYPE_IPV6_TCP, 877 IWL_RSS_HASH_TYPE_IPV6_UDP, 878 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 879 }; 880 881 #define IWL_RSS_HASH_KEY_CNT 10 882 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128 883 #define IWL_RSS_ENABLE 1 884 885 /** 886 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration 887 * 888 * @flags: 1 - enable, 0 - disable 889 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en 890 * @reserved: reserved 891 * @secret_key: 320 bit input of random key configuration from driver 892 * @indirection_table: indirection table 893 */ 894 struct iwl_rss_config_cmd { 895 __le32 flags; 896 u8 hash_mask; 897 u8 reserved[3]; 898 __le32 secret_key[IWL_RSS_HASH_KEY_CNT]; 899 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE]; 900 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */ 901 902 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0 903 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf 904 905 /** 906 * struct iwl_rxq_sync_cmd - RXQ notification trigger 907 * 908 * @flags: flags of the notification. bit 0:3 are the sender queue 909 * @rxq_mask: rx queues to send the notification on 910 * @count: number of bytes in payload, should be DWORD aligned 911 * @payload: data to send to rx queues 912 */ 913 struct iwl_rxq_sync_cmd { 914 __le32 flags; 915 __le32 rxq_mask; 916 __le32 count; 917 u8 payload[]; 918 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 919 920 /** 921 * struct iwl_rxq_sync_notification - Notification triggered by RXQ 922 * sync command 923 * 924 * @count: number of bytes in payload 925 * @payload: data to send to rx queues 926 */ 927 struct iwl_rxq_sync_notification { 928 __le32 count; 929 u8 payload[]; 930 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 931 932 /** 933 * enum iwl_mvm_pm_event - type of station PM event 934 * @IWL_MVM_PM_EVENT_AWAKE: station woke up 935 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep 936 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger 937 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll 938 */ 939 enum iwl_mvm_pm_event { 940 IWL_MVM_PM_EVENT_AWAKE, 941 IWL_MVM_PM_EVENT_ASLEEP, 942 IWL_MVM_PM_EVENT_UAPSD, 943 IWL_MVM_PM_EVENT_PS_POLL, 944 }; /* PEER_PM_NTFY_API_E_VER_1 */ 945 946 /** 947 * struct iwl_mvm_pm_state_notification - station PM state notification 948 * @sta_id: station ID of the station changing state 949 * @type: the new powersave state, see &enum iwl_mvm_pm_event 950 */ 951 struct iwl_mvm_pm_state_notification { 952 u8 sta_id; 953 u8 type; 954 /* private: */ 955 __le16 reserved; 956 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */ 957 958 #define BA_WINDOW_STREAMS_MAX 16 959 #define BA_WINDOW_STATUS_TID_MSK 0x000F 960 #define BA_WINDOW_STATUS_STA_ID_POS 4 961 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0 962 #define BA_WINDOW_STATUS_VALID_MSK BIT(9) 963 964 /** 965 * struct iwl_ba_window_status_notif - reordering window's status notification 966 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63] 967 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid 968 * @start_seq_num: the start sequence number of the bitmap 969 * @mpdu_rx_count: the number of received MPDUs since entering D0i3 970 */ 971 struct iwl_ba_window_status_notif { 972 __le64 bitmap[BA_WINDOW_STREAMS_MAX]; 973 __le16 ra_tid[BA_WINDOW_STREAMS_MAX]; 974 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX]; 975 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX]; 976 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */ 977 978 /** 979 * struct iwl_rfh_queue_config - RX queue configuration 980 * @q_num: Q num 981 * @enable: enable queue 982 * @reserved: alignment 983 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 984 * @fr_bd_cb: DMA address of freeRB table 985 * @ur_bd_cb: DMA address of used RB table 986 * @fr_bd_wid: Initial index of the free table 987 */ 988 struct iwl_rfh_queue_data { 989 u8 q_num; 990 u8 enable; 991 __le16 reserved; 992 __le64 urbd_stts_wrptr; 993 __le64 fr_bd_cb; 994 __le64 ur_bd_cb; 995 __le32 fr_bd_wid; 996 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */ 997 998 /** 999 * struct iwl_rfh_queue_config - RX queue configuration 1000 * @num_queues: number of queues configured 1001 * @reserved: alignment 1002 * @data: DMA addresses per-queue 1003 */ 1004 struct iwl_rfh_queue_config { 1005 u8 num_queues; 1006 u8 reserved[3]; 1007 struct iwl_rfh_queue_data data[]; 1008 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */ 1009 1010 #endif /* __iwl_fw_api_rx_h__ */ 1011