1 /* $OpenBSD: if_iwnreg.h,v 1.59 2021/11/12 11:41:04 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2007, 2008 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define IWN_TX_RING_COUNT 256 21 #define IWN_TX_RING_LOMARK 192 22 #define IWN_TX_RING_HIMARK 224 23 #define IWN_RX_RING_COUNT_LOG 6 24 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 25 26 #define IWN4965_NTXQUEUES 16 27 #define IWN4965_FIRST_AGG_TXQUEUE 7 28 #define IWN5000_NTXQUEUES 20 29 #define IWN5000_FIRST_AGG_TXQUEUE 10 30 31 #define IWN4965_NDMACHNLS 7 32 #define IWN5000_NDMACHNLS 8 33 34 #define IWN_SRVC_DMACHNL 9 35 36 #define IWN_ICT_SIZE 4096 37 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 38 39 /* Maximum number of DMA segments for TX. */ 40 #define IWN_MAX_SCATTER 20 41 42 /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 43 #define IWN_RBUF_SIZE (4 * 1024) 44 45 #if defined(__LP64__) 46 /* HW supports 36-bit DMA addresses. */ 47 #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 48 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 49 #else 50 #define IWN_LOADDR(paddr) (paddr) 51 #define IWN_HIADDR(paddr) (0) 52 #endif 53 54 /* Base Address Register. */ 55 #define IWN_PCI_BAR0 PCI_MAPREG_START 56 57 /* 58 * Control and status registers. 59 */ 60 #define IWN_HW_IF_CONFIG 0x000 61 #define IWN_INT_COALESCING 0x004 62 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 63 #define IWN_INT 0x008 64 #define IWN_INT_MASK 0x00c 65 #define IWN_FH_INT 0x010 66 #define IWN_RESET 0x020 67 #define IWN_GP_CNTRL 0x024 68 #define IWN_HW_REV 0x028 69 #define IWN_EEPROM 0x02c 70 #define IWN_EEPROM_GP 0x030 71 #define IWN_OTP_GP 0x034 72 #define IWN_GIO 0x03c 73 #define IWN_GP_DRIVER 0x050 74 #define IWN_UCODE_GP1_CLR 0x05c 75 #define IWN_LED 0x094 76 #define IWN_DRAM_INT_TBL 0x0a0 77 #define IWN_SHADOW_REG_CTRL 0x0a8 78 #define IWN_GIO_CHICKEN 0x100 79 #define IWN_ANA_PLL 0x20c 80 #define IWN_HW_REV_WA 0x22c 81 #define IWN_DBG_HPET_MEM 0x240 82 #define IWN_DBG_LINK_PWR_MGMT 0x250 83 #define IWN_MEM_RADDR 0x40c 84 #define IWN_MEM_WADDR 0x410 85 #define IWN_MEM_WDATA 0x418 86 #define IWN_MEM_RDATA 0x41c 87 #define IWN_PRPH_WADDR 0x444 88 #define IWN_PRPH_RADDR 0x448 89 #define IWN_PRPH_WDATA 0x44c 90 #define IWN_PRPH_RDATA 0x450 91 #define IWN_HBUS_TARG_WRPTR 0x460 92 93 /* 94 * Flow-Handler registers. 95 */ 96 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 97 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 98 #define IWN_FH_KW_ADDR 0x197c 99 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 100 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 101 #define IWN_FH_STATUS_WPTR 0x1bc0 102 #define IWN_FH_RX_BASE 0x1bc4 103 #define IWN_FH_RX_WPTR 0x1bc8 104 #define IWN_FH_RX_CONFIG 0x1c00 105 #define IWN_FH_RX_STATUS 0x1c44 106 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 107 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 108 #define IWN_FH_TX_CHICKEN 0x1e98 109 #define IWN_FH_TX_STATUS 0x1eb0 110 111 /* 112 * TX scheduler registers. 113 */ 114 #define IWN_SCHED_BASE 0xa02c00 115 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 116 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 117 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 118 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 119 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 120 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 121 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 122 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 123 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 124 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 125 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 126 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 127 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 128 #define IWN5000_SCHED_CHAINEXT_EN (IWN_SCHED_BASE + 0x244) 129 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 130 131 /* 132 * Offsets in TX scheduler's SRAM. 133 */ 134 #define IWN4965_SCHED_CTX_OFF 0x380 135 #define IWN4965_SCHED_CTX_LEN 416 136 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 137 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 138 #define IWN5000_SCHED_CTX_OFF 0x600 139 #define IWN5000_SCHED_CTX_LEN 520 140 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 141 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 142 143 /* 144 * NIC internal memory offsets. 145 */ 146 #define IWN_APMG_CLK_CTRL 0x3000 147 #define IWN_APMG_CLK_EN 0x3004 148 #define IWN_APMG_CLK_DIS 0x3008 149 #define IWN_APMG_PS 0x300c 150 #define IWN_APMG_DIGITAL_SVR 0x3058 151 #define IWN_APMG_ANALOG_SVR 0x306c 152 #define IWN_APMG_PCI_STT 0x3010 153 #define IWN_BSM_WR_CTRL 0x3400 154 #define IWN_BSM_WR_MEM_SRC 0x3404 155 #define IWN_BSM_WR_MEM_DST 0x3408 156 #define IWN_BSM_WR_DWCOUNT 0x340c 157 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 158 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 159 #define IWN_BSM_DRAM_DATA_ADDR 0x3498 160 #define IWN_BSM_DRAM_DATA_SIZE 0x349c 161 #define IWN_BSM_SRAM_BASE 0x3800 162 163 /* Possible flags for register IWN_HW_IF_CONFIG. */ 164 #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 165 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 166 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 167 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 168 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 169 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 170 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 171 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 172 173 /* Possible values for register IWN_INT_PERIODIC. */ 174 #define IWN_INT_PERIODIC_DIS 0x00 175 #define IWN_INT_PERIODIC_ENA 0xff 176 177 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 178 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 179 180 /* Possible values for IWN_BSM_WR_MEM_DST. */ 181 #define IWN_FW_TEXT_BASE 0x00000000 182 #define IWN_FW_DATA_BASE 0x00800000 183 184 /* Possible flags for register IWN_RESET. */ 185 #define IWN_RESET_NEVO (1U << 0) 186 #define IWN_RESET_SW (1U << 7) 187 #define IWN_RESET_MASTER_DISABLED (1U << 8) 188 #define IWN_RESET_STOP_MASTER (1U << 9) 189 #define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) 190 191 /* Possible flags for register IWN_GP_CNTRL. */ 192 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 193 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 194 #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 195 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 196 #define IWN_GP_CNTRL_SLEEP (1 << 4) 197 #define IWN_GP_CNTRL_RFKILL (1 << 27) 198 199 /* Possible flags for register IWN_HW_REV. */ 200 #define IWN_HW_REV_TYPE_SHIFT 4 201 #define IWN_HW_REV_TYPE_MASK 0x000001f0 202 #define IWN_HW_REV_TYPE_4965 0 203 #define IWN_HW_REV_TYPE_5300 2 204 #define IWN_HW_REV_TYPE_5350 3 205 #define IWN_HW_REV_TYPE_5150 4 206 #define IWN_HW_REV_TYPE_5100 5 207 #define IWN_HW_REV_TYPE_1000 6 208 #define IWN_HW_REV_TYPE_6000 7 209 #define IWN_HW_REV_TYPE_6050 8 210 #define IWN_HW_REV_TYPE_6005 11 211 #define IWN_HW_REV_TYPE_2030 12 212 #define IWN_HW_REV_TYPE_2000 16 213 #define IWN_HW_REV_TYPE_105 17 214 #define IWN_HW_REV_TYPE_135 18 215 216 217 /* Possible flags for register IWN_GIO_CHICKEN. */ 218 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 219 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 220 221 /* Possible flags for register IWN_GIO. */ 222 #define IWN_GIO_L0S_ENA (1 << 1) 223 224 /* Possible flags for register IWN_GP_DRIVER. */ 225 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 226 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 227 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 228 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 229 #define IWN_GP_DRIVER_6050_1X2 (1 << 3) 230 #define IWN_GP_DRIVER_RADIO_IQ_INVERT (1 << 7) 231 232 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 233 #define IWN_UCODE_GP1_RFKILL (1 << 1) 234 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 235 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 236 237 /* Possible flags/values for register IWN_LED. */ 238 #define IWN_LED_BSM_CTRL (1 << 5) 239 #define IWN_LED_OFF 0x00000038 240 #define IWN_LED_ON 0x00000078 241 242 /* Possible flags for register IWN_DRAM_INT_TBL. */ 243 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1U << 27) 244 #define IWN_DRAM_INT_TBL_ENABLE (1U << 31) 245 246 /* Possible values for register IWN_ANA_PLL. */ 247 #define IWN_ANA_PLL_INIT 0x00880300 248 249 /* Possible flags for register IWN_FH_RX_STATUS. */ 250 #define IWN_FH_RX_STATUS_IDLE (1 << 24) 251 252 /* Possible flags for register IWN_BSM_WR_CTRL. */ 253 #define IWN_BSM_WR_CTRL_START_EN (1U << 30) 254 #define IWN_BSM_WR_CTRL_START (1U << 31) 255 256 /* Possible flags for register IWN_INT. */ 257 #define IWN_INT_ALIVE (1U << 0) 258 #define IWN_INT_WAKEUP (1U << 1) 259 #define IWN_INT_SW_RX (1U << 3) 260 #define IWN_INT_CT_REACHED (1U << 6) 261 #define IWN_INT_RF_TOGGLED (1U << 7) 262 #define IWN_INT_SW_ERR (1U << 25) 263 #define IWN_INT_SCHED (1U << 26) 264 #define IWN_INT_FH_TX (1U << 27) 265 #define IWN_INT_RX_PERIODIC (1U << 28) 266 #define IWN_INT_HW_ERR (1U << 29) 267 #define IWN_INT_FH_RX (1U << 31) 268 269 /* Shortcut. */ 270 #define IWN_INT_MASK_DEF \ 271 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 272 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 273 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 274 275 /* Possible flags for register IWN_FH_INT. */ 276 #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 277 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 278 #define IWN_FH_INT_HI_PRIOR (1 << 30) 279 /* Shortcuts for the above. */ 280 #define IWN_FH_INT_TX \ 281 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 282 #define IWN_FH_INT_RX \ 283 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 284 285 /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 286 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 287 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 288 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1U << 20) 289 290 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 291 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 292 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 293 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 294 295 /* Possible flags for register IWN_FH_TX_CHICKEN. */ 296 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 297 298 /* Possible flags for register IWN_FH_TX_STATUS. */ 299 #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 300 301 /* Possible flags for register IWN_FH_RX_CONFIG. */ 302 #define IWN_FH_RX_CONFIG_ENA (1U << 31) 303 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 304 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1U << 16) 305 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1U << 15) 306 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1U << 12) 307 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) /* units 32 usec */ 308 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1U << 2) 309 310 /* Possible flags for register IWN_FH_TX_CONFIG. */ 311 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 312 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1U << 3) 313 314 /* Possible flags for register IWN_EEPROM. */ 315 #define IWN_EEPROM_READ_VALID (1 << 0) 316 #define IWN_EEPROM_CMD (1 << 1) 317 318 /* Possible flags for register IWN_EEPROM_GP. */ 319 #define IWN_EEPROM_GP_IF_OWNER 0x00000180 320 321 /* Possible flags for register IWN_OTP_GP. */ 322 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 323 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 324 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 325 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 326 327 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 328 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 329 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 330 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 331 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 332 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 333 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 334 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 335 336 /* Possible flags for registers IWN_APMG_CLK_*. */ 337 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 338 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 339 340 /* Possible flags for register IWN_APMG_PS. */ 341 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 342 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 343 #define IWN_APMG_PS_PWR_SRC_VMAIN 0 344 #define IWN_APMG_PS_PWR_SRC_VAUX 2 345 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 346 #define IWN_APMG_PS_RESET_REQ (1 << 26) 347 348 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 349 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 350 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 351 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 352 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 353 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 354 355 /* Possible flags for IWN_APMG_PCI_STT. */ 356 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 357 358 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 359 #define IWN_FW_UPDATED (1U << 31) 360 361 #define IWN_SCHED_WINSZ 64 362 #define IWN_SCHED_LIMIT 64 363 #define IWN4965_SCHED_COUNT 512 364 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 365 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 366 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 367 368 struct iwn_tx_desc { 369 uint8_t reserved1[3]; 370 uint8_t nsegs; 371 struct { 372 uint32_t addr; 373 uint16_t len; 374 } __packed segs[IWN_MAX_SCATTER]; 375 /* Pad to 128 bytes. */ 376 uint32_t reserved2; 377 } __packed; 378 379 struct iwn_rx_status { 380 uint16_t closed_count; 381 uint16_t closed_rx_count; 382 uint16_t finished_count; 383 uint16_t finished_rx_count; 384 uint32_t reserved[2]; 385 } __packed; 386 387 struct iwn_rx_desc { 388 uint32_t len; 389 #define IWN_RX_DESC_LEN_MASK 0x00003fff 390 #define IWN_RX_DESC_LEN_SHIFT 0 391 #define IWN_RX_DESC_FLAG_FLUSH_RB_REQ 0x80000000 392 #define IWN_RX_DESC_FLAG_IGNORE_TC 0x40000000 393 #define IWN_RX_DESC_FLAG_FAST_IRQ 0x20000000 394 395 uint8_t type; 396 #define IWN_UC_READY 1 397 #define IWN_ADD_NODE_DONE 24 398 #define IWN_TX_DONE 28 399 #define IWN5000_CALIBRATION_RESULT 102 400 #define IWN5000_CALIBRATION_DONE 103 401 #define IWN_START_SCAN 130 402 #define IWN_STOP_SCAN 132 403 #define IWN_RX_STATISTICS 156 404 #define IWN_BEACON_STATISTICS 157 405 #define IWN_STATE_CHANGED 161 406 #define IWN_BEACON_MISSED 162 407 #define IWN_RX_PHY 192 408 #define IWN_MPDU_RX_DONE 193 409 #define IWN_RX_DONE 195 410 #define IWN_RX_COMPRESSED_BA 197 411 412 uint8_t flags; /* XXX iwlwifi calls this "group_id" */ 413 uint8_t idx; 414 uint8_t qid; 415 } __packed; 416 417 /* Possible RX status flags. */ 418 #define IWN_RX_NO_CRC_ERR (1 << 0) 419 #define IWN_RX_NO_OVFL_ERR (1 << 1) 420 /* Shortcut for the above. */ 421 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 422 #define IWN_RX_MPDU_MIC_OK (1 << 6) 423 #define IWN_RX_CIPHER_MASK (7 << 8) 424 #define IWN_RX_CIPHER_CCMP (2 << 8) 425 #define IWN_RX_MPDU_DEC (1 << 11) 426 #define IWN_RX_DECRYPT_MASK (3 << 11) 427 #define IWN_RX_DECRYPT_OK (3 << 11) 428 429 struct iwn_tx_cmd { 430 uint8_t code; 431 #define IWN_CMD_RXON 16 432 #define IWN_CMD_RXON_ASSOC 17 433 #define IWN_CMD_EDCA_PARAMS 19 434 #define IWN_CMD_TIMING 20 435 #define IWN_CMD_ADD_NODE 24 436 #define IWN_CMD_TX_DATA 28 437 #define IWN_CMD_LINK_QUALITY 78 438 #define IWN_CMD_SET_LED 72 439 #define IWN5000_CMD_WIMAX_COEX 90 440 #define IWN5000_CMD_CALIB_CONFIG 101 441 #define IWN_CMD_SET_POWER_MODE 119 442 #define IWN_CMD_SCAN 128 443 #define IWN_CMD_SCAN_ABORT 129 444 #define IWN_CMD_TXPOWER_DBM 149 445 #define IWN_CMD_TXPOWER 151 446 #define IWN5000_CMD_TX_ANT_CONFIG 152 447 #define IWN_CMD_BT_COEX 155 448 #define IWN_CMD_GET_STATISTICS 156 449 #define IWN_CMD_SET_CRITICAL_TEMP 164 450 #define IWN_CMD_SET_SENSITIVITY 168 451 #define IWN_CMD_PHY_CALIB 176 452 #define IWN_CMD_BT_COEX_PRIOTABLE 204 453 #define IWN_CMD_BT_COEX_PROT 205 454 455 uint8_t flags; 456 uint8_t idx; 457 uint8_t qid; 458 uint8_t data[136]; 459 } __packed; 460 461 /* Antenna flags, used in various commands. */ 462 #define IWN_ANT_A (1 << 0) 463 #define IWN_ANT_B (1 << 1) 464 #define IWN_ANT_C (1 << 2) 465 /* Shortcuts. */ 466 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 467 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 468 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 469 470 /* Structure for command IWN_CMD_RXON. */ 471 struct iwn_rxon { 472 uint8_t myaddr[IEEE80211_ADDR_LEN]; 473 uint16_t reserved1; 474 uint8_t bssid[IEEE80211_ADDR_LEN]; 475 uint16_t reserved2; 476 uint8_t wlap[IEEE80211_ADDR_LEN]; 477 uint16_t reserved3; 478 uint8_t mode; 479 #define IWN_MODE_HOSTAP 1 480 #define IWN_MODE_STA 3 481 #define IWN_MODE_IBSS 4 482 #define IWN_MODE_MONITOR 6 483 484 uint8_t air; 485 uint16_t rxchain; 486 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 487 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 488 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 489 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 490 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 491 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 492 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 493 494 uint8_t ofdm_mask; 495 uint8_t cck_mask; 496 uint16_t associd; 497 uint32_t flags; 498 #define IWN_RXON_24GHZ (1 << 0) 499 #define IWN_RXON_CCK (1 << 1) 500 #define IWN_RXON_AUTO (1 << 2) 501 #define IWN_RXON_TGG_PROT (1 << 3) 502 #define IWN_RXON_SHSLOT (1 << 4) 503 #define IWN_RXON_SHPREAMBLE (1 << 5) 504 #define IWN_RXON_NODIVERSITY (1 << 7) 505 #define IWN_RXON_ANTENNA_A (1 << 8) 506 #define IWN_RXON_ANTENNA_B (1 << 9) 507 #define IWN_RXON_TSF (1 << 15) 508 #define IWN_RXON_HT_HT40MINUS (1 << 22) 509 #define IWN_RXON_HT_PROTMODE(x) ((x) << 23) /* 2 bits */ 510 #define IWN_RXON_HT_CHANMODE_PURE40 (1 << 25) 511 #define IWN_RXON_HT_CHANMODE_MIXED2040 (2 << 25) 512 #define IWN_RXON_CTS_TO_SELF (1 << 30) 513 514 uint32_t filter; 515 #define IWN_FILTER_PROMISC (1 << 0) 516 #define IWN_FILTER_CTL (1 << 1) 517 #define IWN_FILTER_MULTICAST (1 << 2) 518 #define IWN_FILTER_NODECRYPT (1 << 3) 519 #define IWN_FILTER_BSS (1 << 5) 520 #define IWN_FILTER_BEACON (1 << 6) 521 522 uint8_t chan; 523 uint8_t reserved4; 524 uint8_t ht_single_mask; 525 uint8_t ht_dual_mask; 526 /* The following fields are for >=5000 Series only. */ 527 uint8_t ht_triple_mask; 528 uint8_t reserved5; 529 uint16_t acquisition; 530 uint16_t reserved6; 531 } __packed; 532 533 /* Structure for command IWN_CMD_RXON_ASSOC. */ 534 struct iwn_rxon_assoc { 535 uint32_t flags; 536 uint32_t filter; 537 uint8_t ofdm_mask; 538 uint8_t cck_mask; 539 uint16_t reserved1; 540 uint8_t ht_single_mask; 541 uint8_t ht_dual_mask; 542 uint8_t ht_triple_mask; 543 uint8_t reserved2; 544 uint16_t rxchain; 545 uint16_t acquisition; 546 uint32_t reserved3; 547 } __packed; 548 549 struct iwn4965_rxon_assoc { 550 uint32_t flags; 551 uint32_t filter; 552 uint8_t ofdm_mask; 553 uint8_t cck_mask; 554 uint8_t ht_single_mask; 555 uint8_t ht_dual_mask; 556 uint16_t rxchain; 557 uint16_t reserved; 558 }; 559 560 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 561 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 562 563 /* Structure for command IWN_CMD_ASSOCIATE. */ 564 struct iwn_assoc { 565 uint32_t flags; 566 uint32_t filter; 567 uint8_t ofdm_mask; 568 uint8_t cck_mask; 569 uint16_t reserved; 570 } __packed; 571 572 /* Structure for command IWN_CMD_EDCA_PARAMS. */ 573 struct iwn_edca_params { 574 uint32_t flags; 575 #define IWN_EDCA_UPDATE (1 << 0) 576 #define IWN_EDCA_TXOP (1 << 4) 577 578 struct { 579 uint16_t cwmin; 580 uint16_t cwmax; 581 uint8_t aifsn; 582 uint8_t reserved; 583 uint16_t txoplimit; 584 } __packed ac[EDCA_NUM_AC]; 585 } __packed; 586 587 /* Structure for command IWN_CMD_TIMING. */ 588 struct iwn_cmd_timing { 589 uint64_t tstamp; 590 uint16_t bintval; 591 uint16_t atim; 592 uint32_t binitval; 593 uint16_t lintval; 594 uint16_t reserved; 595 } __packed; 596 597 /* Structure for command IWN_CMD_ADD_NODE. */ 598 struct iwn_node_info { 599 uint8_t control; 600 #define IWN_NODE_UPDATE (1 << 0) 601 602 uint8_t reserved1[3]; 603 604 uint8_t macaddr[IEEE80211_ADDR_LEN]; 605 uint16_t reserved2; 606 uint8_t id; 607 #define IWN_ID_BSS 0 608 #define IWN5000_ID_BROADCAST 15 609 #define IWN4965_ID_BROADCAST 31 610 611 uint8_t flags; 612 #define IWN_FLAG_SET_KEY (1 << 0) 613 #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 614 #define IWN_FLAG_SET_TXRATE (1 << 2) 615 #define IWN_FLAG_SET_ADDBA (1 << 3) 616 #define IWN_FLAG_SET_DELBA (1 << 4) 617 618 uint16_t reserved3; 619 uint16_t kflags; 620 #define IWN_KFLAG_CCMP (1 << 1) 621 #define IWN_KFLAG_MAP (1 << 3) 622 #define IWN_KFLAG_KID(kid) ((kid) << 8) 623 #define IWN_KFLAG_INVALID (1 << 11) 624 #define IWN_KFLAG_GROUP (1 << 14) 625 626 uint8_t tsc2; /* TKIP TSC2 */ 627 uint8_t reserved4; 628 uint16_t ttak[5]; 629 uint8_t kid; 630 uint8_t reserved5; 631 uint8_t key[16]; 632 /* The following 3 fields are for 5000 Series only. */ 633 uint64_t tsc; 634 uint8_t rxmic[IEEE80211_TKIP_MICLEN]; 635 uint8_t txmic[IEEE80211_TKIP_MICLEN]; 636 637 uint32_t htflags; 638 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 639 #define IWN_AMDPU_SIZE_FACTOR_MASK ((0x3) << 19) 640 #define IWN_40MHZ_ENABLE (1 << 21) 641 #define IWN_MIMO_DISABLE (1 << 22) 642 #define IWN_AMDPU_DENSITY(x) ((x) << 23) 643 #define IWN_AMDPU_DENSITY_MASK ((0x7) << 23) 644 645 uint32_t htmask; 646 uint16_t disable_tid; 647 uint16_t reserved6; 648 uint8_t addba_tid; 649 uint8_t delba_tid; 650 uint16_t addba_ssn; 651 uint32_t reserved7; 652 } __packed; 653 654 struct iwn4965_node_info { 655 uint8_t control; 656 uint8_t reserved1[3]; 657 uint8_t macaddr[IEEE80211_ADDR_LEN]; 658 uint16_t reserved2; 659 uint8_t id; 660 uint8_t flags; 661 uint16_t reserved3; 662 uint16_t kflags; 663 uint8_t tsc2; /* TKIP TSC2 */ 664 uint8_t reserved4; 665 uint16_t ttak[5]; 666 uint8_t kid; 667 uint8_t reserved5; 668 uint8_t key[16]; 669 uint32_t htflags; 670 uint32_t htmask; 671 uint16_t disable_tid; 672 uint16_t reserved6; 673 uint8_t addba_tid; 674 uint8_t delba_tid; 675 uint16_t addba_ssn; 676 uint32_t reserved7; 677 } __packed; 678 679 #define IWN_RFLAG_MCS (1 << 0) 680 #define IWN_RFLAG_CCK (1 << 1) 681 #define IWN_RFLAG_GREENFIELD (1 << 2) 682 #define IWN_RFLAG_HT40 (1 << 3) 683 #define IWN_RFLAG_DUPLICATE (1 << 4) 684 #define IWN_RFLAG_SGI (1 << 5) 685 #define IWN_RFLAG_ANT(x) ((x) << 6) 686 687 /* Structure for command IWN_CMD_TX_DATA. */ 688 struct iwn_cmd_data { 689 uint16_t len; 690 uint16_t lnext; 691 uint32_t flags; 692 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 693 #define IWN_TX_NEED_RTS (1 << 1) 694 #define IWN_TX_NEED_CTS (1 << 2) 695 #define IWN_TX_NEED_ACK (1 << 3) 696 #define IWN_TX_LINKQ (1 << 4) 697 #define IWN_TX_IMM_BA (1 << 6) 698 #define IWN_TX_FULL_TXOP (1 << 7) 699 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 700 #define IWN_TX_AUTO_SEQ (1 << 13) 701 #define IWN_TX_MORE_FRAG (1 << 14) 702 #define IWN_TX_INSERT_TSTAMP (1 << 16) 703 #define IWN_TX_NEED_PADDING (1 << 20) 704 #define IWN_TX_AMPDU_CCMP (1 << 22) 705 706 uint32_t scratch; 707 uint8_t plcp; 708 uint8_t rflags; 709 uint16_t xrflags; 710 711 uint8_t id; 712 uint8_t security; 713 #define IWN_CIPHER_WEP40 1 714 #define IWN_CIPHER_CCMP 2 715 #define IWN_CIPHER_TKIP 3 716 #define IWN_CIPHER_WEP104 9 717 718 uint8_t linkq; 719 uint8_t reserved2; 720 uint8_t key[16]; 721 uint16_t fnext; 722 uint16_t reserved3; 723 uint32_t lifetime; 724 #define IWN_LIFETIME_INFINITE 0xffffffff 725 726 uint32_t loaddr; 727 uint8_t hiaddr; 728 uint8_t rts_ntries; 729 uint8_t data_ntries; 730 uint8_t tid; 731 uint16_t timeout; 732 uint16_t txop; 733 } __packed; 734 735 /* Structure for command IWN_CMD_LINK_QUALITY. */ 736 #define IWN_MAX_TX_RETRIES 16 737 struct iwn_cmd_link_quality { 738 uint8_t id; 739 uint8_t reserved1; 740 uint16_t ctl; 741 uint8_t flags; 742 uint8_t mimo; 743 uint8_t antmsk_1stream; 744 uint8_t antmsk_2stream; 745 uint8_t ridx[EDCA_NUM_AC]; 746 uint16_t ampdu_limit; 747 uint8_t ampdu_threshold; 748 uint8_t ampdu_max; 749 #define IWN_AMPDU_MAX_UNLIMITED 0 750 #define IWN_AMPDU_MAX_NO_AGG 1 751 #define IWN_AMPDU_MAX 63 752 uint32_t reserved2; 753 struct { 754 uint8_t plcp; 755 uint8_t rflags; 756 uint16_t xrflags; 757 } __packed retry[IWN_MAX_TX_RETRIES]; 758 uint32_t reserved3; 759 } __packed; 760 761 /* Structure for command IWN_CMD_SET_LED. */ 762 struct iwn_cmd_led { 763 uint32_t unit; /* multiplier (in usecs) */ 764 uint8_t which; 765 #define IWN_LED_ACTIVITY 1 766 #define IWN_LED_LINK 2 767 768 uint8_t off; 769 uint8_t on; 770 uint8_t reserved; 771 } __packed; 772 773 /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 774 struct iwn5000_wimax_coex { 775 uint32_t flags; 776 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 777 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 778 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 779 #define IWN_WIMAX_COEX_ENABLE (1 << 7) 780 781 struct iwn5000_wimax_event { 782 uint8_t request; 783 uint8_t window; 784 uint8_t reserved; 785 uint8_t flags; 786 } __packed events[16]; 787 } __packed; 788 789 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 790 struct iwn5000_calib_elem { 791 uint32_t enable; 792 uint32_t start; 793 #define IWN5000_CALIB_DC (1 << 1) 794 795 uint32_t send; 796 uint32_t apply; 797 uint32_t reserved; 798 } __packed; 799 800 struct iwn5000_calib_status { 801 struct iwn5000_calib_elem once; 802 struct iwn5000_calib_elem perd; 803 uint32_t flags; 804 } __packed; 805 806 struct iwn5000_calib_config { 807 struct iwn5000_calib_status ucode; 808 struct iwn5000_calib_status driver; 809 uint32_t reserved; 810 } __packed; 811 812 /* Structure for command IWN_CMD_SET_POWER_MODE. */ 813 struct iwn_pmgt_cmd { 814 uint16_t flags; 815 #define IWN_PS_ALLOW_SLEEP (1 << 0) 816 #define IWN_PS_NOTIFY (1 << 1) 817 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 818 #define IWN_PS_PCI_PMGT (1 << 3) 819 #define IWN_PS_FAST_PD (1 << 4) 820 821 uint8_t keepalive; 822 uint8_t debug; 823 uint32_t rxtimeout; 824 uint32_t txtimeout; 825 uint32_t intval[5]; 826 uint32_t beacons; 827 } __packed; 828 829 /* Structures for command IWN_CMD_SCAN. */ 830 struct iwn_scan_essid { 831 uint8_t id; 832 uint8_t len; 833 uint8_t data[IEEE80211_NWID_LEN]; 834 } __packed; 835 836 struct iwn_scan_hdr { 837 uint16_t len; 838 uint8_t reserved1; 839 uint8_t nchan; 840 uint16_t quiet_time; 841 uint16_t quiet_threshold; 842 uint16_t crc_threshold; 843 uint16_t rxchain; 844 uint32_t max_out; /* (in usec) background scans */ 845 uint32_t pause_scan; /* (in usec) background scans */ 846 uint32_t flags; 847 uint32_t filter; 848 849 /* Followed by a struct iwn_cmd_data. */ 850 /* Followed by an array of 20 structs iwn_scan_essid. */ 851 /* Followed by probe request body. */ 852 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 853 } __packed; 854 855 struct iwn_scan_chan { 856 uint32_t flags; 857 #define IWN_CHAN_PASSIVE (0 << 0) 858 #define IWN_CHAN_ACTIVE (1 << 0) 859 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 860 861 uint16_t chan; 862 uint8_t rf_gain; 863 uint8_t dsp_gain; 864 uint16_t active; /* msecs */ 865 uint16_t passive; /* msecs */ 866 } __packed; 867 868 /* Maximum size of a scan command. */ 869 #define IWN_SCAN_MAXSZ (MCLBYTES - 4) 870 871 /* 872 * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after 873 * sending probe req. This should be set long enough to hear probe responses 874 * from more than one AP. 875 */ 876 #define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 877 #define IWN_ACTIVE_DWELL_TIME_5GHZ (20) 878 #define IWN_ACTIVE_DWELL_FACTOR_2GHZ (3) 879 #define IWN_ACTIVE_DWELL_FACTOR_5GHZ (2) 880 881 /* 882 * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. 883 * Must be set longer than active dwell time. 884 * For the most reliable scan, set > AP beacon interval (typically 100msec). 885 */ 886 #define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */ 887 #define IWN_PASSIVE_DWELL_TIME_5GHZ (10) 888 #define IWN_PASSIVE_DWELL_BASE (100) 889 #define IWN_CHANNEL_TUNE_TIME (5) 890 891 /* 892 * If active scanning is requested but a certain channel is 893 * marked passive, we can do active scanning if we detect 894 * transmissions. 895 * 896 * There is an issue with some firmware versions that triggers 897 * a sysassert on a "good CRC threshold" of zero (== disabled), 898 * on a radar channel even though this means that we should NOT 899 * send probes. 900 * 901 * The "good CRC threshold" is the number of frames that we 902 * need to receive during our dwell time on a channel before 903 * sending out probes -- setting this to a huge value will 904 * mean we never reach it, but at the same time work around 905 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 906 * here instead of IWN_GOOD_CRC_TH_DISABLED. 907 * 908 * This was fixed in later versions along with some other 909 * scan changes, and the threshold behaves as a flag in those 910 * versions. 911 */ 912 #define IWN_GOOD_CRC_TH_DISABLED 0 913 #define IWN_GOOD_CRC_TH_DEFAULT htole16(1) 914 #define IWN_GOOD_CRC_TH_NEVER htole16(0xffff) 915 916 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 917 #define IWN_RIDX_MAX 32 918 struct iwn4965_cmd_txpower { 919 uint8_t band; 920 uint8_t reserved1; 921 uint8_t chan; 922 uint8_t reserved2; 923 struct { 924 uint8_t rf_gain[2]; 925 uint8_t dsp_gain[2]; 926 } __packed power[IWN_RIDX_MAX + 1]; 927 } __packed; 928 929 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 930 struct iwn5000_cmd_txpower { 931 int8_t global_limit; /* in half-dBm */ 932 #define IWN5000_TXPOWER_AUTO 0x7f 933 #define IWN5000_TXPOWER_MAX_DBM 16 934 935 uint8_t flags; 936 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 937 938 int8_t srv_limit; /* in half-dBm */ 939 uint8_t reserved; 940 } __packed; 941 942 /* Structures for command IWN_CMD_BLUETOOTH. */ 943 struct iwn_bluetooth { 944 uint8_t flags; 945 #define IWN_BT_COEX_CHAN_ANN (1 << 0) 946 #define IWN_BT_COEX_BT_PRIO (1 << 1) 947 #define IWN_BT_COEX_2_WIRE (1 << 2) 948 949 uint8_t lead_time; 950 #define IWN_BT_LEAD_TIME_DEF 30 951 952 uint8_t max_kill; 953 #define IWN_BT_MAX_KILL_DEF 5 954 955 uint8_t reserved; 956 uint32_t kill_ack; 957 uint32_t kill_cts; 958 } __packed; 959 960 struct iwn6000_btcoex_config { 961 uint8_t flags; 962 #define IWN_BT_COEX6000_CHAN_INHIBITION 1 963 #define IWN_BT_COEX6000_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5)) 964 #define IWN_BT_COEX6000_MODE_SHIFT 3 965 #define IWN_BT_COEX6000_MODE_DISABLED 0 966 #define IWN_BT_COEX6000_MODE_LEGACY_2W 1 967 #define IWN_BT_COEX6000_MODE_3W 2 968 #define IWN_BT_COEX6000_MODE_4W 3 969 #define IWN_BT_UCODE_DEFAULT (1<<6) 970 #define IWN_BT_SYNC_2_BT_DISABLE (1<<7) 971 972 uint8_t lead_time; 973 uint8_t max_kill; 974 uint8_t bt3_t7_timer; 975 uint32_t kill_ack; 976 uint32_t kill_cts; 977 uint8_t sample_time; 978 uint8_t bt3_t2_timer; 979 uint16_t bt4_reaction; 980 uint32_t lookup_table[12]; 981 uint16_t bt4_decision; 982 uint16_t valid; 983 uint8_t prio_boost; 984 uint8_t tx_prio_boost; 985 uint16_t rx_prio_boost; 986 } __packed; 987 988 struct iwn2000_btcoex_config { 989 uint8_t flags; /* same as in iwn6000_btcoex_config */ 990 uint8_t lead_time; 991 uint8_t max_kill; 992 uint8_t bt3_t7_timer; 993 uint32_t kill_ack; 994 uint32_t kill_cts; 995 uint8_t sample_time; 996 uint8_t bt3_t2_timer; 997 uint16_t bt4_reaction; 998 uint32_t lookup_table[12]; 999 uint16_t bt4_decision; 1000 uint16_t valid; 1001 uint32_t prio_boost; 1002 uint8_t reserved; 1003 uint8_t tx_prio_boost; 1004 uint16_t rx_prio_boost; 1005 } __packed; 1006 1007 /* Structure for command IWN_CMD_BT_COEX_PRIOTABLE */ 1008 struct iwn_btcoex_priotable { 1009 uint8_t calib_init1; 1010 uint8_t calib_init2; 1011 uint8_t calib_periodic_low1; 1012 uint8_t calib_periodic_low2; 1013 uint8_t calib_periodic_high1; 1014 uint8_t calib_periodic_high2; 1015 uint8_t dtim; 1016 uint8_t scan52; 1017 uint8_t scan24; 1018 uint8_t reserved[7]; 1019 } __packed; 1020 1021 /* Structure for command IWN_CMD_BT_COEX_PROT */ 1022 struct iwn_btcoex_prot { 1023 uint8_t open; 1024 uint8_t type; 1025 uint8_t reserved[2]; 1026 } __packed; 1027 1028 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 1029 struct iwn_critical_temp { 1030 uint32_t reserved; 1031 uint32_t tempM; 1032 uint32_t tempR; 1033 /* degK <-> degC conversion macros. */ 1034 #define IWN_CTOK(c) ((c) + 273) 1035 #define IWN_KTOC(k) ((k) - 273) 1036 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1037 } __packed; 1038 1039 /* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1040 struct iwn_sensitivity_cmd { 1041 uint16_t which; 1042 #define IWN_SENSITIVITY_DEFAULTTBL 0 1043 #define IWN_SENSITIVITY_WORKTBL 1 1044 1045 uint16_t energy_cck; 1046 uint16_t energy_ofdm; 1047 uint16_t corr_ofdm_x1; 1048 uint16_t corr_ofdm_mrc_x1; 1049 uint16_t corr_cck_mrc_x4; 1050 uint16_t corr_ofdm_x4; 1051 uint16_t corr_ofdm_mrc_x4; 1052 uint16_t corr_barker; 1053 uint16_t corr_barker_mrc; 1054 uint16_t corr_cck_x4; 1055 uint16_t energy_ofdm_th; 1056 } __packed; 1057 1058 struct iwn_enhanced_sensitivity_cmd { 1059 uint16_t which; 1060 uint16_t energy_cck; 1061 uint16_t energy_ofdm; 1062 uint16_t corr_ofdm_x1; 1063 uint16_t corr_ofdm_mrc_x1; 1064 uint16_t corr_cck_mrc_x4; 1065 uint16_t corr_ofdm_x4; 1066 uint16_t corr_ofdm_mrc_x4; 1067 uint16_t corr_barker; 1068 uint16_t corr_barker_mrc; 1069 uint16_t corr_cck_x4; 1070 uint16_t energy_ofdm_th; 1071 /* "Enhanced" part. */ 1072 uint16_t ina_det_ofdm; 1073 uint16_t ina_det_cck; 1074 uint16_t corr_11_9_en; 1075 uint16_t ofdm_det_slope_mrc; 1076 uint16_t ofdm_det_icept_mrc; 1077 uint16_t ofdm_det_slope; 1078 uint16_t ofdm_det_icept; 1079 uint16_t cck_det_slope_mrc; 1080 uint16_t cck_det_icept_mrc; 1081 uint16_t cck_det_slope; 1082 uint16_t cck_det_icept; 1083 uint16_t reserved; 1084 } __packed; 1085 1086 /* Structures for command IWN_CMD_PHY_CALIB. */ 1087 struct iwn_phy_calib { 1088 uint8_t code; 1089 #define IWN4965_PHY_CALIB_DIFF_GAIN 7 1090 #define IWN5000_PHY_CALIB_DC 8 1091 #define IWN5000_PHY_CALIB_LO 9 1092 #define IWN5000_PHY_CALIB_TX_IQ 11 1093 #define IWN5000_PHY_CALIB_CRYSTAL 15 1094 #define IWN5000_PHY_CALIB_BASE_BAND 16 1095 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1096 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1097 #define IWN5000_PHY_CALIB_NOISE_GAIN 19 1098 1099 #define IWN6000_PHY_CALIB_TEMP_OFFSET 18 1100 #define IWN2000_PHY_CALIB_TEMP_OFFSET 18 1101 1102 #define IWN5000_PHY_CALIB_MAX 253 1103 1104 uint8_t group; 1105 uint8_t ngroups; 1106 uint8_t isvalid; 1107 } __packed; 1108 1109 struct iwn5000_phy_calib_crystal { 1110 uint8_t code; 1111 uint8_t group; 1112 uint8_t ngroups; 1113 uint8_t isvalid; 1114 1115 uint8_t cap_pin[2]; 1116 uint8_t reserved[2]; 1117 } __packed; 1118 1119 struct iwn6000_phy_calib_temp_offset { 1120 uint8_t code; 1121 uint8_t group; 1122 uint8_t ngroups; 1123 uint8_t isvalid; 1124 int16_t offset; 1125 #define IWN_DEFAULT_TEMP_OFFSET 2700 1126 1127 uint16_t reserved; 1128 } __packed; 1129 1130 struct iwn2000_phy_calib_temp_offset { 1131 uint8_t code; 1132 uint8_t group; 1133 uint8_t ngroups; 1134 uint8_t isvalid; 1135 int16_t offset_high; 1136 int16_t offset_low; 1137 int16_t burnt_voltage_ref; 1138 int16_t reserved; 1139 } __packed; 1140 1141 struct iwn_phy_calib_gain { 1142 uint8_t code; 1143 uint8_t group; 1144 uint8_t ngroups; 1145 uint8_t isvalid; 1146 1147 int8_t gain[3]; 1148 uint8_t reserved; 1149 } __packed; 1150 1151 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1152 struct iwn_spectrum_cmd { 1153 uint16_t len; 1154 uint8_t token; 1155 uint8_t id; 1156 uint8_t origin; 1157 uint8_t periodic; 1158 uint16_t timeout; 1159 uint32_t start; 1160 uint32_t reserved1; 1161 uint32_t flags; 1162 uint32_t filter; 1163 uint16_t nchan; 1164 uint16_t reserved2; 1165 struct { 1166 uint32_t duration; 1167 uint8_t chan; 1168 uint8_t type; 1169 #define IWN_MEASUREMENT_BASIC (1 << 0) 1170 #define IWN_MEASUREMENT_CCA (1 << 1) 1171 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1172 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1173 #define IWN_MEASUREMENT_FRAME (1 << 4) 1174 #define IWN_MEASUREMENT_IDLE (1 << 7) 1175 1176 uint16_t reserved; 1177 } __packed chan[10]; 1178 } __packed; 1179 1180 /* Structure for IWN_UC_READY notification. */ 1181 #define IWN_NATTEN_GROUPS 5 1182 struct iwn_ucode_info { 1183 uint8_t minor; 1184 uint8_t major; 1185 uint16_t reserved1; 1186 uint8_t revision[8]; 1187 uint8_t type; 1188 uint8_t subtype; 1189 #define IWN_UCODE_RUNTIME 0 1190 #define IWN_UCODE_INIT 9 1191 1192 uint16_t reserved2; 1193 uint32_t logptr; 1194 uint32_t errptr; 1195 uint32_t tstamp; 1196 uint32_t valid; 1197 1198 /* The following fields are for UCODE_INIT only. */ 1199 int32_t volt; 1200 struct { 1201 int32_t chan20MHz; 1202 int32_t chan40MHz; 1203 } __packed temp[4]; 1204 int32_t atten[IWN_NATTEN_GROUPS][2]; 1205 } __packed; 1206 1207 /* Structures for IWN_TX_DONE notification. */ 1208 1209 /* Tx status for aggregated frames (A-MPDU). */ 1210 struct iwn_txagg_status { 1211 uint16_t status; 1212 #define IWN_AGG_TX_STATE_TRANSMITTED 0x0000 1213 #define IWN_AGG_TX_STATE_UNDERRUN 0x0001 1214 #define IWN_AGG_TX_STATE_BT_PRIO 0x0002 1215 #define IWN_AGG_TX_STATE_FEW_BYTES 0x0004 1216 #define IWN_AGG_TX_STATE_ABORT 0x0008 1217 #define IWN_AGG_TX_STATE_LAST_SENT_TTL 0x0010 1218 #define IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020 1219 #define IWN_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040 1220 #define IWN_AGG_TX_STATE_SCD_QUERY 0x0080 1221 #define IWN_AGG_TX_STATE_TEST_BAD_CRC32 0x0100 1222 #define IWN_AGG_TX_STATE_RESPONSE_MASK 0x01ff 1223 #define IWN_AGG_TX_STATE_DUMP_TX 0x0200 1224 #define IWN_AGG_TX_STATE_DELAY_TX 0x0400 1225 #define IWN_AGG_TX_STATUS_MASK 0x0fff 1226 /* Number of TX attempts for first frame in aggregation: */ 1227 #define IWN_AGG_TX_TRY 0xf000 1228 #define IWN_AGG_TX_TRY_SHIFT 12 1229 1230 /* Copied from Tx command we have sent to the firmware. */ 1231 uint8_t idx; 1232 uint8_t qid; 1233 } __packed; 1234 1235 /* For aggregation queues, index must be aligned to frame sequence number. */ 1236 #define IWN_AGG_SSN_TO_TXQ_IDX(x) ((x) & (IWN_TX_RING_COUNT - 1)) 1237 1238 /* Tx status codes for non-aggregated frames. */ 1239 #define IWN_TX_STATUS_SUCCESS 0x01 1240 #define IWN_TX_STATUS_DIRECT_DONE 0x02 1241 #define IWN_TX_STATUS_POSTPONE_DELAY 0x40 1242 #define IWN_TX_STATUS_POSTPONE_FEW_BYTES 0x41 1243 #define IWN_TX_STATUS_POSTPONE_BT_PRIO 0x42 1244 #define IWN_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43 1245 #define IWN_TX_STATUS_POSTPONE_CALC_TTAK 0x44 1246 #define IWN_TX_STATUS_FAIL_CROSSED_RETRY 0x81 1247 #define IWN_TX_STATUS_FAIL_SHORT_LIMIT 0x82 1248 #define IWN_TX_STATUS_FAIL_LONG_LIMIT 0x83 1249 #define IWN_TX_STATUS_FAIL_FIFO_UNDERRUN 0x84 1250 #define IWN_TX_STATUS_FAIL_DRAIN_FLOW 0x85 1251 #define IWN_TX_STATUS_FAIL_RFKILL_FLUSH 0x86 1252 #define IWN_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 1253 #define IWN_TX_STATUS_FAIL_DEST_PS 0x88 1254 #define IWN_TX_STATUS_FAIL_HOST_ABORTED 0x89 1255 #define IWN_TX_STATUS_FAIL_BT_RETRY 0x8a 1256 #define IWN_TX_STATUS_FAIL_STA_INVALID 0x8b 1257 #define IWN_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 1258 #define IWN_TX_STATUS_FAIL_TID_DISABLE 0x8d 1259 #define IWN_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e 1260 #define IWN_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f 1261 #define IWN_TX_STATUS_FAIL_PASSIVE_NO_RX 0x90 1262 #define IWN_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91 1263 1264 struct iwn4965_tx_stat { 1265 uint8_t nframes; 1266 uint8_t btkillcnt; 1267 uint8_t rtsfailcnt; 1268 uint8_t ackfailcnt; 1269 uint8_t rate; 1270 uint8_t rflags; 1271 uint16_t xrflags; 1272 uint16_t duration; 1273 uint16_t reserved; 1274 uint32_t power[2]; 1275 union { 1276 uint32_t status; /* if nframes == 1 */ 1277 struct iwn_txagg_status agg_status[0]; /* nframes elements */ 1278 } stat; 1279 /* Followed by current scheduler SSN (uint32_t). */ 1280 } __packed; 1281 1282 struct iwn5000_tx_stat { 1283 uint8_t nframes; 1284 uint8_t btkillcnt; 1285 uint8_t rtsfailcnt; 1286 uint8_t ackfailcnt; 1287 uint8_t rate; 1288 uint8_t rflags; 1289 uint16_t xrflags; 1290 uint16_t duration; 1291 uint16_t reserved; 1292 uint32_t power[2]; 1293 uint32_t info; 1294 uint16_t seq; 1295 uint16_t len; 1296 uint8_t tlc; 1297 uint8_t ratid; 1298 #define IWN_TX_RES_TID_SHIFT 0 1299 #define IWN_TX_RES_TID 0x0f 1300 #define IWN_TX_RES_RA_SHIFT 4 1301 #define IWN_TX_RES_RA 0xf0 1302 uint8_t fc[2]; 1303 union { 1304 uint32_t status; /* if nframes == 1 */ 1305 struct iwn_txagg_status agg_status[0]; /* nframes elements */ 1306 } stat; 1307 /* Followed by current scheduler SSN (uint32_t). */ 1308 } __packed; 1309 1310 /* Structure for IWN_BEACON_MISSED notification. */ 1311 struct iwn_beacon_missed { 1312 uint32_t consecutive; 1313 uint32_t total; 1314 uint32_t expected; 1315 uint32_t received; 1316 } __packed; 1317 1318 /* Structure for IWN_MPDU_RX_DONE notification. */ 1319 struct iwn_rx_mpdu { 1320 uint16_t len; 1321 uint16_t reserved; 1322 } __packed; 1323 1324 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1325 struct iwn4965_rx_phystat { 1326 uint16_t antenna; 1327 uint16_t agc; 1328 uint8_t rssi[6]; 1329 } __packed; 1330 1331 struct iwn5000_rx_phystat { 1332 uint32_t reserved1; 1333 uint32_t agc; 1334 uint16_t rssi[3]; 1335 } __packed; 1336 1337 struct iwn_rx_stat { 1338 uint8_t phy_len; 1339 uint8_t cfg_phy_len; 1340 #define IWN_STAT_MAXLEN 20 1341 1342 uint8_t id; 1343 uint8_t reserved1; 1344 uint64_t tstamp; 1345 uint32_t beacon; 1346 uint16_t flags; 1347 #define IWN_STAT_FLAG_24GHZ (1 << 0) 1348 #define IWN_STAT_FLAG_MOD_CCK (1 << 1) 1349 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1350 #define IWN_STAT_FLAG_NARROW_BAND (1 << 3) 1351 #define IWN_STAT_FLAG_ANT(x) ((x) << 4) /* 3 bits */ 1352 #define IWN_STAT_FLAG_AGG (1 << 7) 1353 1354 uint16_t chan; 1355 uint8_t phybuf[32]; 1356 uint8_t rate; 1357 uint8_t rflags; 1358 uint16_t xrflags; 1359 uint16_t len; 1360 uint16_t reserve3; 1361 } __packed; 1362 1363 #define IWN_RSSI_TO_DBM 44 1364 1365 /* Structure for IWN_RX_COMPRESSED_BA notification. */ 1366 struct iwn_compressed_ba { 1367 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1368 uint16_t reserved; 1369 uint8_t id; 1370 uint8_t tid; 1371 uint16_t seq; 1372 uint64_t bitmap; 1373 uint16_t qid; 1374 uint16_t ssn; 1375 uint8_t nframes_sent; 1376 uint8_t nframes_acked; 1377 uint16_t reserved2; 1378 } __packed; 1379 1380 /* Structure for IWN_START_SCAN notification. */ 1381 struct iwn_start_scan { 1382 uint64_t tstamp; 1383 uint32_t tbeacon; 1384 uint8_t chan; 1385 uint8_t band; 1386 uint16_t reserved; 1387 uint32_t status; 1388 } __packed; 1389 1390 /* Structure for IWN_STOP_SCAN notification. */ 1391 struct iwn_stop_scan { 1392 uint8_t nchan; 1393 uint8_t status; 1394 uint8_t reserved; 1395 uint8_t chan; 1396 uint64_t tsf; 1397 } __packed; 1398 1399 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1400 struct iwn_spectrum_notif { 1401 uint8_t id; 1402 uint8_t token; 1403 uint8_t idx; 1404 uint8_t state; 1405 #define IWN_MEASUREMENT_START 0 1406 #define IWN_MEASUREMENT_STOP 1 1407 1408 uint32_t start; 1409 uint8_t band; 1410 uint8_t chan; 1411 uint8_t type; 1412 uint8_t reserved1; 1413 uint32_t cca_ofdm; 1414 uint32_t cca_cck; 1415 uint32_t cca_time; 1416 uint8_t basic; 1417 uint8_t reserved2[3]; 1418 uint32_t ofdm[8]; 1419 uint32_t cck[8]; 1420 uint32_t stop; 1421 uint32_t status; 1422 #define IWN_MEASUREMENT_OK 0 1423 #define IWN_MEASUREMENT_CONCURRENT 1 1424 #define IWN_MEASUREMENT_CSA_CONFLICT 2 1425 #define IWN_MEASUREMENT_TGH_CONFLICT 3 1426 #define IWN_MEASUREMENT_STOPPED 6 1427 #define IWN_MEASUREMENT_TIMEOUT 7 1428 #define IWN_MEASUREMENT_FAILED 8 1429 } __packed; 1430 1431 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1432 struct iwn_rx_phy_stats { 1433 uint32_t ina; 1434 uint32_t fina; 1435 uint32_t bad_plcp; 1436 uint32_t bad_crc32; 1437 uint32_t overrun; 1438 uint32_t eoverrun; 1439 uint32_t good_crc32; 1440 uint32_t fa; 1441 uint32_t bad_fina_sync; 1442 uint32_t sfd_timeout; 1443 uint32_t fina_timeout; 1444 uint32_t no_rts_ack; 1445 uint32_t rxe_limit; 1446 uint32_t ack; 1447 uint32_t cts; 1448 uint32_t ba_resp; 1449 uint32_t dsp_kill; 1450 uint32_t bad_mh; 1451 uint32_t rssi_sum; 1452 uint32_t reserved; 1453 } __packed; 1454 1455 struct iwn_rx_general_stats { 1456 uint32_t bad_cts; 1457 uint32_t bad_ack; 1458 uint32_t not_bss; 1459 uint32_t filtered; 1460 uint32_t bad_chan; 1461 uint32_t beacons; 1462 uint32_t missed_beacons; 1463 uint32_t adc_saturated; /* time in 0.8us */ 1464 uint32_t ina_searched; /* time in 0.8us */ 1465 uint32_t noise[3]; 1466 uint32_t flags; 1467 uint32_t load; 1468 uint32_t fa; 1469 uint32_t rssi[3]; 1470 uint32_t energy[3]; 1471 } __packed; 1472 1473 struct iwn_rx_ht_phy_stats { 1474 uint32_t bad_plcp; 1475 uint32_t overrun; 1476 uint32_t eoverrun; 1477 uint32_t good_crc32; 1478 uint32_t bad_crc32; 1479 uint32_t bad_mh; 1480 uint32_t good_ampdu_crc32; 1481 uint32_t ampdu; 1482 uint32_t fragment; 1483 uint32_t reserved; 1484 } __packed; 1485 1486 struct iwn_rx_stats { 1487 struct iwn_rx_phy_stats ofdm; 1488 struct iwn_rx_phy_stats cck; 1489 struct iwn_rx_general_stats general; 1490 struct iwn_rx_ht_phy_stats ht; 1491 } __packed; 1492 1493 struct iwn_tx_stats { 1494 uint32_t preamble; 1495 uint32_t rx_detected; 1496 uint32_t bt_defer; 1497 uint32_t bt_kill; 1498 uint32_t short_len; 1499 uint32_t cts_timeout; 1500 uint32_t ack_timeout; 1501 uint32_t exp_ack; 1502 uint32_t ack; 1503 uint32_t msdu; 1504 uint32_t busrt_err1; 1505 uint32_t burst_err2; 1506 uint32_t cts_collision; 1507 uint32_t ack_collision; 1508 uint32_t ba_timeout; 1509 uint32_t ba_resched; 1510 uint32_t query_ampdu; 1511 uint32_t query; 1512 uint32_t query_ampdu_frag; 1513 uint32_t query_mismatch; 1514 uint32_t not_ready; 1515 uint32_t underrun; 1516 uint32_t bt_ht_kill; 1517 uint32_t rx_ba_resp; 1518 uint32_t reserved[2]; 1519 } __packed; 1520 1521 struct iwn_general_stats { 1522 uint32_t temp; 1523 uint32_t temp_m; 1524 uint32_t burst_check; 1525 uint32_t burst; 1526 uint32_t reserved1[4]; 1527 uint32_t sleep; 1528 uint32_t slot_out; 1529 uint32_t slot_idle; 1530 uint32_t ttl_tstamp; 1531 uint32_t tx_ant_a; 1532 uint32_t tx_ant_b; 1533 uint32_t exec; 1534 uint32_t probe; 1535 uint32_t reserved2[2]; 1536 uint32_t rx_enabled; 1537 uint32_t reserved3[3]; 1538 } __packed; 1539 1540 struct iwn_stats { 1541 uint32_t flags; 1542 #define IWN_STATS_FLAGS_BAND_24G 0x02 1543 #define IWN_STATS_FLAGS_BAND_HT40 0x08 1544 struct iwn_rx_stats rx; 1545 struct iwn_tx_stats tx; 1546 struct iwn_general_stats general; 1547 } __packed; 1548 1549 1550 /* Firmware error dump. */ 1551 struct iwn_fw_dump { 1552 uint32_t valid; 1553 uint32_t id; 1554 uint32_t pc; 1555 uint32_t branch_link[2]; 1556 uint32_t interrupt_link[2]; 1557 uint32_t error_data[2]; 1558 uint32_t src_line; 1559 uint32_t tsf; 1560 uint32_t time[2]; 1561 } __packed; 1562 1563 /* TLV firmware header. */ 1564 struct iwn_fw_tlv_hdr { 1565 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1566 uint32_t signature; 1567 #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1568 1569 uint8_t descr[64]; 1570 uint32_t rev; 1571 #define IWN_FW_API(x) (((x) >> 8) & 0xff) 1572 1573 uint32_t build; 1574 uint64_t altmask; 1575 } __packed; 1576 1577 /* TLV header. */ 1578 struct iwn_fw_tlv { 1579 uint16_t type; 1580 #define IWN_FW_TLV_MAIN_TEXT 1 1581 #define IWN_FW_TLV_MAIN_DATA 2 1582 #define IWN_FW_TLV_INIT_TEXT 3 1583 #define IWN_FW_TLV_INIT_DATA 4 1584 #define IWN_FW_TLV_BOOT_TEXT 5 1585 #define IWN_FW_TLV_PBREQ_MAXLEN 6 1586 #define IWN_FW_TLV_ENH_SENS 14 1587 #define IWN_FW_TLV_PHY_CALIB 15 1588 #define IWN_FW_TLV_FLAGS 18 1589 1590 uint16_t alt; 1591 uint32_t len; 1592 } __packed; 1593 1594 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1595 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1596 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1597 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1598 #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1599 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1600 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1601 1602 /* 1603 * Microcode flags TLV (18.) 1604 */ 1605 1606 /** 1607 * enum iwn_ucode_tlv_flag - ucode API flags 1608 * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 1609 * was a separate TLV but moved here to save space. 1610 * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 1611 * treats good CRC threshold as a boolean 1612 * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 1613 * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 1614 * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 1615 * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 1616 * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 1617 * offload profile config command. 1618 * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 1619 * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 1620 * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 1621 * (rather than two) IPv6 addresses 1622 * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 1623 * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 1624 * from the probe request template. 1625 * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 1626 * connection when going back to D0 1627 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 1628 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 1629 * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 1630 * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 1631 * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 1632 * containing CAM (Continuous Active Mode) indication. 1633 */ 1634 enum iwn_ucode_tlv_flag { 1635 IWN_UCODE_TLV_FLAGS_PAN = (1 << 0), 1636 IWN_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 1637 IWN_UCODE_TLV_FLAGS_MFP = (1 << 2), 1638 IWN_UCODE_TLV_FLAGS_P2P = (1 << 3), 1639 IWN_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 1640 IWN_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 1641 IWN_UCODE_TLV_FLAGS_UAPSD = (1 << 6), 1642 IWN_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 1643 IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 1644 IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 1645 IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 1646 IWN_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 1647 IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 1648 IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 1649 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 1650 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 1651 IWN_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 1652 IWN_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 1653 IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 1654 }; 1655 1656 /* 1657 * Offsets into EEPROM. 1658 */ 1659 #define IWN_EEPROM_MAC 0x015 1660 #define IWN_EEPROM_SKU_CAP 0x045 1661 #define IWN_EEPROM_RFCFG 0x048 1662 #define IWN4965_EEPROM_DOMAIN 0x060 1663 #define IWN4965_EEPROM_BAND1 0x063 1664 #define IWN5000_EEPROM_REG 0x066 1665 #define IWN5000_EEPROM_CAL 0x067 1666 #define IWN4965_EEPROM_BAND2 0x072 1667 #define IWN4965_EEPROM_BAND3 0x080 1668 #define IWN4965_EEPROM_BAND4 0x08d 1669 #define IWN4965_EEPROM_BAND5 0x099 1670 #define IWN4965_EEPROM_BAND6 0x0a0 1671 #define IWN4965_EEPROM_BAND7 0x0a8 1672 #define IWN4965_EEPROM_MAXPOW 0x0e8 1673 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1674 #define IWN4965_EEPROM_BANDS 0x0ea 1675 /* Indirect offsets. */ 1676 #define IWN5000_EEPROM_DOMAIN 0x001 1677 #define IWN5000_EEPROM_BAND1 0x004 1678 #define IWN5000_EEPROM_BAND2 0x013 1679 #define IWN5000_EEPROM_BAND3 0x021 1680 #define IWN5000_EEPROM_BAND4 0x02e 1681 #define IWN5000_EEPROM_BAND5 0x03a 1682 #define IWN5000_EEPROM_BAND6 0x041 1683 #define IWN5000_EEPROM_BAND7 0x049 1684 #define IWN6000_EEPROM_ENHINFO 0x054 1685 #define IWN5000_EEPROM_CRYSTAL 0x128 1686 #define IWN5000_EEPROM_TEMP 0x12a 1687 #define IWN5000_EEPROM_VOLT 0x12b 1688 #define IWN2000_EEPROM_RAWTEMP 0x12b 1689 1690 /* Possible flags for IWN_EEPROM_SKU_CAP. */ 1691 #define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1692 #define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1693 #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1694 1695 /* Possible flags for IWN_EEPROM_RFCFG. */ 1696 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1697 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1698 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1699 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1700 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1701 1702 struct iwn_eeprom_chan { 1703 uint8_t flags; 1704 #define IWN_EEPROM_CHAN_VALID (1 << 0) 1705 #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1706 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1707 #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1708 1709 int8_t maxpwr; 1710 } __packed; 1711 1712 struct iwn_eeprom_enhinfo { 1713 uint8_t flags; 1714 #define IWN_TXP_VALID (1 << 0) 1715 #define IWN_TXP_BAND_52G (1 << 1) 1716 #define IWN_TXP_OFDM (1 << 2) 1717 #define IWN_TXP_40MHZ (1 << 3) 1718 #define IWN_TXP_HT_AP (1 << 4) 1719 #define IWN_TXP_RES1 (1 << 5) 1720 #define IWN_TXP_RES2 (1 << 6) 1721 #define IWN_TXP_COMMON_TYPE (1 << 7) 1722 uint8_t chan; 1723 int8_t chain[3]; /* max power in half-dBm */ 1724 uint8_t delta_20_in_40; 1725 int8_t mimo2; /* max power in half-dBm */ 1726 int8_t mimo3; /* max power in half-dBm */ 1727 } __packed; 1728 1729 struct iwn5000_eeprom_calib_hdr { 1730 uint8_t version; 1731 uint8_t pa_type; 1732 uint16_t volt; 1733 } __packed; 1734 1735 #define IWN_NSAMPLES 3 1736 struct iwn4965_eeprom_chan_samples { 1737 uint8_t num; 1738 struct { 1739 uint8_t temp; 1740 uint8_t gain; 1741 uint8_t power; 1742 int8_t pa_det; 1743 } samples[2][IWN_NSAMPLES]; 1744 } __packed; 1745 1746 #define IWN_NBANDS 8 1747 struct iwn4965_eeprom_band { 1748 uint8_t lo; /* low channel number */ 1749 uint8_t hi; /* high channel number */ 1750 struct iwn4965_eeprom_chan_samples chans[2]; 1751 } __packed; 1752 1753 /* 1754 * Offsets of channels descriptions in EEPROM. 1755 */ 1756 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1757 IWN4965_EEPROM_BAND1, 1758 IWN4965_EEPROM_BAND2, 1759 IWN4965_EEPROM_BAND3, 1760 IWN4965_EEPROM_BAND4, 1761 IWN4965_EEPROM_BAND5, 1762 IWN4965_EEPROM_BAND6, 1763 IWN4965_EEPROM_BAND7 1764 }; 1765 1766 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1767 IWN5000_EEPROM_BAND1, 1768 IWN5000_EEPROM_BAND2, 1769 IWN5000_EEPROM_BAND3, 1770 IWN5000_EEPROM_BAND4, 1771 IWN5000_EEPROM_BAND5, 1772 IWN5000_EEPROM_BAND6, 1773 IWN5000_EEPROM_BAND7 1774 }; 1775 1776 #define IWN_CHAN_BANDS_COUNT 7 1777 #define IWN_MAX_CHAN_PER_BAND 14 1778 static const struct iwn_chan_band { 1779 uint8_t nchan; 1780 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1781 } iwn_bands[] = { 1782 /* 20MHz channels, 2GHz band. */ 1783 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1784 /* 20MHz channels, 5GHz band. */ 1785 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1786 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1787 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1788 { 6, { 145, 149, 153, 157, 161, 165 } }, 1789 /* 40MHz channels (primary channels), 2GHz band. */ 1790 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1791 /* 40MHz channels (primary channels), 5GHz band. */ 1792 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1793 }; 1794 1795 #define IWN1000_OTP_NBLOCKS 3 1796 #define IWN6000_OTP_NBLOCKS 4 1797 #define IWN6050_OTP_NBLOCKS 7 1798 1799 /* HW rate indices. */ 1800 #define IWN_RIDX_CCK1 0 1801 #define IWN_RIDX_OFDM6 4 1802 1803 #define IWN_PLCP_INVALID 0xff 1804 1805 static const struct iwn_rate { 1806 uint8_t rate; 1807 uint8_t plcp; 1808 uint8_t flags; 1809 uint8_t ht_plcp; 1810 uint8_t ht_flags; 1811 } iwn_rates[IWN_RIDX_MAX + 1] = { 1812 /* Legacy */ /* HT */ 1813 { 2, 10, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, 1814 { 4, 20, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, 1815 { 11, 55, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, 1816 { 22, 110, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, 1817 { 12, 0xd, 0, 0, IWN_RFLAG_MCS }, 1818 { 18, 0xf, 0, IWN_PLCP_INVALID, 0 }, 1819 { 24, 0x5, 0, 1, IWN_RFLAG_MCS }, 1820 { 36, 0x7, 0, 2, IWN_RFLAG_MCS, }, 1821 { 48, 0x9, 0, 3, IWN_RFLAG_MCS, }, 1822 { 72, 0xb, 0, 4, IWN_RFLAG_MCS, }, 1823 { 96, 0x1, 0, 5, IWN_RFLAG_MCS, }, 1824 { 108, 0x3, 0, 6, IWN_RFLAG_MCS, }, 1825 { 128, IWN_PLCP_INVALID, 0, 7, IWN_RFLAG_MCS, } 1826 }; 1827 1828 /* Convert an MCS index into an iwn_rates[] index. */ 1829 const int iwn_mcs2ridx[] = { 4, 6, 7, 8, 9, 10, 11, 12 }; 1830 1831 #define IWN4965_MAX_PWR_INDEX 107 1832 1833 /* 1834 * RF Tx gain values from highest to lowest power (values obtained from 1835 * the reference driver.) 1836 */ 1837 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1838 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1839 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1840 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1841 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1842 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1843 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1844 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1845 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1846 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1847 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1848 }; 1849 1850 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1851 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1852 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1853 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1854 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1855 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1856 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1857 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1858 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1859 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1860 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1861 }; 1862 1863 /* 1864 * DSP pre-DAC gain values from highest to lowest power (values obtained 1865 * from the reference driver.) 1866 */ 1867 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1868 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1869 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1870 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1871 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1872 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1873 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1874 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1875 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1876 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1877 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1878 }; 1879 1880 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1881 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1882 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1883 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1884 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1885 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1886 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1887 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1888 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1889 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1890 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1891 }; 1892 1893 /* 1894 * Power saving settings (values obtained from the reference driver.) 1895 */ 1896 #define IWN_NDTIMRANGES 3 1897 #define IWN_NPOWERLEVELS 6 1898 static const struct iwn_pmgt { 1899 uint32_t rxtimeout; 1900 uint32_t txtimeout; 1901 uint32_t intval[5]; 1902 int skip_dtim; 1903 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1904 /* DTIM <= 2 */ 1905 { 1906 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1907 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1908 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1909 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1910 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1911 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1912 }, 1913 /* 3 <= DTIM <= 10 */ 1914 { 1915 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1916 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1917 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1918 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1919 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1920 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1921 }, 1922 /* DTIM >= 11 */ 1923 { 1924 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1925 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1926 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1927 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1928 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1929 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1930 } 1931 }; 1932 1933 struct iwn_sensitivity_limits { 1934 uint32_t min_ofdm_x1; 1935 uint32_t max_ofdm_x1; 1936 uint32_t min_ofdm_mrc_x1; 1937 uint32_t max_ofdm_mrc_x1; 1938 uint32_t min_ofdm_x4; 1939 uint32_t max_ofdm_x4; 1940 uint32_t min_ofdm_mrc_x4; 1941 uint32_t max_ofdm_mrc_x4; 1942 uint32_t min_cck_x4; 1943 uint32_t max_cck_x4; 1944 uint32_t min_cck_mrc_x4; 1945 uint32_t max_cck_mrc_x4; 1946 uint32_t min_energy_cck; 1947 uint32_t energy_cck; 1948 uint32_t energy_ofdm; 1949 }; 1950 1951 /* 1952 * RX sensitivity limits (values obtained from the reference driver.) 1953 */ 1954 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1955 105, 140, 1956 220, 270, 1957 85, 120, 1958 170, 210, 1959 125, 200, 1960 200, 400, 1961 97, 1962 100, 1963 100 1964 }; 1965 1966 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1967 120, 120, /* min = max for performance bug in DSP. */ 1968 240, 240, /* min = max for performance bug in DSP. */ 1969 90, 120, 1970 170, 210, 1971 125, 200, 1972 170, 400, 1973 95, 1974 95, 1975 95 1976 }; 1977 1978 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1979 105, 105, /* min = max for performance bug in DSP. */ 1980 220, 220, /* min = max for performance bug in DSP. */ 1981 90, 120, 1982 170, 210, 1983 125, 200, 1984 170, 400, 1985 95, 1986 95, 1987 95 1988 }; 1989 1990 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1991 120, 155, 1992 240, 290, 1993 90, 120, 1994 170, 210, 1995 125, 200, 1996 170, 400, 1997 95, 1998 95, 1999 95 2000 }; 2001 2002 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 2003 105, 110, 2004 192, 232, 2005 80, 145, 2006 128, 232, 2007 125, 175, 2008 160, 310, 2009 97, 2010 97, 2011 100 2012 }; 2013 2014 static const struct iwn_sensitivity_limits iwn2000_sensitivity_limits = { 2015 105, 110, 2016 192, 232, 2017 80, 145, 2018 128, 232, 2019 125, 175, 2020 160, 310, 2021 97, 2022 97, 2023 100 2024 }; 2025 2026 /* Map TID to TX scheduler's FIFO. */ 2027 #define IWN_NUM_AMPDU_TID 8 2028 #define IWN_NONQOS_TID IWN_NUM_AMPDU_TID 2029 #define IWN_TX_FIFO_BK 0 2030 #define IWN_TX_FIFO_BE 1 2031 #define IWN_TX_FIFO_VI 2 2032 #define IWN_TX_FIFO_VO 3 2033 static const uint8_t iwn_tid2fifo[IWN_NUM_AMPDU_TID] = { 2034 IWN_TX_FIFO_VO, IWN_TX_FIFO_VI, IWN_TX_FIFO_BE, IWN_TX_FIFO_BK, 2035 IWN_TX_FIFO_VO, IWN_TX_FIFO_VI, IWN_TX_FIFO_BE, IWN_TX_FIFO_BK 2036 }; 2037 2038 /* WiFi/WiMAX coexist event priority table for 6050. */ 2039 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 2040 { 0x04, 0x03, 0x00, 0x00 }, 2041 { 0x04, 0x03, 0x00, 0x03 }, 2042 { 0x04, 0x03, 0x00, 0x03 }, 2043 { 0x04, 0x03, 0x00, 0x03 }, 2044 { 0x04, 0x03, 0x00, 0x00 }, 2045 { 0x04, 0x03, 0x00, 0x07 }, 2046 { 0x04, 0x03, 0x00, 0x00 }, 2047 { 0x04, 0x03, 0x00, 0x03 }, 2048 { 0x04, 0x03, 0x00, 0x03 }, 2049 { 0x04, 0x03, 0x00, 0x00 }, 2050 { 0x06, 0x03, 0x00, 0x07 }, 2051 { 0x04, 0x03, 0x00, 0x00 }, 2052 { 0x06, 0x06, 0x00, 0x03 }, 2053 { 0x04, 0x03, 0x00, 0x07 }, 2054 { 0x04, 0x03, 0x00, 0x00 }, 2055 { 0x04, 0x03, 0x00, 0x00 } 2056 }; 2057 2058 /* Firmware errors. */ 2059 static const char * const iwn_fw_errmsg[] = { 2060 "OK", 2061 "FAIL", 2062 "BAD_PARAM", 2063 "BAD_CHECKSUM", 2064 "NMI_INTERRUPT_WDG", 2065 "SYSASSERT", 2066 "FATAL_ERROR", 2067 "BAD_COMMAND", 2068 "HW_ERROR_TUNE_LOCK", 2069 "HW_ERROR_TEMPERATURE", 2070 "ILLEGAL_CHAN_FREQ", 2071 "VCC_NOT_STABLE", 2072 "FH_ERROR", 2073 "NMI_INTERRUPT_HOST", 2074 "NMI_INTERRUPT_ACTION_PT", 2075 "NMI_INTERRUPT_UNKNOWN", 2076 "UCODE_VERSION_MISMATCH", 2077 "HW_ERROR_ABS_LOCK", 2078 "HW_ERROR_CAL_LOCK_FAIL", 2079 "NMI_INTERRUPT_INST_ACTION_PT", 2080 "NMI_INTERRUPT_DATA_ACTION_PT", 2081 "NMI_TRM_HW_ER", 2082 "NMI_INTERRUPT_TRM", 2083 "NMI_INTERRUPT_BREAKPOINT", 2084 "DEBUG_0", 2085 "DEBUG_1", 2086 "DEBUG_2", 2087 "DEBUG_3", 2088 "ADVANCED_SYSASSERT" 2089 }; 2090 2091 /* Find least significant bit that is set. */ 2092 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 2093 2094 #define IWN_READ(sc, reg) \ 2095 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 2096 2097 #define IWN_WRITE(sc, reg, val) \ 2098 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2099 2100 #define IWN_WRITE_1(sc, reg, val) \ 2101 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2102 2103 #define IWN_SETBITS(sc, reg, mask) \ 2104 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 2105 2106 #define IWN_CLRBITS(sc, reg, mask) \ 2107 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 2108 2109 #define IWN_BARRIER_WRITE(sc) \ 2110 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2111 BUS_SPACE_BARRIER_WRITE) 2112 2113 #define IWN_BARRIER_READ_WRITE(sc) \ 2114 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2115 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 2116