xref: /dragonfly/sys/dev/netif/iwn/if_iwnreg.h (revision 977fc0db)
1 /*	$FreeBSD$	*/
2 /*	$OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $	*/
3 
4 /*-
5  * Copyright (c) 2007, 2008
6  *	Damien Bergamini <damien.bergamini@free.fr>
7  *
8  * Permission to use, copy, modify, and distribute this software for any
9  * purpose with or without fee is hereby granted, provided that the above
10  * copyright notice and this permission notice appear in all copies.
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19  */
20 #ifndef	__IF_IWNREG_H__
21 #define	__IF_IWNREG_H__
22 
23 #define	IWN_CT_KILL_THRESHOLD		114	/* in Celsius */
24 #define	IWN_CT_KILL_EXIT_THRESHOLD	95	/* in Celsius */
25 
26 #define IWN_TX_RING_COUNT	256
27 #define IWN_TX_RING_LOMARK	192
28 #define IWN_TX_RING_HIMARK	224
29 #define IWN_RX_RING_COUNT_LOG	6
30 #define IWN_RX_RING_COUNT	(1 << IWN_RX_RING_COUNT_LOG)
31 
32 #define IWN4965_NTXQUEUES	16
33 #define IWN5000_NTXQUEUES	20
34 
35 #define IWN4965_FIRSTAGGQUEUE	7
36 #define IWN5000_FIRSTAGGQUEUE	10
37 
38 #define IWN4965_NDMACHNLS	7
39 #define IWN5000_NDMACHNLS	8
40 
41 #define IWN_SRVC_DMACHNL	9
42 
43 #define IWN_ICT_SIZE		4096
44 #define IWN_ICT_COUNT		(IWN_ICT_SIZE / sizeof (uint32_t))
45 
46 /* For cards with PAN command, default is IWN_CMD_QUEUE_NUM */
47 #define	IWN_CMD_QUEUE_NUM		4
48 #define	IWN_PAN_CMD_QUEUE		9
49 
50 /* Maximum number of DMA segments for TX. */
51 #define IWN_MAX_SCATTER	20
52 
53 /* RX buffers must be large enough to hold a full 4K A-MPDU. */
54 #define IWN_RBUF_SIZE	(4 * 1024)
55 
56 #if defined(__LP64__)
57 /* HW supports 36-bit DMA addresses. */
58 #define IWN_LOADDR(paddr)	((uint32_t)(paddr))
59 #define IWN_HIADDR(paddr)	(((paddr) >> 32) & 0xf)
60 #else
61 #define IWN_LOADDR(paddr)	(paddr)
62 #define IWN_HIADDR(paddr)	(0)
63 #endif
64 
65 /*
66  * Control and status registers.
67  */
68 #define IWN_HW_IF_CONFIG	0x000
69 #define IWN_INT_COALESCING	0x004
70 #define IWN_INT_PERIODIC	0x005	/* use IWN_WRITE_1 */
71 #define IWN_INT			0x008
72 #define IWN_INT_MASK		0x00c
73 #define IWN_FH_INT		0x010
74 #define IWN_GPIO_IN		0x018	/* read external chip pins */
75 #define IWN_RESET		0x020
76 #define IWN_GP_CNTRL		0x024
77 #define IWN_HW_REV		0x028
78 #define IWN_EEPROM		0x02c
79 #define IWN_EEPROM_GP		0x030
80 #define IWN_OTP_GP		0x034
81 #define IWN_GIO			0x03c
82 #define IWN_GP_UCODE		0x048
83 #define IWN_GP_DRIVER		0x050
84 #define IWN_UCODE_GP1		0x054
85 #define IWN_UCODE_GP1_SET	0x058
86 #define IWN_UCODE_GP1_CLR	0x05c
87 #define IWN_UCODE_GP2		0x060
88 #define IWN_LED			0x094
89 #define IWN_DRAM_INT_TBL	0x0a0
90 #define IWN_SHADOW_REG_CTRL	0x0a8
91 #define IWN_GIO_CHICKEN		0x100
92 #define IWN_ANA_PLL		0x20c
93 #define IWN_HW_REV_WA		0x22c
94 #define IWN_DBG_HPET_MEM	0x240
95 #define IWN_DBG_LINK_PWR_MGMT	0x250
96 /* Need nic_lock for use above */
97 #define IWN_MEM_RADDR		0x40c
98 #define IWN_MEM_WADDR		0x410
99 #define IWN_MEM_WDATA		0x418
100 #define IWN_MEM_RDATA		0x41c
101 #define	IWN_TARG_MBX_C		0x430
102 #define IWN_PRPH_WADDR  	0x444
103 #define IWN_PRPH_RADDR   	0x448
104 #define IWN_PRPH_WDATA  	0x44c
105 #define IWN_PRPH_RDATA   	0x450
106 #define IWN_HBUS_TARG_WRPTR	0x460
107 
108 /*
109  * Flow-Handler registers.
110  */
111 #define IWN_FH_TFBD_CTRL0(qid)		(0x1900 + (qid) * 8)
112 #define IWN_FH_TFBD_CTRL1(qid)		(0x1904 + (qid) * 8)
113 #define IWN_FH_KW_ADDR			0x197c
114 #define IWN_FH_SRAM_ADDR(qid)		(0x19a4 + (qid) * 4)
115 #define IWN_FH_CBBC_QUEUE(qid)		(0x19d0 + (qid) * 4)
116 #define IWN_FH_STATUS_WPTR		0x1bc0
117 #define IWN_FH_RX_BASE			0x1bc4
118 #define IWN_FH_RX_WPTR			0x1bc8
119 #define IWN_FH_RX_CONFIG		0x1c00
120 #define IWN_FH_RX_STATUS		0x1c44
121 #define IWN_FH_TX_CONFIG(qid)		(0x1d00 + (qid) * 32)
122 #define IWN_FH_TXBUF_STATUS(qid)	(0x1d08 + (qid) * 32)
123 #define IWN_FH_TX_CHICKEN		0x1e98
124 #define IWN_FH_TX_STATUS		0x1eb0
125 
126 /*
127  * TX scheduler registers.
128  */
129 #define IWN_SCHED_BASE			0xa02c00
130 #define IWN_SCHED_SRAM_ADDR		(IWN_SCHED_BASE + 0x000)
131 #define IWN5000_SCHED_DRAM_ADDR		(IWN_SCHED_BASE + 0x008)
132 #define IWN4965_SCHED_DRAM_ADDR		(IWN_SCHED_BASE + 0x010)
133 #define IWN5000_SCHED_TXFACT		(IWN_SCHED_BASE + 0x010)
134 #define IWN4965_SCHED_TXFACT		(IWN_SCHED_BASE + 0x01c)
135 #define IWN4965_SCHED_QUEUE_RDPTR(qid)	(IWN_SCHED_BASE + 0x064 + (qid) * 4)
136 #define IWN5000_SCHED_QUEUE_RDPTR(qid)	(IWN_SCHED_BASE + 0x068 + (qid) * 4)
137 #define IWN4965_SCHED_QCHAIN_SEL	(IWN_SCHED_BASE + 0x0d0)
138 #define IWN4965_SCHED_INTR_MASK		(IWN_SCHED_BASE + 0x0e4)
139 #define IWN5000_SCHED_QCHAIN_SEL	(IWN_SCHED_BASE + 0x0e8)
140 #define IWN4965_SCHED_QUEUE_STATUS(qid)	(IWN_SCHED_BASE + 0x104 + (qid) * 4)
141 #define IWN5000_SCHED_INTR_MASK		(IWN_SCHED_BASE + 0x108)
142 #define IWN5000_SCHED_QUEUE_STATUS(qid)	(IWN_SCHED_BASE + 0x10c + (qid) * 4)
143 #define IWN5000_SCHED_AGGR_SEL		(IWN_SCHED_BASE + 0x248)
144 
145 /*
146  * Offsets in TX scheduler's SRAM.
147  */
148 #define IWN4965_SCHED_CTX_OFF		0x380
149 #define IWN4965_SCHED_CTX_LEN		416
150 #define IWN4965_SCHED_QUEUE_OFFSET(qid)	(0x380 + (qid) * 8)
151 #define IWN4965_SCHED_TRANS_TBL(qid)	(0x500 + (qid) * 2)
152 #define IWN5000_SCHED_CTX_OFF		0x600
153 #define IWN5000_SCHED_CTX_LEN		520
154 #define IWN5000_SCHED_QUEUE_OFFSET(qid)	(0x600 + (qid) * 8)
155 #define IWN5000_SCHED_TRANS_TBL(qid)	(0x7e0 + (qid) * 2)
156 
157 /*
158  * NIC internal memory offsets.
159  */
160 #define IWN_APMG_CLK_CTRL	0x3000
161 #define IWN_APMG_CLK_EN		0x3004
162 #define IWN_APMG_CLK_DIS	0x3008
163 #define IWN_APMG_PS		0x300c
164 #define IWN_APMG_DIGITAL_SVR	0x3058
165 #define IWN_APMG_ANALOG_SVR	0x306c
166 #define IWN_APMG_PCI_STT	0x3010
167 #define IWN_BSM_WR_CTRL		0x3400
168 #define IWN_BSM_WR_MEM_SRC	0x3404
169 #define IWN_BSM_WR_MEM_DST	0x3408
170 #define IWN_BSM_WR_DWCOUNT	0x340c
171 #define IWN_BSM_DRAM_TEXT_ADDR	0x3490
172 #define IWN_BSM_DRAM_TEXT_SIZE	0x3494
173 #define IWN_BSM_DRAM_DATA_ADDR	0x3498
174 #define IWN_BSM_DRAM_DATA_SIZE	0x349c
175 #define IWN_BSM_SRAM_BASE	0x3800
176 
177 /* Possible flags for register IWN_HW_IF_CONFIG. */
178 #define IWN_HW_IF_CONFIG_4965_R		(1 <<  4)
179 #define IWN_HW_IF_CONFIG_MAC_SI		(1 <<  8)
180 #define IWN_HW_IF_CONFIG_RADIO_SI	(1 <<  9)
181 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED	(1 << 21)
182 #define IWN_HW_IF_CONFIG_NIC_READY	(1 << 22)
183 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A	(1 << 23)
184 #define IWN_HW_IF_CONFIG_PREPARE_DONE	(1 << 25)
185 #define IWN_HW_IF_CONFIG_PREPARE	(1 << 27)
186 
187 /* Possible values for register IWN_INT_PERIODIC. */
188 #define IWN_INT_PERIODIC_DIS	0x00
189 #define IWN_INT_PERIODIC_ENA	0xff
190 
191 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */
192 #define IWN_PRPH_DWORD	((sizeof (uint32_t) - 1) << 24)
193 
194 /* Possible values for IWN_BSM_WR_MEM_DST. */
195 #define IWN_FW_TEXT_BASE	0x00000000
196 #define IWN_FW_DATA_BASE	0x00800000
197 
198 /* Possible flags for register IWN_RESET. */
199 #define IWN_RESET_NEVO			(1 << 0)
200 #define IWN_RESET_SW			(1 << 7)
201 #define IWN_RESET_MASTER_DISABLED	(1 << 8)
202 #define IWN_RESET_STOP_MASTER		(1 << 9)
203 #define IWN_RESET_LINK_PWR_MGMT_DIS	(1U << 31)
204 
205 /* Possible flags for register IWN_GP_CNTRL. */
206 #define IWN_GP_CNTRL_MAC_ACCESS_ENA	(1 << 0)
207 #define IWN_GP_CNTRL_MAC_CLOCK_READY	(1 << 0)
208 #define IWN_GP_CNTRL_INIT_DONE		(1 << 2)
209 #define IWN_GP_CNTRL_MAC_ACCESS_REQ	(1 << 3)
210 #define IWN_GP_CNTRL_SLEEP		(1 << 4)
211 #define IWN_GP_CNTRL_RFKILL		(1 << 27)
212 
213 /* Possible flags for register IWN_GIO_CHICKEN. */
214 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX	(1 << 23)
215 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER	(1 << 29)
216 
217 /* Possible flags for register IWN_GIO. */
218 #define IWN_GIO_L0S_ENA		(1 << 1)
219 
220 /* Possible flags for register IWN_GP_DRIVER. */
221 #define IWN_GP_DRIVER_RADIO_3X3_HYB	(0 << 0)
222 #define IWN_GP_DRIVER_RADIO_2X2_HYB	(1 << 0)
223 #define IWN_GP_DRIVER_RADIO_2X2_IPA	(2 << 0)
224 #define IWN_GP_DRIVER_CALIB_VER6	(1 << 2)
225 #define IWN_GP_DRIVER_6050_1X2		(1 << 3)
226 #define	IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT	(1 << 7)
227 #define	IWN_GP_DRIVER_NONE		0
228 
229 /* Possible flags for register IWN_UCODE_GP1_CLR. */
230 #define IWN_UCODE_GP1_RFKILL		(1 << 1)
231 #define IWN_UCODE_GP1_CMD_BLOCKED	(1 << 2)
232 #define IWN_UCODE_GP1_CTEMP_STOP_RF	(1 << 3)
233 #define	IWN_UCODE_GP1_CFG_COMPLETE	(1 << 5)
234 
235 /* Possible flags/values for register IWN_LED. */
236 #define IWN_LED_BSM_CTRL	(1 << 5)
237 #define IWN_LED_OFF		0x00000038
238 #define IWN_LED_ON		0x00000078
239 
240 #define	IWN_MAX_BLINK_TBL	10
241 #define	IWN_LED_STATIC_ON	0
242 #define	IWN_LED_STATIC_OFF	1
243 #define	IWN_LED_SLOW_BLINK	2
244 #define	IWN_LED_INT_BLINK	3
245 #define	IWN_LED_UNIT		0x1388	/* 5 ms */
246 
247 static const struct {
248 	uint16_t	tpt;	/* Mb/s */
249 	uint8_t		on_time;
250 	uint8_t		off_time;
251 } blink_tbl[] =
252 {
253 	{300, 5, 5},
254 	{200, 8, 8},
255 	{100, 11, 11},
256 	{70, 13, 13},
257 	{50, 15, 15},
258 	{20, 17, 17},
259 	{10, 19, 19},
260 	{5, 22, 22},
261 	{1, 26, 26},
262 	{0, 33, 33},
263 	/* SOLID_ON */
264 };
265 
266 /* Possible flags for register IWN_DRAM_INT_TBL. */
267 #define IWN_DRAM_INT_TBL_WRAP_CHECK	(1 << 27)
268 #define IWN_DRAM_INT_TBL_ENABLE		(1U << 31)
269 
270 /* Possible values for register IWN_ANA_PLL. */
271 #define IWN_ANA_PLL_INIT	0x00880300
272 
273 /* Possible flags for register IWN_FH_RX_STATUS. */
274 #define	IWN_FH_RX_STATUS_IDLE	(1 << 24)
275 
276 /* Possible flags for register IWN_BSM_WR_CTRL. */
277 #define IWN_BSM_WR_CTRL_START_EN	(1 << 30)
278 #define IWN_BSM_WR_CTRL_START		(1U << 31)
279 
280 /* Possible flags for register IWN_INT. */
281 #define IWN_INT_ALIVE		(1 <<  0)
282 #define IWN_INT_WAKEUP		(1 <<  1)
283 #define IWN_INT_SW_RX		(1 <<  3)
284 #define IWN_INT_CT_REACHED	(1 <<  6)
285 #define IWN_INT_RF_TOGGLED	(1 <<  7)
286 #define IWN_INT_SW_ERR		(1 << 25)
287 #define IWN_INT_SCHED		(1 << 26)
288 #define IWN_INT_FH_TX		(1 << 27)
289 #define IWN_INT_RX_PERIODIC	(1 << 28)
290 #define IWN_INT_HW_ERR		(1 << 29)
291 #define IWN_INT_FH_RX		(1U << 31)
292 
293 /* Shortcut. */
294 #define IWN_INT_MASK_DEF						\
295 	(IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX |		\
296 	 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP |		\
297 	 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED)
298 
299 /* Possible flags for register IWN_FH_INT. */
300 #define IWN_FH_INT_TX_CHNL(x)	(1 << (x))
301 #define IWN_FH_INT_RX_CHNL(x)	(1 << ((x) + 16))
302 #define IWN_FH_INT_HI_PRIOR	(1 << 30)
303 /* Shortcuts for the above. */
304 #define IWN_FH_INT_TX							\
305 	(IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1))
306 #define IWN_FH_INT_RX							\
307 	(IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR)
308 
309 /* Possible flags/values for register IWN_FH_TX_CONFIG. */
310 #define IWN_FH_TX_CONFIG_DMA_PAUSE		0
311 #define IWN_FH_TX_CONFIG_DMA_ENA		(1U << 31)
312 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD	(1 << 20)
313 
314 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */
315 #define IWN_FH_TXBUF_STATUS_TBNUM(x)	((x) << 20)
316 #define IWN_FH_TXBUF_STATUS_TBIDX(x)	((x) << 12)
317 #define IWN_FH_TXBUF_STATUS_TFBD_VALID	3
318 
319 /* Possible flags for register IWN_FH_TX_CHICKEN. */
320 #define IWN_FH_TX_CHICKEN_SCHED_RETRY	(1 << 1)
321 
322 /* Possible flags for register IWN_FH_TX_STATUS. */
323 #define IWN_FH_TX_STATUS_IDLE(chnl)	(1 << ((chnl) + 16))
324 
325 /* Possible flags for register IWN_FH_RX_CONFIG. */
326 #define IWN_FH_RX_CONFIG_ENA		(1U << 31)
327 #define IWN_FH_RX_CONFIG_NRBD(x)	((x) << 20)
328 #define IWN_FH_RX_CONFIG_RB_SIZE_8K	(1 << 16)
329 #define IWN_FH_RX_CONFIG_SINGLE_FRAME	(1 << 15)
330 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST	(1 << 12)
331 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x)	((x) << 4)
332 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY	(1 <<  2)
333 
334 /* Possible flags for register IWN_FH_TX_CONFIG. */
335 #define IWN_FH_TX_CONFIG_DMA_ENA	(1U << 31)
336 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA	(1 <<  3)
337 
338 /* Possible flags for register IWN_EEPROM. */
339 #define IWN_EEPROM_READ_VALID	(1 << 0)
340 #define IWN_EEPROM_CMD		(1 << 1)
341 
342 /* Possible flags for register IWN_EEPROM_GP. */
343 #define IWN_EEPROM_GP_IF_OWNER	0x00000180
344 
345 /* Possible flags for register IWN_OTP_GP. */
346 #define IWN_OTP_GP_DEV_SEL_OTP		(1 << 16)
347 #define IWN_OTP_GP_RELATIVE_ACCESS	(1 << 17)
348 #define IWN_OTP_GP_ECC_CORR_STTS	(1 << 20)
349 #define IWN_OTP_GP_ECC_UNCORR_STTS	(1 << 21)
350 
351 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */
352 #define IWN4965_TXQ_STATUS_ACTIVE	0x0007fc01
353 #define IWN4965_TXQ_STATUS_INACTIVE	0x0007fc00
354 #define IWN4965_TXQ_STATUS_AGGR_ENA	(1 << 5 | 1 << 8)
355 #define IWN4965_TXQ_STATUS_CHGACT	(1 << 10)
356 #define IWN5000_TXQ_STATUS_ACTIVE	0x00ff0018
357 #define IWN5000_TXQ_STATUS_INACTIVE	0x00ff0010
358 #define IWN5000_TXQ_STATUS_CHGACT	(1 << 19)
359 
360 /* Possible flags for registers IWN_APMG_CLK_*. */
361 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT	(1 <<  9)
362 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT	(1 << 11)
363 
364 /* Possible flags for register IWN_APMG_PS. */
365 #define IWN_APMG_PS_EARLY_PWROFF_DIS	(1 << 22)
366 #define IWN_APMG_PS_PWR_SRC(x)		((x) << 24)
367 #define IWN_APMG_PS_PWR_SRC_VMAIN	0
368 #define IWN_APMG_PS_PWR_SRC_VAUX	2
369 #define IWN_APMG_PS_PWR_SRC_MASK	IWN_APMG_PS_PWR_SRC(3)
370 #define IWN_APMG_PS_RESET_REQ		(1 << 26)
371 
372 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */
373 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x)		(((x) & 0xf) << 5)
374 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK	\
375 	IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf)
376 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32	\
377 	IWN_APMG_DIGITAL_SVR_VOLTAGE(3)
378 
379 /* Possible flags for IWN_APMG_PCI_STT. */
380 #define IWN_APMG_PCI_STT_L1A_DIS	(1 << 11)
381 
382 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */
383 #define IWN_FW_UPDATED	(1U << 31)
384 
385 #define IWN_SCHED_WINSZ		64
386 #define IWN_SCHED_LIMIT		64
387 #define IWN4965_SCHED_COUNT	512
388 #define IWN5000_SCHED_COUNT	(IWN_TX_RING_COUNT + IWN_SCHED_WINSZ)
389 #define IWN4965_SCHEDSZ		(IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2)
390 #define IWN5000_SCHEDSZ		(IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2)
391 
392 struct iwn_tx_desc {
393 	uint8_t		reserved1[3];
394 	uint8_t		nsegs;
395 	struct {
396 		uint32_t	addr;
397 		uint16_t	len;
398 	} __packed	segs[IWN_MAX_SCATTER];
399 	/* Pad to 128 bytes. */
400 	uint32_t	reserved2;
401 } __packed;
402 
403 struct iwn_rx_status {
404 	uint16_t	closed_count;
405 	uint16_t	closed_rx_count;
406 	uint16_t	finished_count;
407 	uint16_t	finished_rx_count;
408 	uint32_t	reserved[2];
409 } __packed;
410 
411 struct iwn_rx_desc {
412 	/*
413 	 * The first 4 bytes of the RX frame header contain both the RX frame
414 	 * size and some flags.
415 	 * Bit fields:
416 	 * 31:    flag flush RB request
417 	 * 30:    flag ignore TC (terminal counter) request
418 	 * 29:    flag fast IRQ request
419 	 * 28-14: Reserved
420 	 * 13-00: RX frame size
421 	 */
422 	uint32_t	len;
423 	uint8_t		type;
424 #define IWN_UC_READY			  1
425 #define IWN_ADD_NODE_DONE		 24
426 #define IWN_TX_DONE			 28
427 #define	IWN_REPLY_LED_CMD		72
428 #define IWN5000_CALIBRATION_RESULT	102
429 #define IWN5000_CALIBRATION_DONE	103
430 #define IWN_START_SCAN			130
431 #define	IWN_NOTIF_SCAN_RESULT		131
432 #define IWN_STOP_SCAN			132
433 #define IWN_RX_STATISTICS		156
434 #define IWN_BEACON_STATISTICS		157
435 #define IWN_STATE_CHANGED		161
436 #define IWN_BEACON_MISSED		162
437 #define IWN_RX_PHY			192
438 #define IWN_MPDU_RX_DONE		193
439 #define IWN_RX_DONE			195
440 #define IWN_RX_COMPRESSED_BA		197
441 
442 	uint8_t		flags;	/* 0:5 reserved, 6 abort, 7 internal */
443 	uint8_t		idx;	/* position within TX queue */
444 	uint8_t		qid;
445 	/* 0:4 TX queue id - 5:6 reserved - 7 unsolicited RX
446 	 * or uCode-originated notification
447 	 */
448 } __packed;
449 
450 #define	IWN_RX_DESC_QID_MSK		0x1F
451 #define	IWN_UNSOLICITED_RX_NOTIF	0x80
452 
453 /* CARD_STATE_NOTIFICATION */
454 #define	IWN_STATE_CHANGE_HW_CARD_DISABLED		0x01
455 #define	IWN_STATE_CHANGE_SW_CARD_DISABLED		0x02
456 #define	IWN_STATE_CHANGE_CT_CARD_DISABLED		0x04
457 #define	IWN_STATE_CHANGE_RXON_CARD_DISABLED		0x10
458 
459 /* Possible RX status flags. */
460 #define IWN_RX_NO_CRC_ERR	(1 <<  0)
461 #define IWN_RX_NO_OVFL_ERR	(1 <<  1)
462 /* Shortcut for the above. */
463 #define IWN_RX_NOERROR	(IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR)
464 #define IWN_RX_MPDU_MIC_OK	(1 <<  6)
465 #define IWN_RX_CIPHER_MASK	(7 <<  8)
466 #define IWN_RX_CIPHER_CCMP	(2 <<  8)
467 #define IWN_RX_MPDU_DEC		(1 << 11)
468 #define IWN_RX_DECRYPT_MASK	(3 << 11)
469 #define IWN_RX_DECRYPT_OK	(3 << 11)
470 
471 struct iwn_tx_cmd {
472 	uint8_t	code;
473 #define IWN_CMD_RXON			 16
474 #define IWN_CMD_RXON_ASSOC		 17
475 #define IWN_CMD_EDCA_PARAMS		 19
476 #define IWN_CMD_TIMING			 20
477 #define IWN_CMD_ADD_NODE		 24
478 #define IWN_CMD_TX_DATA			 28
479 #define IWN_CMD_LINK_QUALITY		 78
480 #define IWN_CMD_SET_LED			 72
481 #define IWN5000_CMD_WIMAX_COEX		 90
482 #define	IWN_TEMP_NOTIFICATION		98
483 #define IWN5000_CMD_CALIB_CONFIG	101
484 #define IWN5000_CMD_CALIB_RESULT	102
485 #define IWN5000_CMD_CALIB_COMPLETE	103
486 #define IWN_CMD_SET_POWER_MODE		119
487 #define IWN_CMD_SCAN			128
488 #define IWN_CMD_SCAN_RESULTS		131
489 #define IWN_CMD_TXPOWER_DBM		149
490 #define IWN_CMD_TXPOWER			151
491 #define IWN5000_CMD_TX_ANT_CONFIG	152
492 #define IWN_CMD_TXPOWER_DBM_V1		152
493 #define IWN_CMD_BT_COEX			155
494 #define IWN_CMD_GET_STATISTICS		156
495 #define IWN_CMD_SET_CRITICAL_TEMP	164
496 #define IWN_CMD_SET_SENSITIVITY		168
497 #define IWN_CMD_PHY_CALIB		176
498 #define IWN_CMD_BT_COEX_PRIOTABLE	204
499 #define IWN_CMD_BT_COEX_PROT		205
500 #define	IWN_CMD_BT_COEX_NOTIF		206
501 /* PAN commands */
502 #define	IWN_CMD_WIPAN_PARAMS			0xb2
503 #define	IWN_CMD_WIPAN_RXON			0xb3
504 #define	IWN_CMD_WIPAN_RXON_TIMING		0xb4
505 #define	IWN_CMD_WIPAN_RXON_ASSOC		0xb6
506 #define	IWN_CMD_WIPAN_QOS_PARAM			0xb7
507 #define	IWN_CMD_WIPAN_WEPKEY			0xb8
508 #define	IWN_CMD_WIPAN_P2P_CHANNEL_SWITCH	0xb9
509 #define	IWN_CMD_WIPAN_NOA_NOTIFICATION		0xbc
510 #define	IWN_CMD_WIPAN_DEACTIVATION_COMPLETE	0xbd
511 
512 	uint8_t	flags;
513 	uint8_t	idx;
514 	uint8_t	qid;
515 	uint8_t	data[136];
516 } __packed;
517 
518 /*
519  * Structure for IWN_CMD_GET_STATISTICS = (0x9c) 156
520  * all devices identical.
521  *
522  * This command triggers an immediate response containing uCode statistics.
523  * The response is in the same format as IWN_BEACON_STATISTICS (0x9d) 157.
524  *
525  * If the CLEAR_STATS configuration flag is set, uCode will clear its
526  * internal copy of the statistics (counters) after issuing the response.
527  * This flag does not affect IWN_BEACON_STATISTICS after beacons (see below).
528  *
529  * If the DISABLE_NOTIF configuration flag is set, uCode will not issue
530  * IWN_BEACON_STATISTICS after received beacons.  This flag
531  * does not affect the response to the IWN_CMD_GET_STATISTICS 0x9c itself.
532  */
533 struct iwn_statistics_cmd {
534 	uint32_t	configuration_flags;
535 #define	IWN_STATS_CONF_CLEAR_STATS		htole32(0x1)
536 #define	IWN_STATS_CONF_DISABLE_NOTIF	htole32(0x2)
537 } __packed;
538 
539 /* Antenna flags, used in various commands. */
540 #define IWN_ANT_A	(1 << 0)
541 #define IWN_ANT_B	(1 << 1)
542 #define IWN_ANT_C	(1 << 2)
543 /* Shortcuts. */
544 #define IWN_ANT_AB	(IWN_ANT_A | IWN_ANT_B)
545 #define IWN_ANT_BC	(IWN_ANT_B | IWN_ANT_C)
546 #define	IWN_ANT_AC	(IWN_ANT_A | IWN_ANT_C)
547 #define IWN_ANT_ABC	(IWN_ANT_A | IWN_ANT_B | IWN_ANT_C)
548 
549 /* Structure for command IWN_CMD_RXON. */
550 struct iwn_rxon {
551 	uint8_t		myaddr[IEEE80211_ADDR_LEN];
552 	uint16_t	reserved1;
553 	uint8_t		bssid[IEEE80211_ADDR_LEN];
554 	uint16_t	reserved2;
555 	uint8_t		wlap[IEEE80211_ADDR_LEN];
556 	uint16_t	reserved3;
557 	uint8_t		mode;
558 #define IWN_MODE_HOSTAP		1
559 #define IWN_MODE_STA		3
560 #define IWN_MODE_IBSS		4
561 #define IWN_MODE_MONITOR	6
562 #define	IWN_MODE_2STA		8
563 #define	IWN_MODE_P2P		9
564 
565 	uint8_t		air;
566 	uint16_t	rxchain;
567 #define IWN_RXCHAIN_DRIVER_FORCE	(1 << 0)
568 #define IWN_RXCHAIN_VALID(x)		(((x) & IWN_ANT_ABC) << 1)
569 #define IWN_RXCHAIN_FORCE_SEL(x)	(((x) & IWN_ANT_ABC) << 4)
570 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x)	(((x) & IWN_ANT_ABC) << 7)
571 #define IWN_RXCHAIN_IDLE_COUNT(x)	((x) << 10)
572 #define IWN_RXCHAIN_MIMO_COUNT(x)	((x) << 12)
573 #define IWN_RXCHAIN_MIMO_FORCE		(1 << 14)
574 
575 	uint8_t		ofdm_mask;
576 	uint8_t		cck_mask;
577 	uint16_t	associd;
578 	uint32_t	flags;
579 #define IWN_RXON_24GHZ		(1 <<  0)
580 #define IWN_RXON_CCK		(1 <<  1)
581 #define IWN_RXON_AUTO		(1 <<  2)
582 #define IWN_RXON_SHSLOT		(1 <<  4)
583 #define IWN_RXON_SHPREAMBLE	(1 <<  5)
584 #define IWN_RXON_NODIVERSITY	(1 <<  7)
585 #define IWN_RXON_ANTENNA_A	(1 <<  8)
586 #define IWN_RXON_ANTENNA_B	(1 <<  9)
587 #define IWN_RXON_TSF		(1 << 15)
588 #define IWN_RXON_HT_HT40MINUS	(1 << 22)
589 
590 #define IWN_RXON_HT_PROTMODE(x)	(x << 23)
591 
592 /* 0=legacy, 1=pure40, 2=mixed */
593 #define IWN_RXON_HT_MODEPURE40	(1 << 25)
594 #define IWN_RXON_HT_MODEMIXED	(2 << 25)
595 
596 #define IWN_RXON_CTS_TO_SELF	(1 << 30)
597 
598 	uint32_t	filter;
599 #define IWN_FILTER_PROMISC	(1 << 0)
600 #define IWN_FILTER_CTL		(1 << 1)
601 #define IWN_FILTER_MULTICAST	(1 << 2)
602 #define IWN_FILTER_NODECRYPT	(1 << 3)
603 #define IWN_FILTER_BSS		(1 << 5)
604 #define IWN_FILTER_BEACON	(1 << 6)
605 
606 	uint8_t		chan;
607 	uint8_t		reserved4;
608 	uint8_t		ht_single_mask;
609 	uint8_t		ht_dual_mask;
610 	/* The following fields are for >=5000 Series only. */
611 	uint8_t		ht_triple_mask;
612 	uint8_t		reserved5;
613 	uint16_t	acquisition;
614 	uint16_t	reserved6;
615 } __packed;
616 
617 #define IWN4965_RXONSZ	(sizeof (struct iwn_rxon) - 6)
618 #define IWN5000_RXONSZ	(sizeof (struct iwn_rxon))
619 
620 /* Structure for command IWN_CMD_ASSOCIATE. */
621 struct iwn_assoc {
622 	uint32_t	flags;
623 	uint32_t	filter;
624 	uint8_t		ofdm_mask;
625 	uint8_t		cck_mask;
626 	uint16_t	reserved;
627 } __packed;
628 
629 /* Structure for command IWN_CMD_EDCA_PARAMS. */
630 struct iwn_edca_params {
631 	uint32_t	flags;
632 #define IWN_EDCA_UPDATE	(1 << 0)
633 #define IWN_EDCA_TXOP	(1 << 4)
634 
635 	struct {
636 		uint16_t	cwmin;
637 		uint16_t	cwmax;
638 		uint8_t		aifsn;
639 		uint8_t		reserved;
640 		uint16_t	txoplimit;
641 	} __packed	ac[WME_NUM_AC];
642 } __packed;
643 
644 /* Structure for command IWN_CMD_TIMING. */
645 struct iwn_cmd_timing {
646 	uint64_t	tstamp;
647 	uint16_t	bintval;
648 	uint16_t	atim;
649 	uint32_t	binitval;
650 	uint16_t	lintval;
651 	uint8_t		dtim_period;
652 	uint8_t		delta_cp_bss_tbtts;
653 } __packed;
654 
655 /* Structure for command IWN_CMD_ADD_NODE. */
656 struct iwn_node_info {
657 	uint8_t		control;
658 #define IWN_NODE_UPDATE		(1 << 0)
659 
660 	uint8_t		reserved1[3];
661 
662 	uint8_t		macaddr[IEEE80211_ADDR_LEN];
663 	uint16_t	reserved2;
664 	uint8_t		id;
665 #define IWN_ID_BSS		 0
666 #define	IWN_STA_ID		1
667 
668 #define	IWN_PAN_ID_BCAST		14
669 #define IWN5000_ID_BROADCAST	15
670 #define IWN4965_ID_BROADCAST	31
671 
672 	uint8_t		flags;
673 #define IWN_FLAG_SET_KEY		(1 << 0)
674 #define IWN_FLAG_SET_DISABLE_TID	(1 << 1)
675 #define IWN_FLAG_SET_TXRATE		(1 << 2)
676 #define IWN_FLAG_SET_ADDBA		(1 << 3)
677 #define IWN_FLAG_SET_DELBA		(1 << 4)
678 
679 	uint16_t	reserved3;
680 	uint16_t	kflags;
681 #define IWN_KFLAG_CCMP		(1 <<  1)
682 #define IWN_KFLAG_MAP		(1 <<  3)
683 #define IWN_KFLAG_KID(kid)	((kid) << 8)
684 #define IWN_KFLAG_INVALID	(1 << 11)
685 #define IWN_KFLAG_GROUP		(1 << 14)
686 
687 	uint8_t		tsc2;	/* TKIP TSC2 */
688 	uint8_t		reserved4;
689 	uint16_t	ttak[5];
690 	uint8_t		kid;
691 	uint8_t		reserved5;
692 	uint8_t		key[16];
693 	/* The following 3 fields are for 5000 Series only. */
694 	uint64_t	tsc;
695 	uint8_t		rxmic[8];
696 	uint8_t		txmic[8];
697 
698 	uint32_t	htflags;
699 #define IWN_SMPS_MIMO_PROT		(1 << 17)
700 #define IWN_AMDPU_SIZE_FACTOR(x)	((x) << 19)
701 #define IWN_NODE_HT40			(1 << 21)
702 #define IWN_SMPS_MIMO_DIS		(1 << 22)
703 #define IWN_AMDPU_DENSITY(x)		((x) << 23)
704 
705 	uint32_t	mask;
706 	uint16_t	disable_tid;
707 	uint16_t	reserved6;
708 	uint8_t		addba_tid;
709 	uint8_t		delba_tid;
710 	uint16_t	addba_ssn;
711 	uint32_t	reserved7;
712 } __packed;
713 
714 struct iwn4965_node_info {
715 	uint8_t		control;
716 	uint8_t		reserved1[3];
717 	uint8_t		macaddr[IEEE80211_ADDR_LEN];
718 	uint16_t	reserved2;
719 	uint8_t		id;
720 	uint8_t		flags;
721 	uint16_t	reserved3;
722 	uint16_t	kflags;
723 	uint8_t		tsc2;	/* TKIP TSC2 */
724 	uint8_t		reserved4;
725 	uint16_t	ttak[5];
726 	uint8_t		kid;
727 	uint8_t		reserved5;
728 	uint8_t		key[16];
729 	uint32_t	htflags;
730 	uint32_t	mask;
731 	uint16_t	disable_tid;
732 	uint16_t	reserved6;
733 	uint8_t		addba_tid;
734 	uint8_t		delba_tid;
735 	uint16_t	addba_ssn;
736 	uint32_t	reserved7;
737 } __packed;
738 
739 #define IWN_RFLAG_MCS		(1 << 8)
740 #define IWN_RFLAG_CCK		(1 << 9)
741 #define IWN_RFLAG_GREENFIELD	(1 << 10)
742 #define IWN_RFLAG_HT40		(1 << 11)
743 #define IWN_RFLAG_DUPLICATE	(1 << 12)
744 #define IWN_RFLAG_SGI		(1 << 13)
745 #define IWN_RFLAG_ANT(x)	((x) << 14)
746 
747 /* Structure for command IWN_CMD_TX_DATA. */
748 struct iwn_cmd_data {
749 	uint16_t	len;
750 	uint16_t	lnext;
751 	uint32_t	flags;
752 #define IWN_TX_NEED_PROTECTION	(1 <<  0)	/* 5000 only */
753 #define IWN_TX_NEED_RTS		(1 <<  1)
754 #define IWN_TX_NEED_CTS		(1 <<  2)
755 #define IWN_TX_NEED_ACK		(1 <<  3)
756 #define IWN_TX_LINKQ		(1 <<  4)
757 #define IWN_TX_IMM_BA		(1 <<  6)
758 #define IWN_TX_FULL_TXOP	(1 <<  7)
759 #define IWN_TX_BT_DISABLE	(1 << 12)	/* bluetooth coexistence */
760 #define IWN_TX_AUTO_SEQ		(1 << 13)
761 #define IWN_TX_MORE_FRAG	(1 << 14)
762 #define IWN_TX_INSERT_TSTAMP	(1 << 16)
763 #define IWN_TX_NEED_PADDING	(1 << 20)
764 
765 	uint32_t	scratch;
766 	uint32_t	rate;
767 
768 	uint8_t		id;
769 	uint8_t		security;
770 #define IWN_CIPHER_WEP40	1
771 #define IWN_CIPHER_CCMP		2
772 #define IWN_CIPHER_TKIP		3
773 #define IWN_CIPHER_WEP104	9
774 
775 	uint8_t		linkq;
776 	uint8_t		reserved2;
777 	uint8_t		key[16];
778 	uint16_t	fnext;
779 	uint16_t	reserved3;
780 	uint32_t	lifetime;
781 #define IWN_LIFETIME_INFINITE	0xffffffff
782 
783 	uint32_t	loaddr;
784 	uint8_t		hiaddr;
785 	uint8_t		rts_ntries;
786 	uint8_t		data_ntries;
787 	uint8_t		tid;
788 	uint16_t	timeout;
789 	uint16_t	txop;
790 } __packed;
791 
792 /* Structure for command IWN_CMD_LINK_QUALITY. */
793 #define IWN_MAX_TX_RETRIES	16
794 struct iwn_cmd_link_quality {
795 	uint8_t		id;
796 	uint8_t		reserved1;
797 	uint16_t	ctl;
798 	uint8_t		flags;
799 	uint8_t		mimo;
800 	uint8_t		antmsk_1stream;
801 	uint8_t		antmsk_2stream;
802 	uint8_t		ridx[WME_NUM_AC];
803 	uint16_t	ampdu_limit;
804 	uint8_t		ampdu_threshold;
805 	uint8_t		ampdu_max;
806 	uint32_t	reserved2;
807 	uint32_t	retry[IWN_MAX_TX_RETRIES];
808 	uint32_t	reserved3;
809 } __packed;
810 
811 /* Structure for command IWN_CMD_SET_LED. */
812 struct iwn_cmd_led {
813 	uint32_t	unit;	/* multiplier (in usecs) */
814 	uint8_t		which;
815 #define IWN_LED_ACTIVITY	1
816 #define IWN_LED_LINK		2
817 
818 	uint8_t		off;
819 	uint8_t		on;
820 	uint8_t		reserved;
821 } __packed;
822 
823 /* Structure for command IWN5000_CMD_WIMAX_COEX. */
824 struct iwn5000_wimax_coex {
825 	uint32_t	flags;
826 #define IWN_WIMAX_COEX_STA_TABLE_VALID		(1 << 0)
827 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK	(1 << 2)
828 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK		(1 << 3)
829 #define IWN_WIMAX_COEX_ENABLE			(1 << 7)
830 
831 	struct iwn5000_wimax_event {
832 		uint8_t	request;
833 		uint8_t	window;
834 		uint8_t	reserved;
835 		uint8_t	flags;
836 	} __packed	events[16];
837 } __packed;
838 
839 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */
840 struct iwn5000_calib_elem {
841 	uint32_t	enable;
842 	uint32_t	start;
843 #define	IWN5000_CALIB_DC	(1 << 1)
844 
845 	uint32_t	send;
846 	uint32_t	apply;
847 	uint32_t	reserved;
848 } __packed;
849 
850 struct iwn5000_calib_status {
851 	struct iwn5000_calib_elem	once;
852 	struct iwn5000_calib_elem	perd;
853 	uint32_t			flags;
854 } __packed;
855 
856 struct iwn5000_calib_config {
857 	struct iwn5000_calib_status	ucode;
858 	struct iwn5000_calib_status	driver;
859 	uint32_t			reserved;
860 } __packed;
861 
862 /* Structure for command IWN_CMD_SET_POWER_MODE. */
863 struct iwn_pmgt_cmd {
864 	uint16_t	flags;
865 #define IWN_PS_ALLOW_SLEEP	(1 << 0)
866 #define IWN_PS_NOTIFY		(1 << 1)
867 #define IWN_PS_SLEEP_OVER_DTIM	(1 << 2)
868 #define IWN_PS_PCI_PMGT		(1 << 3)
869 #define IWN_PS_FAST_PD		(1 << 4)
870 #define	IWN_PS_BEACON_FILTERING	(1 << 5)
871 #define	IWN_PS_SHADOW_REG	(1 << 6)
872 #define	IWN_PS_CT_KILL		(1 << 7)
873 #define	IWN_PS_BT_SCD		(1 << 8)
874 #define	IWN_PS_ADVANCED_PM	(1 << 9)
875 
876 	uint8_t		keepalive;
877 	uint8_t		debug;
878 	uint32_t	rxtimeout;
879 	uint32_t	txtimeout;
880 	uint32_t	intval[5];
881 	uint32_t	beacons;
882 } __packed;
883 
884 /* Structures for command IWN_CMD_SCAN. */
885 struct iwn_scan_essid {
886 	uint8_t	id;
887 	uint8_t	len;
888 	uint8_t	data[IEEE80211_NWID_LEN];
889 } __packed;
890 
891 struct iwn_scan_hdr {
892 	uint16_t	len;
893 	uint8_t		scan_flags;
894 	uint8_t		nchan;
895 	uint16_t	quiet_time;
896 	uint16_t	quiet_threshold;
897 	uint16_t	crc_threshold;
898 	uint16_t	rxchain;
899 	uint32_t	max_svc;	/* background scans */
900 	uint32_t	pause_svc;	/* background scans */
901 	uint32_t	flags;
902 	uint32_t	filter;
903 
904 	/* Followed by a struct iwn_cmd_data. */
905 	/* Followed by an array of 20 structs iwn_scan_essid. */
906 	/* Followed by probe request body. */
907 	/* Followed by an array of ``nchan'' structs iwn_scan_chan. */
908 } __packed;
909 
910 struct iwn_scan_chan {
911 	uint32_t	flags;
912 #define	IWN_CHAN_PASSIVE	(0 << 0)
913 #define IWN_CHAN_ACTIVE		(1 << 0)
914 #define IWN_CHAN_NPBREQS(x)	(((1 << (x)) - 1) << 1)
915 
916 	uint16_t	chan;
917 	uint8_t		rf_gain;
918 	uint8_t		dsp_gain;
919 	uint16_t	active;		/* msecs */
920 	uint16_t	passive;	/* msecs */
921 } __packed;
922 
923 #define	IWN_SCAN_CRC_TH_DISABLED	0
924 #define	IWN_SCAN_CRC_TH_DEFAULT		htole16(1)
925 #define	IWN_SCAN_CRC_TH_NEVER		htole16(0xffff)
926 
927 /* Maximum size of a scan command. */
928 #define IWN_SCAN_MAXSZ	(MCLBYTES - 4)
929 
930 /*
931  * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
932  * sending probe req.  This should be set long enough to hear probe responses
933  * from more than one AP.
934  */
935 #define	IWN_ACTIVE_DWELL_TIME_2GHZ	(30)	/* all times in msec */
936 #define	IWN_ACTIVE_DWELL_TIME_5GHZ	(20)
937 #define	IWN_ACTIVE_DWELL_FACTOR_2GHZ	(3)
938 #define	IWN_ACTIVE_DWELL_FACTOR_5GHZ	(2)
939 
940 /*
941  * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
942  * Must be set longer than active dwell time.
943  * For the most reliable scan, set > AP beacon interval (typically 100msec).
944  */
945 #define	IWN_PASSIVE_DWELL_TIME_2GHZ	(20)	/* all times in msec */
946 #define	IWN_PASSIVE_DWELL_TIME_5GHZ	(10)
947 #define	IWN_PASSIVE_DWELL_BASE		(100)
948 #define	IWN_CHANNEL_TUNE_TIME		(5)
949 
950 #define	IWN_SCAN_CHAN_TIMEOUT		2
951 #define	IWN_MAX_SCAN_CHANNEL		50
952 
953 /*
954  * If active scanning is requested but a certain channel is
955  * marked passive, we can do active scanning if we detect
956  * transmissions.
957  *
958  * There is an issue with some firmware versions that triggers
959  * a sysassert on a "good CRC threshold" of zero (== disabled),
960  * on a radar channel even though this means that we should NOT
961  * send probes.
962  *
963  * The "good CRC threshold" is the number of frames that we
964  * need to receive during our dwell time on a channel before
965  * sending out probes -- setting this to a huge value will
966  * mean we never reach it, but at the same time work around
967  * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
968  * here instead of IWL_GOOD_CRC_TH_DISABLED.
969  *
970  * This was fixed in later versions along with some other
971  * scan changes, and the threshold behaves as a flag in those
972  * versions.
973  */
974 #define	IWN_GOOD_CRC_TH_DISABLED	0
975 #define	IWN_GOOD_CRC_TH_DEFAULT		htole16(1)
976 #define	IWN_GOOD_CRC_TH_NEVER		htole16(0xffff)
977 
978 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */
979 #define IWN_RIDX_MAX	32
980 struct iwn4965_cmd_txpower {
981 	uint8_t		band;
982 	uint8_t		reserved1;
983 	uint8_t		chan;
984 	uint8_t		reserved2;
985 	struct {
986 		uint8_t	rf_gain[2];
987 		uint8_t	dsp_gain[2];
988 	} __packed	power[IWN_RIDX_MAX + 1];
989 } __packed;
990 
991 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */
992 struct iwn5000_cmd_txpower {
993 	int8_t	global_limit;	/* in half-dBm */
994 #define IWN5000_TXPOWER_AUTO		0x7f
995 #define IWN5000_TXPOWER_MAX_DBM		16
996 
997 	uint8_t	flags;
998 #define IWN5000_TXPOWER_NO_CLOSED	(1 << 6)
999 
1000 	int8_t	srv_limit;	/* in half-dBm */
1001 	uint8_t	reserved;
1002 } __packed;
1003 
1004 /* Structures for command IWN_CMD_BLUETOOTH. */
1005 struct iwn_bluetooth {
1006 	uint8_t		flags;
1007 #define IWN_BT_COEX_CHAN_ANN	(1 << 0)
1008 #define IWN_BT_COEX_BT_PRIO	(1 << 1)
1009 #define IWN_BT_COEX_2_WIRE	(1 << 2)
1010 
1011 	uint8_t		lead_time;
1012 #define IWN_BT_LEAD_TIME_DEF	30
1013 
1014 	uint8_t		max_kill;
1015 #define IWN_BT_MAX_KILL_DEF	5
1016 
1017 	uint8_t		reserved;
1018 	uint32_t	kill_ack;
1019 	uint32_t	kill_cts;
1020 } __packed;
1021 
1022 struct iwn6000_btcoex_config {
1023 	uint8_t		flags;
1024 #define	IWN_BT_FLAG_COEX6000_CHAN_INHIBITION	1
1025 #define	IWN_BT_FLAG_COEX6000_MODE_MASK		((1 << 3) | (1 << 4) | (1 << 5 ))
1026 #define	IWN_BT_FLAG_COEX6000_MODE_SHIFT			3
1027 #define	IWN_BT_FLAG_COEX6000_MODE_DISABLED		0
1028 #define	IWN_BT_FLAG_COEX6000_MODE_LEGACY_2W		1
1029 #define	IWN_BT_FLAG_COEX6000_MODE_3W			2
1030 #define	IWN_BT_FLAG_COEX6000_MODE_4W			3
1031 
1032 #define	IWN_BT_FLAG_UCODE_DEFAULT		(1 << 6)
1033 #define	IWN_BT_FLAG_SYNC_2_BT_DISABLE	(1 << 7)
1034 	uint8_t		lead_time;
1035 	uint8_t		max_kill;
1036 	uint8_t		bt3_t7_timer;
1037 	uint32_t	kill_ack;
1038 	uint32_t	kill_cts;
1039 	uint8_t		sample_time;
1040 	uint8_t		bt3_t2_timer;
1041 	uint16_t	bt4_reaction;
1042 	uint32_t	lookup_table[12];
1043 	uint16_t	bt4_decision;
1044 	uint16_t	valid;
1045 	uint8_t		prio_boost;
1046 	uint8_t		tx_prio_boost;
1047 	uint16_t	rx_prio_boost;
1048 } __packed;
1049 
1050 /* Structure for enhanced command IWN_CMD_BLUETOOTH for 2000 Series. */
1051 struct iwn2000_btcoex_config {
1052 	uint8_t		flags;	/* Cf Flags in iwn6000_btcoex_config */
1053 	uint8_t		lead_time;
1054 	uint8_t		max_kill;
1055 	uint8_t		bt3_t7_timer;
1056 	uint32_t	kill_ack;
1057 	uint32_t	kill_cts;
1058 	uint8_t		sample_time;
1059 	uint8_t		bt3_t2_timer;
1060 	uint16_t	bt4_reaction;
1061 	uint32_t	lookup_table[12];
1062 	uint16_t	bt4_decision;
1063 	uint16_t	valid;
1064 
1065 	uint32_t	prio_boost;	/* size change prior to iwn6000_btcoex_config */
1066 	uint8_t		reserved;	/* added prior to iwn6000_btcoex_config */
1067 
1068 	uint8_t		tx_prio_boost;
1069 	uint16_t	rx_prio_boost;
1070 } __packed;
1071 
1072 struct iwn_btcoex_priotable {
1073 	uint8_t		calib_init1;
1074 	uint8_t		calib_init2;
1075 	uint8_t		calib_periodic_low1;
1076 	uint8_t		calib_periodic_low2;
1077 	uint8_t		calib_periodic_high1;
1078 	uint8_t		calib_periodic_high2;
1079 	uint8_t		dtim;
1080 	uint8_t		scan52;
1081 	uint8_t		scan24;
1082 	uint8_t		reserved[7];
1083 } __packed;
1084 
1085 struct iwn_btcoex_prot {
1086 	uint8_t		open;
1087 	uint8_t		type;
1088 	uint8_t		reserved[2];
1089 } __packed;
1090 
1091 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */
1092 struct iwn_critical_temp {
1093 	uint32_t	reserved;
1094 	uint32_t	tempM;
1095 	uint32_t	tempR;
1096 /* degK <-> degC conversion macros. */
1097 #define IWN_CTOK(c)	((c) + 273)
1098 #define IWN_KTOC(k)	((k) - 273)
1099 #define IWN_CTOMUK(c)	(((c) * 1000000) + 273150000)
1100 } __packed;
1101 
1102 /* Structures for command IWN_CMD_SET_SENSITIVITY. */
1103 struct iwn_sensitivity_cmd {
1104 	uint16_t	which;
1105 #define IWN_SENSITIVITY_DEFAULTTBL	0
1106 #define IWN_SENSITIVITY_WORKTBL		1
1107 
1108 	uint16_t	energy_cck;
1109 	uint16_t	energy_ofdm;
1110 	uint16_t	corr_ofdm_x1;
1111 	uint16_t	corr_ofdm_mrc_x1;
1112 	uint16_t	corr_cck_mrc_x4;
1113 	uint16_t	corr_ofdm_x4;
1114 	uint16_t	corr_ofdm_mrc_x4;
1115 	uint16_t	corr_barker;
1116 	uint16_t	corr_barker_mrc;
1117 	uint16_t	corr_cck_x4;
1118 	uint16_t	energy_ofdm_th;
1119 } __packed;
1120 
1121 struct iwn_enhanced_sensitivity_cmd {
1122 	uint16_t	which;
1123 	uint16_t	energy_cck;
1124 	uint16_t	energy_ofdm;
1125 	uint16_t	corr_ofdm_x1;
1126 	uint16_t	corr_ofdm_mrc_x1;
1127 	uint16_t	corr_cck_mrc_x4;
1128 	uint16_t	corr_ofdm_x4;
1129 	uint16_t	corr_ofdm_mrc_x4;
1130 	uint16_t	corr_barker;
1131 	uint16_t	corr_barker_mrc;
1132 	uint16_t	corr_cck_x4;
1133 	uint16_t	energy_ofdm_th;
1134 	/* "Enhanced" part. */
1135 	uint16_t	ina_det_ofdm;
1136 	uint16_t	ina_det_cck;
1137 	uint16_t	corr_11_9_en;
1138 	uint16_t	ofdm_det_slope_mrc;
1139 	uint16_t	ofdm_det_icept_mrc;
1140 	uint16_t	ofdm_det_slope;
1141 	uint16_t	ofdm_det_icept;
1142 	uint16_t	cck_det_slope_mrc;
1143 	uint16_t	cck_det_icept_mrc;
1144 	uint16_t	cck_det_slope;
1145 	uint16_t	cck_det_icept;
1146 	uint16_t	reserved;
1147 } __packed;
1148 
1149 /*
1150  * Define maximal number of calib result send to runtime firmware
1151  * PS: TEMP_OFFSET count for 2 (std and v2)
1152  */
1153 #define	IWN5000_PHY_CALIB_MAX_RESULT		8
1154 
1155 /* Structures for command IWN_CMD_PHY_CALIB. */
1156 struct iwn_phy_calib {
1157 	uint8_t	code;
1158 #define IWN4965_PHY_CALIB_DIFF_GAIN		 7
1159 #define IWN5000_PHY_CALIB_DC			 8
1160 #define IWN5000_PHY_CALIB_LO			 9
1161 #define IWN5000_PHY_CALIB_TX_IQ			11
1162 #define IWN5000_PHY_CALIB_CRYSTAL		15
1163 #define IWN5000_PHY_CALIB_BASE_BAND		16
1164 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC	17
1165 #define IWN5000_PHY_CALIB_TEMP_OFFSET		18
1166 
1167 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN	18
1168 #define IWN5000_PHY_CALIB_NOISE_GAIN		19
1169 
1170 	uint8_t	group;
1171 	uint8_t	ngroups;
1172 	uint8_t	isvalid;
1173 } __packed;
1174 
1175 struct iwn5000_phy_calib_crystal {
1176 	uint8_t	code;
1177 	uint8_t	group;
1178 	uint8_t	ngroups;
1179 	uint8_t	isvalid;
1180 
1181 	uint8_t	cap_pin[2];
1182 	uint8_t	reserved[2];
1183 } __packed;
1184 
1185 struct iwn5000_phy_calib_temp_offset {
1186 	uint8_t		code;
1187 	uint8_t		group;
1188 	uint8_t		ngroups;
1189 	uint8_t		isvalid;
1190 	int16_t		offset;
1191 #define IWN_DEFAULT_TEMP_OFFSET	2700
1192 
1193 	uint16_t	reserved;
1194 } __packed;
1195 
1196 struct iwn5000_phy_calib_temp_offsetv2 {
1197 	uint8_t		code;
1198 	uint8_t		group;
1199 	uint8_t		ngroups;
1200 	uint8_t		isvalid;
1201 	int16_t		offset_high;
1202 	int16_t		offset_low;
1203 	int16_t		burnt_voltage_ref;
1204 	int16_t		reserved;
1205 } __packed;
1206 
1207 struct iwn_phy_calib_gain {
1208 	uint8_t	code;
1209 	uint8_t	group;
1210 	uint8_t	ngroups;
1211 	uint8_t	isvalid;
1212 
1213 	int8_t	gain[3];
1214 	uint8_t	reserved;
1215 } __packed;
1216 
1217 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */
1218 struct iwn_spectrum_cmd {
1219 	uint16_t	len;
1220 	uint8_t		token;
1221 	uint8_t		id;
1222 	uint8_t		origin;
1223 	uint8_t		periodic;
1224 	uint16_t	timeout;
1225 	uint32_t	start;
1226 	uint32_t	reserved1;
1227 	uint32_t	flags;
1228 	uint32_t	filter;
1229 	uint16_t	nchan;
1230 	uint16_t	reserved2;
1231 	struct {
1232 		uint32_t	duration;
1233 		uint8_t		chan;
1234 		uint8_t		type;
1235 #define IWN_MEASUREMENT_BASIC		(1 << 0)
1236 #define IWN_MEASUREMENT_CCA		(1 << 1)
1237 #define IWN_MEASUREMENT_RPI_HISTOGRAM	(1 << 2)
1238 #define IWN_MEASUREMENT_NOISE_HISTOGRAM	(1 << 3)
1239 #define IWN_MEASUREMENT_FRAME		(1 << 4)
1240 #define IWN_MEASUREMENT_IDLE		(1 << 7)
1241 
1242 		uint16_t	reserved;
1243 	} __packed	chan[10];
1244 } __packed;
1245 
1246 /* Structure for IWN_UC_READY notification. */
1247 #define IWN_NATTEN_GROUPS	5
1248 struct iwn_ucode_info {
1249 	uint8_t		minor;
1250 	uint8_t		major;
1251 	uint16_t	reserved1;
1252 	uint8_t		revision[8];
1253 	uint8_t		type;
1254 	uint8_t		subtype;
1255 #define IWN_UCODE_RUNTIME	0
1256 #define IWN_UCODE_INIT		9
1257 
1258 	uint16_t	reserved2;
1259 	uint32_t	logptr;
1260 	uint32_t	errptr;
1261 	uint32_t	tstamp;
1262 	uint32_t	valid;
1263 
1264 	/* The following fields are for UCODE_INIT only. */
1265 	int32_t		volt;
1266 	struct {
1267 		int32_t	chan20MHz;
1268 		int32_t	chan40MHz;
1269 	} __packed	temp[4];
1270 	int32_t		atten[IWN_NATTEN_GROUPS][2];
1271 } __packed;
1272 
1273 /* Structures for IWN_TX_DONE notification. */
1274 
1275 /*
1276  * TX command response is sent after *agn* transmission attempts.
1277  *
1278  * both postpone and abort status are expected behavior from uCode. there is
1279  * no special operation required from driver; except for RFKILL_FLUSH,
1280  * which required tx flush host command to flush all the tx frames in queues
1281  */
1282 #define	IWN_TX_STATUS_MSK		0x000000ff
1283 #define	IWN_TX_STATUS_DELAY_MSK		0x00000040
1284 #define	IWN_TX_STATUS_ABORT_MSK		0x00000080
1285 #define	IWN_TX_PACKET_MODE_MSK		0x0000ff00
1286 #define	IWN_TX_FIFO_NUMBER_MSK		0x00070000
1287 #define	IWN_TX_RESERVED			0x00780000
1288 #define	IWN_TX_POWER_PA_DETECT_MSK	0x7f800000
1289 #define	IWN_TX_ABORT_REQUIRED_MSK	0x80000000
1290 
1291 /* Success status */
1292 #define	IWN_TX_STATUS_SUCCESS		0x01
1293 #define	IWN_TX_STATUS_DIRECT_DONE	0x02
1294 
1295 /* postpone TX */
1296 #define	IWN_TX_STATUS_POSTPONE_DELAY		0x40
1297 #define	IWN_TX_STATUS_POSTPONE_FEW_BYTES	0x41
1298 #define	IWN_TX_STATUS_POSTPONE_BT_PRIO		0x42
1299 #define	IWN_TX_STATUS_POSTPONE_QUIET_PERIOD	0x43
1300 #define	IWN_TX_STATUS_POSTPONE_CALC_TTAK	0x44
1301 
1302 /* Failures */
1303 #define	IWN_TX_FAIL			0x80	/* all failures have 0x80 set */
1304 #define	IWN_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY	0x81
1305 #define	IWN_TX_FAIL_SHORT_LIMIT		0x82	/* too many RTS retries */
1306 #define	IWN_TX_FAIL_LONG_LIMIT		0x83	/* too many retries */
1307 #define	IWN_TX_FAIL_FIFO_UNDERRRUN	0x84	/* tx fifo not kept running */
1308 #define	IWN_TX_STATUS_FAIL_DRAIN_FLOW	0x85
1309 #define	IWN_TX_STATUS_FAIL_RFKILL_FLUSH	0x86
1310 #define	IWN_TX_STATUS_FAIL_LIFE_EXPIRE	0x87
1311 #define	IWN_TX_FAIL_DEST_IN_PS		0x88	/* sta found in power save */
1312 #define	IWN_TX_STATUS_FAIL_HOST_ABORTED	0x89
1313 #define	IWN_TX_STATUS_FAIL_BT_RETRY	0x8a
1314 #define	IWN_TX_FAIL_STA_INVALID		0x8b	/* XXX STA invalid (???) */
1315 #define	IWN_TX_STATUS_FAIL_FRAG_DROPPED	0x8c
1316 #define	IWN_TX_STATUS_FAIL_TID_DISABLE	0x8d
1317 #define	IWN_TX_STATUS_FAIL_FIFO_FLUSHED	0x8e
1318 #define	IWN_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL	0x8f
1319 #define	IWN_TX_FAIL_TX_LOCKED		0x90	/* waiting to see traffic */
1320 #define	IWN_TX_STATUS_FAIL_NO_BEACON_ON_RADAR	0x91
1321 
1322 /*
1323  * TX command response for A-MPDU packet responses.
1324  *
1325  * The status response is different to the non A-MPDU responses.
1326  * In addition, the sequence number is treated as the sequence
1327  * number of the TX command, NOT the 802.11 sequence number!
1328  */
1329 #define	IWN_AGG_TX_STATE_TRANSMITTED		0x00
1330 #define	IWN_AGG_TX_STATE_UNDERRUN_MSK		0x01
1331 #define	IWN_AGG_TX_STATE_FEW_BYTES_MSK		0x04
1332 #define	IWN_AGG_TX_STATE_ABORT_MSK		0x08
1333 
1334 #define	IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK	0x10
1335 #define	IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK	0x20
1336 
1337 #define	IWN_AGG_TX_STATE_SCD_QUERY_MSK		0x80
1338 
1339 #define	IWN_AGG_TX_STATE_TEST_BAD_CRC32_MSK	0x100
1340 
1341 #define	IWN_AGG_TX_STATE_RESPONSE_MSK		0x1ff
1342 #define	IWN_AGG_TX_STATE_DUMP_TX_MSK		0x200
1343 #define	IWN_AGG_TX_STATE_DELAY_TX_MSK		0x400
1344 
1345 #define	IWN_AGG_TX_STATUS_MSK		0x00000fff
1346 #define	IWN_AGG_TX_TRY_MSK		0x0000f000
1347 
1348 #define	IWN_AGG_TX_STATE_LAST_SENT_MSK		\
1349 	    (IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK | \
1350 	     IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK)
1351 
1352 /* # tx attempts for first frame in aggregation */
1353 #define	IWN_AGG_TX_STATE_TRY_CNT_POS	12
1354 #define	IWN_AGG_TX_STATE_TRY_CNT_MSK	0xf000
1355 
1356 /* Command ID and sequence number of Tx command for this frame */
1357 #define	IWN_AGG_TX_STATE_SEQ_NUM_POS	16
1358 #define	IWN_AGG_TX_STATE_SEQ_NUM_MSK	0xffff0000
1359 
1360 struct iwn4965_tx_stat {
1361 	uint8_t		nframes;
1362 	uint8_t		btkillcnt;
1363 	uint8_t		rtsfailcnt;
1364 	uint8_t		ackfailcnt;
1365 	uint32_t	rate;
1366 	uint16_t	duration;
1367 	uint16_t	reserved;
1368 	uint32_t	power[2];
1369 	uint32_t	status;
1370 } __packed;
1371 
1372 struct iwn5000_tx_stat {
1373 	uint8_t		nframes;	/* 1 no aggregation, >1 aggregation */
1374 	uint8_t		btkillcnt;
1375 	uint8_t		rtsfailcnt;
1376 	uint8_t		ackfailcnt;
1377 	uint32_t	rate;
1378 	uint16_t	duration;
1379 	uint16_t	reserved;
1380 	uint32_t	power[2];
1381 	uint32_t	info;
1382 	uint16_t	seq;
1383 	uint16_t	len;
1384 	uint8_t		tlc;
1385 	uint8_t		ratid;	/* tid (0:3), sta_id (4:7) */
1386 	uint8_t		fc[2];
1387 	uint16_t	status;
1388 	uint16_t	sequence;
1389 } __packed;
1390 
1391 /* Structure for IWN_BEACON_MISSED notification. */
1392 struct iwn_beacon_missed {
1393 	uint32_t	consecutive;
1394 	uint32_t	total;
1395 	uint32_t	expected;
1396 	uint32_t	received;
1397 } __packed;
1398 
1399 /* Structure for IWN_MPDU_RX_DONE notification. */
1400 struct iwn_rx_mpdu {
1401 	uint16_t	len;
1402 	uint16_t	reserved;
1403 } __packed;
1404 
1405 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */
1406 struct iwn4965_rx_phystat {
1407 	uint16_t	antenna;
1408 	uint16_t	agc;
1409 	uint8_t		rssi[6];
1410 } __packed;
1411 
1412 struct iwn5000_rx_phystat {
1413 	uint32_t	reserved1;
1414 	uint32_t	agc;
1415 	uint16_t	rssi[3];
1416 } __packed;
1417 
1418 struct iwn_rx_stat {
1419 	uint8_t		phy_len;
1420 	uint8_t		cfg_phy_len;
1421 #define IWN_STAT_MAXLEN	20
1422 
1423 	uint8_t		id;
1424 	uint8_t		reserved1;
1425 	uint64_t	tstamp;
1426 	uint32_t	beacon;
1427 	uint16_t	flags;
1428 #define IWN_STAT_FLAG_SHPREAMBLE	(1 << 2)
1429 
1430 	uint16_t	chan;
1431 	uint8_t		phybuf[32];
1432 	uint32_t	rate;
1433 /*
1434  * rate bit fields
1435  *
1436  * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"):
1437  *  2-0:  0)   6 Mbps
1438  *        1)  12 Mbps
1439  *        2)  18 Mbps
1440  *        3)  24 Mbps
1441  *        4)  36 Mbps
1442  *        5)  48 Mbps
1443  *        6)  54 Mbps
1444  *        7)  60 Mbps
1445  *
1446  *  4-3:  0)  Single stream (SISO)
1447  *        1)  Dual stream (MIMO)
1448  *        2)  Triple stream (MIMO)
1449  *
1450  *    5:  Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
1451  *
1452  * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"):
1453  *  3-0:  0xD)   6 Mbps
1454  *        0xF)   9 Mbps
1455  *        0x5)  12 Mbps
1456  *        0x7)  18 Mbps
1457  *        0x9)  24 Mbps
1458  *        0xB)  36 Mbps
1459  *        0x1)  48 Mbps
1460  *        0x3)  54 Mbps
1461  *
1462  * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"):
1463  *  6-0:   10)  1 Mbps
1464  *         20)  2 Mbps
1465  *         55)  5.5 Mbps
1466  *        110)  11 Mbps
1467  *
1468  */
1469 	uint16_t	len;
1470 	uint16_t	reserve3;
1471 } __packed;
1472 
1473 #define IWN_RSSI_TO_DBM	44
1474 
1475 /* Structure for IWN_RX_COMPRESSED_BA notification. */
1476 struct iwn_compressed_ba {
1477 	uint8_t		macaddr[IEEE80211_ADDR_LEN];
1478 	uint16_t	reserved;
1479 	uint8_t		id;
1480 	uint8_t		tid;
1481 	uint16_t	seq;
1482 	uint64_t	bitmap;
1483 	uint16_t	qid;
1484 	uint16_t	ssn;
1485 	/* extra fields starting with iwn5000 */
1486 #if 0
1487 	uint8_t		txed;		/* number of frames sent */
1488 	uint8_t		txed_2_done;	/* number of frames acked */
1489 	uint16_t	reserved1;
1490 #endif
1491 } __packed;
1492 
1493 /* Structure for IWN_START_SCAN notification. */
1494 struct iwn_start_scan {
1495 	uint64_t	tstamp;
1496 	uint32_t	tbeacon;
1497 	uint8_t		chan;
1498 	uint8_t		band;
1499 	uint16_t	reserved;
1500 	uint32_t	status;
1501 } __packed;
1502 
1503 /* Structure for IWN_STOP_SCAN notification. */
1504 struct iwn_stop_scan {
1505 	uint8_t		nchan;
1506 	uint8_t		status;
1507 	uint8_t		reserved;
1508 	uint8_t		chan;
1509 	uint64_t	tsf;
1510 } __packed;
1511 
1512 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */
1513 struct iwn_spectrum_notif {
1514 	uint8_t		id;
1515 	uint8_t		token;
1516 	uint8_t		idx;
1517 	uint8_t		state;
1518 #define IWN_MEASUREMENT_START	0
1519 #define IWN_MEASUREMENT_STOP	1
1520 
1521 	uint32_t	start;
1522 	uint8_t		band;
1523 	uint8_t		chan;
1524 	uint8_t		type;
1525 	uint8_t		reserved1;
1526 	uint32_t	cca_ofdm;
1527 	uint32_t	cca_cck;
1528 	uint32_t	cca_time;
1529 	uint8_t		basic;
1530 	uint8_t		reserved2[3];
1531 	uint32_t	ofdm[8];
1532 	uint32_t	cck[8];
1533 	uint32_t	stop;
1534 	uint32_t	status;
1535 #define IWN_MEASUREMENT_OK		0
1536 #define IWN_MEASUREMENT_CONCURRENT	1
1537 #define IWN_MEASUREMENT_CSA_CONFLICT	2
1538 #define IWN_MEASUREMENT_TGH_CONFLICT	3
1539 #define IWN_MEASUREMENT_STOPPED		6
1540 #define IWN_MEASUREMENT_TIMEOUT		7
1541 #define IWN_MEASUREMENT_FAILED		8
1542 } __packed;
1543 
1544 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */
1545 struct iwn_rx_phy_stats {
1546 	uint32_t	ina;
1547 	uint32_t	fina;
1548 	uint32_t	bad_plcp;
1549 	uint32_t	bad_crc32;
1550 	uint32_t	overrun;
1551 	uint32_t	eoverrun;
1552 	uint32_t	good_crc32;
1553 	uint32_t	fa;
1554 	uint32_t	bad_fina_sync;
1555 	uint32_t	sfd_timeout;
1556 	uint32_t	fina_timeout;
1557 	uint32_t	no_rts_ack;
1558 	uint32_t	rxe_limit;
1559 	uint32_t	ack;
1560 	uint32_t	cts;
1561 	uint32_t	ba_resp;
1562 	uint32_t	dsp_kill;
1563 	uint32_t	bad_mh;
1564 	uint32_t	rssi_sum;
1565 	uint32_t	reserved;
1566 } __packed;
1567 
1568 struct iwn_rx_general_stats {
1569 	uint32_t	bad_cts;
1570 	uint32_t	bad_ack;
1571 	uint32_t	not_bss;
1572 	uint32_t	filtered;
1573 	uint32_t	bad_chan;
1574 	uint32_t	beacons;
1575 	uint32_t	missed_beacons;
1576 	uint32_t	adc_saturated;	/* time in 0.8us */
1577 	uint32_t	ina_searched;	/* time in 0.8us */
1578 	uint32_t	noise[3];
1579 	uint32_t	flags;
1580 	uint32_t	load;
1581 	uint32_t	fa;
1582 	uint32_t	rssi[3];
1583 	uint32_t	energy[3];
1584 } __packed;
1585 
1586 struct iwn_rx_ht_phy_stats {
1587 	uint32_t	bad_plcp;
1588 	uint32_t	overrun;
1589 	uint32_t	eoverrun;
1590 	uint32_t	good_crc32;
1591 	uint32_t	bad_crc32;
1592 	uint32_t	bad_mh;
1593 	uint32_t	good_ampdu_crc32;
1594 	uint32_t	ampdu;
1595 	uint32_t	fragment;
1596 	uint32_t	unsupport_mcs;
1597 } __packed;
1598 
1599 struct iwn_rx_stats {
1600 	struct iwn_rx_phy_stats		ofdm;
1601 	struct iwn_rx_phy_stats		cck;
1602 	struct iwn_rx_general_stats	general;
1603 	struct iwn_rx_ht_phy_stats	ht;
1604 } __packed;
1605 
1606 struct iwn_rx_general_stats_bt {
1607 	struct iwn_rx_general_stats common;
1608 	/* additional stats for bt */
1609 	uint32_t num_bt_kills;
1610 	uint32_t reserved[2];
1611 } __packed;
1612 
1613 struct iwn_rx_stats_bt {
1614 	struct iwn_rx_phy_stats		ofdm;
1615 	struct iwn_rx_phy_stats		cck;
1616 	struct iwn_rx_general_stats_bt	general_bt;
1617 	struct iwn_rx_ht_phy_stats	ht;
1618 } __packed;
1619 
1620 struct iwn_tx_stats {
1621 	uint32_t	preamble;
1622 	uint32_t	rx_detected;
1623 	uint32_t	bt_defer;
1624 	uint32_t	bt_kill;
1625 	uint32_t	short_len;
1626 	uint32_t	cts_timeout;
1627 	uint32_t	ack_timeout;
1628 	uint32_t	exp_ack;
1629 	uint32_t	ack;
1630 	uint32_t	msdu;
1631 	uint32_t	burst_err1;
1632 	uint32_t	burst_err2;
1633 	uint32_t	cts_collision;
1634 	uint32_t	ack_collision;
1635 	uint32_t	ba_timeout;
1636 	uint32_t	ba_resched;
1637 	uint32_t	query_ampdu;
1638 	uint32_t	query;
1639 	uint32_t	query_ampdu_frag;
1640 	uint32_t	query_mismatch;
1641 	uint32_t	not_ready;
1642 	uint32_t	underrun;
1643 	uint32_t	bt_ht_kill;
1644 	uint32_t	rx_ba_resp;
1645 	/*
1646 	 * 6000 series only - LSB=ant A, ant B, ant C, MSB=reserved
1647 	 * TX power on chain in 1/2 dBm.
1648 	 */
1649 	uint32_t	tx_power;
1650 	uint32_t	reserved[1];
1651 } __packed;
1652 
1653 struct iwn_general_stats {
1654 	uint32_t	temp;		/* radio temperature */
1655 	uint32_t	temp_m;		/* radio voltage */
1656 	uint32_t	burst_check;
1657 	uint32_t	burst;
1658 	uint32_t	wait_for_silence_timeout_cnt;
1659 	uint32_t	reserved1[3];
1660 	uint32_t	sleep;
1661 	uint32_t	slot_out;
1662 	uint32_t	slot_idle;
1663 	uint32_t	ttl_tstamp;
1664 	uint32_t	tx_ant_a;
1665 	uint32_t	tx_ant_b;
1666 	uint32_t	exec;
1667 	uint32_t	probe;
1668 	uint32_t	reserved2[2];
1669 	uint32_t	rx_enabled;
1670 	/*
1671 	 * This is the number of times we have to re-tune
1672 	 * in order to get out of bad PHY status.
1673 	 */
1674 	uint32_t	num_of_sos_states;
1675 } __packed;
1676 
1677 struct iwn_stats {
1678 	uint32_t			flags;
1679 	struct iwn_rx_stats		rx;
1680 	struct iwn_tx_stats		tx;
1681 	struct iwn_general_stats	general;
1682 	uint32_t			reserved1[2];
1683 } __packed;
1684 
1685 struct iwn_bt_activity_stats {
1686 	/* Tx statistics */
1687 	uint32_t hi_priority_tx_req_cnt;
1688 	uint32_t hi_priority_tx_denied_cnt;
1689 	uint32_t lo_priority_tx_req_cnt;
1690 	uint32_t lo_priority_tx_denied_cnt;
1691 	/* Rx statistics */
1692 	uint32_t hi_priority_rx_req_cnt;
1693 	uint32_t hi_priority_rx_denied_cnt;
1694 	uint32_t lo_priority_rx_req_cnt;
1695 	uint32_t lo_priority_rx_denied_cnt;
1696 } __packed;
1697 
1698 struct iwn_stats_bt {
1699 	uint32_t			flags;
1700 	struct iwn_rx_stats_bt		rx_bt;
1701 	struct iwn_tx_stats		tx;
1702 	struct iwn_general_stats	general;
1703 	struct iwn_bt_activity_stats	activity;
1704 	uint32_t			reserved1[2];
1705 };
1706 
1707 /* Firmware error dump. */
1708 struct iwn_fw_dump {
1709 	uint32_t	valid;
1710 	uint32_t	id;
1711 	uint32_t	pc;
1712 	uint32_t	branch_link[2];
1713 	uint32_t	interrupt_link[2];
1714 	uint32_t	error_data[2];
1715 	uint32_t	src_line;
1716 	uint32_t	tsf;
1717 	uint32_t	time[2];
1718 } __packed;
1719 
1720 /* TLV firmware header. */
1721 struct iwn_fw_tlv_hdr {
1722 	uint32_t	zero;	/* Always 0, to differentiate from legacy. */
1723 	uint32_t	signature;
1724 #define IWN_FW_SIGNATURE	0x0a4c5749	/* "IWL\n" */
1725 
1726 	uint8_t		descr[64];
1727 	uint32_t	rev;
1728 #define IWN_FW_API(x)	(((x) >> 8) & 0xff)
1729 
1730 	uint32_t	build;
1731 	uint64_t	altmask;
1732 } __packed;
1733 
1734 /* TLV header. */
1735 struct iwn_fw_tlv {
1736 	uint16_t	type;
1737 #define IWN_FW_TLV_MAIN_TEXT		1
1738 #define IWN_FW_TLV_MAIN_DATA		2
1739 #define IWN_FW_TLV_INIT_TEXT		3
1740 #define IWN_FW_TLV_INIT_DATA		4
1741 #define IWN_FW_TLV_BOOT_TEXT		5
1742 #define IWN_FW_TLV_PBREQ_MAXLEN		6
1743 #define	IWN_FW_TLV_PAN			7
1744 #define	IWN_FW_TLV_RUNT_EVTLOG_PTR	8
1745 #define	IWN_FW_TLV_RUNT_EVTLOG_SIZE	9
1746 #define	IWN_FW_TLV_RUNT_ERRLOG_PTR	10
1747 #define	IWN_FW_TLV_INIT_EVTLOG_PTR	11
1748 #define	IWN_FW_TLV_INIT_EVTLOG_SIZE	12
1749 #define	IWN_FW_TLV_INIT_ERRLOG_PTR	13
1750 #define IWN_FW_TLV_ENH_SENS		14
1751 #define IWN_FW_TLV_PHY_CALIB		15
1752 #define	IWN_FW_TLV_WOWLAN_INST		16
1753 #define	IWN_FW_TLV_WOWLAN_DATA		17
1754 #define	IWN_FW_TLV_FLAGS		18
1755 
1756 	uint16_t	alt;
1757 	uint32_t	len;
1758 } __packed;
1759 
1760 #define IWN4965_FW_TEXT_MAXSZ	( 96 * 1024)
1761 #define IWN4965_FW_DATA_MAXSZ	( 40 * 1024)
1762 #define IWN5000_FW_TEXT_MAXSZ	(256 * 1024)
1763 #define IWN5000_FW_DATA_MAXSZ	( 80 * 1024)
1764 #define IWN_FW_BOOT_TEXT_MAXSZ	1024
1765 #define IWN4965_FWSZ		(IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ)
1766 #define IWN5000_FWSZ		IWN5000_FW_TEXT_MAXSZ
1767 
1768 /*
1769  * Microcode flags TLV (18.)
1770  */
1771 
1772 /**
1773  * enum iwn_ucode_tlv_flag - ucode API flags
1774  * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
1775  *      was a separate TLV but moved here to save space.
1776  * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
1777  *      treats good CRC threshold as a boolean
1778  * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
1779  * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
1780  * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
1781  * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
1782  * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
1783  *      offload profile config command.
1784  * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api
1785  * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API.
1786  * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
1787  *      (rather than two) IPv6 addresses
1788  * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API
1789  * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
1790  *      from the probe request template.
1791  * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping
1792  *      connection when going back to D0
1793  * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
1794  * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
1795  * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan.
1796  * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API
1797  * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command
1798  *      containing CAM (Continuous Active Mode) indication.
1799  */
1800 enum iwn_ucode_tlv_flag {
1801 	IWN_UCODE_TLV_FLAGS_PAN			= (1 << 0),
1802 	IWN_UCODE_TLV_FLAGS_NEWSCAN		= (1 << 1),
1803 	IWN_UCODE_TLV_FLAGS_MFP			= (1 << 2),
1804 	IWN_UCODE_TLV_FLAGS_P2P			= (1 << 3),
1805 	IWN_UCODE_TLV_FLAGS_DW_BC_TABLE		= (1 << 4),
1806 	IWN_UCODE_TLV_FLAGS_NEWBT_COEX		= (1 << 5),
1807 	IWN_UCODE_TLV_FLAGS_UAPSD		= (1 << 6),
1808 	IWN_UCODE_TLV_FLAGS_SHORT_BL		= (1 << 7),
1809 	IWN_UCODE_TLV_FLAGS_RX_ENERGY_API	= (1 << 8),
1810 	IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2	= (1 << 9),
1811 	IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS	= (1 << 10),
1812 	IWN_UCODE_TLV_FLAGS_BF_UPDATED		= (1 << 11),
1813 	IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID	= (1 << 12),
1814 	IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API	= (1 << 14),
1815 	IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL	= (1 << 15),
1816 	IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE	= (1 << 16),
1817 	IWN_UCODE_TLV_FLAGS_SCHED_SCAN		= (1 << 17),
1818 	IWN_UCODE_TLV_FLAGS_STA_KEY_CMD		= (1 << 19),
1819 	IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD	= (1 << 20),
1820 };
1821 
1822 /*
1823  * Offsets into EEPROM.
1824  */
1825 #define IWN_EEPROM_MAC		0x015
1826 #define IWN_EEPROM_SKU_CAP	0x045
1827 #define IWN_EEPROM_RFCFG	0x048
1828 #define IWN4965_EEPROM_DOMAIN	0x060
1829 #define IWN4965_EEPROM_BAND1	0x063
1830 #define IWN5000_EEPROM_REG	0x066
1831 #define IWN5000_EEPROM_CAL	0x067
1832 #define IWN4965_EEPROM_BAND2	0x072
1833 #define IWN4965_EEPROM_BAND3	0x080
1834 #define IWN4965_EEPROM_BAND4	0x08d
1835 #define IWN4965_EEPROM_BAND5	0x099
1836 #define IWN4965_EEPROM_BAND6	0x0a0
1837 #define IWN4965_EEPROM_BAND7	0x0a8
1838 #define IWN4965_EEPROM_MAXPOW	0x0e8
1839 #define IWN4965_EEPROM_VOLTAGE	0x0e9
1840 #define IWN4965_EEPROM_BANDS	0x0ea
1841 /* Indirect offsets. */
1842 #define	IWN5000_EEPROM_NO_HT40	0x000
1843 #define IWN5000_EEPROM_DOMAIN	0x001
1844 #define IWN5000_EEPROM_BAND1	0x004
1845 #define IWN5000_EEPROM_BAND2	0x013
1846 #define IWN5000_EEPROM_BAND3	0x021
1847 #define IWN5000_EEPROM_BAND4	0x02e
1848 #define IWN5000_EEPROM_BAND5	0x03a
1849 #define IWN5000_EEPROM_BAND6	0x041
1850 #define IWN6000_EEPROM_BAND6	0x040
1851 #define IWN5000_EEPROM_BAND7	0x049
1852 #define IWN6000_EEPROM_ENHINFO	0x054
1853 #define IWN5000_EEPROM_CRYSTAL	0x128
1854 #define IWN5000_EEPROM_TEMP	0x12a
1855 #define IWN5000_EEPROM_VOLT	0x12b
1856 
1857 /* Possible flags for IWN_EEPROM_SKU_CAP. */
1858 #define IWN_EEPROM_SKU_CAP_11N	(1 << 6)
1859 #define IWN_EEPROM_SKU_CAP_AMT	(1 << 7)
1860 #define IWN_EEPROM_SKU_CAP_IPAN	(1 << 8)
1861 
1862 /* Possible flags for IWN_EEPROM_RFCFG. */
1863 #define IWN_RFCFG_TYPE(x)	(((x) >>  0) & 0x3)
1864 #define IWN_RFCFG_STEP(x)	(((x) >>  2) & 0x3)
1865 #define IWN_RFCFG_DASH(x)	(((x) >>  4) & 0x3)
1866 #define IWN_RFCFG_TXANTMSK(x)	(((x) >>  8) & 0xf)
1867 #define IWN_RFCFG_RXANTMSK(x)	(((x) >> 12) & 0xf)
1868 
1869 struct iwn_eeprom_chan {
1870 	uint8_t	flags;
1871 #define IWN_EEPROM_CHAN_VALID	(1 << 0)
1872 #define IWN_EEPROM_CHAN_IBSS	(1 << 1)
1873 #define IWN_EEPROM_CHAN_ACTIVE	(1 << 3)
1874 #define IWN_EEPROM_CHAN_RADAR	(1 << 4)
1875 
1876 	int8_t	maxpwr;
1877 } __packed;
1878 
1879 struct iwn_eeprom_enhinfo {
1880 	uint8_t		flags;
1881 #define IWN_ENHINFO_VALID	0x01
1882 #define IWN_ENHINFO_5GHZ	0x02
1883 #define IWN_ENHINFO_OFDM	0x04
1884 #define IWN_ENHINFO_HT40	0x08
1885 #define IWN_ENHINFO_HTAP	0x10
1886 #define IWN_ENHINFO_RES1	0x20
1887 #define IWN_ENHINFO_RES2	0x40
1888 #define IWN_ENHINFO_COMMON	0x80
1889 
1890 	uint8_t		chan;
1891 	int8_t		chain[3];	/* max power in half-dBm */
1892 	uint8_t		reserved;
1893 	int8_t		mimo2;		/* max power in half-dBm */
1894 	int8_t		mimo3;		/* max power in half-dBm */
1895 } __packed;
1896 
1897 struct iwn5000_eeprom_calib_hdr {
1898 	uint8_t		version;
1899 	uint8_t		pa_type;
1900 	uint16_t	volt;
1901 } __packed;
1902 
1903 #define IWN_NSAMPLES	3
1904 struct iwn4965_eeprom_chan_samples {
1905 	uint8_t	num;
1906 	struct {
1907 		uint8_t temp;
1908 		uint8_t	gain;
1909 		uint8_t	power;
1910 		int8_t	pa_det;
1911 	}	samples[2][IWN_NSAMPLES];
1912 } __packed;
1913 
1914 #define IWN_NBANDS	8
1915 struct iwn4965_eeprom_band {
1916 	uint8_t	lo;	/* low channel number */
1917 	uint8_t	hi;	/* high channel number */
1918 	struct	iwn4965_eeprom_chan_samples chans[2];
1919 } __packed;
1920 
1921 /*
1922  * Offsets of channels descriptions in EEPROM.
1923  */
1924 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = {
1925 	IWN4965_EEPROM_BAND1,
1926 	IWN4965_EEPROM_BAND2,
1927 	IWN4965_EEPROM_BAND3,
1928 	IWN4965_EEPROM_BAND4,
1929 	IWN4965_EEPROM_BAND5,
1930 	IWN4965_EEPROM_BAND6,
1931 	IWN4965_EEPROM_BAND7
1932 };
1933 
1934 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = {
1935 	IWN5000_EEPROM_BAND1,
1936 	IWN5000_EEPROM_BAND2,
1937 	IWN5000_EEPROM_BAND3,
1938 	IWN5000_EEPROM_BAND4,
1939 	IWN5000_EEPROM_BAND5,
1940 	IWN5000_EEPROM_BAND6,
1941 	IWN5000_EEPROM_BAND7
1942 };
1943 
1944 static const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = {
1945 	IWN5000_EEPROM_BAND1,
1946 	IWN5000_EEPROM_BAND2,
1947 	IWN5000_EEPROM_BAND3,
1948 	IWN5000_EEPROM_BAND4,
1949 	IWN5000_EEPROM_BAND5,
1950 	IWN6000_EEPROM_BAND6,
1951 	IWN5000_EEPROM_BAND7
1952 };
1953 
1954 static const uint32_t iwn1000_regulatory_bands[IWN_NBANDS] = {
1955 	IWN5000_EEPROM_BAND1,
1956 	IWN5000_EEPROM_BAND2,
1957 	IWN5000_EEPROM_BAND3,
1958 	IWN5000_EEPROM_BAND4,
1959 	IWN5000_EEPROM_BAND5,
1960 	IWN5000_EEPROM_BAND6,
1961 	IWN5000_EEPROM_NO_HT40,
1962 };
1963 
1964 static const uint32_t iwn2030_regulatory_bands[IWN_NBANDS] = {
1965 	IWN5000_EEPROM_BAND1,
1966 	IWN5000_EEPROM_BAND2,
1967 	IWN5000_EEPROM_BAND3,
1968 	IWN5000_EEPROM_BAND4,
1969 	IWN5000_EEPROM_BAND5,
1970 	IWN6000_EEPROM_BAND6,
1971 	IWN5000_EEPROM_BAND7
1972 };
1973 
1974 #define IWN_CHAN_BANDS_COUNT	 7
1975 #define IWN_MAX_CHAN_PER_BAND	14
1976 static const struct iwn_chan_band {
1977 	uint8_t	nchan;
1978 	uint8_t	chan[IWN_MAX_CHAN_PER_BAND];
1979 } iwn_bands[] = {
1980 	/* 20MHz channels, 2GHz band. */
1981 	{ 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } },
1982 	/* 20MHz channels, 5GHz band. */
1983 	{ 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } },
1984 	{ 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } },
1985 	{ 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } },
1986 	{  6, { 145, 149, 153, 157, 161, 165 } },
1987 	/* 40MHz channels (primary channels), 2GHz band. */
1988 	{  7, { 1, 2, 3, 4, 5, 6, 7 } },
1989 	/* 40MHz channels (primary channels), 5GHz band. */
1990 	{ 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } }
1991 };
1992 
1993 static const uint8_t iwn_bss_ac_to_queue[] = {
1994 	2, 3, 1, 0,
1995 };
1996 
1997 static const uint8_t iwn_pan_ac_to_queue[] = {
1998 	5, 4, 6, 7,
1999 };
2000 #define IWN1000_OTP_NBLOCKS	3
2001 #define IWN6000_OTP_NBLOCKS	4
2002 #define IWN6050_OTP_NBLOCKS	7
2003 
2004 /* HW rate indices. */
2005 #define IWN_RIDX_CCK1	0
2006 #define IWN_RIDX_OFDM6	4
2007 
2008 #define IWN4965_MAX_PWR_INDEX	107
2009 #define	IWN_POWERSAVE_LVL_NONE			0
2010 #define	IWN_POWERSAVE_LVL_VOIP_COMPATIBLE	1
2011 #define	IWN_POWERSAVE_LVL_MAX			5
2012 
2013 #define	IWN_POWERSAVE_LVL_DEFAULT	IWN_POWERSAVE_LVL_NONE
2014 
2015 /* DTIM value to pass in for IWN_POWERSAVE_LVL_VOIP_COMPATIBLE */
2016 #define	IWN_POWERSAVE_DTIM_VOIP_COMPATIBLE	2
2017 
2018 /*
2019  * RF Tx gain values from highest to lowest power (values obtained from
2020  * the reference driver.)
2021  */
2022 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = {
2023 	0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c,
2024 	0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38,
2025 	0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35,
2026 	0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31,
2027 	0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04,
2028 	0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01,
2029 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2030 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2031 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2032 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
2033 };
2034 
2035 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = {
2036 	0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d,
2037 	0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39,
2038 	0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35,
2039 	0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32,
2040 	0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24,
2041 	0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16,
2042 	0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13,
2043 	0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05,
2044 	0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01,
2045 	0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
2046 };
2047 
2048 /*
2049  * DSP pre-DAC gain values from highest to lowest power (values obtained
2050  * from the reference driver.)
2051  */
2052 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = {
2053 	0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2054 	0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2055 	0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2056 	0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2057 	0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2058 	0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2059 	0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a,
2060 	0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f,
2061 	0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44,
2062 	0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b
2063 };
2064 
2065 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = {
2066 	0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2067 	0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2068 	0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2069 	0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2070 	0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2071 	0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2072 	0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2073 	0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2074 	0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2075 	0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e
2076 };
2077 
2078 /*
2079  * Power saving settings (values obtained from the reference driver.)
2080  */
2081 #define IWN_NDTIMRANGES		3
2082 #define IWN_NPOWERLEVELS	6
2083 static const struct iwn_pmgt {
2084 	uint32_t	rxtimeout;
2085 	uint32_t	txtimeout;
2086 	uint32_t	intval[5];
2087 	int		skip_dtim;
2088 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = {
2089 	/* DTIM <= 2 */
2090 	{
2091 	{   0,   0, {  0,  0,  0,  0,  0 }, 0 },	/* CAM */
2092 	{ 200, 500, {  1,  2,  2,  2, -1 }, 0 },	/* PS level 1 */
2093 	{ 200, 300, {  1,  2,  2,  2, -1 }, 0 },	/* PS level 2 */
2094 	{  50, 100, {  2,  2,  2,  2, -1 }, 0 },	/* PS level 3 */
2095 	{  50,  25, {  2,  2,  4,  4, -1 }, 1 },	/* PS level 4 */
2096 	{  25,  25, {  2,  2,  4,  6, -1 }, 2 }		/* PS level 5 */
2097 	},
2098 	/* 3 <= DTIM <= 10 */
2099 	{
2100 	{   0,   0, {  0,  0,  0,  0,  0 }, 0 },	/* CAM */
2101 	{ 200, 500, {  1,  2,  3,  4,  4 }, 0 },	/* PS level 1 */
2102 	{ 200, 300, {  1,  2,  3,  4,  7 }, 0 },	/* PS level 2 */
2103 	{  50, 100, {  2,  4,  6,  7,  9 }, 0 },	/* PS level 3 */
2104 	{  50,  25, {  2,  4,  6,  9, 10 }, 1 },	/* PS level 4 */
2105 	{  25,  25, {  2,  4,  7, 10, 10 }, 2 }		/* PS level 5 */
2106 	},
2107 	/* DTIM >= 11 */
2108 	{
2109 	{   0,   0, {  0,  0,  0,  0,  0 }, 0 },	/* CAM */
2110 	{ 200, 500, {  1,  2,  3,  4, -1 }, 0 },	/* PS level 1 */
2111 	{ 200, 300, {  2,  4,  6,  7, -1 }, 0 },	/* PS level 2 */
2112 	{  50, 100, {  2,  7,  9,  9, -1 }, 0 },	/* PS level 3 */
2113 	{  50,  25, {  2,  7,  9,  9, -1 }, 0 },	/* PS level 4 */
2114 	{  25,  25, {  4,  7, 10, 10, -1 }, 0 }		/* PS level 5 */
2115 	}
2116 };
2117 
2118 struct iwn_sensitivity_limits {
2119 	uint32_t	min_ofdm_x1;
2120 	uint32_t	max_ofdm_x1;
2121 	uint32_t	min_ofdm_mrc_x1;
2122 	uint32_t	max_ofdm_mrc_x1;
2123 	uint32_t	min_ofdm_x4;
2124 	uint32_t	max_ofdm_x4;
2125 	uint32_t	min_ofdm_mrc_x4;
2126 	uint32_t	max_ofdm_mrc_x4;
2127 	uint32_t	min_cck_x4;
2128 	uint32_t	max_cck_x4;
2129 	uint32_t	min_cck_mrc_x4;
2130 	uint32_t	max_cck_mrc_x4;
2131 	uint32_t	min_energy_cck;
2132 	uint32_t	energy_cck;
2133 	uint32_t	energy_ofdm;
2134 	uint32_t	barker_mrc;
2135 };
2136 
2137 /*
2138  * RX sensitivity limits (values obtained from the reference driver.)
2139  */
2140 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = {
2141 	105, 140,
2142 	220, 270,
2143 	 85, 120,
2144 	170, 210,
2145 	125, 200,
2146 	200, 400,
2147 	 97,
2148 	100,
2149 	100,
2150 	390
2151 };
2152 
2153 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = {
2154 	120, 120,	/* min = max for performance bug in DSP. */
2155 	240, 240,	/* min = max for performance bug in DSP. */
2156 	 90, 120,
2157 	170, 210,
2158 	125, 200,
2159 	170, 400,
2160 	 95,
2161 	 95,
2162 	 95,
2163 	 390
2164 };
2165 
2166 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = {
2167 	105, 105,	/* min = max for performance bug in DSP. */
2168 	220, 220,	/* min = max for performance bug in DSP. */
2169 	 90, 120,
2170 	170, 210,
2171 	125, 200,
2172 	170, 400,
2173 	 95,
2174 	 95,
2175 	 95,
2176 	 390,
2177 };
2178 
2179 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = {
2180 	120, 155,
2181 	240, 290,
2182 	 90, 120,
2183 	170, 210,
2184 	125, 200,
2185 	170, 400,
2186 	 95,
2187 	 95,
2188 	 95,
2189 	 390,
2190 };
2191 
2192 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = {
2193 	105, 110,
2194 	192, 232,
2195 	 80, 145,
2196 	128, 232,
2197 	125, 175,
2198 	160, 310,
2199 	 97,
2200 	 97,
2201 	100,
2202 	390
2203 };
2204 
2205 static const struct iwn_sensitivity_limits iwn6235_sensitivity_limits = {
2206 	105, 110,
2207 	192, 232,
2208 	 80, 145,
2209 	128, 232,
2210 	125, 175,
2211 	160, 310,
2212 	100,
2213 	110,
2214 	110,
2215 	336
2216 };
2217 
2218 
2219 /* Get value from linux kernel 3.2.+ in Drivers/net/wireless/iwlwifi/iwl-2000.c*/
2220 static const struct iwn_sensitivity_limits iwn2030_sensitivity_limits = {
2221 	105,110,
2222 	128,232,
2223 	80,145,
2224 	128,232,
2225 	125,175,
2226 	160,310,
2227 	97,
2228 	97,
2229 	110
2230 };
2231 
2232 /* Map TID to TX scheduler's FIFO. */
2233 static const uint8_t iwn_tid2fifo[] = {
2234 	1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3
2235 };
2236 
2237 /* WiFi/WiMAX coexist event priority table for 6050. */
2238 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = {
2239 	{ 0x04, 0x03, 0x00, 0x00 },
2240 	{ 0x04, 0x03, 0x00, 0x03 },
2241 	{ 0x04, 0x03, 0x00, 0x03 },
2242 	{ 0x04, 0x03, 0x00, 0x03 },
2243 	{ 0x04, 0x03, 0x00, 0x00 },
2244 	{ 0x04, 0x03, 0x00, 0x07 },
2245 	{ 0x04, 0x03, 0x00, 0x00 },
2246 	{ 0x04, 0x03, 0x00, 0x03 },
2247 	{ 0x04, 0x03, 0x00, 0x03 },
2248 	{ 0x04, 0x03, 0x00, 0x00 },
2249 	{ 0x06, 0x03, 0x00, 0x07 },
2250 	{ 0x04, 0x03, 0x00, 0x00 },
2251 	{ 0x06, 0x06, 0x00, 0x03 },
2252 	{ 0x04, 0x03, 0x00, 0x07 },
2253 	{ 0x04, 0x03, 0x00, 0x00 },
2254 	{ 0x04, 0x03, 0x00, 0x00 }
2255 };
2256 
2257 /* Firmware errors. */
2258 static const char * const iwn_fw_errmsg[] = {
2259 	"OK",
2260 	"FAIL",
2261 	"BAD_PARAM",
2262 	"BAD_CHECKSUM",
2263 	"NMI_INTERRUPT_WDG",
2264 	"SYSASSERT",
2265 	"FATAL_ERROR",
2266 	"BAD_COMMAND",
2267 	"HW_ERROR_TUNE_LOCK",
2268 	"HW_ERROR_TEMPERATURE",
2269 	"ILLEGAL_CHAN_FREQ",
2270 	"VCC_NOT_STABLE",
2271 	"FH_ERROR",
2272 	"NMI_INTERRUPT_HOST",
2273 	"NMI_INTERRUPT_ACTION_PT",
2274 	"NMI_INTERRUPT_UNKNOWN",
2275 	"UCODE_VERSION_MISMATCH",
2276 	"HW_ERROR_ABS_LOCK",
2277 	"HW_ERROR_CAL_LOCK_FAIL",
2278 	"NMI_INTERRUPT_INST_ACTION_PT",
2279 	"NMI_INTERRUPT_DATA_ACTION_PT",
2280 	"NMI_TRM_HW_ER",
2281 	"NMI_INTERRUPT_TRM",
2282 	"NMI_INTERRUPT_BREAKPOINT",
2283 	"DEBUG_0",
2284 	"DEBUG_1",
2285 	"DEBUG_2",
2286 	"DEBUG_3",
2287 	"ADVANCED_SYSASSERT"
2288 };
2289 
2290 /* Find least significant bit that is set. */
2291 #define IWN_LSB(x)	((((x) - 1) & (x)) ^ (x))
2292 
2293 #define IWN_READ(sc, reg)						\
2294 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
2295 
2296 #define IWN_WRITE(sc, reg, val)						\
2297 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
2298 
2299 #define IWN_WRITE_1(sc, reg, val)					\
2300 	bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
2301 
2302 #define IWN_SETBITS(sc, reg, mask)					\
2303 	IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))
2304 
2305 #define IWN_CLRBITS(sc, reg, mask)					\
2306 	IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))
2307 
2308 #define IWN_BARRIER_WRITE(sc)						\
2309 	bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz,	\
2310 	    BUS_SPACE_BARRIER_WRITE)
2311 
2312 #define IWN_BARRIER_READ_WRITE(sc)					\
2313 	bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz,	\
2314 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
2315 
2316 #endif	/* __IF_IWNREG_H__ */
2317