1 /*
2 * Copyright � 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Wei Lin<wei.w.lin@intel.com>
26 * Yuting Yang<yuting.yang@intel.com>
27 */
28
29 #include "hw_interface_g75.h"
30 #include <math.h>
31
32 #define GENHW_NS_PER_TICK_RENDER_G75 80
33
34 static const STATE_SIP_CMD_G75 g_cInit_STATE_SIP_CMD_G75 = {
35 {
36 OP_LENGTH(SIZE32(STATE_SIP_CMD_G75)), // Length
37 GFXSUBOP_STATE_SIP, // InstructionSubOpcode
38 GFXOP_NONPIPELINED, // InstructionOpcode
39 PIPE_COMMON, // InstructionPipeline
40 INSTRUCTION_GFX // InstructionType
41 },
42 {
43 0
44 }
45 };
46
47 CONST GENHW_SSH_SETTINGS g_SSH_Settings_g75 = {
48 GENHW_SSH_INSTANCES,
49 GENHW_SSH_BINDING_TABLES,
50 GENHW_SSH_SURFACE_STATES,
51 GENHW_SSH_SURFACES_PER_BT,
52 GENHW_SSH_BINDING_TABLE_ALIGN
53 };
54
55 CONST GENHW_PIPECONTROL_PARAM g_PipeControlParam_g75 = {
56 NULL,
57 0,
58 GFX3DCONTROLOP_NOWRITE,
59 0,
60 FALSE,
61 FALSE,
62 FALSE,
63 FALSE,
64 TRUE,
65 FALSE,
66 FALSE
67 };
68
69 CONST GENHW_INDIRECT_PATCH_PARAM g_IndirectPatchParam_g75 = {
70 CMD_INDIRECT_INVALID,
71 NULL,
72 0,
73 NULL,
74 0
75 };
76
77 CONST GENHW_SURFACE_PLANES
78 g_cInitSurfacePlanes_g75[GENHW_PLANES_DEFINITION_COUNT] = {
79 // GENHW_PLANES_PL3
80 {3,
81 {
82 {GENHW_Y_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
83 {GENHW_U_PLANE, 2, 2, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
84 {GENHW_V_PLANE, 2, 2, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM}
85 }
86 },
87 // GENHW_PLANES_NV12
88 {1,
89 {
90 {GENHW_Y_PLANE, 1, 1, 1, 1, 4, 0,
91 GFX3DSTATE_SURFACEFORMAT_PLANAR_420_8}
92 }
93 },
94 // GENHW_PLANES_YUY2
95 {1,
96 {
97 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 2, 0,
98 GFX3DSTATE_SURFACEFORMAT_YCRCB_NORMAL}
99 }
100 },
101 // GENHW_PLANES_UYVY
102 {1,
103 {
104 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 2, 0,
105 GFX3DSTATE_SURFACEFORMAT_YCRCB_SWAPY}
106 }
107 },
108 // GENHW_PLANES_YVYU
109 {1,
110 {
111 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 2, 0,
112 GFX3DSTATE_SURFACEFORMAT_YCRCB_SWAPUV}
113 }
114 },
115 // GENHW_PLANES_VYUY
116 {1,
117 {
118 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 2, 0,
119 GFX3DSTATE_SURFACEFORMAT_YCRCB_SWAPUVY}
120 }
121 },
122 // GENHW_PLANES_ARGB
123 {1,
124 {
125 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 1, 0,
126 GFX3DSTATE_SURFACEFORMAT_B8G8R8A8_UNORM}
127 }
128 },
129 // GENHW_PLANES_XRGB
130 {1,
131 {
132 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 1, 0,
133 GFX3DSTATE_SURFACEFORMAT_B8G8R8X8_UNORM}
134 }
135 },
136 // GENHW_PLANES_ABGR
137 {1,
138 {
139 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 1, 0,
140 GFX3DSTATE_SURFACEFORMAT_R8G8B8A8_UNORM}
141 }
142 },
143 // GENHW_PLANES_XBGR
144 {1,
145 {
146 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 1, 0,
147 GFX3DSTATE_SURFACEFORMAT_R8G8B8X8_UNORM}
148 }
149 },
150 // GENHW_PLANES_RGB16
151 {1,
152 {
153 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 2, 0,
154 GFX3DSTATE_SURFACEFORMAT_B5G6R5_UNORM}
155 }
156 },
157 // GENHW_PLANES_R16U
158 {1,
159 {
160 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 2, 0,
161 GFX3DSTATE_SURFACEFORMAT_R16_UINT}
162 }
163 },
164 // GENHW_PLANES_R16S
165 {1,
166 {
167 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 2, 0,
168 GFX3DSTATE_SURFACEFORMAT_R16_SINT}
169 }
170 },
171 // GENHW_PLANES_R32U
172 {1,
173 {
174 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 1, 0,
175 GFX3DSTATE_SURFACEFORMAT_R32_UINT}
176 }
177 },
178 // GENHW_PLANES_R32S
179 {1,
180 {
181 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 1, 0,
182 GFX3DSTATE_SURFACEFORMAT_R32_SINT}
183 }
184 },
185 // GENHW_PLANES_R32F
186 {1,
187 {
188 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 1, 0,
189 GFX3DSTATE_SURFACEFORMAT_R32_FLOAT}
190 }
191 },
192 // GENHW_PLANES_V8U8
193 {1,
194 {
195 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 2, 0,
196 GFX3DSTATE_SURFACEFORMAT_R8G8_SNORM}
197 }
198 },
199 // GENHW_PLANES_R8G8_UNORM
200 {1,
201 {
202 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 2, 0,
203 GFX3DSTATE_SURFACEFORMAT_R8G8_UNORM}
204 }
205 },
206 // GENHW_PLANES_411P
207 {3,
208 {
209 {GENHW_Y_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
210 {GENHW_U_PLANE, 4, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
211 {GENHW_V_PLANE, 4, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM}
212 }
213 },
214 // GENHW_PLANES_411R
215 {3,
216 {
217 {GENHW_Y_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
218 {GENHW_U_PLANE, 1, 4, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
219 {GENHW_V_PLANE, 1, 4, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM}
220 }
221 },
222 // GENHW_PLANES_422H
223 {3,
224 {
225 {GENHW_Y_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
226 {GENHW_U_PLANE, 2, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
227 {GENHW_V_PLANE, 2, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM}
228 }
229 },
230 // GENHW_PLANES_422V
231 {3,
232 {
233 {GENHW_Y_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
234 {GENHW_U_PLANE, 1, 2, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
235 {GENHW_V_PLANE, 1, 2, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM}
236 }
237 },
238 // GENHW_PLANES_444P
239 {3,
240 {
241 {GENHW_Y_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
242 {GENHW_U_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
243 {GENHW_V_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM}
244 }
245 },
246 // GENHW_PLANES_RGBP
247 {3,
248 {
249 {GENHW_U_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
250 {GENHW_V_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
251 {GENHW_Y_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM}
252 }
253 },
254 // GENHW_PLANES_BGRP
255 {3,
256 {
257 {GENHW_U_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
258 {GENHW_Y_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
259 {GENHW_V_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM}
260 }
261 },
262 // GENHW_PLANES_AI44_PALLETE_0
263 {1,
264 {
265 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 4, 0,
266 GFX3DSTATE_SURFACEFORMAT_P4A4_UNORM_PALETTE_0}
267 }
268 },
269 // GENHW_PLANES_IA44_PALLETE_0
270 {1,
271 {
272 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 4, 0,
273 GFX3DSTATE_SURFACEFORMAT_A4P4_UNORM_PALETTE_0}
274 }
275 },
276 // GENHW_PLANES_P8_PALLETE_0
277 {1,
278 {
279 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 4, 0,
280 GFX3DSTATE_SURFACEFORMAT_P8_UNORM_PALETTE_0}
281 }
282 },
283 // GENHW_PLANES_A8P8_PALLETE_0
284 {1,
285 {
286 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 4, 0,
287 GFX3DSTATE_SURFACEFORMAT_P8A8_UNORM_PALETTE_0}
288 }
289 },
290 // GENHW_PLANES_AI44_PALLETE_1
291 {1,
292 {
293 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 4, 0,
294 GFX3DSTATE_SURFACEFORMAT_P4A4_UNORM_PALETTE_1}
295 }
296 },
297 // GENHW_PLANES_IA44_PALLETE_1
298 {1,
299 {
300 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 4, 0,
301 GFX3DSTATE_SURFACEFORMAT_A4P4_UNORM_PALETTE_1}
302 }
303 },
304 // GENHW_PLANES_P8_PALLETE_1
305 {1,
306 {
307 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 4, 0,
308 GFX3DSTATE_SURFACEFORMAT_P8_UNORM_PALETTE_1}
309 }
310 },
311 // GENHW_PLANES_A8P8_PALLETE_1
312 {1,
313 {
314 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 4, 0,
315 GFX3DSTATE_SURFACEFORMAT_P8A8_UNORM_PALETTE_1}
316 }
317 },
318 // GENHW_PLANES_AYUV
319 {1,
320 {
321 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 1, 0,
322 GFX3DSTATE_SURFACEFORMAT_R8B8G8A8_UNORM}
323 }
324 },
325 // GENHW_PLANES_STMM
326 {1,
327 {
328 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 4, 0,
329 GFX3DSTATE_SURFACEFORMAT_L8_UNORM}
330 }
331 },
332 // GENHW_PLANES_L8
333 {1,
334 {
335 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 4, 0,
336 GFX3DSTATE_SURFACEFORMAT_L8_UNORM}
337 }
338 },
339 // GENHW_PLANES_A8
340 {1,
341 {
342 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 4, 0,
343 GFX3DSTATE_SURFACEFORMAT_A8_UNORM}
344 }
345 },
346 // GENHW_PLANES_R8
347 {1,
348 {
349 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 4, 0,
350 GFX3DSTATE_SURFACEFORMAT_R8_UNORM}
351 }
352 },
353 // GENHW_PLANES_NV12_2PLANES
354 {2,
355 {
356 {GENHW_Y_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
357 {GENHW_U_PLANE, 2, 2, 1, 1, 2, 0, GFX3DSTATE_SURFACEFORMAT_R8G8_UNORM}
358 }
359 },
360 // GENHW_PLANES_R16_UNORM
361 {1,
362 {
363 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 2, 0,
364 GFX3DSTATE_SURFACEFORMAT_R16_UNORM}
365 }
366 },
367 // GENHW_PLANES_A16B16G16R16
368 {1,
369 {
370 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 0, 0,
371 GFX3DSTATE_SURFACEFORMAT_R16G16B16A16_UNORM}
372 }
373 },
374 // GENHW_PLANES_R10G10B10A2
375 {1,
376 {
377 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 1, 0,
378 GFX3DSTATE_SURFACEFORMAT_R10G10B10A2_UNORM}
379 }
380 },
381 // GENHW_PLANES_L16
382 {1,
383 {
384 {GENHW_GENERIC_PLANE, 1, 1, 1, 1, 2, 0,
385 GFX3DSTATE_SURFACEFORMAT_L16_UNORM}
386 }
387 },
388 // GENHW_PLANES_NV21
389 {2,
390 {
391 {GENHW_Y_PLANE, 1, 1, 1, 1, 4, 0, GFX3DSTATE_SURFACEFORMAT_R8_UNORM},
392 {GENHW_U_PLANE, 2, 2, 1, 1, 2, 0, GFX3DSTATE_SURFACEFORMAT_R8G8_UNORM}
393 }
394 },
395 // GENHW_PLANES_YV12
396 {1,
397 {
398 {GENHW_Y_PLANE, 1, 1, 1, 1, 4, 0,
399 GFX3DSTATE_SURFACEFORMAT_PLANAR_420_8}
400 }
401 },
402 // GENHW_PLANES_P016
403 {2,
404 {
405 {GENHW_Y_PLANE, 1, 1, 1, 1, 2, 0, GFX3DSTATE_SURFACEFORMAT_R16_UNORM},
406 {GENHW_U_PLANE, 2, 2, 1, 1, 1, 0,
407 GFX3DSTATE_SURFACEFORMAT_R16G16_UNORM}
408 }
409 },
410 // GENHW_PLANES_P010
411 {2,
412 {
413 {GENHW_Y_PLANE, 1, 1, 1, 1, 2, 0, GFX3DSTATE_SURFACEFORMAT_R16_UNORM},
414 {GENHW_U_PLANE, 2, 2, 1, 1, 1, 0,
415 GFX3DSTATE_SURFACEFORMAT_R16G16_UNORM}
416 }
417 }
418 };
419
420 CONST GENHW_HW_CAPS g_IntelGen_HwCaps_g75_gt1 = {
421 GENHW_SSH_SURFACES_PER_BT_MAX - 1,
422 GENHW_MEDIA_THREADS_MAX_G75_GT1,
423 512,
424 GENHW_URB_SIZE_MAX_G75,
425 GENHW_URB_ENTRIES_MAX_G75_GT1,
426 GENHW_URB_ENTRY_SIZE_MAX_G75,
427 GENHW_CURBE_SIZE_MAX_G75,
428 GENHW_INTERFACE_DESCRIPTOR_ENTRIES_MAX_G75,
429 GENHW_SUBSLICES_MAX_G75_GT1,
430 GENHW_EU_INDEX_MAX_G75,
431 GENHW_MEDIA_THREADS_PER_EU_MAX_G75,
432 GENHW_SIZE_REGISTERS_PER_THREAD_G75
433 };
434
435 CONST GENHW_HW_CAPS g_IntelGen_HwCaps_g75_gt2 = {
436 GENHW_SSH_SURFACES_PER_BT_MAX - 1,
437 GENHW_MEDIA_THREADS_MAX_G75_GT2,
438 512,
439 GENHW_URB_SIZE_MAX_G75,
440 GENHW_URB_ENTRIES_MAX_G75_GT2,
441 GENHW_URB_ENTRY_SIZE_MAX_G75,
442 GENHW_CURBE_SIZE_MAX_G75,
443 GENHW_INTERFACE_DESCRIPTOR_ENTRIES_MAX_G75,
444 GENHW_SUBSLICES_MAX_G75_GT2,
445 GENHW_EU_INDEX_MAX_G75,
446 GENHW_MEDIA_THREADS_PER_EU_MAX_G75,
447 GENHW_SIZE_REGISTERS_PER_THREAD_G75
448 };
449
450 CONST GENHW_HW_CAPS g_IntelGen_HwCaps_g75_gt3 = {
451 GENHW_SSH_SURFACES_PER_BT_MAX - 1,
452 GENHW_MEDIA_THREADS_MAX_G75_GT3,
453 512,
454 GENHW_URB_SIZE_MAX_G75,
455 GENHW_URB_ENTRIES_MAX_G75_GT2,
456 GENHW_URB_ENTRY_SIZE_MAX_G75,
457 GENHW_CURBE_SIZE_MAX_G75,
458 GENHW_INTERFACE_DESCRIPTOR_ENTRIES_MAX_G75,
459 GENHW_SUBSLICES_MAX_G75_GT3,
460 GENHW_EU_INDEX_MAX_G75,
461 GENHW_MEDIA_THREADS_PER_EU_MAX_G75,
462 GENHW_SIZE_REGISTERS_PER_THREAD_G75
463 };
464
465 CONST GENHW_GSH_SETTINGS g_GSH_Settings_g75 = {
466 GENHW_SYNC_SIZE_G75,
467 GENHW_MEDIA_STATES_G75,
468 GENHW_MEDIA_IDS_G75,
469 GENHW_CURBE_SIZE_G75,
470 GENHW_KERNEL_COUNT_G75,
471 GENHW_KERNEL_HEAP_G75,
472 GENHW_KERNEL_BLOCK_SIZE_G75,
473 0,
474 GENHW_MAX_SIP_SIZE
475 };
476
IntelGen_HwGetSurfaceMemoryObjectControl_g75(PGENHW_HW_INTERFACE pHwInterface,PGENHW_SURFACE_STATE_PARAMS pParams)477 DWORD IntelGen_HwGetSurfaceMemoryObjectControl_g75(PGENHW_HW_INTERFACE
478 pHwInterface,
479 PGENHW_SURFACE_STATE_PARAMS
480 pParams)
481 {
482 return pParams->MemObjCtl;
483 }
484
IntelGen_HwAssignBindingTable_g75(PGENHW_HW_INTERFACE pHwInterface,PINT piBindingTable)485 GENOS_STATUS IntelGen_HwAssignBindingTable_g75(PGENHW_HW_INTERFACE pHwInterface,
486 PINT piBindingTable)
487 {
488 PGENHW_SSH pSSH;
489 PGENHW_HW_COMMANDS pHwCommands;
490 PBINDING_TABLE_STATE_G5 pBindingTableEntry;
491 DWORD dwOffset;
492 INT i;
493 GENOS_STATUS eStatus;
494
495 GENHW_HW_ASSERT(pHwInterface);
496 GENHW_HW_ASSERT(piBindingTable);
497 GENHW_HW_ASSERT(pHwInterface->pSurfaceStateHeap);
498 GENHW_HW_ASSERT(pHwInterface->pHwCommands);
499
500 *piBindingTable = -1;
501 pSSH = pHwInterface->pSurfaceStateHeap;
502 pHwCommands = pHwInterface->pHwCommands;
503 eStatus = GENOS_STATUS_UNKNOWN;
504
505 if (pSSH->iCurrentBindingTable >=
506 pHwInterface->SshSettings.iBindingTables) {
507 GENHW_HW_ASSERTMESSAGE
508 ("Unable to allocate Binding Table. Exceeds Maximum.");
509 goto finish;
510 }
511
512 *piBindingTable = pSSH->iCurrentBindingTable;
513
514 dwOffset = IntelGen_HwGetCurBindingTableBase(pSSH) +
515 (*piBindingTable * pSSH->iBindingTableSize);
516
517 pBindingTableEntry =
518 (PBINDING_TABLE_STATE_G5) (pSSH->pSshBuffer + dwOffset);
519
520 for (i = pHwInterface->SshSettings.iSurfacesPerBT; i > 0;
521 i--, pBindingTableEntry++) {
522 *pBindingTableEntry = *(pHwCommands->pBindingTableState_g75);
523 }
524
525 ++pSSH->iCurrentBindingTable;
526
527 eStatus = GENOS_STATUS_SUCCESS;
528
529 finish:
530 return eStatus;
531 }
532
IntelGen_HwSetupSurfaceState_g75(PGENHW_HW_INTERFACE pHwInterface,PGENHW_SURFACE pSurface,PGENHW_SURFACE_STATE_PARAMS pParams,PINT piNumEntries,PGENHW_SURFACE_STATE_ENTRY * ppSurfaceEntries)533 GENOS_STATUS IntelGen_HwSetupSurfaceState_g75(PGENHW_HW_INTERFACE pHwInterface,
534 PGENHW_SURFACE pSurface,
535 PGENHW_SURFACE_STATE_PARAMS
536 pParams, PINT piNumEntries,
537 PGENHW_SURFACE_STATE_ENTRY *
538 ppSurfaceEntries)
539 {
540 PGENHW_HW_COMMANDS pHwCommands;
541 PGENHW_SSH pSSH;
542 PSURFACE_STATE_G7 pSurfaceState_g75;
543 PGENHW_SURFACE_STATE_ENTRY pSurfaceEntry;
544 PGENHW_PLANE_OFFSET pPlaneOffset;
545 INT i;
546 DWORD dwPixelsPerSampleUV;
547 UINT uSurfPitch;
548 UINT uBytesPerPixelShift;
549 UINT uYPlaneTopLvlIndexY;
550 UINT uYPlane2ndLvlIndexY;
551 UINT uYPlaneTopLvlIndexX;
552 UINT uYPlane2ndLvlIndexX;
553 UINT uUVPlaneTopLvlIndexY;
554 UINT uUVPlane2ndLvlIndexY;
555 UINT uUVPlaneTopLvlIndexX;
556 UINT uUVPlane2ndLvlIndexX;
557 RECT tempRect;
558 GENOS_STATUS eStatus;
559
560 GENHW_HW_ASSERT(pHwInterface);
561 GENHW_HW_ASSERT(pSurface);
562 GENHW_HW_ASSERT(pParams);
563 GENHW_HW_ASSERT(ppSurfaceEntries);
564 GENHW_HW_ASSERT(pHwInterface->pHwCommands);
565 GENHW_HW_ASSERT(pHwInterface->pSurfaceStateHeap);
566
567 eStatus = GENOS_STATUS_UNKNOWN;
568 pSSH = pHwInterface->pSurfaceStateHeap;
569 pHwCommands = pHwInterface->pHwCommands;
570 uSurfPitch = 0;
571
572 uYPlaneTopLvlIndexY = uYPlaneTopLvlIndexX = 0;
573 uYPlane2ndLvlIndexY = uYPlane2ndLvlIndexX = 0;
574 uUVPlaneTopLvlIndexY = uUVPlaneTopLvlIndexX = 0;
575 uUVPlane2ndLvlIndexY = uUVPlane2ndLvlIndexX = 0;
576
577 if (pParams->b32MWColorFillKernWA == TRUE) {
578 tempRect = pSurface->rcDst;
579 uSurfPitch = pSurface->dwPitch;
580
581 pSurface->YPlaneOffset.iXOffset = tempRect.left;
582 pSurface->YPlaneOffset.iYOffset = tempRect.top;
583
584 pSurface->rcDst.left =
585 tempRect.left & (GENHW_MACROBLOCK_SIZE - 1);
586 pSurface->rcDst.top =
587 tempRect.top & (GENHW_MACROBLOCK_SIZE - 1);
588
589 pSurface->dwWidth = pSurface->rcDst.right =
590 tempRect.right - (tempRect.left & ~0xf);
591 pSurface->dwHeight = pSurface->rcDst.bottom =
592 tempRect.bottom - (tempRect.top & ~0xf);
593
594 switch (pSurface->Format) {
595 case Format_A8B8G8R8:
596 case Format_X8B8G8R8:
597 case Format_A8R8G8B8:
598 case Format_X8R8G8B8:
599 uBytesPerPixelShift = 2;
600 break;
601 case Format_YUY2:
602 case Format_YUYV:
603 case Format_YVYU:
604 case Format_UYVY:
605 case Format_VYUY:
606 uBytesPerPixelShift = 1;
607 break;
608 case Format_NV12:
609 uBytesPerPixelShift = 0;
610 break;
611 default:
612 uBytesPerPixelShift = 0;
613 break;
614 }
615
616 uYPlaneTopLvlIndexY = tempRect.top >> GENHW_YTILE_H_SHIFTBITS;
617
618 uYPlane2ndLvlIndexY =
619 (tempRect.top & (GENHW_YTILE_H_ALIGNMENT -
620 1)) & ~(GENHW_MACROBLOCK_SIZE - 1);
621
622 uYPlaneTopLvlIndexX =
623 tempRect.left >> (GENHW_YTILE_W_SHIFTBITS -
624 uBytesPerPixelShift);
625
626 uYPlane2ndLvlIndexX = ((tempRect.left &
627 ((GENHW_YTILE_W_ALIGNMENT >>
628 uBytesPerPixelShift) -
629 1)) & ~(GENHW_MACROBLOCK_SIZE -
630 1)) >> (2 -
631 uBytesPerPixelShift);
632
633 if (pSurface->Format == Format_NV12) {
634 uUVPlaneTopLvlIndexY =
635 tempRect.top >> (GENHW_YTILE_H_SHIFTBITS + 1);
636 uUVPlane2ndLvlIndexY =
637 ((tempRect.top & ((GENHW_YTILE_H_ALIGNMENT << 1) -
638 1)) & ~(GENHW_MACROBLOCK_SIZE -
639 1)) >> 1;
640 uUVPlaneTopLvlIndexX = uYPlaneTopLvlIndexX;
641 uUVPlane2ndLvlIndexX = uYPlane2ndLvlIndexX;
642 }
643 }
644
645 GENHW_HW_CHK_STATUS(pHwInterface->pfnGetSurfaceStateEntries
646 (pHwInterface, pSurface, pParams, piNumEntries,
647 ppSurfaceEntries));
648
649 for (i = 0; i < *piNumEntries; i++) {
650 pSurfaceEntry = ppSurfaceEntries[i];
651
652 pSurfaceEntry->dwSurfStateOffset =
653 IntelGen_HwGetCurSurfaceStateBase(pSSH) +
654 (pSurfaceEntry->iSurfStateID * sizeof(SURFACE_STATE_G7));
655
656 pSurfaceState_g75 =
657 &pSurfaceEntry->pSurfaceState->
658 PacketSurfaceState_g75.cmdSurfaceState_g75;
659
660 *pSurfaceState_g75 = *(pHwCommands->pSurfaceState_g75);
661
662 if (pSurfaceEntry->YUVPlane == GENHW_U_PLANE ||
663 pSurfaceEntry->YUVPlane == GENHW_V_PLANE) {
664 pPlaneOffset =
665 (pSurfaceEntry->YUVPlane == GENHW_U_PLANE)
666 ? &pSurface->UPlaneOffset : &pSurface->VPlaneOffset;
667
668 if (pParams->b32MWColorFillKernWA == TRUE) {
669 pPlaneOffset->iSurfaceOffset +=
670 uUVPlaneTopLvlIndexY *
671 (uSurfPitch >>
672 GENHW_YTILE_W_SHIFTBITS) * GENHW_PAGE_SIZE;
673
674 pPlaneOffset->iSurfaceOffset +=
675 uUVPlaneTopLvlIndexX * GENHW_PAGE_SIZE;
676
677 pSurfaceState_g75->DW5.YOffset =
678 uUVPlane2ndLvlIndexY >> 1;
679 } else {
680 pSurfaceState_g75->DW5.YOffset =
681 pPlaneOffset->iYOffset >> 1;
682 }
683
684 if (pParams->bWidthInDword_UV) {
685 IntelGen_GetPixelsPerSample
686 (pSurface->Format, &dwPixelsPerSampleUV);
687 } else {
688 dwPixelsPerSampleUV = 1;
689 }
690
691 if (dwPixelsPerSampleUV == 1) {
692 pSurfaceState_g75->DW5.XOffset =
693 pPlaneOffset->iXOffset >> 2;
694 } else {
695 if (pParams->b32MWColorFillKernWA == TRUE) {
696 pSurfaceState_g75->DW5.XOffset =
697 uUVPlane2ndLvlIndexX >> 2;
698 } else {
699 pSurfaceState_g75->DW5.XOffset =
700 (pPlaneOffset->iXOffset /
701 (DWORD) sizeof(DWORD)) >> 2;
702 }
703 }
704 } else {
705 if (pParams->b32MWColorFillKernWA == TRUE) {
706 pSurface->dwOffset +=
707 uYPlaneTopLvlIndexY * (uSurfPitch /
708 GENHW_YTILE_W_ALIGNMENT)
709 * GENHW_PAGE_SIZE;
710
711 pSurface->dwOffset +=
712 uYPlaneTopLvlIndexX * GENHW_PAGE_SIZE;
713
714 pSurfaceState_g75->DW5.XOffset =
715 uYPlane2ndLvlIndexX >> 2;
716
717 pSurfaceState_g75->DW5.YOffset =
718 uYPlane2ndLvlIndexY >> 1;
719 } else {
720 pSurfaceState_g75->DW5.XOffset =
721 (pSurface->YPlaneOffset.iXOffset /
722 (DWORD) sizeof(DWORD)) >> 2;
723 pSurfaceState_g75->DW5.YOffset =
724 pSurface->YPlaneOffset.iYOffset >> 1;
725 }
726
727 if (pSurfaceEntry->dwFormat ==
728 GFX3DSTATE_SURFACEFORMAT_PLANAR_420_8) {
729 pSurfaceState_g75->DW6.XOffsetUVPlane = 0;
730 pSurfaceState_g75->DW6.YOffsetUVPlane =
731 (WORD) pSurface->dwHeight;
732 }
733 }
734
735 pSurfaceState_g75->DW0.SurfaceType =
736 (pSurface->dwDepth >
737 1) ? GFX3DSTATE_SURFACETYPE_3D : GFX3DSTATE_SURFACETYPE_2D;
738
739 pSurfaceState_g75->DW0.VerticalLineStrideOffset =
740 pSurfaceEntry->bVertStrideOffs;
741 pSurfaceState_g75->DW0.VerticalLineStride =
742 pSurfaceEntry->bVertStride;
743 pSurfaceState_g75->DW0.TileWalk = pSurfaceEntry->bTileWalk;
744 pSurfaceState_g75->DW0.TiledSurface =
745 pSurfaceEntry->bTiledSurface;
746 pSurfaceState_g75->DW0.SurfaceFormat = pSurfaceEntry->dwFormat;
747
748 pSurfaceState_g75->DW1.SurfaceBaseAddress = 0;
749 pSurfaceState_g75->DW2.Width = pSurfaceEntry->dwWidth - 1;
750 pSurfaceState_g75->DW2.Height = pSurfaceEntry->dwHeight - 1;
751 pSurfaceState_g75->DW3.SurfacePitch =
752 pSurfaceEntry->dwPitch - 1;
753 pSurfaceState_g75->DW3.Depth = MAX(1, pSurface->dwDepth) - 1;
754 pSurfaceState_g75->DW5.SurfaceObjectControlState =
755 pHwInterface->pfnGetSurfaceMemoryObjectControl
756 (pHwInterface, pParams);
757
758 GENHW_HW_CHK_STATUS(pHwInterface->pfnSetupSurfaceStateOs
759 (pHwInterface, pSurface, pParams,
760 pSurfaceEntry));
761 }
762
763 eStatus = GENOS_STATUS_SUCCESS;
764
765 finish:
766 return eStatus;
767 }
768
IntelGen_HwSetupBufferSurfaceState_g75(PGENHW_HW_INTERFACE pHwInterface,PGENHW_SURFACE pSurface,PGENHW_SURFACE_STATE_PARAMS pParams,PGENHW_SURFACE_STATE_ENTRY * ppSurfaceEntry)769 GENOS_STATUS IntelGen_HwSetupBufferSurfaceState_g75(PGENHW_HW_INTERFACE
770 pHwInterface,
771 PGENHW_SURFACE pSurface,
772 PGENHW_SURFACE_STATE_PARAMS
773 pParams,
774 PGENHW_SURFACE_STATE_ENTRY *
775 ppSurfaceEntry)
776 {
777 GENOS_STATUS eStatus;
778 PGENHW_SSH pSSH;
779 PSURFACE_STATE_G7 pState_g75;
780 PGENHW_SURFACE_STATE_ENTRY pSurfaceEntry;
781 BYTE iWidth;
782 USHORT iHeight;
783 USHORT iDepth;
784 DWORD bufferSize;
785
786 GENHW_HW_ASSERT(pHwInterface);
787 GENHW_HW_ASSERT(pSurface);
788 GENHW_HW_ASSERT(ppSurfaceEntry);
789 GENHW_HW_ASSERT(pSurface->dwWidth > 0);
790
791 eStatus = GENOS_STATUS_SUCCESS;
792 pSSH = pHwInterface->pSurfaceStateHeap;
793
794 pParams->Type = GENHW_SURFACE_TYPE_G7;
795
796 GENHW_HW_CHK_STATUS(pHwInterface->pfnAssignSurfaceState(pHwInterface,
797 GENHW_SURFACE_TYPE_G7,
798 ppSurfaceEntry));
799
800 pSurfaceEntry = *ppSurfaceEntry;
801 GENHW_HW_ASSERT(pSurfaceEntry);
802
803 switch (pSurface->Format) {
804 case Format_Buffer:
805 {
806 pSurfaceEntry->dwFormat =
807 GFX3DSTATE_SURFACEFORMAT_L8_UNORM;
808 break;
809 }
810 case Format_RAW:
811 {
812 pSurfaceEntry->dwFormat = GFX3DSTATE_SURFACEFORMAT_RAW;
813 break;
814 }
815 default:
816 {
817 GENHW_HW_ASSERTMESSAGE
818 ("Invalid Buffer Surface Format.");
819 break;
820 }
821 }
822
823 pSurfaceEntry->dwSurfStateOffset =
824 IntelGen_HwGetCurSurfaceStateBase(pSSH) +
825 (pSurfaceEntry->iSurfStateID * sizeof(SURFACE_STATE_G7));
826
827 bufferSize = pSurface->dwWidth - 1;
828
829 iWidth = (BYTE) (bufferSize & GFX_MASK(0, 6));
830 iHeight = (USHORT) ((bufferSize & GFX_MASK(7, 20)) >> 7);
831 if (Format_RAW == pSurface->Format) {
832 iDepth = (USHORT) ((bufferSize & GFX_MASK(21, 30)) >> 21);
833 } else {
834 iDepth = (USHORT) ((bufferSize & GFX_MASK(21, 26)) >> 21);
835 }
836
837 pState_g75 =
838 &pSurfaceEntry->pSurfaceState->PacketSurfaceState_g75.
839 cmdSurfaceState_g75;
840
841 *pState_g75 = *(pHwInterface->pHwCommands->pSurfaceState_g75);
842
843 pState_g75->DW0.SurfaceFormat = pSurfaceEntry->dwFormat;
844 pState_g75->DW0.TileWalk = 0;
845 pState_g75->DW0.TiledSurface = FALSE;
846 pState_g75->DW0.SurfaceType = GFX3DSTATE_SURFACETYPE_BUFFER;
847 pState_g75->DW1.SurfaceBaseAddress = 0;
848 pState_g75->DW2.Width = iWidth;
849 pState_g75->DW2.Height = iHeight;
850 pState_g75->DW3.Depth = iDepth;
851 pState_g75->DW3.SurfacePitch = 0;
852 pState_g75->DW5.SurfaceObjectControlState =
853 pHwInterface->pfnGetSurfaceMemoryObjectControl(pHwInterface,
854 pParams);
855
856 GENHW_HW_CHK_STATUS(pHwInterface->pfnSetupSurfaceStateOs(pHwInterface,
857 pSurface,
858 pParams,
859 pSurfaceEntry));
860
861 finish:
862 return eStatus;
863 }
864
IntelGen_HwSendPipelineSelectCmd_g75(PGENHW_HW_INTERFACE pHwInterface,PGENOS_COMMAND_BUFFER pCmdBuffer,DWORD dwGfxPipelineSelect)865 GENOS_STATUS IntelGen_HwSendPipelineSelectCmd_g75(PGENHW_HW_INTERFACE
866 pHwInterface,
867 PGENOS_COMMAND_BUFFER
868 pCmdBuffer,
869 DWORD dwGfxPipelineSelect)
870 {
871 GENOS_STATUS eStatus;
872 PPIPELINE_SELECT_CMD_G5 pPipelineSelectCmd;
873 DWORD dwCmdSize;
874
875 GENHW_HW_ASSERT(pHwInterface);
876 GENHW_HW_ASSERT(pCmdBuffer);
877
878 eStatus = GENOS_STATUS_SUCCESS;
879 dwCmdSize = sizeof(PIPELINE_SELECT_CMD_G5);
880
881 pPipelineSelectCmd =
882 (PPIPELINE_SELECT_CMD_G5) IntelGen_OsGetCmdBufferSpace(pCmdBuffer,
883 dwCmdSize);
884 GENHW_HW_CHK_NULL(pPipelineSelectCmd);
885
886 *pPipelineSelectCmd =
887 *(pHwInterface->pHwCommands->pPipelineSelectMedia);
888 pPipelineSelectCmd->DW0.PipelineSelect = dwGfxPipelineSelect;
889
890 IntelGen_OsAdjustCmdBufferFreeSpace(pCmdBuffer, dwCmdSize);
891
892 finish:
893 return eStatus;
894 }
895
IntelGen_HwSkipPipeControlCmdBb_g75(PGENHW_HW_INTERFACE pHwInterface,PGENHW_BATCH_BUFFER pBatchBuffer,PGENHW_PIPECONTROL_PARAM pParam)896 VOID IntelGen_HwSkipPipeControlCmdBb_g75(PGENHW_HW_INTERFACE pHwInterface,
897 PGENHW_BATCH_BUFFER pBatchBuffer,
898 PGENHW_PIPECONTROL_PARAM pParam)
899 {
900 GENHW_HW_ASSERT(pHwInterface);
901 GENHW_HW_ASSERT(pBatchBuffer);
902 GENHW_HW_ASSERT(pParam);
903 GENHW_HW_ASSERT((pBatchBuffer->iSize - pBatchBuffer->iCurrent) >=
904 (long)sizeof(PIPE_CONTROL_CMD_G7));
905
906 pBatchBuffer->iCurrent += sizeof(PIPE_CONTROL_CMD_G7);
907 }
908
IntelGen_HwLoadCurbeData_g75(PGENHW_HW_INTERFACE pHwInterface,PGENHW_MEDIA_STATE pCurMediaState,PVOID pData,INT iSize)909 INT IntelGen_HwLoadCurbeData_g75(PGENHW_HW_INTERFACE pHwInterface,
910 PGENHW_MEDIA_STATE pCurMediaState,
911 PVOID pData, INT iSize)
912 {
913 INT iOffset;
914 INT iCurbeSize;
915 PBYTE pPtrCurbe;
916 PGENHW_GSH pGSH;
917
918 iOffset = -1;
919 pGSH = (pHwInterface) ? pHwInterface->pGeneralStateHeap : NULL;
920 if (pGSH && pCurMediaState) {
921 iCurbeSize =
922 GENOS_ALIGN_CEIL(iSize, GENHW_CURBE_BLOCK_ALIGN_G7);
923 if (pCurMediaState->iCurbeOffset + iCurbeSize <=
924 (int)pGSH->dwSizeCurbe) {
925 iOffset = pCurMediaState->iCurbeOffset;
926 pCurMediaState->iCurbeOffset += iCurbeSize;
927
928 if (pData) {
929 pPtrCurbe = pGSH->pGSH +
930 pGSH->pCurMediaState->dwOffset +
931 pGSH->dwOffsetCurbe + iOffset;
932
933 GENOS_SecureMemcpy(pPtrCurbe, iSize, pData,
934 iSize);
935
936 iCurbeSize -= iSize;
937 if (iCurbeSize > 0) {
938 GENOS_ZeroMemory(pPtrCurbe + iSize,
939 iCurbeSize);
940 }
941 }
942 }
943 }
944
945 return iOffset;
946 }
947
IntelGen_HwInitInterfaceDescriptor_g75(PGENHW_HW_INTERFACE pHwInterface,PBYTE pBase,DWORD dwBase,DWORD dwOffsetID)948 VOID IntelGen_HwInitInterfaceDescriptor_g75(PGENHW_HW_INTERFACE pHwInterface,
949 PBYTE pBase,
950 DWORD dwBase, DWORD dwOffsetID)
951 {
952 PINTERFACE_DESCRIPTOR_DATA_G6 pInterfaceDescriptor;
953
954 pInterfaceDescriptor =
955 (INTERFACE_DESCRIPTOR_DATA_G6 *) (pBase + dwOffsetID);
956 *pInterfaceDescriptor =
957 *(pHwInterface->pHwCommands->pInterfaceDescriptor_g75);
958 }
959
IntelGen_HwSetupInterfaceDescriptor_g75(PGENHW_HW_INTERFACE pHwInterface,PGENHW_MEDIA_STATE pMediaState,PGENHW_KRN_ALLOCATION pKernelAllocation,PGENHW_INTERFACE_DESCRIPTOR_PARAMS pInterfaceDescriptorParams,PGENHW_GPGPU_WALKER_PARAMS pGpGpuWalkerParams)960 VOID IntelGen_HwSetupInterfaceDescriptor_g75(PGENHW_HW_INTERFACE pHwInterface,
961 PGENHW_MEDIA_STATE pMediaState,
962 PGENHW_KRN_ALLOCATION
963 pKernelAllocation,
964 PGENHW_INTERFACE_DESCRIPTOR_PARAMS
965 pInterfaceDescriptorParams,
966 PGENHW_GPGPU_WALKER_PARAMS
967 pGpGpuWalkerParams)
968 {
969 PGENHW_GSH pGSH;
970 PGENHW_SSH pSSH;
971 PINTERFACE_DESCRIPTOR_DATA_G6 pInterfaceDescriptor;
972 DWORD dwBTOffset;
973
974 pGSH = pHwInterface->pGeneralStateHeap;
975 pSSH = pHwInterface->pSurfaceStateHeap;
976
977 dwBTOffset = IntelGen_HwGetCurBindingTableBase(pSSH) +
978 (pInterfaceDescriptorParams->iBindingTableID *
979 pSSH->iBindingTableSize);
980
981 pInterfaceDescriptor = (PINTERFACE_DESCRIPTOR_DATA_G6)
982 (pGSH->pGSH +
983 pMediaState->dwOffset +
984 pGSH->dwOffsetMediaID +
985 (pInterfaceDescriptorParams->iMediaID * pGSH->dwSizeMediaID));
986
987 pInterfaceDescriptor->DW0.KernelStartPointer =
988 pKernelAllocation->dwOffset >> 6;
989 pInterfaceDescriptor->DW3.BindingTablePointer = dwBTOffset >> 5;
990 pInterfaceDescriptor->DW4.ConstantURBEntryReadOffset =
991 pInterfaceDescriptorParams->iCurbeOffset >> 5;
992 pInterfaceDescriptor->DW4.ConstantURBEntryReadLength =
993 pInterfaceDescriptorParams->iCurbeLength >> 5;
994
995 if (pGpGpuWalkerParams && pGpGpuWalkerParams->GpGpuEnable) {
996 pInterfaceDescriptor->DW5.BarrierEnable = 1;
997 pInterfaceDescriptor->DW5.NumberofThreadsInGPGPUGroup =
998 pGpGpuWalkerParams->ThreadWidth *
999 pGpGpuWalkerParams->ThreadHeight;
1000 pInterfaceDescriptor->DW5.SharedLocalMemorySize =
1001 GENOS_ALIGN_CEIL(pGpGpuWalkerParams->SLMSize, 4) >> 2;
1002 pInterfaceDescriptor->DW6.CrsThdConDataRdLn =
1003 pInterfaceDescriptorParams->iCrsThrdConstDataLn >> 5;
1004 } else {
1005 pInterfaceDescriptor->DW5.Value = 0;
1006 pInterfaceDescriptor->DW6.Value = 0;
1007 }
1008 }
1009
IntelGen_HwSendCurbeLoad_g75(PGENHW_HW_INTERFACE pHwInterface,PGENOS_COMMAND_BUFFER pCmdBuffer)1010 GENOS_STATUS IntelGen_HwSendCurbeLoad_g75(PGENHW_HW_INTERFACE pHwInterface,
1011 PGENOS_COMMAND_BUFFER pCmdBuffer)
1012 {
1013 PMEDIA_CURBE_LOAD_CMD_G6 pMediaCurbeLoad;
1014 PGENHW_HW_COMMANDS pHwCommands;
1015 PGENHW_GSH pGSH;
1016 GENOS_STATUS eStatus;
1017 DWORD dwCmdSize;
1018
1019 GENHW_HW_ASSERT(pHwInterface);
1020 GENHW_HW_ASSERT(pCmdBuffer);
1021 GENHW_HW_ASSERT(pHwInterface->pHwCommands);
1022 GENHW_HW_ASSERT(pHwInterface->pGeneralStateHeap);
1023 GENHW_HW_ASSERT(pHwInterface->pGeneralStateHeap->pCurMediaState);
1024
1025 eStatus = GENOS_STATUS_SUCCESS;
1026 dwCmdSize = sizeof(MEDIA_CURBE_LOAD_CMD_G6);
1027 pHwCommands = pHwInterface->pHwCommands;
1028 pGSH = pHwInterface->pGeneralStateHeap;
1029
1030 pMediaCurbeLoad =
1031 (PMEDIA_CURBE_LOAD_CMD_G6) IntelGen_OsGetCmdBufferSpace(pCmdBuffer,
1032 dwCmdSize);
1033 GENHW_HW_CHK_NULL(pMediaCurbeLoad);
1034
1035 *pMediaCurbeLoad = *(pHwCommands->pMediaCurbeLoad_g75);
1036
1037 if (pGSH->pCurMediaState->iCurbeOffset != 0) {
1038 pMediaCurbeLoad->DW2.CURBETotalDataLength =
1039 pGSH->pCurMediaState->iCurbeOffset;
1040 } else {
1041 goto finish;
1042 }
1043
1044 pMediaCurbeLoad->DW3.CURBEDataStartAddress =
1045 pGSH->pCurMediaState->dwOffset + pGSH->dwOffsetCurbe;
1046
1047 IntelGen_OsAdjustCmdBufferFreeSpace(pCmdBuffer, dwCmdSize);
1048
1049 finish:
1050 return eStatus;
1051 }
1052
IntelGen_HwSendIDLoad_g75(PGENHW_HW_INTERFACE pHwInterface,PGENOS_COMMAND_BUFFER pCmdBuffer)1053 GENOS_STATUS IntelGen_HwSendIDLoad_g75(PGENHW_HW_INTERFACE pHwInterface,
1054 PGENOS_COMMAND_BUFFER pCmdBuffer)
1055 {
1056 PMEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD_G6 pMediaIDLoad;
1057 PGENHW_HW_COMMANDS pHwCommands;
1058 PGENHW_GSH pGSH;
1059 GENOS_STATUS eStatus;
1060 DWORD dwCmdSize;
1061
1062 GENHW_HW_ASSERT(pHwInterface);
1063 GENHW_HW_ASSERT(pCmdBuffer);
1064 GENHW_HW_ASSERT(pHwInterface->pHwCommands);
1065 GENHW_HW_ASSERT(pHwInterface->pGeneralStateHeap);
1066 GENHW_HW_ASSERT(pHwInterface->pGeneralStateHeap->pCurMediaState);
1067
1068 eStatus = GENOS_STATUS_SUCCESS;
1069 dwCmdSize = sizeof(MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD_G6);
1070 pHwCommands = pHwInterface->pHwCommands;
1071 pGSH = pHwInterface->pGeneralStateHeap;
1072
1073 pMediaIDLoad = (PMEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD_G6)
1074 IntelGen_OsGetCmdBufferSpace(pCmdBuffer, dwCmdSize);
1075 GENHW_HW_CHK_NULL(pMediaIDLoad);
1076
1077 *pMediaIDLoad = *(pHwCommands->pMediaIDLoad_g75);
1078
1079 pMediaIDLoad->DW2.InterfaceDescriptorLength =
1080 pHwInterface->GshSettings.iMediaIDs * pGSH->dwSizeMediaID;
1081
1082 pMediaIDLoad->DW3.InterfaceDescriptorStartAddress =
1083 pGSH->pCurMediaState->dwOffset + pGSH->dwOffsetMediaID;
1084
1085 IntelGen_OsAdjustCmdBufferFreeSpace(pCmdBuffer, dwCmdSize);
1086
1087 finish:
1088 return eStatus;
1089 }
1090
IntelGen_HwSendGpGpuWalkerState_g75(PGENHW_HW_INTERFACE pHwInterface,PGENOS_COMMAND_BUFFER pCmdBuffer,PGENHW_GPGPU_WALKER_PARAMS pGpGpuWalkerParams)1091 GENOS_STATUS IntelGen_HwSendGpGpuWalkerState_g75(PGENHW_HW_INTERFACE
1092 pHwInterface,
1093 PGENOS_COMMAND_BUFFER
1094 pCmdBuffer,
1095 PGENHW_GPGPU_WALKER_PARAMS
1096 pGpGpuWalkerParams)
1097 {
1098 GENOS_STATUS eStatus;
1099 PGPGPU_WALKER_CMD_G75 pGpuWalker;
1100 DWORD dwCmdSize;
1101
1102 eStatus = GENOS_STATUS_SUCCESS;
1103 dwCmdSize = sizeof(GPGPU_WALKER_CMD_G75);
1104
1105 pGpuWalker =
1106 (PGPGPU_WALKER_CMD_G75) IntelGen_OsGetCmdBufferSpace(pCmdBuffer,
1107 dwCmdSize);
1108 GENHW_HW_CHK_NULL(pGpuWalker);
1109
1110 *pGpuWalker = *(pHwInterface->pHwCommands->pGpGpuWalker_g75);
1111
1112 pGpuWalker->DW1.InterfaceDescriptorOffset =
1113 pGpGpuWalkerParams->InterfaceDescriptorOffset;
1114 pGpuWalker->DW2.SIMDSize = 2;
1115 pGpuWalker->DW2.ThreadWidthCounterMax =
1116 pGpGpuWalkerParams->ThreadWidth - 1;
1117 pGpuWalker->DW2.ThreadHeightCounterMax =
1118 pGpGpuWalkerParams->ThreadHeight - 1;
1119 pGpuWalker->DW2.ThreadDepthCounterMax = 0;
1120 pGpuWalker->DW3.ThreadGroupIDStartingX = 0;
1121 pGpuWalker->DW4.ThreadGroupIDDimensionX =
1122 pGpGpuWalkerParams->GroupWidth;
1123 pGpuWalker->DW5.ThreadGroupIDStartingY = 0;
1124 pGpuWalker->DW6.ThreadGroupIDDimensionY =
1125 pGpGpuWalkerParams->GroupHeight;
1126 pGpuWalker->DW7.ThreadGroupIDStartingZ = 0;
1127 pGpuWalker->DW8.ThreadGroupIDDimensionZ = 1;
1128 pGpuWalker->DW9.RightExecutionMask = 0xffffffff;
1129 pGpuWalker->DW10.BottomExecutionMask = 0xffffffff;
1130
1131 IntelGen_OsAdjustCmdBufferFreeSpace(pCmdBuffer, dwCmdSize);
1132
1133 finish:
1134 return eStatus;
1135 }
1136
IntelGen_HwAddMediaObjectCmdBb_g75(PGENHW_HW_INTERFACE pHwInterface,PGENHW_BATCH_BUFFER pBatchBuffer,PGENHW_HW_MEDIAOBJECT_PARAM pParam)1137 VOID IntelGen_HwAddMediaObjectCmdBb_g75(PGENHW_HW_INTERFACE pHwInterface,
1138 PGENHW_BATCH_BUFFER pBatchBuffer,
1139 PGENHW_HW_MEDIAOBJECT_PARAM pParam)
1140 {
1141 PBYTE pBuffer;
1142 PMEDIA_OBJECT_HEADER_G6 pCmd;
1143
1144 GENHW_HW_ASSERT(pHwInterface);
1145 GENHW_HW_ASSERT(pBatchBuffer);
1146 GENHW_HW_ASSERT(pBatchBuffer->pData);
1147 GENHW_HW_ASSERT(pParam);
1148 GENHW_HW_ASSERT(pParam->dwMediaObjectSize >=
1149 sizeof(MEDIA_OBJECT_HEADER_G6));
1150 GENHW_HW_ASSERT((pBatchBuffer->iSize - pBatchBuffer->iCurrent) >=
1151 (long)sizeof(MEDIA_OBJECT_HEADER_G6));
1152
1153 pBuffer = pBatchBuffer->pData + pBatchBuffer->iCurrent;
1154 pCmd = (PMEDIA_OBJECT_HEADER_G6) pBuffer;
1155 *pCmd = g_cInit_MEDIA_OBJECT_HEADER_G6;
1156
1157 pCmd->DW0.DWordLength =
1158 OP_LENGTH(SIZE_IN_DW(pParam->dwMediaObjectSize));
1159 pCmd->DW1.InterfaceDescriptorOffset = pParam->dwIDOffset;
1160
1161 pBatchBuffer->iCurrent += sizeof(MEDIA_OBJECT_HEADER_G6);
1162 }
1163
IntelGen_HwConvertToNanoSeconds_g75(PGENHW_HW_INTERFACE pHwInterface,UINT64 iTicks,PUINT64 piNs)1164 VOID IntelGen_HwConvertToNanoSeconds_g75(PGENHW_HW_INTERFACE pHwInterface,
1165 UINT64 iTicks, PUINT64 piNs)
1166 {
1167 GENHW_HW_ASSERT(pHwInterface);
1168 GENHW_HW_ASSERT(piNs);
1169
1170 *piNs = iTicks * GENHW_NS_PER_TICK_RENDER_G75;
1171 }
1172
IntelGen_HwInitCommands_g75(PGENHW_HW_INTERFACE pHwInterface)1173 VOID IntelGen_HwInitCommands_g75(PGENHW_HW_INTERFACE pHwInterface)
1174 {
1175 PGENHW_HW_COMMANDS pHwCommands;
1176
1177 pHwInterface->pfnInitCommandsCommon(pHwInterface);
1178 pHwCommands = pHwInterface->pHwCommands;
1179
1180 pHwCommands->dwMediaObjectHeaderCmdSize =
1181 sizeof(MEDIA_OBJECT_HEADER_G6);
1182
1183 pHwCommands->pPipelineSelectMedia =
1184 &g_cInit_PIPELINE_SELECT_CMD_MEDIA_G575;
1185
1186 pHwCommands->pcPipeControlParam = &g_PipeControlParam_g75;
1187 pHwCommands->pcPatchParam = &g_IndirectPatchParam_g75;
1188 }
1189
IntelGen_HwGetMediaWalkerStatus_g75(PGENHW_HW_INTERFACE pHwInterface)1190 BOOL IntelGen_HwGetMediaWalkerStatus_g75(PGENHW_HW_INTERFACE pHwInterface)
1191 {
1192 if (pHwInterface->MediaWalkerMode == GENHW_MEDIA_WALKER_DISABLED) {
1193 return FALSE;
1194 }
1195
1196 return TRUE;
1197 }
1198
IntelGen_HwGetMediaWalkerBlockSize_g75(PGENHW_HW_INTERFACE pHwInterface)1199 UINT IntelGen_HwGetMediaWalkerBlockSize_g75(PGENHW_HW_INTERFACE pHwInterface)
1200 {
1201 return 32;
1202 }
1203
IntelGen_HwAddPipeControlCmdBb_g75(PGENHW_HW_INTERFACE pHwInterface,PGENHW_BATCH_BUFFER pBatchBuffer,PGENHW_PIPECONTROL_PARAM pParam)1204 VOID IntelGen_HwAddPipeControlCmdBb_g75(PGENHW_HW_INTERFACE pHwInterface,
1205 PGENHW_BATCH_BUFFER pBatchBuffer,
1206 PGENHW_PIPECONTROL_PARAM pParam)
1207 {
1208 PBYTE pBuffer;
1209 PPIPE_CONTROL_CMD_G7 pCmd;
1210
1211 GENHW_HW_ASSERT(pHwInterface);
1212 GENHW_HW_ASSERT(pBatchBuffer);
1213 GENHW_HW_ASSERT(pParam);
1214 GENHW_HW_ASSERT((pBatchBuffer->iSize - pBatchBuffer->iCurrent) >=
1215 (long)sizeof(PIPE_CONTROL_CMD_G7));
1216
1217 pBuffer = pBatchBuffer->pData + pBatchBuffer->iCurrent;
1218 pCmd = (PPIPE_CONTROL_CMD_G7) pBuffer;
1219 *pCmd = g_cInit_PIPE_CONTROL_CMD_G7;
1220
1221 pCmd->DW1.StateCacheInvalidationEnable = pParam->dwInvalidateStateCache;
1222 pCmd->DW1.ConstantCacheInvalidationEnable =
1223 pParam->dwInvaliateConstantCache;
1224 pCmd->DW1.VFCacheInvalidationEnable = pParam->dwInvalidateVFECache;
1225 pCmd->DW1.InstructionCacheInvalidateEnable =
1226 pParam->dwInvalidateInstructionCache;
1227 pCmd->DW1.RenderTargetCacheFlushEnable =
1228 pParam->dwFlushRenderTargetCache;
1229 pCmd->DW1.TLBInvalidate = pParam->dwTlbInvalidate;
1230 pCmd->DW1.PostSyncOperation = pParam->Operation;
1231 pCmd->DW1.CSStall = pParam->dwCSStall;
1232 pCmd->DW3.ImmediateData = pParam->dwImmData;
1233 pCmd->DW1.DestinationAddressType = 0;
1234
1235 pCmd->DW1.DCFlushEnable = TRUE;
1236 pCmd->DW1.PIPE_CONTROLFlushEnable = TRUE;
1237
1238 pBatchBuffer->iCurrent += sizeof(PIPE_CONTROL_CMD_G7);
1239 }
1240
IntelGen_HwSendMISetPredicateCmd_g75(PGENHW_HW_INTERFACE pHwInterface,PGENOS_COMMAND_BUFFER pCmdBuffer,DWORD PredicateEnable)1241 GENOS_STATUS IntelGen_HwSendMISetPredicateCmd_g75(PGENHW_HW_INTERFACE
1242 pHwInterface,
1243 PGENOS_COMMAND_BUFFER
1244 pCmdBuffer,
1245 DWORD PredicateEnable)
1246 {
1247 GENOS_STATUS eStatus;
1248 PMI_SET_PREDICATE_CMD_G75 pMiSetPredicate;
1249 DWORD dwCmdSize;
1250
1251 eStatus = GENOS_STATUS_SUCCESS;
1252 dwCmdSize = sizeof(MI_SET_PREDICATE_CMD_G75);
1253
1254 pMiSetPredicate =
1255 (PMI_SET_PREDICATE_CMD_G75) IntelGen_OsGetCmdBufferSpace(pCmdBuffer,
1256 dwCmdSize);
1257 GENHW_HW_CHK_NULL(pMiSetPredicate);
1258
1259 *pMiSetPredicate = g_cInit_MI_SET_PREDICATE_CMD_G75;
1260 pMiSetPredicate->DW0.Enable = PredicateEnable;
1261
1262 IntelGen_OsAdjustCmdBufferFreeSpace(pCmdBuffer, dwCmdSize);
1263
1264 finish:
1265 return eStatus;
1266 }
1267
IntelGen_HwSendMIArbCheck_g75(PGENHW_HW_INTERFACE pHwInterface,PGENOS_COMMAND_BUFFER pCmdBuffer)1268 GENOS_STATUS IntelGen_HwSendMIArbCheck_g75(PGENHW_HW_INTERFACE pHwInterface,
1269 PGENOS_COMMAND_BUFFER pCmdBuffer)
1270 {
1271 GENOS_STATUS eStatus;
1272 PMI_ARB_CHECK_CMD_G75 pArbChkCmd;
1273 DWORD dwCmdSize;
1274
1275 GENHW_HW_ASSERT(pHwInterface);
1276 GENHW_HW_ASSERT(pCmdBuffer);
1277 GENHW_HW_ASSERT(pHwInterface->pHwCommands);
1278
1279 eStatus = GENOS_STATUS_SUCCESS;
1280 dwCmdSize = sizeof(MI_ARB_CHECK_CMD_G75);
1281 pArbChkCmd =
1282 (PMI_ARB_CHECK_CMD_G75) IntelGen_OsGetCmdBufferSpace(pCmdBuffer,
1283 dwCmdSize);
1284
1285 GENHW_HW_CHK_NULL(pArbChkCmd);
1286
1287 *pArbChkCmd = *pHwInterface->pHwCommands->pArbCheck_g75;
1288
1289 IntelGen_OsAdjustCmdBufferFreeSpace(pCmdBuffer, dwCmdSize);
1290
1291 finish:
1292 return eStatus;
1293 }
1294
IntelGen_HwSelectWalkerStateMode_g75(PGENHW_HW_INTERFACE pHwInterface)1295 GENHW_MEDIA_WALKER_MODE IntelGen_HwSelectWalkerStateMode_g75(PGENHW_HW_INTERFACE
1296 pHwInterface)
1297 {
1298 GENHW_MEDIA_WALKER_MODE Mode;
1299
1300 Mode = pHwInterface->MediaWalkerMode;
1301
1302 if (pHwInterface->Platform.GtType == GTTYPE_GT1) {
1303 Mode = GENHW_MEDIA_WALKER_REPEL_MODE;
1304 } else if (pHwInterface->Platform.GtType == GTTYPE_GT2) {
1305 if (pHwInterface->MediaWalkerMode !=
1306 GENHW_MEDIA_WALKER_REPEL_MODE) {
1307 Mode = GENHW_MEDIA_WALKER_DUAL_MODE;
1308 }
1309 } else if (pHwInterface->Platform.GtType == GTTYPE_GT3) {
1310 if ((pHwInterface->MediaWalkerMode !=
1311 GENHW_MEDIA_WALKER_REPEL_MODE)
1312 && (pHwInterface->MediaWalkerMode !=
1313 GENHW_MEDIA_WALKER_DUAL_MODE)) {
1314 Mode = GENHW_MEDIA_WALKER_QUAD_MODE;
1315 }
1316 }
1317
1318 return Mode;
1319 }
1320
IntelGen_HwSendWalkerState_g75(PGENHW_HW_INTERFACE pHwInterface,PGENOS_COMMAND_BUFFER pCmdBuffer,PGENHW_WALKER_PARAMS pWalkerParams)1321 GENOS_STATUS IntelGen_HwSendWalkerState_g75(PGENHW_HW_INTERFACE pHwInterface,
1322 PGENOS_COMMAND_BUFFER pCmdBuffer,
1323 PGENHW_WALKER_PARAMS pWalkerParams)
1324 {
1325 MEDIA_OBJECT_WALKER_CMD_G6 MediaObjWalker;
1326 PMEDIA_OBJECT_WALKER_CMD_G6 pMediaObjWalker;
1327 GENHW_MEDIA_WALKER_MODE Mode;
1328 GENOS_STATUS eStatus;
1329
1330 eStatus = GENOS_STATUS_SUCCESS;
1331 Mode = IntelGen_HwSelectWalkerStateMode_g75(pHwInterface);
1332 pMediaObjWalker = &MediaObjWalker;
1333 *pMediaObjWalker = *pHwInterface->pHwCommands->pMediaWalker_g75;
1334
1335 pMediaObjWalker->DW0.Length =
1336 OP_LENGTH(SIZE32(MEDIA_OBJECT_WALKER_CMD_G6)) +
1337 pWalkerParams->InlineDataLength / sizeof(DWORD);
1338 pMediaObjWalker->DW1.InterfaceDescriptorOffset =
1339 pWalkerParams->InterfaceDescriptorOffset;
1340 pMediaObjWalker->DW2.UseScoreboard =
1341 pHwInterface->VfeScoreboard.ScoreboardEnable;
1342 pMediaObjWalker->DW5.ScoreboardMask =
1343 pHwInterface->VfeScoreboard.ScoreboardMask;
1344 pMediaObjWalker->DW6.Value = 0;
1345
1346 pMediaObjWalker->DW6.ColorCountMinusOne =
1347 pWalkerParams->ColorCountMinusOne;
1348
1349 switch (Mode) {
1350 case GENHW_MEDIA_WALKER_REPEL_MODE:
1351 pMediaObjWalker->DW6.Repel = 1;
1352 break;
1353 case GENHW_MEDIA_WALKER_DUAL_MODE:
1354 pMediaObjWalker->DW6.DualMode = 1;
1355
1356 break;
1357 case GENHW_MEDIA_WALKER_QUAD_MODE:
1358 pMediaObjWalker->DW6.QuadMode = 1;
1359 break;
1360 default:
1361 GENHW_HW_ASSERTMESSAGE
1362 ("Unsupported mode of media walker for G75");
1363 eStatus = GENOS_STATUS_UNKNOWN;
1364 goto finish;
1365 }
1366
1367 pMediaObjWalker->DW6.MidLoopUnitX = pWalkerParams->MidLoopUnitX;
1368 pMediaObjWalker->DW6.MidLoopUnitY = pWalkerParams->MidLoopUnitY;
1369 pMediaObjWalker->DW6.MidLoopExtraSteps =
1370 pWalkerParams->MiddleLoopExtraSteps;
1371
1372 pMediaObjWalker->DW7.Value = pWalkerParams->LoopExecCount.value;
1373 pMediaObjWalker->DW8.Value = pWalkerParams->BlockResolution.value;
1374 pMediaObjWalker->DW9.Value = pWalkerParams->LocalStart.value;
1375 pMediaObjWalker->DW10.Value = pWalkerParams->LocalEnd.value;
1376 pMediaObjWalker->DW11.Value = pWalkerParams->LocalOutLoopStride.value;
1377 pMediaObjWalker->DW12.Value = pWalkerParams->LocalInnerLoopUnit.value;
1378 pMediaObjWalker->DW13.Value = pWalkerParams->GlobalResolution.value;
1379 pMediaObjWalker->DW14.Value = pWalkerParams->GlobalStart.value;
1380 pMediaObjWalker->DW15.Value =
1381 pWalkerParams->GlobalOutlerLoopStride.value;
1382 pMediaObjWalker->DW16.Value = pWalkerParams->GlobalInnerLoopUnit.value;
1383
1384 if ((Mode == GENHW_MEDIA_WALKER_QUAD_MODE)
1385 && ((pHwInterface->Platform.GtType == GTTYPE_GT3)
1386 || pHwInterface->bRequestSingleSlice)) {
1387 pHwInterface->pfnSendMISetPredicateCmd(pHwInterface, pCmdBuffer,
1388 MI_SET_PREDICATE_ENABLE_ON_CLEAR);
1389
1390 GENHW_HW_CHK_STATUS(IntelGen_OsAddCommand(pCmdBuffer,
1391 pMediaObjWalker,
1392 sizeof
1393 (MEDIA_OBJECT_WALKER_CMD_G6)));
1394
1395 if (pWalkerParams->InlineDataLength) {
1396 GENHW_HW_CHK_STATUS(IntelGen_OsAddCommand(pCmdBuffer,
1397 pWalkerParams->
1398 pInlineData,
1399 pWalkerParams->
1400 InlineDataLength));
1401 }
1402
1403 pHwInterface->pfnSendMISetPredicateCmd(pHwInterface,
1404 pCmdBuffer,
1405 MI_SET_PREDICATE_ENABLE_ON_SET);
1406
1407 pMediaObjWalker->DW6.Repel = 0;
1408 pMediaObjWalker->DW6.DualMode = 1;
1409 pMediaObjWalker->DW6.QuadMode = 0;
1410 GENHW_HW_CHK_STATUS(IntelGen_OsAddCommand(pCmdBuffer,
1411 pMediaObjWalker,
1412 sizeof
1413 (MEDIA_OBJECT_WALKER_CMD_G6)));
1414
1415 if (pWalkerParams->InlineDataLength) {
1416 GENHW_HW_CHK_STATUS(IntelGen_OsAddCommand(pCmdBuffer,
1417 pWalkerParams->
1418 pInlineData,
1419 pWalkerParams->
1420 InlineDataLength));
1421 }
1422
1423 pHwInterface->pfnSendMISetPredicateCmd(pHwInterface,
1424 pCmdBuffer,
1425 MI_SET_PREDICATE_DISABLE);
1426 } else {
1427 GENHW_HW_CHK_STATUS(IntelGen_OsAddCommand(pCmdBuffer,
1428 pMediaObjWalker,
1429 sizeof
1430 (MEDIA_OBJECT_WALKER_CMD_G6)));
1431
1432 if (pWalkerParams->InlineDataLength) {
1433 GENHW_HW_CHK_STATUS(IntelGen_OsAddCommand(pCmdBuffer,
1434 pWalkerParams->
1435 pInlineData,
1436 pWalkerParams->
1437 InlineDataLength));
1438 }
1439 }
1440
1441 finish:
1442 return eStatus;
1443 }
1444
IntelGen_HwSendVfeState_g75(PGENHW_HW_INTERFACE pHwInterface,PGENOS_COMMAND_BUFFER pCmdBuffer,BOOL blGpGpuWalkerMode)1445 GENOS_STATUS IntelGen_HwSendVfeState_g75(PGENHW_HW_INTERFACE pHwInterface,
1446 PGENOS_COMMAND_BUFFER pCmdBuffer,
1447 BOOL blGpGpuWalkerMode)
1448 {
1449 MEDIA_VFE_STATE_CMD_G6 VideoFrontEnd;
1450 PGENHW_HW_COMMANDS pHwCommands;
1451 PGENHW_GSH pGSH;
1452 PCGENHW_HW_CAPS pHwCaps;
1453 DWORD dwMaxURBSize;
1454 DWORD dwCURBEAllocationSize;
1455 DWORD dwURBEntryAllocationSize;
1456 DWORD dwNumberofURBEntries;
1457 DWORD dwMaxInterfaceDescriptorEntries;
1458 GENOS_STATUS eStatus;
1459 INT iSize;
1460 INT iRemain;
1461 INT iPerThreadScratchSize;
1462
1463 GENHW_HW_ASSERT(pHwInterface);
1464 GENHW_HW_ASSERT(pCmdBuffer);
1465 GENHW_HW_ASSERT(pHwInterface->pHwCommands);
1466 GENHW_HW_ASSERT(pHwInterface->pGeneralStateHeap);
1467
1468 eStatus = GENOS_STATUS_SUCCESS;
1469 pHwCommands = pHwInterface->pHwCommands;
1470 pGSH = pHwInterface->pGeneralStateHeap;
1471 pHwCaps = pHwInterface->pHwCaps;
1472
1473 VideoFrontEnd = *(pHwCommands->pVideoFrontEnd_g75);
1474
1475 if (pHwInterface->GshSettings.iPerThreadScratchSize > 0) {
1476 GENHW_HW_ASSERT(pHwInterface->GshSettings.
1477 iPerThreadScratchSize ==
1478 GENOS_ALIGN_CEIL(pHwInterface->GshSettings.
1479 iPerThreadScratchSize, 1024));
1480
1481 iPerThreadScratchSize =
1482 pHwInterface->GshSettings.iPerThreadScratchSize >> 10;
1483
1484 iRemain = iPerThreadScratchSize % 2;
1485 iPerThreadScratchSize = iPerThreadScratchSize / 2;
1486 iSize = 0;
1487 while (!iRemain && (iPerThreadScratchSize / 2)) {
1488 iSize++;
1489 iRemain = iPerThreadScratchSize % 2;
1490 iPerThreadScratchSize = iPerThreadScratchSize / 2;
1491 }
1492
1493 GENHW_HW_ASSERT(!iRemain && iPerThreadScratchSize);
1494 GENHW_HW_ASSERT(iSize < 12);
1495 VideoFrontEnd.DW1.PerThreadScratchSpace = iSize;
1496
1497 VideoFrontEnd.DW1.ScratchSpaceBasePointer =
1498 pGSH->dwScratchSpaceBase >> 10;
1499 }
1500 dwMaxURBSize = pHwCaps->dwMaxURBSize;
1501 dwMaxInterfaceDescriptorEntries =
1502 pHwCaps->dwMaxInterfaceDescriptorEntries;
1503
1504 dwCURBEAllocationSize =
1505 GENOS_ROUNDUP_SHIFT(pHwInterface->VfeStateParams.
1506 dwCURBEAllocationSize, 5);
1507
1508 dwURBEntryAllocationSize =
1509 GENOS_ROUNDUP_SHIFT(pHwInterface->VfeStateParams.
1510 dwURBEntryAllocationSize, 5);
1511 dwURBEntryAllocationSize = GFX_MAX(1, dwURBEntryAllocationSize);
1512
1513 dwNumberofURBEntries =
1514 (dwMaxURBSize - dwCURBEAllocationSize -
1515 dwMaxInterfaceDescriptorEntries) / dwURBEntryAllocationSize;
1516 dwNumberofURBEntries = GFX_CLAMP_MIN_MAX(dwNumberofURBEntries, 1, 32);
1517
1518 VideoFrontEnd.DW2.DebugCounterControl =
1519 pHwInterface->VfeStateParams.dwDebugCounterControl;
1520 VideoFrontEnd.DW2.NumberofURBEntries = dwNumberofURBEntries;
1521 VideoFrontEnd.DW2.MaximumNumberofThreads =
1522 pHwInterface->VfeStateParams.dwMaximumNumberofThreads - 1;
1523 VideoFrontEnd.DW4.CURBEAllocationSize = dwCURBEAllocationSize;
1524 VideoFrontEnd.DW4.URBEntryAllocationSize = dwURBEntryAllocationSize;
1525
1526 if (pHwInterface->VfeScoreboard.ScoreboardEnable) {
1527 VideoFrontEnd.DW5.ScoreboardEnable = 1;
1528 VideoFrontEnd.DW5.ScoreboardMask =
1529 pHwInterface->VfeScoreboard.ScoreboardMask;
1530 VideoFrontEnd.DW5.ScoreboardType =
1531 pHwInterface->VfeScoreboard.ScoreboardType;
1532 VideoFrontEnd.DW6.Value = pHwInterface->VfeScoreboard.Value[0];
1533 VideoFrontEnd.DW7.Value = pHwInterface->VfeScoreboard.Value[1];
1534 }
1535
1536 if (blGpGpuWalkerMode) {
1537 VideoFrontEnd.DW2.GPGPUMode = MEDIASTATE_GPGPU_MODE;
1538 VideoFrontEnd.DW2.BypassGatewayControl = 1;
1539 }
1540
1541 GENHW_HW_ASSERT(VideoFrontEnd.DW2.NumberofURBEntries <=
1542 pHwCaps->dwMaxURBEntries);
1543 GENHW_HW_ASSERT(VideoFrontEnd.DW4.CURBEAllocationSize <=
1544 pHwCaps->dwMaxCURBEAllocationSize);
1545 GENHW_HW_ASSERT(VideoFrontEnd.DW4.URBEntryAllocationSize <=
1546 pHwCaps->dwMaxURBEntryAllocationSize);
1547 GENHW_HW_ASSERT(VideoFrontEnd.DW2.NumberofURBEntries *
1548 VideoFrontEnd.DW4.URBEntryAllocationSize +
1549 VideoFrontEnd.DW4.CURBEAllocationSize +
1550 dwMaxInterfaceDescriptorEntries <= dwMaxURBSize);
1551
1552 GENHW_HW_CHK_STATUS(IntelGen_OsAddCommand(pCmdBuffer,
1553 &VideoFrontEnd,
1554 sizeof(VideoFrontEnd)));
1555
1556 finish:
1557 return eStatus;
1558 }
1559
IntelGen_HwIs2PlaneNV12Needed_g75(PGENHW_HW_INTERFACE pHwInterface,PGENHW_SURFACE pSurface)1560 BOOL IntelGen_HwIs2PlaneNV12Needed_g75(PGENHW_HW_INTERFACE pHwInterface,
1561 PGENHW_SURFACE pSurface)
1562 {
1563 WORD wWidthAlignUnit;
1564 WORD wHeightAlignUnit;
1565 DWORD dwSurfaceHeight;
1566 DWORD dwSurfaceWidth;
1567
1568 pHwInterface->pfnGetAlignUnit(&wWidthAlignUnit, &wHeightAlignUnit,
1569 pSurface);
1570
1571 dwSurfaceHeight =
1572 GENOS_ALIGN_CEIL(pSurface->dwHeight, wHeightAlignUnit);
1573 dwSurfaceWidth = GENOS_ALIGN_CEIL(pSurface->dwWidth, wWidthAlignUnit);
1574
1575 return (!GENOS_IS_ALIGNED(dwSurfaceHeight, 4)
1576 || !GENOS_IS_ALIGNED(dwSurfaceWidth, 4));
1577 }
1578
IntelGen_GetScratchSpaceSize_g75(PGENHW_HW_INTERFACE pHwInterface,DWORD iPerThreadScratchSpaceSize)1579 DWORD IntelGen_GetScratchSpaceSize_g75(PGENHW_HW_INTERFACE pHwInterface,
1580 DWORD iPerThreadScratchSpaceSize)
1581 {
1582 DWORD dwScratchSpaceSize = (GENHW_MEDIA_THREADS_MAX_G75_GT1 +
1583 (pHwInterface->pHwCaps->dwMaxThreads /
1584 GENHW_MEDIA_THREADS_MAX_G75_GT1 -
1585 1) *
1586 GENHW_MEDIAL_SUBSLICE_SCRATCH_DISTANCE_G75)
1587 * iPerThreadScratchSpaceSize;
1588
1589 return dwScratchSpaceSize;
1590 }
1591
IntelGen_HwSendMediaStateFlush_g75(PGENHW_HW_INTERFACE pHwInterface,PGENOS_COMMAND_BUFFER pCmdBuffer)1592 GENOS_STATUS IntelGen_HwSendMediaStateFlush_g75(PGENHW_HW_INTERFACE
1593 pHwInterface,
1594 PGENOS_COMMAND_BUFFER
1595 pCmdBuffer)
1596 {
1597 GENOS_STATUS eStatus;
1598 PMEDIA_STATE_FLUSH_CMD_G75 pMediaStateFlush;
1599 DWORD dwCmdSize;
1600
1601 GENHW_HW_ASSERT(pHwInterface);
1602 GENHW_HW_ASSERT(pCmdBuffer);
1603 GENHW_HW_ASSERT(pHwInterface->pHwCommands);
1604
1605 eStatus = GENOS_STATUS_SUCCESS;
1606 dwCmdSize = sizeof(MEDIA_STATE_FLUSH_CMD_G75);
1607 pMediaStateFlush = (PMEDIA_STATE_FLUSH_CMD_G75)
1608 IntelGen_OsGetCmdBufferSpace(pCmdBuffer, dwCmdSize);
1609
1610 GENHW_HW_CHK_NULL(pMediaStateFlush);
1611
1612 *pMediaStateFlush = *pHwInterface->pHwCommands->pMediaStateFlush_g75;
1613
1614 IntelGen_OsAdjustCmdBufferFreeSpace(pCmdBuffer, dwCmdSize);
1615
1616 finish:
1617 return eStatus;
1618 }
1619
IntelGen_HwSendStateSip_g75(PGENHW_HW_INTERFACE pHw,PGENOS_COMMAND_BUFFER pCmd)1620 static GENOS_STATUS IntelGen_HwSendStateSip_g75(PGENHW_HW_INTERFACE pHw,
1621 PGENOS_COMMAND_BUFFER pCmd)
1622 {
1623 GENOS_STATUS eStatus = GENOS_STATUS_SUCCESS;
1624 PGENHW_GSH pGsh = pHw->pGeneralStateHeap;
1625 STATE_SIP_CMD_G75 *pStateSipCmd;
1626
1627 pStateSipCmd = (PSTATE_SIP_CMD_G75)IntelGen_OsGetCmdBufferSpace(pCmd,
1628 sizeof(*pStateSipCmd));
1629 GENHW_HW_CHK_NULL(pStateSipCmd);
1630
1631 *pStateSipCmd = g_cInit_STATE_SIP_CMD_G75;
1632
1633 // We use a bitfield so bits [3:0] of DWord1 will be zero
1634 pStateSipCmd->DW1.SystemInstructionPointer = pGsh->dwSipBase >> 4;
1635
1636 IntelGen_OsAdjustCmdBufferFreeSpace(pCmd, sizeof(*pStateSipCmd));
1637
1638 finish:
1639 return eStatus;
1640 }
1641
IntelGen_HwSendDebugCtl_g75(PGENHW_HW_INTERFACE pHw,PGENOS_COMMAND_BUFFER pCmdBuffer)1642 static GENOS_STATUS IntelGen_HwSendDebugCtl_g75(PGENHW_HW_INTERFACE pHw,
1643 PGENOS_COMMAND_BUFFER pCmdBuffer)
1644 {
1645 GENOS_STATUS eStatus = GENOS_STATUS_SUCCESS;
1646 GENHW_LOAD_REGISTER_IMM_PARAM lri;
1647 DWORD tdCtlRegs[] = { GENHW_REG_TD_CTL_S0_SS0, GENHW_REG_TD_CTL_S0_SS1,
1648 GENHW_REG_TD_CTL_S1_SS0, GENHW_REG_TD_CTL_S1_SS1 };
1649 unsigned i;
1650
1651 GENHW_HW_ASSERT(pHw);
1652
1653 for (i = 0; i < sizeof(tdCtlRegs) / sizeof(tdCtlRegs[0]); i++) {
1654 // Select the right sub-slice
1655 lri.dwRegisterAddress = GENHW_REG_MBCTL;
1656 lri.dwData = i << GENHW_REG_MBCHT_RDRETSEL_OFFSET;
1657 GENHW_HW_CHK_STATUS(pHw->pfnSendLoadRegImmCmd(pHw, pCmdBuffer, &lri));
1658
1659 lri.dwRegisterAddress = tdCtlRegs[i];
1660 lri.dwData = GENHW_REG_TD_CTL_FORCE_BKPT_ENABLE |
1661 GENHW_REG_TD_CTL_FORCE_EXCEPTION_ENABLE;
1662 GENHW_HW_CHK_STATUS(pHw->pfnSendLoadRegImmCmd(pHw, pCmdBuffer, &lri));
1663 }
1664
1665 finish:
1666 return eStatus;
1667 }
1668
IntelGen_HwInitInterface_g75(PGENHW_HW_INTERFACE pHwInterface)1669 VOID IntelGen_HwInitInterface_g75(PGENHW_HW_INTERFACE pHwInterface)
1670 {
1671 if (pHwInterface->Platform.GtType == GTTYPE_GT1) {
1672 pHwInterface->pHwCaps = &g_IntelGen_HwCaps_g75_gt1;
1673 } else if (pHwInterface->Platform.GtType == GTTYPE_GT2) {
1674 pHwInterface->pHwCaps = &g_IntelGen_HwCaps_g75_gt2;
1675 } else {
1676 pHwInterface->pHwCaps = &g_IntelGen_HwCaps_g75_gt3;
1677 }
1678
1679 pHwInterface->GshSettings = g_GSH_Settings_g75;
1680
1681 pHwInterface->SshSettings = g_SSH_Settings_g75;
1682
1683 pHwInterface->SurfaceTypeDefault = GENHW_SURFACE_TYPE_G7;
1684 pHwInterface->bUsesPatchList = TRUE;
1685
1686 pHwInterface->pPlaneDefinitions = g_cInitSurfacePlanes_g75;
1687 pHwInterface->iSizeBindingTableState = sizeof(BINDING_TABLE_STATE_G5);
1688 pHwInterface->iSizeInstructionCache = GENHW_INSTRUCTION_CACHE_G75;
1689 pHwInterface->iSizeInterfaceDescriptor =
1690 sizeof(INTERFACE_DESCRIPTOR_DATA_G6);
1691 pHwInterface->bEnableYV12SinglePass = FALSE;
1692
1693 pHwInterface->VfeStateParams.dwDebugCounterControl = 0;
1694 pHwInterface->VfeStateParams.dwMaximumNumberofThreads =
1695 pHwInterface->pHwCaps->dwMaxThreads;
1696
1697 pHwInterface->pfnInitCommands = IntelGen_HwInitCommands_g75;
1698 pHwInterface->pfnAssignBindingTable = IntelGen_HwAssignBindingTable_g75;
1699 pHwInterface->pfnSetupSurfaceState = IntelGen_HwSetupSurfaceState_g75;
1700 pHwInterface->pfnSetupBufferSurfaceState =
1701 IntelGen_HwSetupBufferSurfaceState_g75;
1702 pHwInterface->pfnLoadCurbeData = IntelGen_HwLoadCurbeData_g75;
1703 pHwInterface->pfnInitInterfaceDescriptor =
1704 IntelGen_HwInitInterfaceDescriptor_g75;
1705 pHwInterface->pfnSetupInterfaceDescriptor =
1706 IntelGen_HwSetupInterfaceDescriptor_g75;
1707 pHwInterface->pfnGetMediaWalkerStatus =
1708 IntelGen_HwGetMediaWalkerStatus_g75;
1709 pHwInterface->pfnGetMediaWalkerBlockSize =
1710 IntelGen_HwGetMediaWalkerBlockSize_g75;
1711
1712 pHwInterface->pfnSendVfeState = IntelGen_HwSendVfeState_g75;
1713 pHwInterface->pfnSendCurbeLoad = IntelGen_HwSendCurbeLoad_g75;
1714 pHwInterface->pfnSendIDLoad = IntelGen_HwSendIDLoad_g75;
1715 pHwInterface->pfnAddMediaObjectCmdBb =
1716 IntelGen_HwAddMediaObjectCmdBb_g75;
1717 pHwInterface->pfnGetSurfaceMemoryObjectControl =
1718 IntelGen_HwGetSurfaceMemoryObjectControl_g75;
1719 pHwInterface->pfnSendMediaObjectWalker = IntelGen_HwSendWalkerState_g75;
1720 pHwInterface->pfnSendMISetPredicateCmd =
1721 IntelGen_HwSendMISetPredicateCmd_g75;
1722 pHwInterface->pfnSendPipelineSelectCmd =
1723 IntelGen_HwSendPipelineSelectCmd_g75;
1724 pHwInterface->pfnGetScratchSpaceSize = IntelGen_GetScratchSpaceSize_g75;
1725 pHwInterface->pfnConvertToNanoSeconds =
1726 IntelGen_HwConvertToNanoSeconds_g75;
1727 pHwInterface->pfnSendGpGpuWalkerState =
1728 IntelGen_HwSendGpGpuWalkerState_g75;
1729 pHwInterface->pfnAddPipeControlCmdBb =
1730 IntelGen_HwAddPipeControlCmdBb_g75;
1731 pHwInterface->pfnSkipPipeControlCmdBb =
1732 IntelGen_HwSkipPipeControlCmdBb_g75;
1733 pHwInterface->pfnSendMediaStateFlush =
1734 IntelGen_HwSendMediaStateFlush_g75;
1735 pHwInterface->pfnSendMIArbCheckCmd = IntelGen_HwSendMIArbCheck_g75;
1736 pHwInterface->pfnSendStateSip = IntelGen_HwSendStateSip_g75;
1737 pHwInterface->pfnSendDebugCtl = IntelGen_HwSendDebugCtl_g75;
1738
1739 pHwInterface->pfnIs2PlaneNV12Needed = IntelGen_HwIs2PlaneNV12Needed_g75;
1740 }
1741