1 //===-- ArchSpec.cpp ------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "lldb/Utility/ArchSpec.h"
10 #include "lldb/Utility/LLDBLog.h"
11
12 #include "lldb/Utility/Log.h"
13 #include "lldb/Utility/StringList.h"
14 #include "lldb/lldb-defines.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/BinaryFormat/COFF.h"
17 #include "llvm/BinaryFormat/ELF.h"
18 #include "llvm/BinaryFormat/MachO.h"
19 #include "llvm/Support/ARMTargetParser.h"
20 #include "llvm/Support/Compiler.h"
21
22 using namespace lldb;
23 using namespace lldb_private;
24
25 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
26 bool try_inverse, bool enforce_exact_match);
27
28 namespace lldb_private {
29
30 struct CoreDefinition {
31 ByteOrder default_byte_order;
32 uint32_t addr_byte_size;
33 uint32_t min_opcode_byte_size;
34 uint32_t max_opcode_byte_size;
35 llvm::Triple::ArchType machine;
36 ArchSpec::Core core;
37 const char *const name;
38 };
39
40 } // namespace lldb_private
41
42 // This core information can be looked using the ArchSpec::Core as the index
43 static const CoreDefinition g_core_definitions[] = {
44 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic,
45 "arm"},
46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4,
47 "armv4"},
48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t,
49 "armv4t"},
50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5,
51 "armv5"},
52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e,
53 "armv5e"},
54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t,
55 "armv5t"},
56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6,
57 "armv6"},
58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m,
59 "armv6m"},
60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
61 "armv7"},
62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
63 "armv7l"},
64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
65 "armv7f"},
66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
67 "armv7s"},
68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k,
69 "armv7k"},
70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m,
71 "armv7m"},
72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em,
73 "armv7em"},
74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale,
75 "xscale"},
76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb,
77 "thumb"},
78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t,
79 "thumbv4t"},
80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5,
81 "thumbv5"},
82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e,
83 "thumbv5e"},
84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6,
85 "thumbv6"},
86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m,
87 "thumbv6m"},
88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7,
89 "thumbv7"},
90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f,
91 "thumbv7f"},
92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s,
93 "thumbv7s"},
94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k,
95 "thumbv7k"},
96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m,
97 "thumbv7m"},
98 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em,
99 "thumbv7em"},
100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
101 ArchSpec::eCore_arm_arm64, "arm64"},
102 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
103 ArchSpec::eCore_arm_armv8, "armv8"},
104 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv8l,
105 "armv8l"},
106 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
107 ArchSpec::eCore_arm_arm64e, "arm64e"},
108 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32,
109 ArchSpec::eCore_arm_arm64_32, "arm64_32"},
110 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
111 ArchSpec::eCore_arm_aarch64, "aarch64"},
112
113 // mips32, mips32r2, mips32r3, mips32r5, mips32r6
114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32,
115 "mips"},
116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2,
117 "mipsr2"},
118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3,
119 "mipsr3"},
120 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5,
121 "mipsr5"},
122 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6,
123 "mipsr6"},
124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el,
125 "mipsel"},
126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
127 ArchSpec::eCore_mips32r2el, "mipsr2el"},
128 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
129 ArchSpec::eCore_mips32r3el, "mipsr3el"},
130 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
131 ArchSpec::eCore_mips32r5el, "mipsr5el"},
132 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
133 ArchSpec::eCore_mips32r6el, "mipsr6el"},
134
135 // mips64, mips64r2, mips64r3, mips64r5, mips64r6
136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64,
137 "mips64"},
138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2,
139 "mips64r2"},
140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3,
141 "mips64r3"},
142 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5,
143 "mips64r5"},
144 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6,
145 "mips64r6"},
146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
147 ArchSpec::eCore_mips64el, "mips64el"},
148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
149 ArchSpec::eCore_mips64r2el, "mips64r2el"},
150 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
151 ArchSpec::eCore_mips64r3el, "mips64r3el"},
152 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
153 ArchSpec::eCore_mips64r5el, "mips64r5el"},
154 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
155 ArchSpec::eCore_mips64r6el, "mips64r6el"},
156
157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic,
158 "powerpc"},
159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601,
160 "ppc601"},
161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602,
162 "ppc602"},
163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603,
164 "ppc603"},
165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e,
166 "ppc603e"},
167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev,
168 "ppc603ev"},
169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604,
170 "ppc604"},
171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e,
172 "ppc604e"},
173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620,
174 "ppc620"},
175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750,
176 "ppc750"},
177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400,
178 "ppc7400"},
179 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450,
180 "ppc7450"},
181 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970,
182 "ppc970"},
183
184 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le,
185 ArchSpec::eCore_ppc64le_generic, "powerpc64le"},
186 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic,
187 "powerpc64"},
188 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64,
189 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"},
190
191 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz,
192 ArchSpec::eCore_s390x_generic, "s390x"},
193
194 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc,
195 ArchSpec::eCore_sparc_generic, "sparc"},
196 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9,
197 ArchSpec::eCore_sparc9_generic, "sparcv9"},
198
199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386,
200 "i386"},
201 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486,
202 "i486"},
203 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86,
204 ArchSpec::eCore_x86_32_i486sx, "i486sx"},
205 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686,
206 "i686"},
207
208 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
209 ArchSpec::eCore_x86_64_x86_64, "x86_64"},
210 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
211 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"},
212 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
213 ArchSpec::eCore_x86_64_amd64, "amd64"},
214 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
215 ArchSpec::eCore_hexagon_generic, "hexagon"},
216 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
217 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"},
218 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
219 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
220
221 {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
222 "riscv32"},
223 {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
224 "riscv64"},
225
226 {eByteOrderLittle, 4, 4, 4, llvm::Triple::loongarch32,
227 ArchSpec::eCore_loongarch32, "loongarch32"},
228 {eByteOrderLittle, 8, 4, 4, llvm::Triple::loongarch64,
229 ArchSpec::eCore_loongarch64, "loongarch64"},
230
231 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
232 ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
233 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
234 ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
235 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"},
236
237 {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"},
238
239 {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32,
240 "wasm32"},
241 };
242
243 // Ensure that we have an entry in the g_core_definitions for each core. If you
244 // comment out an entry above, you will need to comment out the corresponding
245 // ArchSpec::Core enumeration.
246 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) ==
247 ArchSpec::kNumCores,
248 "make sure we have one core definition for each core");
249
250 struct ArchDefinitionEntry {
251 ArchSpec::Core core;
252 uint32_t cpu;
253 uint32_t sub;
254 uint32_t cpu_mask;
255 uint32_t sub_mask;
256 };
257
258 struct ArchDefinition {
259 ArchitectureType type;
260 size_t num_entries;
261 const ArchDefinitionEntry *entries;
262 const char *name;
263 };
264
ListSupportedArchNames(StringList & list)265 void ArchSpec::ListSupportedArchNames(StringList &list) {
266 for (const auto &def : g_core_definitions)
267 list.AppendString(def.name);
268 }
269
AutoComplete(CompletionRequest & request)270 void ArchSpec::AutoComplete(CompletionRequest &request) {
271 for (const auto &def : g_core_definitions)
272 request.TryCompleteCurrentArg(def.name);
273 }
274
275 #define CPU_ANY (UINT32_MAX)
276
277 //===----------------------------------------------------------------------===//
278 // A table that gets searched linearly for matches. This table is used to
279 // convert cpu type and subtypes to architecture names, and to convert
280 // architecture names to cpu types and subtypes. The ordering is important and
281 // allows the precedence to be set when the table is built.
282 #define SUBTYPE_MASK 0x00FFFFFFu
283
284 // clang-format off
285 static const ArchDefinitionEntry g_macho_arch_entries[] = {
286 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, UINT32_MAX, UINT32_MAX},
287 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
288 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
289 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
290 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
291 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
292 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
293 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
294 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
295 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_XSCALE, UINT32_MAX, SUBTYPE_MASK},
296 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
297 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
298 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
299 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
300 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
301 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
302 {ArchSpec::eCore_arm_arm64e, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64E, UINT32_MAX, SUBTYPE_MASK},
303 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_ALL, UINT32_MAX, SUBTYPE_MASK},
304 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_V8, UINT32_MAX, SUBTYPE_MASK},
305 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, SUBTYPE_MASK},
306 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, UINT32_MAX, SUBTYPE_MASK},
307 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, UINT32_MAX, SUBTYPE_MASK},
308 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
309 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
310 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
311 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
312 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
313 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
314 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
315 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
316 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
317 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
318 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
319 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
320 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
321 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, UINT32_MAX, UINT32_MAX},
322 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
323 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_601, UINT32_MAX, SUBTYPE_MASK},
324 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_602, UINT32_MAX, SUBTYPE_MASK},
325 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603, UINT32_MAX, SUBTYPE_MASK},
326 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603e, UINT32_MAX, SUBTYPE_MASK},
327 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK},
328 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604, UINT32_MAX, SUBTYPE_MASK},
329 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604e, UINT32_MAX, SUBTYPE_MASK},
330 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_620, UINT32_MAX, SUBTYPE_MASK},
331 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_750, UINT32_MAX, SUBTYPE_MASK},
332 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7400, UINT32_MAX, SUBTYPE_MASK},
333 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7450, UINT32_MAX, SUBTYPE_MASK},
334 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_970, UINT32_MAX, SUBTYPE_MASK},
335 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
336 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
337 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, UINT32_MAX, SUBTYPE_MASK},
338 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_I386_ALL, UINT32_MAX, SUBTYPE_MASK},
339 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486, UINT32_MAX, SUBTYPE_MASK},
340 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486SX, UINT32_MAX, SUBTYPE_MASK},
341 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, UINT32_MAX, UINT32_MAX},
342 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_ALL, UINT32_MAX, SUBTYPE_MASK},
343 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_ARCH1, UINT32_MAX, SUBTYPE_MASK},
344 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_H, UINT32_MAX, SUBTYPE_MASK},
345 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, UINT32_MAX, UINT32_MAX},
346 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
347 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u},
348 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}};
349 // clang-format on
350
351 static const ArchDefinition g_macho_arch_def = {eArchTypeMachO,
352 std::size(g_macho_arch_entries),
353 g_macho_arch_entries, "mach-o"};
354
355 //===----------------------------------------------------------------------===//
356 // A table that gets searched linearly for matches. This table is used to
357 // convert cpu type and subtypes to architecture names, and to convert
358 // architecture names to cpu types and subtypes. The ordering is important and
359 // allows the precedence to be set when the table is built.
360 static const ArchDefinitionEntry g_elf_arch_entries[] = {
361 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE,
362 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc
363 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE,
364 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386
365 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE,
366 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct?
367 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE,
368 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
369 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64,
370 ArchSpec::eCore_ppc64le_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
371 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64,
372 ArchSpec::eCore_ppc64_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
373 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE,
374 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
375 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
376 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64
377 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE,
378 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ
379 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9,
380 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9
381 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE,
382 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
383 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32,
384 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32
385 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS,
386 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2
387 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS,
388 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6
389 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS,
390 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el
391 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS,
392 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el
393 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS,
394 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el
395 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64,
396 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64
397 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS,
398 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2
399 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS,
400 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6
401 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS,
402 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el
403 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS,
404 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el
405 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS,
406 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el
407 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
408 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
409 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
410 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC
411 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu,
412 0xFFFFFFFFu}, // AVR
413 {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
414 ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
415 {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
416 ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64
417 {ArchSpec::eCore_loongarch32, llvm::ELF::EM_LOONGARCH,
418 ArchSpec::eLoongArchSubType_loongarch32, 0xFFFFFFFFu,
419 0xFFFFFFFFu}, // loongarch32
420 {ArchSpec::eCore_loongarch64, llvm::ELF::EM_LOONGARCH,
421 ArchSpec::eLoongArchSubType_loongarch64, 0xFFFFFFFFu,
422 0xFFFFFFFFu}, // loongarch64
423 };
424
425 static const ArchDefinition g_elf_arch_def = {
426 eArchTypeELF,
427 std::size(g_elf_arch_entries),
428 g_elf_arch_entries,
429 "elf",
430 };
431
432 static const ArchDefinitionEntry g_coff_arch_entries[] = {
433 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386,
434 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86
435 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC,
436 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
437 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP,
438 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU)
439 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM,
440 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
441 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT,
442 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
443 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB,
444 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
445 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64,
446 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
447 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64,
448 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64
449 };
450
451 static const ArchDefinition g_coff_arch_def = {
452 eArchTypeCOFF,
453 std::size(g_coff_arch_entries),
454 g_coff_arch_entries,
455 "pe-coff",
456 };
457
458 //===----------------------------------------------------------------------===//
459 // Table of all ArchDefinitions
460 static const ArchDefinition *g_arch_definitions[] = {
461 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def};
462
463 //===----------------------------------------------------------------------===//
464 // Static helper functions.
465
466 // Get the architecture definition for a given object type.
FindArchDefinition(ArchitectureType arch_type)467 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) {
468 for (const ArchDefinition *def : g_arch_definitions) {
469 if (def->type == arch_type)
470 return def;
471 }
472 return nullptr;
473 }
474
475 // Get an architecture definition by name.
FindCoreDefinition(llvm::StringRef name)476 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) {
477 for (const auto &def : g_core_definitions) {
478 if (name.equals_insensitive(def.name))
479 return &def;
480 }
481 return nullptr;
482 }
483
FindCoreDefinition(ArchSpec::Core core)484 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) {
485 if (core < std::size(g_core_definitions))
486 return &g_core_definitions[core];
487 return nullptr;
488 }
489
490 // Get a definition entry by cpu type and subtype.
491 static const ArchDefinitionEntry *
FindArchDefinitionEntry(const ArchDefinition * def,uint32_t cpu,uint32_t sub)492 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) {
493 if (def == nullptr)
494 return nullptr;
495
496 const ArchDefinitionEntry *entries = def->entries;
497 for (size_t i = 0; i < def->num_entries; ++i) {
498 if (entries[i].cpu == (cpu & entries[i].cpu_mask))
499 if (entries[i].sub == (sub & entries[i].sub_mask))
500 return &entries[i];
501 }
502 return nullptr;
503 }
504
505 static const ArchDefinitionEntry *
FindArchDefinitionEntry(const ArchDefinition * def,ArchSpec::Core core)506 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) {
507 if (def == nullptr)
508 return nullptr;
509
510 const ArchDefinitionEntry *entries = def->entries;
511 for (size_t i = 0; i < def->num_entries; ++i) {
512 if (entries[i].core == core)
513 return &entries[i];
514 }
515 return nullptr;
516 }
517
518 //===----------------------------------------------------------------------===//
519 // Constructors and destructors.
520
521 ArchSpec::ArchSpec() = default;
522
ArchSpec(const char * triple_cstr)523 ArchSpec::ArchSpec(const char *triple_cstr) {
524 if (triple_cstr)
525 SetTriple(triple_cstr);
526 }
527
ArchSpec(llvm::StringRef triple_str)528 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); }
529
ArchSpec(const llvm::Triple & triple)530 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); }
531
ArchSpec(ArchitectureType arch_type,uint32_t cpu,uint32_t subtype)532 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) {
533 SetArchitecture(arch_type, cpu, subtype);
534 }
535
536 ArchSpec::~ArchSpec() = default;
537
Clear()538 void ArchSpec::Clear() {
539 m_triple = llvm::Triple();
540 m_core = kCore_invalid;
541 m_byte_order = eByteOrderInvalid;
542 m_distribution_id.Clear();
543 m_flags = 0;
544 }
545
546 //===----------------------------------------------------------------------===//
547 // Predicates.
548
GetArchitectureName() const549 const char *ArchSpec::GetArchitectureName() const {
550 const CoreDefinition *core_def = FindCoreDefinition(m_core);
551 if (core_def)
552 return core_def->name;
553 return "unknown";
554 }
555
IsMIPS() const556 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); }
557
GetTargetABI() const558 std::string ArchSpec::GetTargetABI() const {
559
560 std::string abi;
561
562 if (IsMIPS()) {
563 switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
564 case ArchSpec::eMIPSABI_N64:
565 abi = "n64";
566 return abi;
567 case ArchSpec::eMIPSABI_N32:
568 abi = "n32";
569 return abi;
570 case ArchSpec::eMIPSABI_O32:
571 abi = "o32";
572 return abi;
573 default:
574 return abi;
575 }
576 }
577 return abi;
578 }
579
SetFlags(const std::string & elf_abi)580 void ArchSpec::SetFlags(const std::string &elf_abi) {
581
582 uint32_t flag = GetFlags();
583 if (IsMIPS()) {
584 if (elf_abi == "n64")
585 flag |= ArchSpec::eMIPSABI_N64;
586 else if (elf_abi == "n32")
587 flag |= ArchSpec::eMIPSABI_N32;
588 else if (elf_abi == "o32")
589 flag |= ArchSpec::eMIPSABI_O32;
590 }
591 SetFlags(flag);
592 }
593
GetClangTargetCPU() const594 std::string ArchSpec::GetClangTargetCPU() const {
595 std::string cpu;
596 if (IsMIPS()) {
597 switch (m_core) {
598 case ArchSpec::eCore_mips32:
599 case ArchSpec::eCore_mips32el:
600 cpu = "mips32";
601 break;
602 case ArchSpec::eCore_mips32r2:
603 case ArchSpec::eCore_mips32r2el:
604 cpu = "mips32r2";
605 break;
606 case ArchSpec::eCore_mips32r3:
607 case ArchSpec::eCore_mips32r3el:
608 cpu = "mips32r3";
609 break;
610 case ArchSpec::eCore_mips32r5:
611 case ArchSpec::eCore_mips32r5el:
612 cpu = "mips32r5";
613 break;
614 case ArchSpec::eCore_mips32r6:
615 case ArchSpec::eCore_mips32r6el:
616 cpu = "mips32r6";
617 break;
618 case ArchSpec::eCore_mips64:
619 case ArchSpec::eCore_mips64el:
620 cpu = "mips64";
621 break;
622 case ArchSpec::eCore_mips64r2:
623 case ArchSpec::eCore_mips64r2el:
624 cpu = "mips64r2";
625 break;
626 case ArchSpec::eCore_mips64r3:
627 case ArchSpec::eCore_mips64r3el:
628 cpu = "mips64r3";
629 break;
630 case ArchSpec::eCore_mips64r5:
631 case ArchSpec::eCore_mips64r5el:
632 cpu = "mips64r5";
633 break;
634 case ArchSpec::eCore_mips64r6:
635 case ArchSpec::eCore_mips64r6el:
636 cpu = "mips64r6";
637 break;
638 default:
639 break;
640 }
641 }
642
643 if (GetTriple().isARM())
644 cpu = llvm::ARM::getARMCPUForArch(GetTriple(), "").str();
645 return cpu;
646 }
647
GetMachOCPUType() const648 uint32_t ArchSpec::GetMachOCPUType() const {
649 const CoreDefinition *core_def = FindCoreDefinition(m_core);
650 if (core_def) {
651 const ArchDefinitionEntry *arch_def =
652 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core);
653 if (arch_def) {
654 return arch_def->cpu;
655 }
656 }
657 return LLDB_INVALID_CPUTYPE;
658 }
659
GetMachOCPUSubType() const660 uint32_t ArchSpec::GetMachOCPUSubType() const {
661 const CoreDefinition *core_def = FindCoreDefinition(m_core);
662 if (core_def) {
663 const ArchDefinitionEntry *arch_def =
664 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core);
665 if (arch_def) {
666 return arch_def->sub;
667 }
668 }
669 return LLDB_INVALID_CPUTYPE;
670 }
671
GetDataByteSize() const672 uint32_t ArchSpec::GetDataByteSize() const {
673 return 1;
674 }
675
GetCodeByteSize() const676 uint32_t ArchSpec::GetCodeByteSize() const {
677 return 1;
678 }
679
GetMachine() const680 llvm::Triple::ArchType ArchSpec::GetMachine() const {
681 const CoreDefinition *core_def = FindCoreDefinition(m_core);
682 if (core_def)
683 return core_def->machine;
684
685 return llvm::Triple::UnknownArch;
686 }
687
GetDistributionId() const688 ConstString ArchSpec::GetDistributionId() const {
689 return m_distribution_id;
690 }
691
SetDistributionId(const char * distribution_id)692 void ArchSpec::SetDistributionId(const char *distribution_id) {
693 m_distribution_id.SetCString(distribution_id);
694 }
695
GetAddressByteSize() const696 uint32_t ArchSpec::GetAddressByteSize() const {
697 const CoreDefinition *core_def = FindCoreDefinition(m_core);
698 if (core_def) {
699 if (core_def->machine == llvm::Triple::mips64 ||
700 core_def->machine == llvm::Triple::mips64el) {
701 // For N32/O32 applications Address size is 4 bytes.
702 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32))
703 return 4;
704 }
705 return core_def->addr_byte_size;
706 }
707 return 0;
708 }
709
GetDefaultEndian() const710 ByteOrder ArchSpec::GetDefaultEndian() const {
711 const CoreDefinition *core_def = FindCoreDefinition(m_core);
712 if (core_def)
713 return core_def->default_byte_order;
714 return eByteOrderInvalid;
715 }
716
CharIsSignedByDefault() const717 bool ArchSpec::CharIsSignedByDefault() const {
718 switch (m_triple.getArch()) {
719 default:
720 return true;
721
722 case llvm::Triple::aarch64:
723 case llvm::Triple::aarch64_32:
724 case llvm::Triple::aarch64_be:
725 case llvm::Triple::arm:
726 case llvm::Triple::armeb:
727 case llvm::Triple::thumb:
728 case llvm::Triple::thumbeb:
729 return m_triple.isOSDarwin() || m_triple.isOSWindows();
730
731 case llvm::Triple::ppc:
732 case llvm::Triple::ppc64:
733 return m_triple.isOSDarwin();
734
735 case llvm::Triple::ppc64le:
736 case llvm::Triple::systemz:
737 case llvm::Triple::xcore:
738 case llvm::Triple::arc:
739 return false;
740 }
741 }
742
GetByteOrder() const743 lldb::ByteOrder ArchSpec::GetByteOrder() const {
744 if (m_byte_order == eByteOrderInvalid)
745 return GetDefaultEndian();
746 return m_byte_order;
747 }
748
749 //===----------------------------------------------------------------------===//
750 // Mutators.
751
SetTriple(const llvm::Triple & triple)752 bool ArchSpec::SetTriple(const llvm::Triple &triple) {
753 m_triple = triple;
754 UpdateCore();
755 return IsValid();
756 }
757
ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,ArchSpec & arch)758 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,
759 ArchSpec &arch) {
760 // Accept "12-10" or "12.10" as cpu type/subtype
761 if (triple_str.empty())
762 return false;
763
764 size_t pos = triple_str.find_first_of("-.");
765 if (pos == llvm::StringRef::npos)
766 return false;
767
768 llvm::StringRef cpu_str = triple_str.substr(0, pos);
769 llvm::StringRef remainder = triple_str.substr(pos + 1);
770 if (cpu_str.empty() || remainder.empty())
771 return false;
772
773 llvm::StringRef sub_str;
774 llvm::StringRef vendor;
775 llvm::StringRef os;
776 std::tie(sub_str, remainder) = remainder.split('-');
777 std::tie(vendor, os) = remainder.split('-');
778
779 uint32_t cpu = 0;
780 uint32_t sub = 0;
781 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub))
782 return false;
783
784 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub))
785 return false;
786 if (!vendor.empty() && !os.empty()) {
787 arch.GetTriple().setVendorName(vendor);
788 arch.GetTriple().setOSName(os);
789 }
790
791 return true;
792 }
793
SetTriple(llvm::StringRef triple)794 bool ArchSpec::SetTriple(llvm::StringRef triple) {
795 if (triple.empty()) {
796 Clear();
797 return false;
798 }
799
800 if (ParseMachCPUDashSubtypeTriple(triple, *this))
801 return true;
802
803 SetTriple(llvm::Triple(llvm::Triple::normalize(triple)));
804 return IsValid();
805 }
806
ContainsOnlyArch(const llvm::Triple & normalized_triple)807 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) {
808 return !normalized_triple.getArchName().empty() &&
809 normalized_triple.getOSName().empty() &&
810 normalized_triple.getVendorName().empty() &&
811 normalized_triple.getEnvironmentName().empty();
812 }
813
MergeFrom(const ArchSpec & other)814 void ArchSpec::MergeFrom(const ArchSpec &other) {
815 // ios-macabi always wins over macosx.
816 if ((GetTriple().getOS() == llvm::Triple::MacOSX ||
817 GetTriple().getOS() == llvm::Triple::UnknownOS) &&
818 other.GetTriple().getOS() == llvm::Triple::IOS &&
819 other.GetTriple().getEnvironment() == llvm::Triple::MacABI) {
820 (*this) = other;
821 return;
822 }
823
824 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified())
825 GetTriple().setVendor(other.GetTriple().getVendor());
826 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified())
827 GetTriple().setOS(other.GetTriple().getOS());
828 if (GetTriple().getArch() == llvm::Triple::UnknownArch) {
829 GetTriple().setArch(other.GetTriple().getArch());
830
831 // MachO unknown64 isn't really invalid as the debugger can still obtain
832 // information from the binary, e.g. line tables. As such, we don't update
833 // the core here.
834 if (other.GetCore() != eCore_uknownMach64)
835 UpdateCore();
836 }
837 if (!TripleEnvironmentWasSpecified() &&
838 other.TripleEnvironmentWasSpecified()) {
839 GetTriple().setEnvironment(other.GetTriple().getEnvironment());
840 }
841 // If this and other are both arm ArchSpecs and this ArchSpec is a generic
842 // "some kind of arm" spec but the other ArchSpec is a specific arm core,
843 // adopt the specific arm core.
844 if (GetTriple().getArch() == llvm::Triple::arm &&
845 other.GetTriple().getArch() == llvm::Triple::arm &&
846 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic &&
847 other.GetCore() != ArchSpec::eCore_arm_generic) {
848 m_core = other.GetCore();
849 CoreUpdated(false);
850 }
851 if (GetFlags() == 0) {
852 SetFlags(other.GetFlags());
853 }
854 }
855
SetArchitecture(ArchitectureType arch_type,uint32_t cpu,uint32_t sub,uint32_t os)856 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu,
857 uint32_t sub, uint32_t os) {
858 m_core = kCore_invalid;
859 bool update_triple = true;
860 const ArchDefinition *arch_def = FindArchDefinition(arch_type);
861 if (arch_def) {
862 const ArchDefinitionEntry *arch_def_entry =
863 FindArchDefinitionEntry(arch_def, cpu, sub);
864 if (arch_def_entry) {
865 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core);
866 if (core_def) {
867 m_core = core_def->core;
868 update_triple = false;
869 // Always use the architecture name because it might be more
870 // descriptive than the architecture enum ("armv7" ->
871 // llvm::Triple::arm).
872 m_triple.setArchName(llvm::StringRef(core_def->name));
873 if (arch_type == eArchTypeMachO) {
874 m_triple.setVendor(llvm::Triple::Apple);
875
876 // Don't set the OS. It could be simulator, macosx, ios, watchos,
877 // tvos, bridgeos. We could get close with the cpu type - but we
878 // can't get it right all of the time. Better to leave this unset
879 // so other sections of code will set it when they have more
880 // information. NB: don't call m_triple.setOS
881 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and
882 // the ArchSpec::TripleVendorWasSpecified() method says that any
883 // OSName setting means it was specified.
884 } else if (arch_type == eArchTypeELF) {
885 switch (os) {
886 case llvm::ELF::ELFOSABI_AIX:
887 m_triple.setOS(llvm::Triple::OSType::AIX);
888 break;
889 case llvm::ELF::ELFOSABI_FREEBSD:
890 m_triple.setOS(llvm::Triple::OSType::FreeBSD);
891 break;
892 case llvm::ELF::ELFOSABI_GNU:
893 m_triple.setOS(llvm::Triple::OSType::Linux);
894 break;
895 case llvm::ELF::ELFOSABI_NETBSD:
896 m_triple.setOS(llvm::Triple::OSType::NetBSD);
897 break;
898 case llvm::ELF::ELFOSABI_OPENBSD:
899 m_triple.setOS(llvm::Triple::OSType::OpenBSD);
900 break;
901 case llvm::ELF::ELFOSABI_SOLARIS:
902 m_triple.setOS(llvm::Triple::OSType::Solaris);
903 break;
904 }
905 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) {
906 m_triple.setVendor(llvm::Triple::PC);
907 m_triple.setOS(llvm::Triple::Win32);
908 } else {
909 m_triple.setVendor(llvm::Triple::UnknownVendor);
910 m_triple.setOS(llvm::Triple::UnknownOS);
911 }
912 // Fall back onto setting the machine type if the arch by name
913 // failed...
914 if (m_triple.getArch() == llvm::Triple::UnknownArch)
915 m_triple.setArch(core_def->machine);
916 }
917 } else {
918 Log *log(GetLog(LLDBLog::Target | LLDBLog::Process | LLDBLog::Platform));
919 LLDB_LOGF(log,
920 "Unable to find a core definition for cpu 0x%" PRIx32
921 " sub %" PRId32,
922 cpu, sub);
923 }
924 }
925 CoreUpdated(update_triple);
926 return IsValid();
927 }
928
GetMinimumOpcodeByteSize() const929 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const {
930 const CoreDefinition *core_def = FindCoreDefinition(m_core);
931 if (core_def)
932 return core_def->min_opcode_byte_size;
933 return 0;
934 }
935
GetMaximumOpcodeByteSize() const936 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const {
937 const CoreDefinition *core_def = FindCoreDefinition(m_core);
938 if (core_def)
939 return core_def->max_opcode_byte_size;
940 return 0;
941 }
942
IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs,llvm::Triple::EnvironmentType rhs)943 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs,
944 llvm::Triple::EnvironmentType rhs) {
945 if (lhs == rhs)
946 return true;
947
948 // Apple simulators are a different platform than what they simulate.
949 // As the environments are different at this point, if one of them is a
950 // simulator, then they are different.
951 if (lhs == llvm::Triple::Simulator || rhs == llvm::Triple::Simulator)
952 return false;
953
954 // If any of the environment is unknown then they are compatible
955 if (lhs == llvm::Triple::UnknownEnvironment ||
956 rhs == llvm::Triple::UnknownEnvironment)
957 return true;
958
959 // If one of the environment is Android and the other one is EABI then they
960 // are considered to be compatible. This is required as a workaround for
961 // shared libraries compiled for Android without the NOTE section indicating
962 // that they are using the Android ABI.
963 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) ||
964 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) ||
965 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) ||
966 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) ||
967 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) ||
968 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF))
969 return true;
970
971 return false;
972 }
973
IsMatch(const ArchSpec & rhs,MatchType match) const974 bool ArchSpec::IsMatch(const ArchSpec &rhs, MatchType match) const {
975 // explicitly ignoring m_distribution_id in this method.
976
977 if (GetByteOrder() != rhs.GetByteOrder() ||
978 !cores_match(GetCore(), rhs.GetCore(), true, match == ExactMatch))
979 return false;
980
981 const llvm::Triple &lhs_triple = GetTriple();
982 const llvm::Triple &rhs_triple = rhs.GetTriple();
983
984 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
985 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
986
987 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
988 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
989
990 bool both_windows = lhs_triple.isOSWindows() && rhs_triple.isOSWindows();
991
992 // On Windows, the vendor field doesn't have any practical effect, but
993 // it is often set to either "pc" or "w64".
994 if ((lhs_triple_vendor != rhs_triple_vendor) &&
995 (match == ExactMatch || !both_windows)) {
996 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
997 const bool lhs_vendor_specified = TripleVendorWasSpecified();
998 // Both architectures had the vendor specified, so if they aren't equal
999 // then we return false
1000 if (rhs_vendor_specified && lhs_vendor_specified)
1001 return false;
1002
1003 // Only fail if both vendor types are not unknown
1004 if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
1005 rhs_triple_vendor != llvm::Triple::UnknownVendor)
1006 return false;
1007 }
1008
1009 const llvm::Triple::EnvironmentType lhs_triple_env =
1010 lhs_triple.getEnvironment();
1011 const llvm::Triple::EnvironmentType rhs_triple_env =
1012 rhs_triple.getEnvironment();
1013
1014 if (match == CompatibleMatch) {
1015 // x86_64-apple-ios-macabi, x86_64-apple-macosx are compatible, no match.
1016 if ((lhs_triple_os == llvm::Triple::IOS &&
1017 lhs_triple_env == llvm::Triple::MacABI &&
1018 rhs_triple_os == llvm::Triple::MacOSX) ||
1019 (lhs_triple_os == llvm::Triple::MacOSX &&
1020 rhs_triple_os == llvm::Triple::IOS &&
1021 rhs_triple_env == llvm::Triple::MacABI))
1022 return true;
1023 }
1024
1025 // x86_64-apple-ios-macabi and x86_64-apple-ios are not compatible.
1026 if (lhs_triple_os == llvm::Triple::IOS &&
1027 rhs_triple_os == llvm::Triple::IOS &&
1028 (lhs_triple_env == llvm::Triple::MacABI ||
1029 rhs_triple_env == llvm::Triple::MacABI) &&
1030 lhs_triple_env != rhs_triple_env)
1031 return false;
1032
1033 if (lhs_triple_os != rhs_triple_os) {
1034 const bool lhs_os_specified = TripleOSWasSpecified();
1035 const bool rhs_os_specified = rhs.TripleOSWasSpecified();
1036 // If both OS types are specified and different, fail.
1037 if (lhs_os_specified && rhs_os_specified)
1038 return false;
1039
1040 // If the pair of os+env is both unspecified, match any other os+env combo.
1041 if (match == CompatibleMatch &&
1042 ((!lhs_os_specified && !lhs_triple.hasEnvironment()) ||
1043 (!rhs_os_specified && !rhs_triple.hasEnvironment())))
1044 return true;
1045 }
1046
1047 if (match == CompatibleMatch && both_windows)
1048 return true; // The Windows environments (MSVC vs GNU) are compatible
1049
1050 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env);
1051 }
1052
UpdateCore()1053 void ArchSpec::UpdateCore() {
1054 llvm::StringRef arch_name(m_triple.getArchName());
1055 const CoreDefinition *core_def = FindCoreDefinition(arch_name);
1056 if (core_def) {
1057 m_core = core_def->core;
1058 // Set the byte order to the default byte order for an architecture. This
1059 // can be modified if needed for cases when cores handle both big and
1060 // little endian
1061 m_byte_order = core_def->default_byte_order;
1062 } else {
1063 Clear();
1064 }
1065 }
1066
1067 //===----------------------------------------------------------------------===//
1068 // Helper methods.
1069
CoreUpdated(bool update_triple)1070 void ArchSpec::CoreUpdated(bool update_triple) {
1071 const CoreDefinition *core_def = FindCoreDefinition(m_core);
1072 if (core_def) {
1073 if (update_triple)
1074 m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
1075 m_byte_order = core_def->default_byte_order;
1076 } else {
1077 if (update_triple)
1078 m_triple = llvm::Triple();
1079 m_byte_order = eByteOrderInvalid;
1080 }
1081 }
1082
1083 //===----------------------------------------------------------------------===//
1084 // Operators.
1085
cores_match(const ArchSpec::Core core1,const ArchSpec::Core core2,bool try_inverse,bool enforce_exact_match)1086 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
1087 bool try_inverse, bool enforce_exact_match) {
1088 if (core1 == core2)
1089 return true;
1090
1091 switch (core1) {
1092 case ArchSpec::kCore_any:
1093 return true;
1094
1095 case ArchSpec::eCore_arm_generic:
1096 if (enforce_exact_match)
1097 break;
1098 [[fallthrough]];
1099 case ArchSpec::kCore_arm_any:
1100 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
1101 return true;
1102 if (core2 >= ArchSpec::kCore_thumb_first &&
1103 core2 <= ArchSpec::kCore_thumb_last)
1104 return true;
1105 if (core2 == ArchSpec::kCore_arm_any)
1106 return true;
1107 break;
1108
1109 case ArchSpec::kCore_x86_32_any:
1110 if ((core2 >= ArchSpec::kCore_x86_32_first &&
1111 core2 <= ArchSpec::kCore_x86_32_last) ||
1112 (core2 == ArchSpec::kCore_x86_32_any))
1113 return true;
1114 break;
1115
1116 case ArchSpec::kCore_x86_64_any:
1117 if ((core2 >= ArchSpec::kCore_x86_64_first &&
1118 core2 <= ArchSpec::kCore_x86_64_last) ||
1119 (core2 == ArchSpec::kCore_x86_64_any))
1120 return true;
1121 break;
1122
1123 case ArchSpec::kCore_ppc_any:
1124 if ((core2 >= ArchSpec::kCore_ppc_first &&
1125 core2 <= ArchSpec::kCore_ppc_last) ||
1126 (core2 == ArchSpec::kCore_ppc_any))
1127 return true;
1128 break;
1129
1130 case ArchSpec::kCore_ppc64_any:
1131 if ((core2 >= ArchSpec::kCore_ppc64_first &&
1132 core2 <= ArchSpec::kCore_ppc64_last) ||
1133 (core2 == ArchSpec::kCore_ppc64_any))
1134 return true;
1135 break;
1136
1137 case ArchSpec::kCore_hexagon_any:
1138 if ((core2 >= ArchSpec::kCore_hexagon_first &&
1139 core2 <= ArchSpec::kCore_hexagon_last) ||
1140 (core2 == ArchSpec::kCore_hexagon_any))
1141 return true;
1142 break;
1143
1144 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1145 // Cortex-M0 - ARMv6-M - armv6m
1146 // Cortex-M3 - ARMv7-M - armv7m
1147 // Cortex-M4 - ARMv7E-M - armv7em
1148 case ArchSpec::eCore_arm_armv7em:
1149 if (!enforce_exact_match) {
1150 if (core2 == ArchSpec::eCore_arm_generic)
1151 return true;
1152 if (core2 == ArchSpec::eCore_arm_armv7m)
1153 return true;
1154 if (core2 == ArchSpec::eCore_arm_armv6m)
1155 return true;
1156 if (core2 == ArchSpec::eCore_arm_armv7)
1157 return true;
1158 try_inverse = true;
1159 }
1160 break;
1161
1162 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1163 // Cortex-M0 - ARMv6-M - armv6m
1164 // Cortex-M3 - ARMv7-M - armv7m
1165 // Cortex-M4 - ARMv7E-M - armv7em
1166 case ArchSpec::eCore_arm_armv7m:
1167 if (!enforce_exact_match) {
1168 if (core2 == ArchSpec::eCore_arm_generic)
1169 return true;
1170 if (core2 == ArchSpec::eCore_arm_armv6m)
1171 return true;
1172 if (core2 == ArchSpec::eCore_arm_armv7)
1173 return true;
1174 if (core2 == ArchSpec::eCore_arm_armv7em)
1175 return true;
1176 try_inverse = true;
1177 }
1178 break;
1179
1180 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1181 // Cortex-M0 - ARMv6-M - armv6m
1182 // Cortex-M3 - ARMv7-M - armv7m
1183 // Cortex-M4 - ARMv7E-M - armv7em
1184 case ArchSpec::eCore_arm_armv6m:
1185 if (!enforce_exact_match) {
1186 if (core2 == ArchSpec::eCore_arm_generic)
1187 return true;
1188 if (core2 == ArchSpec::eCore_arm_armv7em)
1189 return true;
1190 if (core2 == ArchSpec::eCore_arm_armv7)
1191 return true;
1192 if (core2 == ArchSpec::eCore_arm_armv6m)
1193 return true;
1194 try_inverse = false;
1195 }
1196 break;
1197
1198 case ArchSpec::eCore_arm_armv7f:
1199 case ArchSpec::eCore_arm_armv7k:
1200 case ArchSpec::eCore_arm_armv7s:
1201 case ArchSpec::eCore_arm_armv7l:
1202 case ArchSpec::eCore_arm_armv8l:
1203 if (!enforce_exact_match) {
1204 if (core2 == ArchSpec::eCore_arm_generic)
1205 return true;
1206 if (core2 == ArchSpec::eCore_arm_armv7)
1207 return true;
1208 try_inverse = false;
1209 }
1210 break;
1211
1212 case ArchSpec::eCore_x86_64_x86_64h:
1213 if (!enforce_exact_match) {
1214 if (core2 == ArchSpec::eCore_x86_64_x86_64)
1215 return true;
1216 try_inverse = false;
1217 }
1218 break;
1219
1220 case ArchSpec::eCore_x86_64_amd64:
1221 if (!enforce_exact_match) {
1222 if (core2 == ArchSpec::eCore_x86_64_x86_64)
1223 return true;
1224 try_inverse = false;
1225 }
1226 break;
1227
1228 case ArchSpec::eCore_arm_armv8:
1229 if (!enforce_exact_match) {
1230 if (core2 == ArchSpec::eCore_arm_arm64)
1231 return true;
1232 if (core2 == ArchSpec::eCore_arm_aarch64)
1233 return true;
1234 if (core2 == ArchSpec::eCore_arm_arm64e)
1235 return true;
1236 try_inverse = false;
1237 }
1238 break;
1239
1240 case ArchSpec::eCore_arm_arm64e:
1241 if (!enforce_exact_match) {
1242 if (core2 == ArchSpec::eCore_arm_arm64)
1243 return true;
1244 if (core2 == ArchSpec::eCore_arm_aarch64)
1245 return true;
1246 if (core2 == ArchSpec::eCore_arm_armv8)
1247 return true;
1248 try_inverse = false;
1249 }
1250 break;
1251 case ArchSpec::eCore_arm_aarch64:
1252 if (!enforce_exact_match) {
1253 if (core2 == ArchSpec::eCore_arm_arm64)
1254 return true;
1255 if (core2 == ArchSpec::eCore_arm_armv8)
1256 return true;
1257 if (core2 == ArchSpec::eCore_arm_arm64e)
1258 return true;
1259 try_inverse = false;
1260 }
1261 break;
1262
1263 case ArchSpec::eCore_arm_arm64:
1264 if (!enforce_exact_match) {
1265 if (core2 == ArchSpec::eCore_arm_aarch64)
1266 return true;
1267 if (core2 == ArchSpec::eCore_arm_armv8)
1268 return true;
1269 if (core2 == ArchSpec::eCore_arm_arm64e)
1270 return true;
1271 try_inverse = false;
1272 }
1273 break;
1274
1275 case ArchSpec::eCore_arm_arm64_32:
1276 if (!enforce_exact_match) {
1277 if (core2 == ArchSpec::eCore_arm_generic)
1278 return true;
1279 try_inverse = false;
1280 }
1281 break;
1282
1283 case ArchSpec::eCore_mips32:
1284 if (!enforce_exact_match) {
1285 if (core2 >= ArchSpec::kCore_mips32_first &&
1286 core2 <= ArchSpec::kCore_mips32_last)
1287 return true;
1288 try_inverse = false;
1289 }
1290 break;
1291
1292 case ArchSpec::eCore_mips32el:
1293 if (!enforce_exact_match) {
1294 if (core2 >= ArchSpec::kCore_mips32el_first &&
1295 core2 <= ArchSpec::kCore_mips32el_last)
1296 return true;
1297 try_inverse = true;
1298 }
1299 break;
1300
1301 case ArchSpec::eCore_mips64:
1302 if (!enforce_exact_match) {
1303 if (core2 >= ArchSpec::kCore_mips32_first &&
1304 core2 <= ArchSpec::kCore_mips32_last)
1305 return true;
1306 if (core2 >= ArchSpec::kCore_mips64_first &&
1307 core2 <= ArchSpec::kCore_mips64_last)
1308 return true;
1309 try_inverse = false;
1310 }
1311 break;
1312
1313 case ArchSpec::eCore_mips64el:
1314 if (!enforce_exact_match) {
1315 if (core2 >= ArchSpec::kCore_mips32el_first &&
1316 core2 <= ArchSpec::kCore_mips32el_last)
1317 return true;
1318 if (core2 >= ArchSpec::kCore_mips64el_first &&
1319 core2 <= ArchSpec::kCore_mips64el_last)
1320 return true;
1321 try_inverse = false;
1322 }
1323 break;
1324
1325 case ArchSpec::eCore_mips64r2:
1326 case ArchSpec::eCore_mips64r3:
1327 case ArchSpec::eCore_mips64r5:
1328 if (!enforce_exact_match) {
1329 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
1330 return true;
1331 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
1332 return true;
1333 try_inverse = false;
1334 }
1335 break;
1336
1337 case ArchSpec::eCore_mips64r2el:
1338 case ArchSpec::eCore_mips64r3el:
1339 case ArchSpec::eCore_mips64r5el:
1340 if (!enforce_exact_match) {
1341 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
1342 return true;
1343 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
1344 return true;
1345 try_inverse = false;
1346 }
1347 break;
1348
1349 case ArchSpec::eCore_mips32r2:
1350 case ArchSpec::eCore_mips32r3:
1351 case ArchSpec::eCore_mips32r5:
1352 if (!enforce_exact_match) {
1353 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
1354 return true;
1355 }
1356 break;
1357
1358 case ArchSpec::eCore_mips32r2el:
1359 case ArchSpec::eCore_mips32r3el:
1360 case ArchSpec::eCore_mips32r5el:
1361 if (!enforce_exact_match) {
1362 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
1363 return true;
1364 }
1365 break;
1366
1367 case ArchSpec::eCore_mips32r6:
1368 if (!enforce_exact_match) {
1369 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1370 return true;
1371 }
1372 break;
1373
1374 case ArchSpec::eCore_mips32r6el:
1375 if (!enforce_exact_match) {
1376 if (core2 == ArchSpec::eCore_mips32el ||
1377 core2 == ArchSpec::eCore_mips32r6el)
1378 return true;
1379 }
1380 break;
1381
1382 case ArchSpec::eCore_mips64r6:
1383 if (!enforce_exact_match) {
1384 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1385 return true;
1386 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
1387 return true;
1388 }
1389 break;
1390
1391 case ArchSpec::eCore_mips64r6el:
1392 if (!enforce_exact_match) {
1393 if (core2 == ArchSpec::eCore_mips32el ||
1394 core2 == ArchSpec::eCore_mips32r6el)
1395 return true;
1396 if (core2 == ArchSpec::eCore_mips64el ||
1397 core2 == ArchSpec::eCore_mips64r6el)
1398 return true;
1399 }
1400 break;
1401
1402 default:
1403 break;
1404 }
1405 if (try_inverse)
1406 return cores_match(core2, core1, false, enforce_exact_match);
1407 return false;
1408 }
1409
operator <(const ArchSpec & lhs,const ArchSpec & rhs)1410 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) {
1411 const ArchSpec::Core lhs_core = lhs.GetCore();
1412 const ArchSpec::Core rhs_core = rhs.GetCore();
1413 return lhs_core < rhs_core;
1414 }
1415
1416
operator ==(const ArchSpec & lhs,const ArchSpec & rhs)1417 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) {
1418 return lhs.GetCore() == rhs.GetCore();
1419 }
1420
IsFullySpecifiedTriple() const1421 bool ArchSpec::IsFullySpecifiedTriple() const {
1422 if (!TripleOSWasSpecified())
1423 return false;
1424
1425 if (!TripleVendorWasSpecified())
1426 return false;
1427
1428 const unsigned unspecified = 0;
1429 const llvm::Triple &triple = GetTriple();
1430 if (triple.isOSDarwin() && triple.getOSMajorVersion() == unspecified)
1431 return false;
1432
1433 return true;
1434 }
1435
PiecewiseTripleCompare(const ArchSpec & other,bool & arch_different,bool & vendor_different,bool & os_different,bool & os_version_different,bool & env_different) const1436 void ArchSpec::PiecewiseTripleCompare(
1437 const ArchSpec &other, bool &arch_different, bool &vendor_different,
1438 bool &os_different, bool &os_version_different, bool &env_different) const {
1439 const llvm::Triple &me(GetTriple());
1440 const llvm::Triple &them(other.GetTriple());
1441
1442 arch_different = (me.getArch() != them.getArch());
1443
1444 vendor_different = (me.getVendor() != them.getVendor());
1445
1446 os_different = (me.getOS() != them.getOS());
1447
1448 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion());
1449
1450 env_different = (me.getEnvironment() != them.getEnvironment());
1451 }
1452
IsAlwaysThumbInstructions() const1453 bool ArchSpec::IsAlwaysThumbInstructions() const {
1454 std::string Status;
1455 if (GetTriple().getArch() == llvm::Triple::arm ||
1456 GetTriple().getArch() == llvm::Triple::thumb) {
1457 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M
1458 //
1459 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only
1460 // execute thumb instructions. We map the cores to arch names like this:
1461 //
1462 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4,
1463 // Cortex-M7: armv7em
1464
1465 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m ||
1466 GetCore() == ArchSpec::Core::eCore_arm_armv7em ||
1467 GetCore() == ArchSpec::Core::eCore_arm_armv6m ||
1468 GetCore() == ArchSpec::Core::eCore_thumbv7m ||
1469 GetCore() == ArchSpec::Core::eCore_thumbv7em ||
1470 GetCore() == ArchSpec::Core::eCore_thumbv6m) {
1471 return true;
1472 }
1473 // Windows on ARM is always thumb.
1474 if (GetTriple().isOSWindows())
1475 return true;
1476 }
1477 return false;
1478 }
1479
DumpTriple(llvm::raw_ostream & s) const1480 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const {
1481 const llvm::Triple &triple = GetTriple();
1482 llvm::StringRef arch_str = triple.getArchName();
1483 llvm::StringRef vendor_str = triple.getVendorName();
1484 llvm::StringRef os_str = triple.getOSName();
1485 llvm::StringRef environ_str = triple.getEnvironmentName();
1486
1487 s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str,
1488 vendor_str.empty() ? "*" : vendor_str,
1489 os_str.empty() ? "*" : os_str);
1490
1491 if (!environ_str.empty())
1492 s << "-" << environ_str;
1493 }
1494