1 /* $NetBSD: jmide_reg.h,v 1.4 2011/10/24 16:06:43 njoly Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 /* registers definitions for the JMicon JMB36x IDE/SATA controllers */ 29 30 #define PCI_JM_CONTROL0 0x40 /* controller control register 0 */ 31 #define JM_CONTROL0_ROM_EN 0x80000000 /* external ROM enable */ 32 #define JM_CONTROL0_ID_WR 0x40000000 /* device ID write enable */ 33 #define JM_CONTROL0_PCIIDE0_MS 0x00800000 /* sata M/S on chan0, PATA0 on chan1 */ 34 #define JM_CONTROL0_PCIIDE_CS 0x00400000 /* pciide channels swap */ 35 #define JM_CONTROL0_SATA_PS 0x00200000 /* SATA channel M/S swap */ 36 #define JM_CONTROL0_AHCI_PS 0x00100000 /* SATA AHCI ports swap */ 37 #define JM_CONTROL0_SATA1_AHCI 0x00008000 /* SATA port 1 AHCI enable */ 38 #define JM_CONTROL0_SATA1_IDE 0x00004000 /* SATA port 1 PCIIDE enable */ 39 #define JM_CONTROL0_SATA0_AHCI 0x00002000 /* SATA port 0 AHCI enable */ 40 #define JM_CONTROL0_SATA0_IDE 0x00001000 /* SATA port 0 PCIIDE enable */ 41 #define JM_CONTROL0_AHCI_F1 0x00000200 /* AHCI on function 1 */ 42 #define JM_CONTROL0_AHCI_EN 0x00000100 /* AHCI enable */ 43 #define JM_CONTROL0_PATA0_RST 0x00000040 /* PATA port 0 reset */ 44 #define JM_CONTROL0_PATA0_EN 0x00000020 /* PATA port 0 enable */ 45 #define JM_CONTROL0_PATA0_SEC 0x00000010 /* PATA 0 enable on secondary chan */ 46 #define JM_CONTROL0_PATA0_40P 0x00000008 /* PATA 0 40pin cable */ 47 #define JM_CONTROL0_PCIIDE_F1 0x00000002 /* PCIIDE on function 1 */ 48 #define JM_CONTROL0_PATA0_PRI 0x00000001 /* PATA 0 enable on primary chan */ 49 50 #define PCI_JM_CONTROL1 0x80 /* controller control register 5 */ 51 #define JM_CONTROL1_PATA1_PRI 0x01000000 /* force PATA 1 on chan0 */ 52 #define JM_CONTROL1_PATA1_RST 0x00400000 /* PATA 1 reset */ 53 #define JM_CONTROL1_PATA1_EN 0x00200000 /* PATA 1 enable */ 54 #define JM_CONTROL1_PATA1_40P 0x00080000 /* PATA 1 40pin cable */ 55