1 //===-- M68kISelLowering.cpp - M68k DAG Lowering Impl -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the interfaces that M68k uses to lower LLVM code into a
11 /// selection DAG.
12 ///
13 //===----------------------------------------------------------------------===//
14
15 #include "M68kISelLowering.h"
16 #include "M68kCallingConv.h"
17 #include "M68kMachineFunction.h"
18 #include "M68kSubtarget.h"
19 #include "M68kTargetMachine.h"
20 #include "M68kTargetObjectFile.h"
21
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/SelectionDAG.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/GlobalVariable.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/KnownBits.h"
38 #include "llvm/Support/raw_ostream.h"
39
40 using namespace llvm;
41
42 #define DEBUG_TYPE "M68k-isel"
43
44 STATISTIC(NumTailCalls, "Number of tail calls");
45
M68kTargetLowering(const M68kTargetMachine & TM,const M68kSubtarget & STI)46 M68kTargetLowering::M68kTargetLowering(const M68kTargetMachine &TM,
47 const M68kSubtarget &STI)
48 : TargetLowering(TM), Subtarget(STI), TM(TM) {
49
50 MVT PtrVT = MVT::i32;
51
52 setBooleanContents(ZeroOrOneBooleanContent);
53
54 auto *RegInfo = Subtarget.getRegisterInfo();
55 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
56
57 // Set up the register classes.
58 addRegisterClass(MVT::i8, &M68k::DR8RegClass);
59 addRegisterClass(MVT::i16, &M68k::XR16RegClass);
60 addRegisterClass(MVT::i32, &M68k::XR32RegClass);
61
62 for (auto VT : MVT::integer_valuetypes()) {
63 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
64 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
65 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
66 }
67
68 // We don't accept any truncstore of integer registers.
69 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
70 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
71 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
72 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
73 setTruncStoreAction(MVT::i32, MVT::i8, Expand);
74 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
75
76 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i8, Promote);
77 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i16, Legal);
78 if (Subtarget.atLeastM68020())
79 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, Legal);
80 else
81 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, LibCall);
82 setOperationAction(ISD::MUL, MVT::i64, LibCall);
83
84 for (auto OP :
85 {ISD::SREM, ISD::UREM, ISD::UDIVREM, ISD::SDIVREM,
86 ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) {
87 setOperationAction(OP, MVT::i8, Promote);
88 setOperationAction(OP, MVT::i16, Legal);
89 setOperationAction(OP, MVT::i32, LibCall);
90 }
91
92 for (auto OP : {ISD::UMUL_LOHI, ISD::SMUL_LOHI}) {
93 setOperationAction(OP, MVT::i8, Expand);
94 setOperationAction(OP, MVT::i16, Expand);
95 }
96
97 for (auto OP : {ISD::SMULO, ISD::UMULO}) {
98 setOperationAction(OP, MVT::i8, Custom);
99 setOperationAction(OP, MVT::i16, Custom);
100 setOperationAction(OP, MVT::i32, Custom);
101 }
102
103 for (auto OP : {ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS})
104 setOperationAction(OP, MVT::i32, Custom);
105
106 // Add/Sub overflow ops with MVT::Glues are lowered to CCR dependences.
107 for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
108 setOperationAction(ISD::ADDC, VT, Custom);
109 setOperationAction(ISD::ADDE, VT, Custom);
110 setOperationAction(ISD::SUBC, VT, Custom);
111 setOperationAction(ISD::SUBE, VT, Custom);
112 }
113
114 // SADDO and friends are legal with this setup, i hope
115 for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
116 setOperationAction(ISD::SADDO, VT, Custom);
117 setOperationAction(ISD::UADDO, VT, Custom);
118 setOperationAction(ISD::SSUBO, VT, Custom);
119 setOperationAction(ISD::USUBO, VT, Custom);
120 }
121
122 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
123 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
124
125 for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
126 setOperationAction(ISD::BR_CC, VT, Expand);
127 setOperationAction(ISD::SELECT, VT, Custom);
128 setOperationAction(ISD::SELECT_CC, VT, Expand);
129 setOperationAction(ISD::SETCC, VT, Custom);
130 setOperationAction(ISD::SETCCCARRY, VT, Custom);
131 }
132
133 for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
134 setOperationAction(ISD::BSWAP, VT, Expand);
135 setOperationAction(ISD::CTTZ, VT, Expand);
136 setOperationAction(ISD::CTLZ, VT, Expand);
137 setOperationAction(ISD::CTPOP, VT, Expand);
138 }
139
140 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
141 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
142 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
143 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
144 setOperationAction(ISD::ExternalSymbol, MVT::i32, Custom);
145 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
146
147 setOperationAction(ISD::VASTART, MVT::Other, Custom);
148 setOperationAction(ISD::VAEND, MVT::Other, Expand);
149 setOperationAction(ISD::VAARG, MVT::Other, Expand);
150 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
151
152 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
153 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
154
155 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
156
157 computeRegisterProperties(STI.getRegisterInfo());
158
159 // We lower the `atomic-compare-and-swap` to `__sync_val_compare_and_swap`
160 // for subtarget < M68020
161 setMaxAtomicSizeInBitsSupported(32);
162 setOperationAction(ISD::ATOMIC_CMP_SWAP, {MVT::i8, MVT::i16, MVT::i32},
163 Subtarget.atLeastM68020() ? Legal : LibCall);
164
165 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
166
167 // M68k does not have native read-modify-write support, so expand all of them
168 // to `__sync_fetch_*` for target < M68020, otherwise expand to CmpxChg.
169 // See `shouldExpandAtomicRMWInIR` below.
170 setOperationAction(
171 {
172 ISD::ATOMIC_LOAD_ADD,
173 ISD::ATOMIC_LOAD_SUB,
174 ISD::ATOMIC_LOAD_AND,
175 ISD::ATOMIC_LOAD_OR,
176 ISD::ATOMIC_LOAD_XOR,
177 ISD::ATOMIC_LOAD_NAND,
178 ISD::ATOMIC_LOAD_MIN,
179 ISD::ATOMIC_LOAD_MAX,
180 ISD::ATOMIC_LOAD_UMIN,
181 ISD::ATOMIC_LOAD_UMAX,
182 ISD::ATOMIC_SWAP,
183 },
184 {MVT::i8, MVT::i16, MVT::i32}, LibCall);
185
186 setMinFunctionAlignment(Align(2));
187 }
188
189 TargetLoweringBase::AtomicExpansionKind
shouldExpandAtomicRMWInIR(AtomicRMWInst * RMW) const190 M68kTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
191 return Subtarget.atLeastM68020()
192 ? TargetLoweringBase::AtomicExpansionKind::CmpXChg
193 : TargetLoweringBase::AtomicExpansionKind::None;
194 }
195
196 Register
getExceptionPointerRegister(const Constant *) const197 M68kTargetLowering::getExceptionPointerRegister(const Constant *) const {
198 return M68k::D0;
199 }
200
201 Register
getExceptionSelectorRegister(const Constant *) const202 M68kTargetLowering::getExceptionSelectorRegister(const Constant *) const {
203 return M68k::D1;
204 }
205
206 InlineAsm::ConstraintCode
getInlineAsmMemConstraint(StringRef ConstraintCode) const207 M68kTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
208 return StringSwitch<InlineAsm::ConstraintCode>(ConstraintCode)
209 .Case("Q", InlineAsm::ConstraintCode::Q)
210 // We borrow ConstraintCode::Um for 'U'.
211 .Case("U", InlineAsm::ConstraintCode::Um)
212 .Default(TargetLowering::getInlineAsmMemConstraint(ConstraintCode));
213 }
214
getSetCCResultType(const DataLayout & DL,LLVMContext & Context,EVT VT) const215 EVT M68kTargetLowering::getSetCCResultType(const DataLayout &DL,
216 LLVMContext &Context, EVT VT) const {
217 // M68k SETcc producess either 0x00 or 0xFF
218 return MVT::i8;
219 }
220
getScalarShiftAmountTy(const DataLayout & DL,EVT Ty) const221 MVT M68kTargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
222 EVT Ty) const {
223 if (Ty.isSimple()) {
224 return Ty.getSimpleVT();
225 }
226 return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
227 }
228
229 #include "M68kGenCallingConv.inc"
230
231 enum StructReturnType { NotStructReturn, RegStructReturn, StackStructReturn };
232
233 static StructReturnType
callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> & Outs)234 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
235 if (Outs.empty())
236 return NotStructReturn;
237
238 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
239 if (!Flags.isSRet())
240 return NotStructReturn;
241 if (Flags.isInReg())
242 return RegStructReturn;
243 return StackStructReturn;
244 }
245
246 /// Determines whether a function uses struct return semantics.
247 static StructReturnType
argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> & Ins)248 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
249 if (Ins.empty())
250 return NotStructReturn;
251
252 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
253 if (!Flags.isSRet())
254 return NotStructReturn;
255 if (Flags.isInReg())
256 return RegStructReturn;
257 return StackStructReturn;
258 }
259
260 /// Make a copy of an aggregate at address specified by "Src" to address
261 /// "Dst" with size and alignment information specified by the specific
262 /// parameter attribute. The copy will be passed as a byval function parameter.
CreateCopyOfByValArgument(SDValue Src,SDValue Dst,SDValue Chain,ISD::ArgFlagsTy Flags,SelectionDAG & DAG,const SDLoc & DL)263 static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
264 SDValue Chain, ISD::ArgFlagsTy Flags,
265 SelectionDAG &DAG, const SDLoc &DL) {
266 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), DL, MVT::i32);
267
268 return DAG.getMemcpy(
269 Chain, DL, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
270 /*isVolatile=*/false, /*AlwaysInline=*/true,
271 /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
272 }
273
274 /// Return true if the calling convention is one that we can guarantee TCO for.
canGuaranteeTCO(CallingConv::ID CC)275 static bool canGuaranteeTCO(CallingConv::ID CC) { return false; }
276
277 /// Return true if we might ever do TCO for calls with this calling convention.
mayTailCallThisCC(CallingConv::ID CC)278 static bool mayTailCallThisCC(CallingConv::ID CC) {
279 switch (CC) {
280 // C calling conventions:
281 case CallingConv::C:
282 return true;
283 default:
284 return canGuaranteeTCO(CC);
285 }
286 }
287
288 /// Return true if the function is being made into a tailcall target by
289 /// changing its ABI.
shouldGuaranteeTCO(CallingConv::ID CC,bool GuaranteedTailCallOpt)290 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
291 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
292 }
293
294 /// Return true if the given stack call argument is already available in the
295 /// same position (relatively) of the caller's incoming argument stack.
MatchingStackOffset(SDValue Arg,unsigned Offset,ISD::ArgFlagsTy Flags,MachineFrameInfo & MFI,const MachineRegisterInfo * MRI,const M68kInstrInfo * TII,const CCValAssign & VA)296 static bool MatchingStackOffset(SDValue Arg, unsigned Offset,
297 ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI,
298 const MachineRegisterInfo *MRI,
299 const M68kInstrInfo *TII,
300 const CCValAssign &VA) {
301 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
302
303 for (;;) {
304 // Look through nodes that don't alter the bits of the incoming value.
305 unsigned Op = Arg.getOpcode();
306 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
307 Arg = Arg.getOperand(0);
308 continue;
309 }
310 if (Op == ISD::TRUNCATE) {
311 const SDValue &TruncInput = Arg.getOperand(0);
312 if (TruncInput.getOpcode() == ISD::AssertZext &&
313 cast<VTSDNode>(TruncInput.getOperand(1))->getVT() ==
314 Arg.getValueType()) {
315 Arg = TruncInput.getOperand(0);
316 continue;
317 }
318 }
319 break;
320 }
321
322 int FI = INT_MAX;
323 if (Arg.getOpcode() == ISD::CopyFromReg) {
324 Register VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
325 if (!Register::isVirtualRegister(VR))
326 return false;
327 MachineInstr *Def = MRI->getVRegDef(VR);
328 if (!Def)
329 return false;
330 if (!Flags.isByVal()) {
331 if (!TII->isLoadFromStackSlot(*Def, FI))
332 return false;
333 } else {
334 unsigned Opcode = Def->getOpcode();
335 if ((Opcode == M68k::LEA32p || Opcode == M68k::LEA32f) &&
336 Def->getOperand(1).isFI()) {
337 FI = Def->getOperand(1).getIndex();
338 Bytes = Flags.getByValSize();
339 } else
340 return false;
341 }
342 } else if (auto *Ld = dyn_cast<LoadSDNode>(Arg)) {
343 if (Flags.isByVal())
344 // ByVal argument is passed in as a pointer but it's now being
345 // dereferenced. e.g.
346 // define @foo(%struct.X* %A) {
347 // tail call @bar(%struct.X* byval %A)
348 // }
349 return false;
350 SDValue Ptr = Ld->getBasePtr();
351 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
352 if (!FINode)
353 return false;
354 FI = FINode->getIndex();
355 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
356 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
357 FI = FINode->getIndex();
358 Bytes = Flags.getByValSize();
359 } else
360 return false;
361
362 assert(FI != INT_MAX);
363 if (!MFI.isFixedObjectIndex(FI))
364 return false;
365
366 if (Offset != MFI.getObjectOffset(FI))
367 return false;
368
369 if (VA.getLocVT().getSizeInBits() > Arg.getValueType().getSizeInBits()) {
370 // If the argument location is wider than the argument type, check that any
371 // extension flags match.
372 if (Flags.isZExt() != MFI.isObjectZExt(FI) ||
373 Flags.isSExt() != MFI.isObjectSExt(FI)) {
374 return false;
375 }
376 }
377
378 return Bytes == MFI.getObjectSize(FI);
379 }
380
381 SDValue
getReturnAddressFrameIndex(SelectionDAG & DAG) const382 M68kTargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
383 MachineFunction &MF = DAG.getMachineFunction();
384 M68kMachineFunctionInfo *FuncInfo = MF.getInfo<M68kMachineFunctionInfo>();
385 int ReturnAddrIndex = FuncInfo->getRAIndex();
386
387 if (ReturnAddrIndex == 0) {
388 // Set up a frame object for the return address.
389 unsigned SlotSize = Subtarget.getSlotSize();
390 ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(
391 SlotSize, -(int64_t)SlotSize, false);
392 FuncInfo->setRAIndex(ReturnAddrIndex);
393 }
394
395 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
396 }
397
EmitTailCallLoadRetAddr(SelectionDAG & DAG,SDValue & OutRetAddr,SDValue Chain,bool IsTailCall,int FPDiff,const SDLoc & DL) const398 SDValue M68kTargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
399 SDValue &OutRetAddr,
400 SDValue Chain,
401 bool IsTailCall, int FPDiff,
402 const SDLoc &DL) const {
403 EVT VT = getPointerTy(DAG.getDataLayout());
404 OutRetAddr = getReturnAddressFrameIndex(DAG);
405
406 // Load the "old" Return address.
407 OutRetAddr = DAG.getLoad(VT, DL, Chain, OutRetAddr, MachinePointerInfo());
408 return SDValue(OutRetAddr.getNode(), 1);
409 }
410
EmitTailCallStoreRetAddr(SelectionDAG & DAG,MachineFunction & MF,SDValue Chain,SDValue RetFI,EVT PtrVT,unsigned SlotSize,int FPDiff,const SDLoc & DL) const411 SDValue M68kTargetLowering::EmitTailCallStoreRetAddr(
412 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue RetFI,
413 EVT PtrVT, unsigned SlotSize, int FPDiff, const SDLoc &DL) const {
414 if (!FPDiff)
415 return Chain;
416
417 // Calculate the new stack slot for the return address.
418 int NewFO = MF.getFrameInfo().CreateFixedObject(
419 SlotSize, (int64_t)FPDiff - SlotSize, false);
420
421 SDValue NewFI = DAG.getFrameIndex(NewFO, PtrVT);
422 // Store the return address to the appropriate stack slot.
423 Chain = DAG.getStore(
424 Chain, DL, RetFI, NewFI,
425 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewFO));
426 return Chain;
427 }
428
429 SDValue
LowerMemArgument(SDValue Chain,CallingConv::ID CallConv,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,const CCValAssign & VA,MachineFrameInfo & MFI,unsigned ArgIdx) const430 M68kTargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
431 const SmallVectorImpl<ISD::InputArg> &Ins,
432 const SDLoc &DL, SelectionDAG &DAG,
433 const CCValAssign &VA,
434 MachineFrameInfo &MFI,
435 unsigned ArgIdx) const {
436 // Create the nodes corresponding to a load from this parameter slot.
437 ISD::ArgFlagsTy Flags = Ins[ArgIdx].Flags;
438 EVT ValVT;
439
440 // If value is passed by pointer we have address passed instead of the value
441 // itself.
442 if (VA.getLocInfo() == CCValAssign::Indirect)
443 ValVT = VA.getLocVT();
444 else
445 ValVT = VA.getValVT();
446
447 // Because we are dealing with BE architecture we need to offset loading of
448 // partial types
449 int Offset = VA.getLocMemOffset();
450 if (VA.getValVT() == MVT::i8) {
451 Offset += 3;
452 } else if (VA.getValVT() == MVT::i16) {
453 Offset += 2;
454 }
455
456 // TODO Interrupt handlers
457 // Calculate SP offset of interrupt parameter, re-arrange the slot normally
458 // taken by a return address.
459
460 // FIXME For now, all byval parameter objects are marked mutable. This can
461 // be changed with more analysis. In case of tail call optimization mark all
462 // arguments mutable. Since they could be overwritten by lowering of arguments
463 // in case of a tail call.
464 bool AlwaysUseMutable = shouldGuaranteeTCO(
465 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
466 bool IsImmutable = !AlwaysUseMutable && !Flags.isByVal();
467
468 if (Flags.isByVal()) {
469 unsigned Bytes = Flags.getByValSize();
470 if (Bytes == 0)
471 Bytes = 1; // Don't create zero-sized stack objects.
472 int FI = MFI.CreateFixedObject(Bytes, Offset, IsImmutable);
473 // TODO Interrupt handlers
474 // Adjust SP offset of interrupt parameter.
475 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
476 } else {
477 int FI =
478 MFI.CreateFixedObject(ValVT.getSizeInBits() / 8, Offset, IsImmutable);
479
480 // Set SExt or ZExt flag.
481 if (VA.getLocInfo() == CCValAssign::ZExt) {
482 MFI.setObjectZExt(FI, true);
483 } else if (VA.getLocInfo() == CCValAssign::SExt) {
484 MFI.setObjectSExt(FI, true);
485 }
486
487 // TODO Interrupt handlers
488 // Adjust SP offset of interrupt parameter.
489
490 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
491 SDValue Val = DAG.getLoad(
492 ValVT, DL, Chain, FIN,
493 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
494 return VA.isExtInLoc() ? DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val)
495 : Val;
496 }
497 }
498
LowerMemOpCallTo(SDValue Chain,SDValue StackPtr,SDValue Arg,const SDLoc & DL,SelectionDAG & DAG,const CCValAssign & VA,ISD::ArgFlagsTy Flags) const499 SDValue M68kTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
500 SDValue Arg, const SDLoc &DL,
501 SelectionDAG &DAG,
502 const CCValAssign &VA,
503 ISD::ArgFlagsTy Flags) const {
504 unsigned LocMemOffset = VA.getLocMemOffset();
505 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, DL);
506 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
507 StackPtr, PtrOff);
508 if (Flags.isByVal())
509 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, DL);
510
511 return DAG.getStore(
512 Chain, DL, Arg, PtrOff,
513 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
514 }
515
516 //===----------------------------------------------------------------------===//
517 // Call
518 //===----------------------------------------------------------------------===//
519
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const520 SDValue M68kTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
521 SmallVectorImpl<SDValue> &InVals) const {
522 SelectionDAG &DAG = CLI.DAG;
523 SDLoc &DL = CLI.DL;
524 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
525 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
526 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
527 SDValue Chain = CLI.Chain;
528 SDValue Callee = CLI.Callee;
529 CallingConv::ID CallConv = CLI.CallConv;
530 bool &IsTailCall = CLI.IsTailCall;
531 bool IsVarArg = CLI.IsVarArg;
532
533 MachineFunction &MF = DAG.getMachineFunction();
534 StructReturnType SR = callIsStructReturn(Outs);
535 bool IsSibcall = false;
536 M68kMachineFunctionInfo *MFI = MF.getInfo<M68kMachineFunctionInfo>();
537 // const M68kRegisterInfo *TRI = Subtarget.getRegisterInfo();
538
539 if (CallConv == CallingConv::M68k_INTR)
540 report_fatal_error("M68k interrupts may not be called directly");
541
542 auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
543 if (Attr.getValueAsBool())
544 IsTailCall = false;
545
546 // FIXME Add tailcalls support
547
548 bool IsMustTail = CLI.CB && CLI.CB->isMustTailCall();
549 if (IsMustTail) {
550 // Force this to be a tail call. The verifier rules are enough to ensure
551 // that we can lower this successfully without moving the return address
552 // around.
553 IsTailCall = true;
554 } else if (IsTailCall) {
555 // Check if it's really possible to do a tail call.
556 IsTailCall = IsEligibleForTailCallOptimization(
557 Callee, CallConv, IsVarArg, SR != NotStructReturn,
558 MF.getFunction().hasStructRetAttr(), CLI.RetTy, Outs, OutVals, Ins,
559 DAG);
560
561 // Sibcalls are automatically detected tailcalls which do not require
562 // ABI changes.
563 if (!MF.getTarget().Options.GuaranteedTailCallOpt && IsTailCall)
564 IsSibcall = true;
565
566 if (IsTailCall)
567 ++NumTailCalls;
568 }
569
570 assert(!(IsVarArg && canGuaranteeTCO(CallConv)) &&
571 "Var args not supported with calling convention fastcc");
572
573 // Analyze operands of the call, assigning locations to each operand.
574 SmallVector<CCValAssign, 16> ArgLocs;
575 SmallVector<Type *, 4> ArgTypes;
576 for (const auto &Arg : CLI.getArgs())
577 ArgTypes.emplace_back(Arg.Ty);
578 M68kCCState CCInfo(ArgTypes, CallConv, IsVarArg, MF, ArgLocs,
579 *DAG.getContext());
580 CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
581
582 // Get a count of how many bytes are to be pushed on the stack.
583 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
584 if (IsSibcall) {
585 // This is a sibcall. The memory operands are available in caller's
586 // own caller's stack.
587 NumBytes = 0;
588 } else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
589 canGuaranteeTCO(CallConv)) {
590 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
591 }
592
593 int FPDiff = 0;
594 if (IsTailCall && !IsSibcall && !IsMustTail) {
595 // Lower arguments at fp - stackoffset + fpdiff.
596 unsigned NumBytesCallerPushed = MFI->getBytesToPopOnReturn();
597
598 FPDiff = NumBytesCallerPushed - NumBytes;
599
600 // Set the delta of movement of the returnaddr stackslot.
601 // But only set if delta is greater than previous delta.
602 if (FPDiff < MFI->getTCReturnAddrDelta())
603 MFI->setTCReturnAddrDelta(FPDiff);
604 }
605
606 unsigned NumBytesToPush = NumBytes;
607 unsigned NumBytesToPop = NumBytes;
608
609 // If we have an inalloca argument, all stack space has already been allocated
610 // for us and be right at the top of the stack. We don't support multiple
611 // arguments passed in memory when using inalloca.
612 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
613 NumBytesToPush = 0;
614 if (!ArgLocs.back().isMemLoc())
615 report_fatal_error("cannot use inalloca attribute on a register "
616 "parameter");
617 if (ArgLocs.back().getLocMemOffset() != 0)
618 report_fatal_error("any parameter with the inalloca attribute must be "
619 "the only memory argument");
620 }
621
622 if (!IsSibcall)
623 Chain = DAG.getCALLSEQ_START(Chain, NumBytesToPush,
624 NumBytes - NumBytesToPush, DL);
625
626 SDValue RetFI;
627 // Load return address for tail calls.
628 if (IsTailCall && FPDiff)
629 Chain = EmitTailCallLoadRetAddr(DAG, RetFI, Chain, IsTailCall, FPDiff, DL);
630
631 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
632 SmallVector<SDValue, 8> MemOpChains;
633 SDValue StackPtr;
634
635 // Walk the register/memloc assignments, inserting copies/loads. In the case
636 // of tail call optimization arguments are handle later.
637 const M68kRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
638 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
639 ISD::ArgFlagsTy Flags = Outs[i].Flags;
640
641 // Skip inalloca arguments, they have already been written.
642 if (Flags.isInAlloca())
643 continue;
644
645 CCValAssign &VA = ArgLocs[i];
646 EVT RegVT = VA.getLocVT();
647 SDValue Arg = OutVals[i];
648 bool IsByVal = Flags.isByVal();
649
650 // Promote the value if needed.
651 switch (VA.getLocInfo()) {
652 default:
653 llvm_unreachable("Unknown loc info!");
654 case CCValAssign::Full:
655 break;
656 case CCValAssign::SExt:
657 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
658 break;
659 case CCValAssign::ZExt:
660 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
661 break;
662 case CCValAssign::AExt:
663 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
664 break;
665 case CCValAssign::BCvt:
666 Arg = DAG.getBitcast(RegVT, Arg);
667 break;
668 case CCValAssign::Indirect: {
669 // Store the argument.
670 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
671 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
672 Chain = DAG.getStore(
673 Chain, DL, Arg, SpillSlot,
674 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
675 Arg = SpillSlot;
676 break;
677 }
678 }
679
680 if (VA.isRegLoc()) {
681 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
682 } else if (!IsSibcall && (!IsTailCall || IsByVal)) {
683 assert(VA.isMemLoc());
684 if (!StackPtr.getNode()) {
685 StackPtr = DAG.getCopyFromReg(Chain, DL, RegInfo->getStackRegister(),
686 getPointerTy(DAG.getDataLayout()));
687 }
688 MemOpChains.push_back(
689 LowerMemOpCallTo(Chain, StackPtr, Arg, DL, DAG, VA, Flags));
690 }
691 }
692
693 if (!MemOpChains.empty())
694 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
695
696 // FIXME Make sure PIC style GOT works as expected
697 // The only time GOT is really needed is for Medium-PIC static data
698 // otherwise we are happy with pc-rel or static references
699
700 if (IsVarArg && IsMustTail) {
701 const auto &Forwards = MFI->getForwardedMustTailRegParms();
702 for (const auto &F : Forwards) {
703 SDValue Val = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT);
704 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
705 }
706 }
707
708 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
709 // don't need this because the eligibility check rejects calls that require
710 // shuffling arguments passed in memory.
711 if (!IsSibcall && IsTailCall) {
712 // Force all the incoming stack arguments to be loaded from the stack
713 // before any new outgoing arguments are stored to the stack, because the
714 // outgoing stack slots may alias the incoming argument stack slots, and
715 // the alias isn't otherwise explicit. This is slightly more conservative
716 // than necessary, because it means that each store effectively depends
717 // on every argument instead of just those arguments it would clobber.
718 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
719
720 SmallVector<SDValue, 8> MemOpChains2;
721 SDValue FIN;
722 int FI = 0;
723 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
724 CCValAssign &VA = ArgLocs[i];
725 if (VA.isRegLoc())
726 continue;
727 assert(VA.isMemLoc());
728 SDValue Arg = OutVals[i];
729 ISD::ArgFlagsTy Flags = Outs[i].Flags;
730 // Skip inalloca arguments. They don't require any work.
731 if (Flags.isInAlloca())
732 continue;
733 // Create frame index.
734 int32_t Offset = VA.getLocMemOffset() + FPDiff;
735 uint32_t OpSize = (VA.getLocVT().getSizeInBits() + 7) / 8;
736 FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
737 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
738
739 if (Flags.isByVal()) {
740 // Copy relative to framepointer.
741 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), DL);
742 if (!StackPtr.getNode()) {
743 StackPtr = DAG.getCopyFromReg(Chain, DL, RegInfo->getStackRegister(),
744 getPointerTy(DAG.getDataLayout()));
745 }
746 Source = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
747 StackPtr, Source);
748
749 MemOpChains2.push_back(
750 CreateCopyOfByValArgument(Source, FIN, ArgChain, Flags, DAG, DL));
751 } else {
752 // Store relative to framepointer.
753 MemOpChains2.push_back(DAG.getStore(
754 ArgChain, DL, Arg, FIN,
755 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
756 }
757 }
758
759 if (!MemOpChains2.empty())
760 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains2);
761
762 // Store the return address to the appropriate stack slot.
763 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetFI,
764 getPointerTy(DAG.getDataLayout()),
765 Subtarget.getSlotSize(), FPDiff, DL);
766 }
767
768 // Build a sequence of copy-to-reg nodes chained together with token chain
769 // and flag operands which copy the outgoing args into registers.
770 SDValue InGlue;
771 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
772 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
773 RegsToPass[i].second, InGlue);
774 InGlue = Chain.getValue(1);
775 }
776
777 if (Callee->getOpcode() == ISD::GlobalAddress) {
778 // If the callee is a GlobalAddress node (quite common, every direct call
779 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
780 // it.
781 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
782
783 // We should use extra load for direct calls to dllimported functions in
784 // non-JIT mode.
785 const GlobalValue *GV = G->getGlobal();
786 if (!GV->hasDLLImportStorageClass()) {
787 unsigned char OpFlags = Subtarget.classifyGlobalFunctionReference(GV);
788
789 Callee = DAG.getTargetGlobalAddress(
790 GV, DL, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
791
792 if (OpFlags == M68kII::MO_GOTPCREL) {
793
794 // Add a wrapper.
795 Callee = DAG.getNode(M68kISD::WrapperPC, DL,
796 getPointerTy(DAG.getDataLayout()), Callee);
797
798 // Add extra indirection
799 Callee = DAG.getLoad(
800 getPointerTy(DAG.getDataLayout()), DL, DAG.getEntryNode(), Callee,
801 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
802 }
803 }
804 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
805 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
806 unsigned char OpFlags =
807 Subtarget.classifyGlobalFunctionReference(nullptr, *Mod);
808
809 Callee = DAG.getTargetExternalSymbol(
810 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
811 }
812
813 // Returns a chain & a flag for retval copy to use.
814 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
815 SmallVector<SDValue, 8> Ops;
816
817 if (!IsSibcall && IsTailCall) {
818 Chain = DAG.getCALLSEQ_END(Chain, NumBytesToPop, 0, InGlue, DL);
819 InGlue = Chain.getValue(1);
820 }
821
822 Ops.push_back(Chain);
823 Ops.push_back(Callee);
824
825 if (IsTailCall)
826 Ops.push_back(DAG.getConstant(FPDiff, DL, MVT::i32));
827
828 // Add argument registers to the end of the list so that they are known live
829 // into the call.
830 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
831 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
832 RegsToPass[i].second.getValueType()));
833
834 // Add a register mask operand representing the call-preserved registers.
835 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
836 assert(Mask && "Missing call preserved mask for calling convention");
837
838 Ops.push_back(DAG.getRegisterMask(Mask));
839
840 if (InGlue.getNode())
841 Ops.push_back(InGlue);
842
843 if (IsTailCall) {
844 MF.getFrameInfo().setHasTailCall();
845 return DAG.getNode(M68kISD::TC_RETURN, DL, NodeTys, Ops);
846 }
847
848 Chain = DAG.getNode(M68kISD::CALL, DL, NodeTys, Ops);
849 InGlue = Chain.getValue(1);
850
851 // Create the CALLSEQ_END node.
852 unsigned NumBytesForCalleeToPop;
853 if (M68k::isCalleePop(CallConv, IsVarArg,
854 DAG.getTarget().Options.GuaranteedTailCallOpt)) {
855 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
856 } else if (!canGuaranteeTCO(CallConv) && SR == StackStructReturn) {
857 // If this is a call to a struct-return function, the callee
858 // pops the hidden struct pointer, so we have to push it back.
859 NumBytesForCalleeToPop = 4;
860 } else {
861 NumBytesForCalleeToPop = 0; // Callee pops nothing.
862 }
863
864 if (CLI.DoesNotReturn && !getTargetMachine().Options.TrapUnreachable) {
865 // No need to reset the stack after the call if the call doesn't return. To
866 // make the MI verify, we'll pretend the callee does it for us.
867 NumBytesForCalleeToPop = NumBytes;
868 }
869
870 // Returns a flag for retval copy to use.
871 if (!IsSibcall) {
872 Chain = DAG.getCALLSEQ_END(Chain, NumBytesToPop, NumBytesForCalleeToPop,
873 InGlue, DL);
874 InGlue = Chain.getValue(1);
875 }
876
877 // Handle result values, copying them out of physregs into vregs that we
878 // return.
879 return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins, DL, DAG,
880 InVals);
881 }
882
LowerCallResult(SDValue Chain,SDValue InGlue,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const883 SDValue M68kTargetLowering::LowerCallResult(
884 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool IsVarArg,
885 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
886 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
887
888 // Assign locations to each value returned by this call.
889 SmallVector<CCValAssign, 16> RVLocs;
890 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
891 *DAG.getContext());
892 CCInfo.AnalyzeCallResult(Ins, RetCC_M68k);
893
894 // Copy all of the result registers out of their specified physreg.
895 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
896 CCValAssign &VA = RVLocs[i];
897 EVT CopyVT = VA.getLocVT();
898
899 /// ??? is this correct?
900 Chain = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), CopyVT, InGlue)
901 .getValue(1);
902 SDValue Val = Chain.getValue(0);
903
904 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
905 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
906
907 InGlue = Chain.getValue(2);
908 InVals.push_back(Val);
909 }
910
911 return Chain;
912 }
913
914 //===----------------------------------------------------------------------===//
915 // Formal Arguments Calling Convention Implementation
916 //===----------------------------------------------------------------------===//
917
LowerFormalArguments(SDValue Chain,CallingConv::ID CCID,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const918 SDValue M68kTargetLowering::LowerFormalArguments(
919 SDValue Chain, CallingConv::ID CCID, bool IsVarArg,
920 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
921 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
922 MachineFunction &MF = DAG.getMachineFunction();
923 M68kMachineFunctionInfo *MMFI = MF.getInfo<M68kMachineFunctionInfo>();
924 // const TargetFrameLowering &TFL = *Subtarget.getFrameLowering();
925
926 MachineFrameInfo &MFI = MF.getFrameInfo();
927
928 // Assign locations to all of the incoming arguments.
929 SmallVector<CCValAssign, 16> ArgLocs;
930 SmallVector<Type *, 4> ArgTypes;
931 for (const Argument &Arg : MF.getFunction().args())
932 ArgTypes.emplace_back(Arg.getType());
933 M68kCCState CCInfo(ArgTypes, CCID, IsVarArg, MF, ArgLocs, *DAG.getContext());
934
935 CCInfo.AnalyzeFormalArguments(Ins, CC_M68k);
936
937 unsigned LastVal = ~0U;
938 SDValue ArgValue;
939 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
940 CCValAssign &VA = ArgLocs[i];
941 assert(VA.getValNo() != LastVal && "Same value in different locations");
942
943 LastVal = VA.getValNo();
944
945 if (VA.isRegLoc()) {
946 EVT RegVT = VA.getLocVT();
947 const TargetRegisterClass *RC;
948 if (RegVT == MVT::i32)
949 RC = &M68k::XR32RegClass;
950 else
951 llvm_unreachable("Unknown argument type!");
952
953 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
954 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
955
956 // If this is an 8 or 16-bit value, it is really passed promoted to 32
957 // bits. Insert an assert[sz]ext to capture this, then truncate to the
958 // right size.
959 if (VA.getLocInfo() == CCValAssign::SExt) {
960 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
961 DAG.getValueType(VA.getValVT()));
962 } else if (VA.getLocInfo() == CCValAssign::ZExt) {
963 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
964 DAG.getValueType(VA.getValVT()));
965 } else if (VA.getLocInfo() == CCValAssign::BCvt) {
966 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
967 }
968
969 if (VA.isExtInLoc()) {
970 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
971 }
972 } else {
973 assert(VA.isMemLoc());
974 ArgValue = LowerMemArgument(Chain, CCID, Ins, DL, DAG, VA, MFI, i);
975 }
976
977 // If value is passed via pointer - do a load.
978 // TODO Make sure this handling on indirect arguments is correct
979 if (VA.getLocInfo() == CCValAssign::Indirect)
980 ArgValue =
981 DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue, MachinePointerInfo());
982
983 InVals.push_back(ArgValue);
984 }
985
986 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
987 // Swift calling convention does not require we copy the sret argument
988 // into %D0 for the return. We don't set SRetReturnReg for Swift.
989 if (CCID == CallingConv::Swift)
990 continue;
991
992 // ABI require that for returning structs by value we copy the sret argument
993 // into %D0 for the return. Save the argument into a virtual register so
994 // that we can access it from the return points.
995 if (Ins[i].Flags.isSRet()) {
996 unsigned Reg = MMFI->getSRetReturnReg();
997 if (!Reg) {
998 MVT PtrTy = getPointerTy(DAG.getDataLayout());
999 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
1000 MMFI->setSRetReturnReg(Reg);
1001 }
1002 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
1003 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
1004 break;
1005 }
1006 }
1007
1008 unsigned StackSize = CCInfo.getStackSize();
1009 // Align stack specially for tail calls.
1010 if (shouldGuaranteeTCO(CCID, MF.getTarget().Options.GuaranteedTailCallOpt))
1011 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1012
1013 // If the function takes variable number of arguments, make a frame index for
1014 // the start of the first vararg value... for expansion of llvm.va_start. We
1015 // can skip this if there are no va_start calls.
1016 if (MFI.hasVAStart()) {
1017 MMFI->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
1018 }
1019
1020 if (IsVarArg && MFI.hasMustTailInVarArgFunc()) {
1021 // We forward some GPRs and some vector types.
1022 SmallVector<MVT, 2> RegParmTypes;
1023 MVT IntVT = MVT::i32;
1024 RegParmTypes.push_back(IntVT);
1025
1026 // Compute the set of forwarded registers. The rest are scratch.
1027 // ??? what is this for?
1028 SmallVectorImpl<ForwardedRegister> &Forwards =
1029 MMFI->getForwardedMustTailRegParms();
1030 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_M68k);
1031
1032 // Copy all forwards from physical to virtual registers.
1033 for (ForwardedRegister &F : Forwards) {
1034 // FIXME Can we use a less constrained schedule?
1035 SDValue RegVal = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT);
1036 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
1037 Chain = DAG.getCopyToReg(Chain, DL, F.VReg, RegVal);
1038 }
1039 }
1040
1041 // Some CCs need callee pop.
1042 if (M68k::isCalleePop(CCID, IsVarArg,
1043 MF.getTarget().Options.GuaranteedTailCallOpt)) {
1044 MMFI->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1045 } else {
1046 MMFI->setBytesToPopOnReturn(0); // Callee pops nothing.
1047 // If this is an sret function, the return should pop the hidden pointer.
1048 if (!canGuaranteeTCO(CCID) && argsAreStructReturn(Ins) == StackStructReturn)
1049 MMFI->setBytesToPopOnReturn(4);
1050 }
1051
1052 MMFI->setArgumentStackSize(StackSize);
1053
1054 return Chain;
1055 }
1056
1057 //===----------------------------------------------------------------------===//
1058 // Return Value Calling Convention Implementation
1059 //===----------------------------------------------------------------------===//
1060
CanLowerReturn(CallingConv::ID CCID,MachineFunction & MF,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,LLVMContext & Context) const1061 bool M68kTargetLowering::CanLowerReturn(
1062 CallingConv::ID CCID, MachineFunction &MF, bool IsVarArg,
1063 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1064 SmallVector<CCValAssign, 16> RVLocs;
1065 CCState CCInfo(CCID, IsVarArg, MF, RVLocs, Context);
1066 return CCInfo.CheckReturn(Outs, RetCC_M68k);
1067 }
1068
1069 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CCID,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & DL,SelectionDAG & DAG) const1070 M68kTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CCID,
1071 bool IsVarArg,
1072 const SmallVectorImpl<ISD::OutputArg> &Outs,
1073 const SmallVectorImpl<SDValue> &OutVals,
1074 const SDLoc &DL, SelectionDAG &DAG) const {
1075 MachineFunction &MF = DAG.getMachineFunction();
1076 M68kMachineFunctionInfo *MFI = MF.getInfo<M68kMachineFunctionInfo>();
1077
1078 SmallVector<CCValAssign, 16> RVLocs;
1079 CCState CCInfo(CCID, IsVarArg, MF, RVLocs, *DAG.getContext());
1080 CCInfo.AnalyzeReturn(Outs, RetCC_M68k);
1081
1082 SDValue Glue;
1083 SmallVector<SDValue, 6> RetOps;
1084 // Operand #0 = Chain (updated below)
1085 RetOps.push_back(Chain);
1086 // Operand #1 = Bytes To Pop
1087 RetOps.push_back(
1088 DAG.getTargetConstant(MFI->getBytesToPopOnReturn(), DL, MVT::i32));
1089
1090 // Copy the result values into the output registers.
1091 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1092 CCValAssign &VA = RVLocs[i];
1093 assert(VA.isRegLoc() && "Can only return in registers!");
1094 SDValue ValToCopy = OutVals[i];
1095 EVT ValVT = ValToCopy.getValueType();
1096
1097 // Promote values to the appropriate types.
1098 if (VA.getLocInfo() == CCValAssign::SExt)
1099 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy);
1100 else if (VA.getLocInfo() == CCValAssign::ZExt)
1101 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), ValToCopy);
1102 else if (VA.getLocInfo() == CCValAssign::AExt) {
1103 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
1104 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy);
1105 else
1106 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), ValToCopy);
1107 } else if (VA.getLocInfo() == CCValAssign::BCvt)
1108 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
1109
1110 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), ValToCopy, Glue);
1111 Glue = Chain.getValue(1);
1112 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1113 }
1114
1115 // Swift calling convention does not require we copy the sret argument
1116 // into %d0 for the return, and SRetReturnReg is not set for Swift.
1117
1118 // ABI require that for returning structs by value we copy the sret argument
1119 // into %D0 for the return. Save the argument into a virtual register so that
1120 // we can access it from the return points.
1121 //
1122 // Checking Function.hasStructRetAttr() here is insufficient because the IR
1123 // may not have an explicit sret argument. If MFI.CanLowerReturn is
1124 // false, then an sret argument may be implicitly inserted in the SelDAG. In
1125 // either case MFI->setSRetReturnReg() will have been called.
1126 if (unsigned SRetReg = MFI->getSRetReturnReg()) {
1127 // ??? Can i just move this to the top and escape this explanation?
1128 // When we have both sret and another return value, we should use the
1129 // original Chain stored in RetOps[0], instead of the current Chain updated
1130 // in the above loop. If we only have sret, RetOps[0] equals to Chain.
1131
1132 // For the case of sret and another return value, we have
1133 // Chain_0 at the function entry
1134 // Chain_1 = getCopyToReg(Chain_0) in the above loop
1135 // If we use Chain_1 in getCopyFromReg, we will have
1136 // Val = getCopyFromReg(Chain_1)
1137 // Chain_2 = getCopyToReg(Chain_1, Val) from below
1138
1139 // getCopyToReg(Chain_0) will be glued together with
1140 // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
1141 // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
1142 // Data dependency from Unit B to Unit A due to usage of Val in
1143 // getCopyToReg(Chain_1, Val)
1144 // Chain dependency from Unit A to Unit B
1145
1146 // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
1147 SDValue Val = DAG.getCopyFromReg(RetOps[0], DL, SRetReg,
1148 getPointerTy(MF.getDataLayout()));
1149
1150 // ??? How will this work if CC does not use registers for args passing?
1151 // ??? What if I return multiple structs?
1152 unsigned RetValReg = M68k::D0;
1153 Chain = DAG.getCopyToReg(Chain, DL, RetValReg, Val, Glue);
1154 Glue = Chain.getValue(1);
1155
1156 RetOps.push_back(
1157 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
1158 }
1159
1160 RetOps[0] = Chain; // Update chain.
1161
1162 // Add the glue if we have it.
1163 if (Glue.getNode())
1164 RetOps.push_back(Glue);
1165
1166 return DAG.getNode(M68kISD::RET, DL, MVT::Other, RetOps);
1167 }
1168
1169 //===----------------------------------------------------------------------===//
1170 // Fast Calling Convention (tail call) implementation
1171 //===----------------------------------------------------------------------===//
1172
1173 // Like std call, callee cleans arguments, convention except that ECX is
1174 // reserved for storing the tail called function address. Only 2 registers are
1175 // free for argument passing (inreg). Tail call optimization is performed
1176 // provided:
1177 // * tailcallopt is enabled
1178 // * caller/callee are fastcc
1179 // On M68k_64 architecture with GOT-style position independent code only
1180 // local (within module) calls are supported at the moment. To keep the stack
1181 // aligned according to platform abi the function GetAlignedArgumentStackSize
1182 // ensures that argument delta is always multiples of stack alignment. (Dynamic
1183 // linkers need this - darwin's dyld for example) If a tail called function
1184 // callee has more arguments than the caller the caller needs to make sure that
1185 // there is room to move the RETADDR to. This is achieved by reserving an area
1186 // the size of the argument delta right after the original RETADDR, but before
1187 // the saved framepointer or the spilled registers e.g. caller(arg1, arg2)
1188 // calls callee(arg1, arg2,arg3,arg4) stack layout:
1189 // arg1
1190 // arg2
1191 // RETADDR
1192 // [ new RETADDR
1193 // move area ]
1194 // (possible EBP)
1195 // ESI
1196 // EDI
1197 // local1 ..
1198
1199 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
1200 /// requirement.
1201 unsigned
GetAlignedArgumentStackSize(unsigned StackSize,SelectionDAG & DAG) const1202 M68kTargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1203 SelectionDAG &DAG) const {
1204 const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
1205 unsigned StackAlignment = TFI.getStackAlignment();
1206 uint64_t AlignMask = StackAlignment - 1;
1207 int64_t Offset = StackSize;
1208 unsigned SlotSize = Subtarget.getSlotSize();
1209 if ((Offset & AlignMask) <= (StackAlignment - SlotSize)) {
1210 // Number smaller than 12 so just add the difference.
1211 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1212 } else {
1213 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1214 Offset =
1215 ((~AlignMask) & Offset) + StackAlignment + (StackAlignment - SlotSize);
1216 }
1217 return Offset;
1218 }
1219
1220 /// Check whether the call is eligible for tail call optimization. Targets
1221 /// that want to do tail call optimization should implement this function.
IsEligibleForTailCallOptimization(SDValue Callee,CallingConv::ID CalleeCC,bool IsVarArg,bool IsCalleeStructRet,bool IsCallerStructRet,Type * RetTy,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SmallVectorImpl<ISD::InputArg> & Ins,SelectionDAG & DAG) const1222 bool M68kTargetLowering::IsEligibleForTailCallOptimization(
1223 SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
1224 bool IsCalleeStructRet, bool IsCallerStructRet, Type *RetTy,
1225 const SmallVectorImpl<ISD::OutputArg> &Outs,
1226 const SmallVectorImpl<SDValue> &OutVals,
1227 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
1228 if (!mayTailCallThisCC(CalleeCC))
1229 return false;
1230
1231 // If -tailcallopt is specified, make fastcc functions tail-callable.
1232 MachineFunction &MF = DAG.getMachineFunction();
1233 const auto &CallerF = MF.getFunction();
1234
1235 CallingConv::ID CallerCC = CallerF.getCallingConv();
1236 bool CCMatch = CallerCC == CalleeCC;
1237
1238 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
1239 if (canGuaranteeTCO(CalleeCC) && CCMatch)
1240 return true;
1241 return false;
1242 }
1243
1244 // Look for obvious safe cases to perform tail call optimization that do not
1245 // require ABI changes. This is what gcc calls sibcall.
1246
1247 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
1248 // emit a special epilogue.
1249 const M68kRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1250 if (RegInfo->hasStackRealignment(MF))
1251 return false;
1252
1253 // Also avoid sibcall optimization if either caller or callee uses struct
1254 // return semantics.
1255 if (IsCalleeStructRet || IsCallerStructRet)
1256 return false;
1257
1258 // Do not sibcall optimize vararg calls unless all arguments are passed via
1259 // registers.
1260 LLVMContext &C = *DAG.getContext();
1261 if (IsVarArg && !Outs.empty()) {
1262
1263 SmallVector<CCValAssign, 16> ArgLocs;
1264 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, C);
1265
1266 CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
1267 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
1268 if (!ArgLocs[i].isRegLoc())
1269 return false;
1270 }
1271
1272 // Check that the call results are passed in the same way.
1273 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins, RetCC_M68k,
1274 RetCC_M68k))
1275 return false;
1276
1277 // The callee has to preserve all registers the caller needs to preserve.
1278 const M68kRegisterInfo *TRI = Subtarget.getRegisterInfo();
1279 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
1280 if (!CCMatch) {
1281 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
1282 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
1283 return false;
1284 }
1285
1286 unsigned StackArgsSize = 0;
1287
1288 // If the callee takes no arguments then go on to check the results of the
1289 // call.
1290 if (!Outs.empty()) {
1291 // Check if stack adjustment is needed. For now, do not do this if any
1292 // argument is passed on the stack.
1293 SmallVector<CCValAssign, 16> ArgLocs;
1294 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, C);
1295
1296 CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
1297 StackArgsSize = CCInfo.getStackSize();
1298
1299 if (StackArgsSize) {
1300 // Check if the arguments are already laid out in the right way as
1301 // the caller's fixed stack objects.
1302 MachineFrameInfo &MFI = MF.getFrameInfo();
1303 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1304 const M68kInstrInfo *TII = Subtarget.getInstrInfo();
1305 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1306 CCValAssign &VA = ArgLocs[i];
1307 SDValue Arg = OutVals[i];
1308 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1309 if (VA.getLocInfo() == CCValAssign::Indirect)
1310 return false;
1311 if (!VA.isRegLoc()) {
1312 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, MFI, MRI,
1313 TII, VA))
1314 return false;
1315 }
1316 }
1317 }
1318
1319 bool PositionIndependent = isPositionIndependent();
1320 // If the tailcall address may be in a register, then make sure it's
1321 // possible to register allocate for it. The call address can
1322 // only target %A0 or %A1 since the tail call must be scheduled after
1323 // callee-saved registers are restored. These happen to be the same
1324 // registers used to pass 'inreg' arguments so watch out for those.
1325 if ((!isa<GlobalAddressSDNode>(Callee) &&
1326 !isa<ExternalSymbolSDNode>(Callee)) ||
1327 PositionIndependent) {
1328 unsigned NumInRegs = 0;
1329 // In PIC we need an extra register to formulate the address computation
1330 // for the callee.
1331 unsigned MaxInRegs = PositionIndependent ? 1 : 2;
1332
1333 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1334 CCValAssign &VA = ArgLocs[i];
1335 if (!VA.isRegLoc())
1336 continue;
1337 Register Reg = VA.getLocReg();
1338 switch (Reg) {
1339 default:
1340 break;
1341 case M68k::A0:
1342 case M68k::A1:
1343 if (++NumInRegs == MaxInRegs)
1344 return false;
1345 break;
1346 }
1347 }
1348 }
1349
1350 const MachineRegisterInfo &MRI = MF.getRegInfo();
1351 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
1352 return false;
1353 }
1354
1355 bool CalleeWillPop = M68k::isCalleePop(
1356 CalleeCC, IsVarArg, MF.getTarget().Options.GuaranteedTailCallOpt);
1357
1358 if (unsigned BytesToPop =
1359 MF.getInfo<M68kMachineFunctionInfo>()->getBytesToPopOnReturn()) {
1360 // If we have bytes to pop, the callee must pop them.
1361 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
1362 if (!CalleePopMatches)
1363 return false;
1364 } else if (CalleeWillPop && StackArgsSize > 0) {
1365 // If we don't have bytes to pop, make sure the callee doesn't pop any.
1366 return false;
1367 }
1368
1369 return true;
1370 }
1371
1372 //===----------------------------------------------------------------------===//
1373 // Custom Lower
1374 //===----------------------------------------------------------------------===//
1375
LowerOperation(SDValue Op,SelectionDAG & DAG) const1376 SDValue M68kTargetLowering::LowerOperation(SDValue Op,
1377 SelectionDAG &DAG) const {
1378 switch (Op.getOpcode()) {
1379 default:
1380 llvm_unreachable("Should not custom lower this!");
1381 case ISD::SADDO:
1382 case ISD::UADDO:
1383 case ISD::SSUBO:
1384 case ISD::USUBO:
1385 case ISD::SMULO:
1386 case ISD::UMULO:
1387 return LowerXALUO(Op, DAG);
1388 case ISD::SETCC:
1389 return LowerSETCC(Op, DAG);
1390 case ISD::SETCCCARRY:
1391 return LowerSETCCCARRY(Op, DAG);
1392 case ISD::SELECT:
1393 return LowerSELECT(Op, DAG);
1394 case ISD::BRCOND:
1395 return LowerBRCOND(Op, DAG);
1396 case ISD::ADDC:
1397 case ISD::ADDE:
1398 case ISD::SUBC:
1399 case ISD::SUBE:
1400 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1401 case ISD::ConstantPool:
1402 return LowerConstantPool(Op, DAG);
1403 case ISD::GlobalAddress:
1404 return LowerGlobalAddress(Op, DAG);
1405 case ISD::ExternalSymbol:
1406 return LowerExternalSymbol(Op, DAG);
1407 case ISD::BlockAddress:
1408 return LowerBlockAddress(Op, DAG);
1409 case ISD::JumpTable:
1410 return LowerJumpTable(Op, DAG);
1411 case ISD::VASTART:
1412 return LowerVASTART(Op, DAG);
1413 case ISD::DYNAMIC_STACKALLOC:
1414 return LowerDYNAMIC_STACKALLOC(Op, DAG);
1415 case ISD::SHL_PARTS:
1416 return LowerShiftLeftParts(Op, DAG);
1417 case ISD::SRA_PARTS:
1418 return LowerShiftRightParts(Op, DAG, true);
1419 case ISD::SRL_PARTS:
1420 return LowerShiftRightParts(Op, DAG, false);
1421 case ISD::ATOMIC_FENCE:
1422 return LowerATOMICFENCE(Op, DAG);
1423 case ISD::GlobalTLSAddress:
1424 return LowerGlobalTLSAddress(Op, DAG);
1425 }
1426 }
1427
LowerExternalSymbolCall(SelectionDAG & DAG,SDLoc Loc,llvm::StringRef SymbolName,ArgListTy && ArgList) const1428 SDValue M68kTargetLowering::LowerExternalSymbolCall(SelectionDAG &DAG,
1429 SDLoc Loc,
1430 llvm::StringRef SymbolName,
1431 ArgListTy &&ArgList) const {
1432 PointerType *PtrTy = PointerType::get(*DAG.getContext(), 0);
1433 CallLoweringInfo CLI(DAG);
1434 CLI.setDebugLoc(Loc)
1435 .setChain(DAG.getEntryNode())
1436 .setLibCallee(CallingConv::C, PtrTy,
1437 DAG.getExternalSymbol(SymbolName.data(),
1438 getPointerMemTy(DAG.getDataLayout())),
1439 std::move(ArgList));
1440 return LowerCallTo(CLI).first;
1441 }
1442
getTLSGetAddr(GlobalAddressSDNode * GA,SelectionDAG & DAG,unsigned TargetFlags) const1443 SDValue M68kTargetLowering::getTLSGetAddr(GlobalAddressSDNode *GA,
1444 SelectionDAG &DAG,
1445 unsigned TargetFlags) const {
1446 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1447 SDValue TGA = DAG.getTargetGlobalAddress(
1448 GA->getGlobal(), GA, GA->getValueType(0), GA->getOffset(), TargetFlags);
1449 SDValue Arg = DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, GOT, TGA);
1450
1451 PointerType *PtrTy = PointerType::get(*DAG.getContext(), 0);
1452
1453 ArgListTy Args;
1454 ArgListEntry Entry;
1455 Entry.Node = Arg;
1456 Entry.Ty = PtrTy;
1457 Args.push_back(Entry);
1458 return LowerExternalSymbolCall(DAG, SDLoc(GA), "__tls_get_addr",
1459 std::move(Args));
1460 }
1461
getM68kReadTp(SDLoc Loc,SelectionDAG & DAG) const1462 SDValue M68kTargetLowering::getM68kReadTp(SDLoc Loc, SelectionDAG &DAG) const {
1463 return LowerExternalSymbolCall(DAG, Loc, "__m68k_read_tp", ArgListTy());
1464 }
1465
LowerTLSGeneralDynamic(GlobalAddressSDNode * GA,SelectionDAG & DAG) const1466 SDValue M68kTargetLowering::LowerTLSGeneralDynamic(GlobalAddressSDNode *GA,
1467 SelectionDAG &DAG) const {
1468 return getTLSGetAddr(GA, DAG, M68kII::MO_TLSGD);
1469 }
1470
LowerTLSLocalDynamic(GlobalAddressSDNode * GA,SelectionDAG & DAG) const1471 SDValue M68kTargetLowering::LowerTLSLocalDynamic(GlobalAddressSDNode *GA,
1472 SelectionDAG &DAG) const {
1473 SDValue Addr = getTLSGetAddr(GA, DAG, M68kII::MO_TLSLDM);
1474 SDValue TGA =
1475 DAG.getTargetGlobalAddress(GA->getGlobal(), GA, GA->getValueType(0),
1476 GA->getOffset(), M68kII::MO_TLSLD);
1477 return DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, TGA, Addr);
1478 }
1479
LowerTLSInitialExec(GlobalAddressSDNode * GA,SelectionDAG & DAG) const1480 SDValue M68kTargetLowering::LowerTLSInitialExec(GlobalAddressSDNode *GA,
1481 SelectionDAG &DAG) const {
1482 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1483 SDValue Tp = getM68kReadTp(SDLoc(GA), DAG);
1484 SDValue TGA =
1485 DAG.getTargetGlobalAddress(GA->getGlobal(), GA, GA->getValueType(0),
1486 GA->getOffset(), M68kII::MO_TLSIE);
1487 SDValue Addr = DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, TGA, GOT);
1488 SDValue Offset =
1489 DAG.getLoad(MVT::i32, SDLoc(GA), DAG.getEntryNode(), Addr,
1490 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1491
1492 return DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, Offset, Tp);
1493 }
1494
LowerTLSLocalExec(GlobalAddressSDNode * GA,SelectionDAG & DAG) const1495 SDValue M68kTargetLowering::LowerTLSLocalExec(GlobalAddressSDNode *GA,
1496 SelectionDAG &DAG) const {
1497 SDValue Tp = getM68kReadTp(SDLoc(GA), DAG);
1498 SDValue TGA =
1499 DAG.getTargetGlobalAddress(GA->getGlobal(), GA, GA->getValueType(0),
1500 GA->getOffset(), M68kII::MO_TLSLE);
1501 return DAG.getNode(ISD::ADD, SDLoc(GA), MVT::i32, TGA, Tp);
1502 }
1503
LowerGlobalTLSAddress(SDValue Op,SelectionDAG & DAG) const1504 SDValue M68kTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1505 SelectionDAG &DAG) const {
1506 assert(Subtarget.isTargetELF());
1507
1508 auto *GA = cast<GlobalAddressSDNode>(Op);
1509 TLSModel::Model AccessModel = DAG.getTarget().getTLSModel(GA->getGlobal());
1510
1511 switch (AccessModel) {
1512 case TLSModel::GeneralDynamic:
1513 return LowerTLSGeneralDynamic(GA, DAG);
1514 case TLSModel::LocalDynamic:
1515 return LowerTLSLocalDynamic(GA, DAG);
1516 case TLSModel::InitialExec:
1517 return LowerTLSInitialExec(GA, DAG);
1518 case TLSModel::LocalExec:
1519 return LowerTLSLocalExec(GA, DAG);
1520 }
1521
1522 llvm_unreachable("Unexpected TLS access model type");
1523 }
1524
decomposeMulByConstant(LLVMContext & Context,EVT VT,SDValue C) const1525 bool M68kTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
1526 SDValue C) const {
1527 // Shifts and add instructions in M68000 and M68010 support
1528 // up to 32 bits, but mul only has 16-bit variant. So it's almost
1529 // certainly beneficial to lower 8/16/32-bit mul to their
1530 // add / shifts counterparts. But for 64-bits mul, it might be
1531 // safer to just leave it to compiler runtime implementations.
1532 return VT.bitsLE(MVT::i32) || Subtarget.atLeastM68020();
1533 }
1534
isOverflowArithmetic(unsigned Opcode)1535 static bool isOverflowArithmetic(unsigned Opcode) {
1536 switch (Opcode) {
1537 case ISD::UADDO:
1538 case ISD::SADDO:
1539 case ISD::USUBO:
1540 case ISD::SSUBO:
1541 case ISD::UMULO:
1542 case ISD::SMULO:
1543 return true;
1544 default:
1545 return false;
1546 }
1547 }
1548
lowerOverflowArithmetic(SDValue Op,SelectionDAG & DAG,SDValue & Result,SDValue & CCR,unsigned & CC)1549 static void lowerOverflowArithmetic(SDValue Op, SelectionDAG &DAG,
1550 SDValue &Result, SDValue &CCR,
1551 unsigned &CC) {
1552 SDNode *N = Op.getNode();
1553 EVT VT = N->getValueType(0);
1554 SDValue LHS = N->getOperand(0);
1555 SDValue RHS = N->getOperand(1);
1556 SDLoc DL(Op);
1557
1558 unsigned TruncOp = 0;
1559 auto PromoteMULO = [&](unsigned ExtOp) {
1560 // We don't have 8-bit multiplications, so promote i8 version of U/SMULO
1561 // to i16.
1562 // Ideally this should be done by legalizer but sadly there is no promotion
1563 // rule for U/SMULO at this moment.
1564 if (VT == MVT::i8) {
1565 LHS = DAG.getNode(ExtOp, DL, MVT::i16, LHS);
1566 RHS = DAG.getNode(ExtOp, DL, MVT::i16, RHS);
1567 VT = MVT::i16;
1568 TruncOp = ISD::TRUNCATE;
1569 }
1570 };
1571
1572 bool NoOverflow = false;
1573 unsigned BaseOp = 0;
1574 switch (Op.getOpcode()) {
1575 default:
1576 llvm_unreachable("Unknown ovf instruction!");
1577 case ISD::SADDO:
1578 BaseOp = M68kISD::ADD;
1579 CC = M68k::COND_VS;
1580 break;
1581 case ISD::UADDO:
1582 BaseOp = M68kISD::ADD;
1583 CC = M68k::COND_CS;
1584 break;
1585 case ISD::SSUBO:
1586 BaseOp = M68kISD::SUB;
1587 CC = M68k::COND_VS;
1588 break;
1589 case ISD::USUBO:
1590 BaseOp = M68kISD::SUB;
1591 CC = M68k::COND_CS;
1592 break;
1593 case ISD::UMULO:
1594 PromoteMULO(ISD::ZERO_EXTEND);
1595 NoOverflow = VT != MVT::i32;
1596 BaseOp = NoOverflow ? ISD::MUL : M68kISD::UMUL;
1597 CC = M68k::COND_VS;
1598 break;
1599 case ISD::SMULO:
1600 PromoteMULO(ISD::SIGN_EXTEND);
1601 NoOverflow = VT != MVT::i32;
1602 BaseOp = NoOverflow ? ISD::MUL : M68kISD::SMUL;
1603 CC = M68k::COND_VS;
1604 break;
1605 }
1606
1607 SDVTList VTs;
1608 if (NoOverflow)
1609 VTs = DAG.getVTList(VT);
1610 else
1611 // Also sets CCR.
1612 VTs = DAG.getVTList(VT, MVT::i8);
1613
1614 SDValue Arith = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
1615 Result = Arith.getValue(0);
1616 if (TruncOp)
1617 // Right now the only place to truncate is from i16 to i8.
1618 Result = DAG.getNode(TruncOp, DL, MVT::i8, Arith);
1619
1620 if (NoOverflow)
1621 CCR = DAG.getConstant(0, DL, N->getValueType(1));
1622 else
1623 CCR = Arith.getValue(1);
1624 }
1625
LowerXALUO(SDValue Op,SelectionDAG & DAG) const1626 SDValue M68kTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
1627 SDNode *N = Op.getNode();
1628 SDLoc DL(Op);
1629
1630 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
1631 // a "setcc" instruction that checks the overflow flag.
1632 SDValue Result, CCR;
1633 unsigned CC;
1634 lowerOverflowArithmetic(Op, DAG, Result, CCR, CC);
1635
1636 SDValue Overflow;
1637 if (isa<ConstantSDNode>(CCR)) {
1638 // It's likely a result of operations that will not overflow
1639 // hence no setcc is needed.
1640 Overflow = CCR;
1641 } else {
1642 // Generate a M68kISD::SETCC.
1643 Overflow = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1),
1644 DAG.getConstant(CC, DL, MVT::i8), CCR);
1645 }
1646
1647 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Overflow);
1648 }
1649
1650 /// Create a BTST (Bit Test) node - Test bit \p BitNo in \p Src and set
1651 /// condition according to equal/not-equal condition code \p CC.
getBitTestCondition(SDValue Src,SDValue BitNo,ISD::CondCode CC,const SDLoc & DL,SelectionDAG & DAG)1652 static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC,
1653 const SDLoc &DL, SelectionDAG &DAG) {
1654 // If Src is i8, promote it to i32 with any_extend. There is no i8 BTST
1655 // instruction. Since the shift amount is in-range-or-undefined, we know
1656 // that doing a bittest on the i32 value is ok.
1657 if (Src.getValueType() == MVT::i8 || Src.getValueType() == MVT::i16)
1658 Src = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Src);
1659
1660 // If the operand types disagree, extend the shift amount to match. Since
1661 // BTST ignores high bits (like shifts) we can use anyextend.
1662 if (Src.getValueType() != BitNo.getValueType())
1663 BitNo = DAG.getNode(ISD::ANY_EXTEND, DL, Src.getValueType(), BitNo);
1664
1665 SDValue BTST = DAG.getNode(M68kISD::BTST, DL, MVT::i32, Src, BitNo);
1666
1667 // NOTE BTST sets CCR.Z flag
1668 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ;
1669 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
1670 DAG.getConstant(Cond, DL, MVT::i8), BTST);
1671 }
1672
1673 /// Result of 'and' is compared against zero. Change to a BTST node if possible.
LowerAndToBTST(SDValue And,ISD::CondCode CC,const SDLoc & DL,SelectionDAG & DAG)1674 static SDValue LowerAndToBTST(SDValue And, ISD::CondCode CC, const SDLoc &DL,
1675 SelectionDAG &DAG) {
1676 SDValue Op0 = And.getOperand(0);
1677 SDValue Op1 = And.getOperand(1);
1678 if (Op0.getOpcode() == ISD::TRUNCATE)
1679 Op0 = Op0.getOperand(0);
1680 if (Op1.getOpcode() == ISD::TRUNCATE)
1681 Op1 = Op1.getOperand(0);
1682
1683 SDValue LHS, RHS;
1684 if (Op1.getOpcode() == ISD::SHL)
1685 std::swap(Op0, Op1);
1686 if (Op0.getOpcode() == ISD::SHL) {
1687 if (isOneConstant(Op0.getOperand(0))) {
1688 // If we looked past a truncate, check that it's only truncating away
1689 // known zeros.
1690 unsigned BitWidth = Op0.getValueSizeInBits();
1691 unsigned AndBitWidth = And.getValueSizeInBits();
1692 if (BitWidth > AndBitWidth) {
1693 auto Known = DAG.computeKnownBits(Op0);
1694 if (Known.countMinLeadingZeros() < BitWidth - AndBitWidth)
1695 return SDValue();
1696 }
1697 LHS = Op1;
1698 RHS = Op0.getOperand(1);
1699 }
1700 } else if (auto *AndRHS = dyn_cast<ConstantSDNode>(Op1)) {
1701 uint64_t AndRHSVal = AndRHS->getZExtValue();
1702 SDValue AndLHS = Op0;
1703
1704 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
1705 LHS = AndLHS.getOperand(0);
1706 RHS = AndLHS.getOperand(1);
1707 }
1708
1709 // Use BTST if the immediate can't be encoded in a TEST instruction.
1710 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
1711 LHS = AndLHS;
1712 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), DL, LHS.getValueType());
1713 }
1714 }
1715
1716 if (LHS.getNode())
1717 return getBitTestCondition(LHS, RHS, CC, DL, DAG);
1718
1719 return SDValue();
1720 }
1721
TranslateIntegerM68kCC(ISD::CondCode SetCCOpcode)1722 static M68k::CondCode TranslateIntegerM68kCC(ISD::CondCode SetCCOpcode) {
1723 switch (SetCCOpcode) {
1724 default:
1725 llvm_unreachable("Invalid integer condition!");
1726 case ISD::SETEQ:
1727 return M68k::COND_EQ;
1728 case ISD::SETGT:
1729 return M68k::COND_GT;
1730 case ISD::SETGE:
1731 return M68k::COND_GE;
1732 case ISD::SETLT:
1733 return M68k::COND_LT;
1734 case ISD::SETLE:
1735 return M68k::COND_LE;
1736 case ISD::SETNE:
1737 return M68k::COND_NE;
1738 case ISD::SETULT:
1739 return M68k::COND_CS;
1740 case ISD::SETUGE:
1741 return M68k::COND_CC;
1742 case ISD::SETUGT:
1743 return M68k::COND_HI;
1744 case ISD::SETULE:
1745 return M68k::COND_LS;
1746 }
1747 }
1748
1749 /// Do a one-to-one translation of a ISD::CondCode to the M68k-specific
1750 /// condition code, returning the condition code and the LHS/RHS of the
1751 /// comparison to make.
TranslateM68kCC(ISD::CondCode SetCCOpcode,const SDLoc & DL,bool IsFP,SDValue & LHS,SDValue & RHS,SelectionDAG & DAG)1752 static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
1753 bool IsFP, SDValue &LHS, SDValue &RHS,
1754 SelectionDAG &DAG) {
1755 if (!IsFP) {
1756 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1757 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnes()) {
1758 // X > -1 -> X == 0, jump !sign.
1759 RHS = DAG.getConstant(0, DL, RHS.getValueType());
1760 return M68k::COND_PL;
1761 }
1762 if (SetCCOpcode == ISD::SETLT && RHSC->isZero()) {
1763 // X < 0 -> X == 0, jump on sign.
1764 return M68k::COND_MI;
1765 }
1766 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
1767 // X < 1 -> X <= 0
1768 RHS = DAG.getConstant(0, DL, RHS.getValueType());
1769 return M68k::COND_LE;
1770 }
1771 }
1772
1773 return TranslateIntegerM68kCC(SetCCOpcode);
1774 }
1775
1776 // First determine if it is required or is profitable to flip the operands.
1777
1778 // If LHS is a foldable load, but RHS is not, flip the condition.
1779 if (ISD::isNON_EXTLoad(LHS.getNode()) && !ISD::isNON_EXTLoad(RHS.getNode())) {
1780 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
1781 std::swap(LHS, RHS);
1782 }
1783
1784 switch (SetCCOpcode) {
1785 default:
1786 break;
1787 case ISD::SETOLT:
1788 case ISD::SETOLE:
1789 case ISD::SETUGT:
1790 case ISD::SETUGE:
1791 std::swap(LHS, RHS);
1792 break;
1793 }
1794
1795 // On a floating point condition, the flags are set as follows:
1796 // ZF PF CF op
1797 // 0 | 0 | 0 | X > Y
1798 // 0 | 0 | 1 | X < Y
1799 // 1 | 0 | 0 | X == Y
1800 // 1 | 1 | 1 | unordered
1801 switch (SetCCOpcode) {
1802 default:
1803 llvm_unreachable("Condcode should be pre-legalized away");
1804 case ISD::SETUEQ:
1805 case ISD::SETEQ:
1806 return M68k::COND_EQ;
1807 case ISD::SETOLT: // flipped
1808 case ISD::SETOGT:
1809 case ISD::SETGT:
1810 return M68k::COND_HI;
1811 case ISD::SETOLE: // flipped
1812 case ISD::SETOGE:
1813 case ISD::SETGE:
1814 return M68k::COND_CC;
1815 case ISD::SETUGT: // flipped
1816 case ISD::SETULT:
1817 case ISD::SETLT:
1818 return M68k::COND_CS;
1819 case ISD::SETUGE: // flipped
1820 case ISD::SETULE:
1821 case ISD::SETLE:
1822 return M68k::COND_LS;
1823 case ISD::SETONE:
1824 case ISD::SETNE:
1825 return M68k::COND_NE;
1826 case ISD::SETOEQ:
1827 case ISD::SETUNE:
1828 return M68k::COND_INVALID;
1829 }
1830 }
1831
1832 // Convert (truncate (srl X, N) to i1) to (bt X, N)
LowerTruncateToBTST(SDValue Op,ISD::CondCode CC,const SDLoc & DL,SelectionDAG & DAG)1833 static SDValue LowerTruncateToBTST(SDValue Op, ISD::CondCode CC,
1834 const SDLoc &DL, SelectionDAG &DAG) {
1835
1836 assert(Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1 &&
1837 "Expected TRUNCATE to i1 node");
1838
1839 if (Op.getOperand(0).getOpcode() != ISD::SRL)
1840 return SDValue();
1841
1842 SDValue ShiftRight = Op.getOperand(0);
1843 return getBitTestCondition(ShiftRight.getOperand(0), ShiftRight.getOperand(1),
1844 CC, DL, DAG);
1845 }
1846
1847 /// \brief return true if \c Op has a use that doesn't just read flags.
hasNonFlagsUse(SDValue Op)1848 static bool hasNonFlagsUse(SDValue Op) {
1849 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
1850 ++UI) {
1851 SDNode *User = *UI;
1852 unsigned UOpNo = UI.getOperandNo();
1853 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
1854 // Look pass truncate.
1855 UOpNo = User->use_begin().getOperandNo();
1856 User = *User->use_begin();
1857 }
1858
1859 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
1860 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
1861 return true;
1862 }
1863 return false;
1864 }
1865
EmitTest(SDValue Op,unsigned M68kCC,const SDLoc & DL,SelectionDAG & DAG) const1866 SDValue M68kTargetLowering::EmitTest(SDValue Op, unsigned M68kCC,
1867 const SDLoc &DL, SelectionDAG &DAG) const {
1868
1869 // CF and OF aren't always set the way we want. Determine which
1870 // of these we need.
1871 bool NeedCF = false;
1872 bool NeedOF = false;
1873 switch (M68kCC) {
1874 default:
1875 break;
1876 case M68k::COND_HI:
1877 case M68k::COND_CC:
1878 case M68k::COND_CS:
1879 case M68k::COND_LS:
1880 NeedCF = true;
1881 break;
1882 case M68k::COND_GT:
1883 case M68k::COND_GE:
1884 case M68k::COND_LT:
1885 case M68k::COND_LE:
1886 case M68k::COND_VS:
1887 case M68k::COND_VC: {
1888 // Check if we really need to set the
1889 // Overflow flag. If NoSignedWrap is present
1890 // that is not actually needed.
1891 switch (Op->getOpcode()) {
1892 case ISD::ADD:
1893 case ISD::SUB:
1894 case ISD::MUL:
1895 case ISD::SHL: {
1896 if (Op.getNode()->getFlags().hasNoSignedWrap())
1897 break;
1898 [[fallthrough]];
1899 }
1900 default:
1901 NeedOF = true;
1902 break;
1903 }
1904 break;
1905 }
1906 }
1907 // See if we can use the CCR value from the operand instead of
1908 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
1909 // we prove that the arithmetic won't overflow, we can't use OF or CF.
1910 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
1911 // Emit a CMP with 0, which is the TEST pattern.
1912 return DAG.getNode(M68kISD::CMP, DL, MVT::i8,
1913 DAG.getConstant(0, DL, Op.getValueType()), Op);
1914 }
1915 unsigned Opcode = 0;
1916 unsigned NumOperands = 0;
1917
1918 // Truncate operations may prevent the merge of the SETCC instruction
1919 // and the arithmetic instruction before it. Attempt to truncate the operands
1920 // of the arithmetic instruction and use a reduced bit-width instruction.
1921 bool NeedTruncation = false;
1922 SDValue ArithOp = Op;
1923 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
1924 SDValue Arith = Op->getOperand(0);
1925 // Both the trunc and the arithmetic op need to have one user each.
1926 if (Arith->hasOneUse())
1927 switch (Arith.getOpcode()) {
1928 default:
1929 break;
1930 case ISD::ADD:
1931 case ISD::SUB:
1932 case ISD::AND:
1933 case ISD::OR:
1934 case ISD::XOR: {
1935 NeedTruncation = true;
1936 ArithOp = Arith;
1937 }
1938 }
1939 }
1940
1941 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
1942 // which may be the result of a CAST. We use the variable 'Op', which is the
1943 // non-casted variable when we check for possible users.
1944 switch (ArithOp.getOpcode()) {
1945 case ISD::ADD:
1946 Opcode = M68kISD::ADD;
1947 NumOperands = 2;
1948 break;
1949 case ISD::SHL:
1950 case ISD::SRL:
1951 // If we have a constant logical shift that's only used in a comparison
1952 // against zero turn it into an equivalent AND. This allows turning it into
1953 // a TEST instruction later.
1954 if ((M68kCC == M68k::COND_EQ || M68kCC == M68k::COND_NE) &&
1955 Op->hasOneUse() && isa<ConstantSDNode>(Op->getOperand(1)) &&
1956 !hasNonFlagsUse(Op)) {
1957 EVT VT = Op.getValueType();
1958 unsigned BitWidth = VT.getSizeInBits();
1959 unsigned ShAmt = Op->getConstantOperandVal(1);
1960 if (ShAmt >= BitWidth) // Avoid undefined shifts.
1961 break;
1962 APInt Mask = ArithOp.getOpcode() == ISD::SRL
1963 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
1964 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
1965 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
1966 break;
1967 Op = DAG.getNode(ISD::AND, DL, VT, Op->getOperand(0),
1968 DAG.getConstant(Mask, DL, VT));
1969 }
1970 break;
1971
1972 case ISD::AND:
1973 // If the primary 'and' result isn't used, don't bother using
1974 // M68kISD::AND, because a TEST instruction will be better.
1975 if (!hasNonFlagsUse(Op)) {
1976 SDValue Op0 = ArithOp->getOperand(0);
1977 SDValue Op1 = ArithOp->getOperand(1);
1978 EVT VT = ArithOp.getValueType();
1979 bool IsAndn = isBitwiseNot(Op0) || isBitwiseNot(Op1);
1980 bool IsLegalAndnType = VT == MVT::i32 || VT == MVT::i64;
1981
1982 // But if we can combine this into an ANDN operation, then create an AND
1983 // now and allow it to be pattern matched into an ANDN.
1984 if (/*!Subtarget.hasBMI() ||*/ !IsAndn || !IsLegalAndnType)
1985 break;
1986 }
1987 [[fallthrough]];
1988 case ISD::SUB:
1989 case ISD::OR:
1990 case ISD::XOR:
1991 // Due to the ISEL shortcoming noted above, be conservative if this op is
1992 // likely to be selected as part of a load-modify-store instruction.
1993 for (const auto *U : Op.getNode()->uses())
1994 if (U->getOpcode() == ISD::STORE)
1995 goto default_case;
1996
1997 // Otherwise use a regular CCR-setting instruction.
1998 switch (ArithOp.getOpcode()) {
1999 default:
2000 llvm_unreachable("unexpected operator!");
2001 case ISD::SUB:
2002 Opcode = M68kISD::SUB;
2003 break;
2004 case ISD::XOR:
2005 Opcode = M68kISD::XOR;
2006 break;
2007 case ISD::AND:
2008 Opcode = M68kISD::AND;
2009 break;
2010 case ISD::OR:
2011 Opcode = M68kISD::OR;
2012 break;
2013 }
2014
2015 NumOperands = 2;
2016 break;
2017 case M68kISD::ADD:
2018 case M68kISD::SUB:
2019 case M68kISD::OR:
2020 case M68kISD::XOR:
2021 case M68kISD::AND:
2022 return SDValue(Op.getNode(), 1);
2023 default:
2024 default_case:
2025 break;
2026 }
2027
2028 // If we found that truncation is beneficial, perform the truncation and
2029 // update 'Op'.
2030 if (NeedTruncation) {
2031 EVT VT = Op.getValueType();
2032 SDValue WideVal = Op->getOperand(0);
2033 EVT WideVT = WideVal.getValueType();
2034 unsigned ConvertedOp = 0;
2035 // Use a target machine opcode to prevent further DAGCombine
2036 // optimizations that may separate the arithmetic operations
2037 // from the setcc node.
2038 switch (WideVal.getOpcode()) {
2039 default:
2040 break;
2041 case ISD::ADD:
2042 ConvertedOp = M68kISD::ADD;
2043 break;
2044 case ISD::SUB:
2045 ConvertedOp = M68kISD::SUB;
2046 break;
2047 case ISD::AND:
2048 ConvertedOp = M68kISD::AND;
2049 break;
2050 case ISD::OR:
2051 ConvertedOp = M68kISD::OR;
2052 break;
2053 case ISD::XOR:
2054 ConvertedOp = M68kISD::XOR;
2055 break;
2056 }
2057
2058 if (ConvertedOp) {
2059 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2060 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
2061 SDValue V0 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(0));
2062 SDValue V1 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(1));
2063 Op = DAG.getNode(ConvertedOp, DL, VT, V0, V1);
2064 }
2065 }
2066 }
2067
2068 if (Opcode == 0) {
2069 // Emit a CMP with 0, which is the TEST pattern.
2070 return DAG.getNode(M68kISD::CMP, DL, MVT::i8,
2071 DAG.getConstant(0, DL, Op.getValueType()), Op);
2072 }
2073 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i8);
2074 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
2075
2076 SDValue New = DAG.getNode(Opcode, DL, VTs, Ops);
2077 DAG.ReplaceAllUsesWith(Op, New);
2078 return SDValue(New.getNode(), 1);
2079 }
2080
2081 /// \brief Return true if the condition is an unsigned comparison operation.
isM68kCCUnsigned(unsigned M68kCC)2082 static bool isM68kCCUnsigned(unsigned M68kCC) {
2083 switch (M68kCC) {
2084 default:
2085 llvm_unreachable("Invalid integer condition!");
2086 case M68k::COND_EQ:
2087 case M68k::COND_NE:
2088 case M68k::COND_CS:
2089 case M68k::COND_HI:
2090 case M68k::COND_LS:
2091 case M68k::COND_CC:
2092 return true;
2093 case M68k::COND_GT:
2094 case M68k::COND_GE:
2095 case M68k::COND_LT:
2096 case M68k::COND_LE:
2097 return false;
2098 }
2099 }
2100
EmitCmp(SDValue Op0,SDValue Op1,unsigned M68kCC,const SDLoc & DL,SelectionDAG & DAG) const2101 SDValue M68kTargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned M68kCC,
2102 const SDLoc &DL, SelectionDAG &DAG) const {
2103 if (isNullConstant(Op1))
2104 return EmitTest(Op0, M68kCC, DL, DAG);
2105
2106 assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
2107 "Unexpected comparison operation for MVT::i1 operands");
2108
2109 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
2110 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
2111 // Only promote the compare up to I32 if it is a 16 bit operation
2112 // with an immediate. 16 bit immediates are to be avoided.
2113 if ((Op0.getValueType() == MVT::i16 &&
2114 (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1))) &&
2115 !DAG.getMachineFunction().getFunction().hasMinSize()) {
2116 unsigned ExtendOp =
2117 isM68kCCUnsigned(M68kCC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
2118 Op0 = DAG.getNode(ExtendOp, DL, MVT::i32, Op0);
2119 Op1 = DAG.getNode(ExtendOp, DL, MVT::i32, Op1);
2120 }
2121 // Use SUB instead of CMP to enable CSE between SUB and CMP.
2122 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i8);
2123 SDValue Sub = DAG.getNode(M68kISD::SUB, DL, VTs, Op0, Op1);
2124 return SDValue(Sub.getNode(), 1);
2125 }
2126 return DAG.getNode(M68kISD::CMP, DL, MVT::i8, Op0, Op1);
2127 }
2128
2129 /// Result of 'and' or 'trunc to i1' is compared against zero.
2130 /// Change to a BTST node if possible.
LowerToBTST(SDValue Op,ISD::CondCode CC,const SDLoc & DL,SelectionDAG & DAG) const2131 SDValue M68kTargetLowering::LowerToBTST(SDValue Op, ISD::CondCode CC,
2132 const SDLoc &DL,
2133 SelectionDAG &DAG) const {
2134 if (Op.getOpcode() == ISD::AND)
2135 return LowerAndToBTST(Op, CC, DL, DAG);
2136 if (Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1)
2137 return LowerTruncateToBTST(Op, CC, DL, DAG);
2138 return SDValue();
2139 }
2140
LowerSETCC(SDValue Op,SelectionDAG & DAG) const2141 SDValue M68kTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2142 MVT VT = Op.getSimpleValueType();
2143 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
2144
2145 SDValue Op0 = Op.getOperand(0);
2146 SDValue Op1 = Op.getOperand(1);
2147 SDLoc DL(Op);
2148 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2149
2150 // Optimize to BTST if possible.
2151 // Lower (X & (1 << N)) == 0 to BTST(X, N).
2152 // Lower ((X >>u N) & 1) != 0 to BTST(X, N).
2153 // Lower ((X >>s N) & 1) != 0 to BTST(X, N).
2154 // Lower (trunc (X >> N) to i1) to BTST(X, N).
2155 if (Op0.hasOneUse() && isNullConstant(Op1) &&
2156 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2157 if (SDValue NewSetCC = LowerToBTST(Op0, CC, DL, DAG)) {
2158 if (VT == MVT::i1)
2159 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, NewSetCC);
2160 return NewSetCC;
2161 }
2162 }
2163
2164 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
2165 // these.
2166 if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
2167 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2168
2169 // If the input is a setcc, then reuse the input setcc or use a new one with
2170 // the inverted condition.
2171 if (Op0.getOpcode() == M68kISD::SETCC) {
2172 M68k::CondCode CCode = (M68k::CondCode)Op0.getConstantOperandVal(0);
2173 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
2174 if (!Invert)
2175 return Op0;
2176
2177 CCode = M68k::GetOppositeBranchCondition(CCode);
2178 SDValue SetCC =
2179 DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
2180 DAG.getConstant(CCode, DL, MVT::i8), Op0.getOperand(1));
2181 if (VT == MVT::i1)
2182 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
2183 return SetCC;
2184 }
2185 }
2186 if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2187 if (isOneConstant(Op1)) {
2188 ISD::CondCode NewCC = ISD::GlobalISel::getSetCCInverse(CC, true);
2189 return DAG.getSetCC(DL, VT, Op0, DAG.getConstant(0, DL, MVT::i1), NewCC);
2190 }
2191 if (!isNullConstant(Op1)) {
2192 SDValue Xor = DAG.getNode(ISD::XOR, DL, MVT::i1, Op0, Op1);
2193 return DAG.getSetCC(DL, VT, Xor, DAG.getConstant(0, DL, MVT::i1), CC);
2194 }
2195 }
2196
2197 bool IsFP = Op1.getSimpleValueType().isFloatingPoint();
2198 unsigned M68kCC = TranslateM68kCC(CC, DL, IsFP, Op0, Op1, DAG);
2199 if (M68kCC == M68k::COND_INVALID)
2200 return SDValue();
2201
2202 SDValue CCR = EmitCmp(Op0, Op1, M68kCC, DL, DAG);
2203 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
2204 DAG.getConstant(M68kCC, DL, MVT::i8), CCR);
2205 }
2206
LowerSETCCCARRY(SDValue Op,SelectionDAG & DAG) const2207 SDValue M68kTargetLowering::LowerSETCCCARRY(SDValue Op,
2208 SelectionDAG &DAG) const {
2209 SDValue LHS = Op.getOperand(0);
2210 SDValue RHS = Op.getOperand(1);
2211 SDValue Carry = Op.getOperand(2);
2212 SDValue Cond = Op.getOperand(3);
2213 SDLoc DL(Op);
2214
2215 assert(LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only.");
2216 M68k::CondCode CC = TranslateIntegerM68kCC(cast<CondCodeSDNode>(Cond)->get());
2217
2218 EVT CarryVT = Carry.getValueType();
2219 APInt NegOne = APInt::getAllOnes(CarryVT.getScalarSizeInBits());
2220 Carry = DAG.getNode(M68kISD::ADD, DL, DAG.getVTList(CarryVT, MVT::i32), Carry,
2221 DAG.getConstant(NegOne, DL, CarryVT));
2222
2223 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
2224 SDValue Cmp =
2225 DAG.getNode(M68kISD::SUBX, DL, VTs, LHS, RHS, Carry.getValue(1));
2226
2227 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
2228 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
2229 }
2230
2231 /// Return true if opcode is a M68k logical comparison.
isM68kLogicalCmp(SDValue Op)2232 static bool isM68kLogicalCmp(SDValue Op) {
2233 unsigned Opc = Op.getNode()->getOpcode();
2234 if (Opc == M68kISD::CMP)
2235 return true;
2236 if (Op.getResNo() == 1 &&
2237 (Opc == M68kISD::ADD || Opc == M68kISD::SUB || Opc == M68kISD::ADDX ||
2238 Opc == M68kISD::SUBX || Opc == M68kISD::SMUL || Opc == M68kISD::UMUL ||
2239 Opc == M68kISD::OR || Opc == M68kISD::XOR || Opc == M68kISD::AND))
2240 return true;
2241
2242 if (Op.getResNo() == 2 && Opc == M68kISD::UMUL)
2243 return true;
2244
2245 return false;
2246 }
2247
isTruncWithZeroHighBitsInput(SDValue V,SelectionDAG & DAG)2248 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
2249 if (V.getOpcode() != ISD::TRUNCATE)
2250 return false;
2251
2252 SDValue VOp0 = V.getOperand(0);
2253 unsigned InBits = VOp0.getValueSizeInBits();
2254 unsigned Bits = V.getValueSizeInBits();
2255 return DAG.MaskedValueIsZero(VOp0,
2256 APInt::getHighBitsSet(InBits, InBits - Bits));
2257 }
2258
LowerSELECT(SDValue Op,SelectionDAG & DAG) const2259 SDValue M68kTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2260 bool addTest = true;
2261 SDValue Cond = Op.getOperand(0);
2262 SDValue Op1 = Op.getOperand(1);
2263 SDValue Op2 = Op.getOperand(2);
2264 SDLoc DL(Op);
2265 SDValue CC;
2266
2267 if (Cond.getOpcode() == ISD::SETCC) {
2268 if (SDValue NewCond = LowerSETCC(Cond, DAG))
2269 Cond = NewCond;
2270 }
2271
2272 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
2273 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
2274 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
2275 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
2276 if (Cond.getOpcode() == M68kISD::SETCC &&
2277 Cond.getOperand(1).getOpcode() == M68kISD::CMP &&
2278 isNullConstant(Cond.getOperand(1).getOperand(0))) {
2279 SDValue Cmp = Cond.getOperand(1);
2280
2281 unsigned CondCode = Cond.getConstantOperandVal(0);
2282
2283 if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
2284 (CondCode == M68k::COND_EQ || CondCode == M68k::COND_NE)) {
2285 SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
2286
2287 SDValue CmpOp0 = Cmp.getOperand(1);
2288 // Apply further optimizations for special cases
2289 // (select (x != 0), -1, 0) -> neg & sbb
2290 // (select (x == 0), 0, -1) -> neg & sbb
2291 if (isNullConstant(Y) &&
2292 (isAllOnesConstant(Op1) == (CondCode == M68k::COND_NE))) {
2293
2294 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
2295
2296 SDValue Neg =
2297 DAG.getNode(M68kISD::SUB, DL, VTs,
2298 DAG.getConstant(0, DL, CmpOp0.getValueType()), CmpOp0);
2299
2300 SDValue Res = DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2301 DAG.getConstant(M68k::COND_CS, DL, MVT::i8),
2302 SDValue(Neg.getNode(), 1));
2303 return Res;
2304 }
2305
2306 Cmp = DAG.getNode(M68kISD::CMP, DL, MVT::i8,
2307 DAG.getConstant(1, DL, CmpOp0.getValueType()), CmpOp0);
2308
2309 SDValue Res = // Res = 0 or -1.
2310 DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2311 DAG.getConstant(M68k::COND_CS, DL, MVT::i8), Cmp);
2312
2313 if (isAllOnesConstant(Op1) != (CondCode == M68k::COND_EQ))
2314 Res = DAG.getNOT(DL, Res, Res.getValueType());
2315
2316 if (!isNullConstant(Op2))
2317 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
2318 return Res;
2319 }
2320 }
2321
2322 // Look past (and (setcc_carry (cmp ...)), 1).
2323 if (Cond.getOpcode() == ISD::AND &&
2324 Cond.getOperand(0).getOpcode() == M68kISD::SETCC_CARRY &&
2325 isOneConstant(Cond.getOperand(1)))
2326 Cond = Cond.getOperand(0);
2327
2328 // If condition flag is set by a M68kISD::CMP, then use it as the condition
2329 // setting operand in place of the M68kISD::SETCC.
2330 unsigned CondOpcode = Cond.getOpcode();
2331 if (CondOpcode == M68kISD::SETCC || CondOpcode == M68kISD::SETCC_CARRY) {
2332 CC = Cond.getOperand(0);
2333
2334 SDValue Cmp = Cond.getOperand(1);
2335 unsigned Opc = Cmp.getOpcode();
2336
2337 bool IllegalFPCMov = false;
2338
2339 if ((isM68kLogicalCmp(Cmp) && !IllegalFPCMov) || Opc == M68kISD::BTST) {
2340 Cond = Cmp;
2341 addTest = false;
2342 }
2343 } else if (isOverflowArithmetic(CondOpcode)) {
2344 // Result is unused here.
2345 SDValue Result;
2346 unsigned CCode;
2347 lowerOverflowArithmetic(Cond, DAG, Result, Cond, CCode);
2348 CC = DAG.getConstant(CCode, DL, MVT::i8);
2349 addTest = false;
2350 }
2351
2352 if (addTest) {
2353 // Look past the truncate if the high bits are known zero.
2354 if (isTruncWithZeroHighBitsInput(Cond, DAG))
2355 Cond = Cond.getOperand(0);
2356
2357 // We know the result of AND is compared against zero. Try to match
2358 // it to BT.
2359 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
2360 if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) {
2361 CC = NewSetCC.getOperand(0);
2362 Cond = NewSetCC.getOperand(1);
2363 addTest = false;
2364 }
2365 }
2366 }
2367
2368 if (addTest) {
2369 CC = DAG.getConstant(M68k::COND_NE, DL, MVT::i8);
2370 Cond = EmitTest(Cond, M68k::COND_NE, DL, DAG);
2371 }
2372
2373 // a < b ? -1 : 0 -> RES = ~setcc_carry
2374 // a < b ? 0 : -1 -> RES = setcc_carry
2375 // a >= b ? -1 : 0 -> RES = setcc_carry
2376 // a >= b ? 0 : -1 -> RES = ~setcc_carry
2377 if (Cond.getOpcode() == M68kISD::SUB) {
2378 unsigned CondCode = CC->getAsZExtVal();
2379
2380 if ((CondCode == M68k::COND_CC || CondCode == M68k::COND_CS) &&
2381 (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
2382 (isNullConstant(Op1) || isNullConstant(Op2))) {
2383 SDValue Res =
2384 DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2385 DAG.getConstant(M68k::COND_CS, DL, MVT::i8), Cond);
2386 if (isAllOnesConstant(Op1) != (CondCode == M68k::COND_CS))
2387 return DAG.getNOT(DL, Res, Res.getValueType());
2388 return Res;
2389 }
2390 }
2391
2392 // M68k doesn't have an i8 cmov. If both operands are the result of a
2393 // truncate widen the cmov and push the truncate through. This avoids
2394 // introducing a new branch during isel and doesn't add any extensions.
2395 if (Op.getValueType() == MVT::i8 && Op1.getOpcode() == ISD::TRUNCATE &&
2396 Op2.getOpcode() == ISD::TRUNCATE) {
2397 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
2398 if (T1.getValueType() == T2.getValueType() &&
2399 // Block CopyFromReg so partial register stalls are avoided.
2400 T1.getOpcode() != ISD::CopyFromReg &&
2401 T2.getOpcode() != ISD::CopyFromReg) {
2402 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
2403 SDValue Cmov = DAG.getNode(M68kISD::CMOV, DL, VTs, T2, T1, CC, Cond);
2404 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
2405 }
2406 }
2407
2408 // Simple optimization when Cond is a constant to avoid generating
2409 // M68kISD::CMOV if possible.
2410 // TODO: Generalize this to use SelectionDAG::computeKnownBits.
2411 if (auto *Const = dyn_cast<ConstantSDNode>(Cond.getNode())) {
2412 const APInt &C = Const->getAPIntValue();
2413 if (C.countr_zero() >= 5)
2414 return Op2;
2415 else if (C.countr_one() >= 5)
2416 return Op1;
2417 }
2418
2419 // M68kISD::CMOV means set the result (which is operand 1) to the RHS if
2420 // condition is true.
2421 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
2422 SDValue Ops[] = {Op2, Op1, CC, Cond};
2423 return DAG.getNode(M68kISD::CMOV, DL, VTs, Ops);
2424 }
2425
2426 /// Return true if node is an ISD::AND or ISD::OR of two M68k::SETcc nodes
2427 /// each of which has no other use apart from the AND / OR.
isAndOrOfSetCCs(SDValue Op,unsigned & Opc)2428 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
2429 Opc = Op.getOpcode();
2430 if (Opc != ISD::OR && Opc != ISD::AND)
2431 return false;
2432 return (M68k::IsSETCC(Op.getOperand(0).getOpcode()) &&
2433 Op.getOperand(0).hasOneUse() &&
2434 M68k::IsSETCC(Op.getOperand(1).getOpcode()) &&
2435 Op.getOperand(1).hasOneUse());
2436 }
2437
2438 /// Return true if node is an ISD::XOR of a M68kISD::SETCC and 1 and that the
2439 /// SETCC node has a single use.
isXor1OfSetCC(SDValue Op)2440 static bool isXor1OfSetCC(SDValue Op) {
2441 if (Op.getOpcode() != ISD::XOR)
2442 return false;
2443 if (isOneConstant(Op.getOperand(1)))
2444 return Op.getOperand(0).getOpcode() == M68kISD::SETCC &&
2445 Op.getOperand(0).hasOneUse();
2446 return false;
2447 }
2448
LowerBRCOND(SDValue Op,SelectionDAG & DAG) const2449 SDValue M68kTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
2450 bool AddTest = true;
2451 SDValue Chain = Op.getOperand(0);
2452 SDValue Cond = Op.getOperand(1);
2453 SDValue Dest = Op.getOperand(2);
2454 SDLoc DL(Op);
2455 SDValue CC;
2456 bool Inverted = false;
2457
2458 if (Cond.getOpcode() == ISD::SETCC) {
2459 // Check for setcc([su]{add,sub}o == 0).
2460 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
2461 isNullConstant(Cond.getOperand(1)) &&
2462 Cond.getOperand(0).getResNo() == 1 &&
2463 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
2464 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
2465 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
2466 Cond.getOperand(0).getOpcode() == ISD::USUBO)) {
2467 Inverted = true;
2468 Cond = Cond.getOperand(0);
2469 } else {
2470 if (SDValue NewCond = LowerSETCC(Cond, DAG))
2471 Cond = NewCond;
2472 }
2473 }
2474
2475 // Look pass (and (setcc_carry (cmp ...)), 1).
2476 if (Cond.getOpcode() == ISD::AND &&
2477 Cond.getOperand(0).getOpcode() == M68kISD::SETCC_CARRY &&
2478 isOneConstant(Cond.getOperand(1)))
2479 Cond = Cond.getOperand(0);
2480
2481 // If condition flag is set by a M68kISD::CMP, then use it as the condition
2482 // setting operand in place of the M68kISD::SETCC.
2483 unsigned CondOpcode = Cond.getOpcode();
2484 if (CondOpcode == M68kISD::SETCC || CondOpcode == M68kISD::SETCC_CARRY) {
2485 CC = Cond.getOperand(0);
2486
2487 SDValue Cmp = Cond.getOperand(1);
2488 unsigned Opc = Cmp.getOpcode();
2489
2490 if (isM68kLogicalCmp(Cmp) || Opc == M68kISD::BTST) {
2491 Cond = Cmp;
2492 AddTest = false;
2493 } else {
2494 switch (CC->getAsZExtVal()) {
2495 default:
2496 break;
2497 case M68k::COND_VS:
2498 case M68k::COND_CS:
2499 // These can only come from an arithmetic instruction with overflow,
2500 // e.g. SADDO, UADDO.
2501 Cond = Cond.getNode()->getOperand(1);
2502 AddTest = false;
2503 break;
2504 }
2505 }
2506 }
2507 CondOpcode = Cond.getOpcode();
2508 if (isOverflowArithmetic(CondOpcode)) {
2509 SDValue Result;
2510 unsigned CCode;
2511 lowerOverflowArithmetic(Cond, DAG, Result, Cond, CCode);
2512
2513 if (Inverted)
2514 CCode = M68k::GetOppositeBranchCondition((M68k::CondCode)CCode);
2515 CC = DAG.getConstant(CCode, DL, MVT::i8);
2516
2517 AddTest = false;
2518 } else {
2519 unsigned CondOpc;
2520 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
2521 SDValue Cmp = Cond.getOperand(0).getOperand(1);
2522 if (CondOpc == ISD::OR) {
2523 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
2524 // two branches instead of an explicit OR instruction with a
2525 // separate test.
2526 if (Cmp == Cond.getOperand(1).getOperand(1) && isM68kLogicalCmp(Cmp)) {
2527 CC = Cond.getOperand(0).getOperand(0);
2528 Chain = DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain,
2529 Dest, CC, Cmp);
2530 CC = Cond.getOperand(1).getOperand(0);
2531 Cond = Cmp;
2532 AddTest = false;
2533 }
2534 } else { // ISD::AND
2535 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
2536 // two branches instead of an explicit AND instruction with a
2537 // separate test. However, we only do this if this block doesn't
2538 // have a fall-through edge, because this requires an explicit
2539 // jmp when the condition is false.
2540 if (Cmp == Cond.getOperand(1).getOperand(1) && isM68kLogicalCmp(Cmp) &&
2541 Op.getNode()->hasOneUse()) {
2542 M68k::CondCode CCode =
2543 (M68k::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
2544 CCode = M68k::GetOppositeBranchCondition(CCode);
2545 CC = DAG.getConstant(CCode, DL, MVT::i8);
2546 SDNode *User = *Op.getNode()->use_begin();
2547 // Look for an unconditional branch following this conditional branch.
2548 // We need this because we need to reverse the successors in order
2549 // to implement FCMP_OEQ.
2550 if (User->getOpcode() == ISD::BR) {
2551 SDValue FalseBB = User->getOperand(1);
2552 SDNode *NewBR =
2553 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
2554 assert(NewBR == User);
2555 (void)NewBR;
2556 Dest = FalseBB;
2557
2558 Chain = DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain,
2559 Dest, CC, Cmp);
2560 M68k::CondCode CCode =
2561 (M68k::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
2562 CCode = M68k::GetOppositeBranchCondition(CCode);
2563 CC = DAG.getConstant(CCode, DL, MVT::i8);
2564 Cond = Cmp;
2565 AddTest = false;
2566 }
2567 }
2568 }
2569 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
2570 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
2571 // It should be transformed during dag combiner except when the condition
2572 // is set by a arithmetics with overflow node.
2573 M68k::CondCode CCode =
2574 (M68k::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
2575 CCode = M68k::GetOppositeBranchCondition(CCode);
2576 CC = DAG.getConstant(CCode, DL, MVT::i8);
2577 Cond = Cond.getOperand(0).getOperand(1);
2578 AddTest = false;
2579 }
2580 }
2581
2582 if (AddTest) {
2583 // Look pass the truncate if the high bits are known zero.
2584 if (isTruncWithZeroHighBitsInput(Cond, DAG))
2585 Cond = Cond.getOperand(0);
2586
2587 // We know the result is compared against zero. Try to match it to BT.
2588 if (Cond.hasOneUse()) {
2589 if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) {
2590 CC = NewSetCC.getOperand(0);
2591 Cond = NewSetCC.getOperand(1);
2592 AddTest = false;
2593 }
2594 }
2595 }
2596
2597 if (AddTest) {
2598 M68k::CondCode MxCond = Inverted ? M68k::COND_EQ : M68k::COND_NE;
2599 CC = DAG.getConstant(MxCond, DL, MVT::i8);
2600 Cond = EmitTest(Cond, MxCond, DL, DAG);
2601 }
2602 return DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain, Dest, CC,
2603 Cond);
2604 }
2605
LowerADDC_ADDE_SUBC_SUBE(SDValue Op,SelectionDAG & DAG) const2606 SDValue M68kTargetLowering::LowerADDC_ADDE_SUBC_SUBE(SDValue Op,
2607 SelectionDAG &DAG) const {
2608 MVT VT = Op.getNode()->getSimpleValueType(0);
2609
2610 // Let legalize expand this if it isn't a legal type yet.
2611 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
2612 return SDValue();
2613
2614 SDVTList VTs = DAG.getVTList(VT, MVT::i8);
2615
2616 unsigned Opc;
2617 bool ExtraOp = false;
2618 switch (Op.getOpcode()) {
2619 default:
2620 llvm_unreachable("Invalid code");
2621 case ISD::ADDC:
2622 Opc = M68kISD::ADD;
2623 break;
2624 case ISD::ADDE:
2625 Opc = M68kISD::ADDX;
2626 ExtraOp = true;
2627 break;
2628 case ISD::SUBC:
2629 Opc = M68kISD::SUB;
2630 break;
2631 case ISD::SUBE:
2632 Opc = M68kISD::SUBX;
2633 ExtraOp = true;
2634 break;
2635 }
2636
2637 if (!ExtraOp)
2638 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
2639 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
2640 Op.getOperand(2));
2641 }
2642
2643 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2644 // their target countpart wrapped in the M68kISD::Wrapper node. Suppose N is
2645 // one of the above mentioned nodes. It has to be wrapped because otherwise
2646 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2647 // be used to form addressing mode. These wrapped nodes will be selected
2648 // into MOV32ri.
LowerConstantPool(SDValue Op,SelectionDAG & DAG) const2649 SDValue M68kTargetLowering::LowerConstantPool(SDValue Op,
2650 SelectionDAG &DAG) const {
2651 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2652
2653 // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2654 // global base reg.
2655 unsigned char OpFlag = Subtarget.classifyLocalReference(nullptr);
2656
2657 unsigned WrapperKind = M68kISD::Wrapper;
2658 if (M68kII::isPCRelGlobalReference(OpFlag)) {
2659 WrapperKind = M68kISD::WrapperPC;
2660 }
2661
2662 MVT PtrVT = getPointerTy(DAG.getDataLayout());
2663 SDValue Result = DAG.getTargetConstantPool(
2664 CP->getConstVal(), PtrVT, CP->getAlign(), CP->getOffset(), OpFlag);
2665
2666 SDLoc DL(CP);
2667 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2668
2669 // With PIC, the address is actually $g + Offset.
2670 if (M68kII::isGlobalRelativeToPICBase(OpFlag)) {
2671 Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2672 DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2673 Result);
2674 }
2675
2676 return Result;
2677 }
2678
LowerExternalSymbol(SDValue Op,SelectionDAG & DAG) const2679 SDValue M68kTargetLowering::LowerExternalSymbol(SDValue Op,
2680 SelectionDAG &DAG) const {
2681 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
2682
2683 // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2684 // global base reg.
2685 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
2686 unsigned char OpFlag = Subtarget.classifyExternalReference(*Mod);
2687
2688 unsigned WrapperKind = M68kISD::Wrapper;
2689 if (M68kII::isPCRelGlobalReference(OpFlag)) {
2690 WrapperKind = M68kISD::WrapperPC;
2691 }
2692
2693 auto PtrVT = getPointerTy(DAG.getDataLayout());
2694 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
2695
2696 SDLoc DL(Op);
2697 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2698
2699 // With PIC, the address is actually $g + Offset.
2700 if (M68kII::isGlobalRelativeToPICBase(OpFlag)) {
2701 Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2702 DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2703 Result);
2704 }
2705
2706 // For symbols that require a load from a stub to get the address, emit the
2707 // load.
2708 if (M68kII::isGlobalStubReference(OpFlag)) {
2709 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2710 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2711 }
2712
2713 return Result;
2714 }
2715
LowerBlockAddress(SDValue Op,SelectionDAG & DAG) const2716 SDValue M68kTargetLowering::LowerBlockAddress(SDValue Op,
2717 SelectionDAG &DAG) const {
2718 unsigned char OpFlags = Subtarget.classifyBlockAddressReference();
2719 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2720 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
2721 SDLoc DL(Op);
2722 auto PtrVT = getPointerTy(DAG.getDataLayout());
2723
2724 // Create the TargetBlockAddressAddress node.
2725 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
2726
2727 if (M68kII::isPCRelBlockReference(OpFlags)) {
2728 Result = DAG.getNode(M68kISD::WrapperPC, DL, PtrVT, Result);
2729 } else {
2730 Result = DAG.getNode(M68kISD::Wrapper, DL, PtrVT, Result);
2731 }
2732
2733 // With PIC, the address is actually $g + Offset.
2734 if (M68kII::isGlobalRelativeToPICBase(OpFlags)) {
2735 Result =
2736 DAG.getNode(ISD::ADD, DL, PtrVT,
2737 DAG.getNode(M68kISD::GLOBAL_BASE_REG, DL, PtrVT), Result);
2738 }
2739
2740 return Result;
2741 }
2742
LowerGlobalAddress(const GlobalValue * GV,const SDLoc & DL,int64_t Offset,SelectionDAG & DAG) const2743 SDValue M68kTargetLowering::LowerGlobalAddress(const GlobalValue *GV,
2744 const SDLoc &DL, int64_t Offset,
2745 SelectionDAG &DAG) const {
2746 unsigned char OpFlags = Subtarget.classifyGlobalReference(GV);
2747 auto PtrVT = getPointerTy(DAG.getDataLayout());
2748
2749 // Create the TargetGlobalAddress node, folding in the constant
2750 // offset if it is legal.
2751 SDValue Result;
2752 if (M68kII::isDirectGlobalReference(OpFlags)) {
2753 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Offset);
2754 Offset = 0;
2755 } else {
2756 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2757 }
2758
2759 if (M68kII::isPCRelGlobalReference(OpFlags))
2760 Result = DAG.getNode(M68kISD::WrapperPC, DL, PtrVT, Result);
2761 else
2762 Result = DAG.getNode(M68kISD::Wrapper, DL, PtrVT, Result);
2763
2764 // With PIC, the address is actually $g + Offset.
2765 if (M68kII::isGlobalRelativeToPICBase(OpFlags)) {
2766 Result =
2767 DAG.getNode(ISD::ADD, DL, PtrVT,
2768 DAG.getNode(M68kISD::GLOBAL_BASE_REG, DL, PtrVT), Result);
2769 }
2770
2771 // For globals that require a load from a stub to get the address, emit the
2772 // load.
2773 if (M68kII::isGlobalStubReference(OpFlags)) {
2774 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2775 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2776 }
2777
2778 // If there was a non-zero offset that we didn't fold, create an explicit
2779 // addition for it.
2780 if (Offset != 0) {
2781 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
2782 DAG.getConstant(Offset, DL, PtrVT));
2783 }
2784
2785 return Result;
2786 }
2787
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const2788 SDValue M68kTargetLowering::LowerGlobalAddress(SDValue Op,
2789 SelectionDAG &DAG) const {
2790 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2791 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
2792 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
2793 }
2794
2795 //===----------------------------------------------------------------------===//
2796 // Custom Lower Jump Table
2797 //===----------------------------------------------------------------------===//
2798
LowerJumpTable(SDValue Op,SelectionDAG & DAG) const2799 SDValue M68kTargetLowering::LowerJumpTable(SDValue Op,
2800 SelectionDAG &DAG) const {
2801 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2802
2803 // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2804 // global base reg.
2805 unsigned char OpFlag = Subtarget.classifyLocalReference(nullptr);
2806
2807 unsigned WrapperKind = M68kISD::Wrapper;
2808 if (M68kII::isPCRelGlobalReference(OpFlag)) {
2809 WrapperKind = M68kISD::WrapperPC;
2810 }
2811
2812 auto PtrVT = getPointerTy(DAG.getDataLayout());
2813 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
2814 SDLoc DL(JT);
2815 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2816
2817 // With PIC, the address is actually $g + Offset.
2818 if (M68kII::isGlobalRelativeToPICBase(OpFlag)) {
2819 Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2820 DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2821 Result);
2822 }
2823
2824 return Result;
2825 }
2826
getJumpTableEncoding() const2827 unsigned M68kTargetLowering::getJumpTableEncoding() const {
2828 return Subtarget.getJumpTableEncoding();
2829 }
2830
LowerCustomJumpTableEntry(const MachineJumpTableInfo * MJTI,const MachineBasicBlock * MBB,unsigned uid,MCContext & Ctx) const2831 const MCExpr *M68kTargetLowering::LowerCustomJumpTableEntry(
2832 const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB,
2833 unsigned uid, MCContext &Ctx) const {
2834 return MCSymbolRefExpr::create(MBB->getSymbol(), MCSymbolRefExpr::VK_GOTOFF,
2835 Ctx);
2836 }
2837
getPICJumpTableRelocBase(SDValue Table,SelectionDAG & DAG) const2838 SDValue M68kTargetLowering::getPICJumpTableRelocBase(SDValue Table,
2839 SelectionDAG &DAG) const {
2840 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_Custom32)
2841 return DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(),
2842 getPointerTy(DAG.getDataLayout()));
2843
2844 // MachineJumpTableInfo::EK_LabelDifference32 entry
2845 return Table;
2846 }
2847
2848 // NOTE This only used for MachineJumpTableInfo::EK_LabelDifference32 entries
getPICJumpTableRelocBaseExpr(const MachineFunction * MF,unsigned JTI,MCContext & Ctx) const2849 const MCExpr *M68kTargetLowering::getPICJumpTableRelocBaseExpr(
2850 const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const {
2851 return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
2852 }
2853
2854 M68kTargetLowering::ConstraintType
getConstraintType(StringRef Constraint) const2855 M68kTargetLowering::getConstraintType(StringRef Constraint) const {
2856 if (Constraint.size() > 0) {
2857 switch (Constraint[0]) {
2858 case 'a':
2859 case 'd':
2860 return C_RegisterClass;
2861 case 'I':
2862 case 'J':
2863 case 'K':
2864 case 'L':
2865 case 'M':
2866 case 'N':
2867 case 'O':
2868 case 'P':
2869 return C_Immediate;
2870 case 'C':
2871 if (Constraint.size() == 2)
2872 switch (Constraint[1]) {
2873 case '0':
2874 case 'i':
2875 case 'j':
2876 return C_Immediate;
2877 default:
2878 break;
2879 }
2880 break;
2881 case 'Q':
2882 case 'U':
2883 return C_Memory;
2884 default:
2885 break;
2886 }
2887 }
2888
2889 return TargetLowering::getConstraintType(Constraint);
2890 }
2891
LowerAsmOperandForConstraint(SDValue Op,StringRef Constraint,std::vector<SDValue> & Ops,SelectionDAG & DAG) const2892 void M68kTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2893 StringRef Constraint,
2894 std::vector<SDValue> &Ops,
2895 SelectionDAG &DAG) const {
2896 SDValue Result;
2897
2898 if (Constraint.size() == 1) {
2899 // Constant constraints
2900 switch (Constraint[0]) {
2901 case 'I':
2902 case 'J':
2903 case 'K':
2904 case 'L':
2905 case 'M':
2906 case 'N':
2907 case 'O':
2908 case 'P': {
2909 auto *C = dyn_cast<ConstantSDNode>(Op);
2910 if (!C)
2911 return;
2912
2913 int64_t Val = C->getSExtValue();
2914 switch (Constraint[0]) {
2915 case 'I': // constant integer in the range [1,8]
2916 if (Val > 0 && Val <= 8)
2917 break;
2918 return;
2919 case 'J': // constant signed 16-bit integer
2920 if (isInt<16>(Val))
2921 break;
2922 return;
2923 case 'K': // constant that is NOT in the range of [-0x80, 0x80)
2924 if (Val < -0x80 || Val >= 0x80)
2925 break;
2926 return;
2927 case 'L': // constant integer in the range [-8,-1]
2928 if (Val < 0 && Val >= -8)
2929 break;
2930 return;
2931 case 'M': // constant that is NOT in the range of [-0x100, 0x100]
2932 if (Val < -0x100 || Val >= 0x100)
2933 break;
2934 return;
2935 case 'N': // constant integer in the range [24,31]
2936 if (Val >= 24 && Val <= 31)
2937 break;
2938 return;
2939 case 'O': // constant integer 16
2940 if (Val == 16)
2941 break;
2942 return;
2943 case 'P': // constant integer in the range [8,15]
2944 if (Val >= 8 && Val <= 15)
2945 break;
2946 return;
2947 default:
2948 llvm_unreachable("Unhandled constant constraint");
2949 }
2950
2951 Result = DAG.getTargetConstant(Val, SDLoc(Op), Op.getValueType());
2952 break;
2953 }
2954 default:
2955 break;
2956 }
2957 }
2958
2959 if (Constraint.size() == 2) {
2960 switch (Constraint[0]) {
2961 case 'C':
2962 // Constant constraints start with 'C'
2963 switch (Constraint[1]) {
2964 case '0':
2965 case 'i':
2966 case 'j': {
2967 auto *C = dyn_cast<ConstantSDNode>(Op);
2968 if (!C)
2969 break;
2970
2971 int64_t Val = C->getSExtValue();
2972 switch (Constraint[1]) {
2973 case '0': // constant integer 0
2974 if (!Val)
2975 break;
2976 return;
2977 case 'i': // constant integer
2978 break;
2979 case 'j': // integer constant that doesn't fit in 16 bits
2980 if (!isInt<16>(C->getSExtValue()))
2981 break;
2982 return;
2983 default:
2984 llvm_unreachable("Unhandled constant constraint");
2985 }
2986
2987 Result = DAG.getTargetConstant(Val, SDLoc(Op), Op.getValueType());
2988 break;
2989 }
2990 default:
2991 break;
2992 }
2993 break;
2994 default:
2995 break;
2996 }
2997 }
2998
2999 if (Result.getNode()) {
3000 Ops.push_back(Result);
3001 return;
3002 }
3003
3004 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3005 }
3006
3007 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,StringRef Constraint,MVT VT) const3008 M68kTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3009 StringRef Constraint,
3010 MVT VT) const {
3011 if (Constraint.size() == 1) {
3012 switch (Constraint[0]) {
3013 case 'r':
3014 case 'd':
3015 switch (VT.SimpleTy) {
3016 case MVT::i8:
3017 return std::make_pair(0U, &M68k::DR8RegClass);
3018 case MVT::i16:
3019 return std::make_pair(0U, &M68k::DR16RegClass);
3020 case MVT::i32:
3021 return std::make_pair(0U, &M68k::DR32RegClass);
3022 default:
3023 break;
3024 }
3025 break;
3026 case 'a':
3027 switch (VT.SimpleTy) {
3028 case MVT::i16:
3029 return std::make_pair(0U, &M68k::AR16RegClass);
3030 case MVT::i32:
3031 return std::make_pair(0U, &M68k::AR32RegClass);
3032 default:
3033 break;
3034 }
3035 break;
3036 default:
3037 break;
3038 }
3039 }
3040
3041 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3042 }
3043
3044 /// Determines whether the callee is required to pop its own arguments.
3045 /// Callee pop is necessary to support tail calls.
isCalleePop(CallingConv::ID CC,bool IsVarArg,bool GuaranteeTCO)3046 bool M68k::isCalleePop(CallingConv::ID CC, bool IsVarArg, bool GuaranteeTCO) {
3047 return CC == CallingConv::M68k_RTD && !IsVarArg;
3048 }
3049
3050 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
3051 // together with other CMOV pseudo-opcodes into a single basic-block with
3052 // conditional jump around it.
isCMOVPseudo(MachineInstr & MI)3053 static bool isCMOVPseudo(MachineInstr &MI) {
3054 switch (MI.getOpcode()) {
3055 case M68k::CMOV8d:
3056 case M68k::CMOV16d:
3057 case M68k::CMOV32r:
3058 return true;
3059
3060 default:
3061 return false;
3062 }
3063 }
3064
3065 // The CCR operand of SelectItr might be missing a kill marker
3066 // because there were multiple uses of CCR, and ISel didn't know
3067 // which to mark. Figure out whether SelectItr should have had a
3068 // kill marker, and set it if it should. Returns the correct kill
3069 // marker value.
checkAndUpdateCCRKill(MachineBasicBlock::iterator SelectItr,MachineBasicBlock * BB,const TargetRegisterInfo * TRI)3070 static bool checkAndUpdateCCRKill(MachineBasicBlock::iterator SelectItr,
3071 MachineBasicBlock *BB,
3072 const TargetRegisterInfo *TRI) {
3073 // Scan forward through BB for a use/def of CCR.
3074 MachineBasicBlock::iterator miI(std::next(SelectItr));
3075 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
3076 const MachineInstr &mi = *miI;
3077 if (mi.readsRegister(M68k::CCR))
3078 return false;
3079 if (mi.definesRegister(M68k::CCR))
3080 break; // Should have kill-flag - update below.
3081 }
3082
3083 // If we hit the end of the block, check whether CCR is live into a
3084 // successor.
3085 if (miI == BB->end())
3086 for (const auto *SBB : BB->successors())
3087 if (SBB->isLiveIn(M68k::CCR))
3088 return false;
3089
3090 // We found a def, or hit the end of the basic block and CCR wasn't live
3091 // out. SelectMI should have a kill flag on CCR.
3092 SelectItr->addRegisterKilled(M68k::CCR, TRI);
3093 return true;
3094 }
3095
3096 MachineBasicBlock *
EmitLoweredSelect(MachineInstr & MI,MachineBasicBlock * MBB) const3097 M68kTargetLowering::EmitLoweredSelect(MachineInstr &MI,
3098 MachineBasicBlock *MBB) const {
3099 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3100 DebugLoc DL = MI.getDebugLoc();
3101
3102 // To "insert" a SELECT_CC instruction, we actually have to insert the
3103 // diamond control-flow pattern. The incoming instruction knows the
3104 // destination vreg to set, the condition code register to branch on, the
3105 // true/false values to select between, and a branch opcode to use.
3106 const BasicBlock *BB = MBB->getBasicBlock();
3107 MachineFunction::iterator It = ++MBB->getIterator();
3108
3109 // ThisMBB:
3110 // ...
3111 // TrueVal = ...
3112 // cmp ccX, r1, r2
3113 // bcc Copy1MBB
3114 // fallthrough --> Copy0MBB
3115 MachineBasicBlock *ThisMBB = MBB;
3116 MachineFunction *F = MBB->getParent();
3117
3118 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
3119 // as described above, by inserting a MBB, and then making a PHI at the join
3120 // point to select the true and false operands of the CMOV in the PHI.
3121 //
3122 // The code also handles two different cases of multiple CMOV opcodes
3123 // in a row.
3124 //
3125 // Case 1:
3126 // In this case, there are multiple CMOVs in a row, all which are based on
3127 // the same condition setting (or the exact opposite condition setting).
3128 // In this case we can lower all the CMOVs using a single inserted MBB, and
3129 // then make a number of PHIs at the join point to model the CMOVs. The only
3130 // trickiness here, is that in a case like:
3131 //
3132 // t2 = CMOV cond1 t1, f1
3133 // t3 = CMOV cond1 t2, f2
3134 //
3135 // when rewriting this into PHIs, we have to perform some renaming on the
3136 // temps since you cannot have a PHI operand refer to a PHI result earlier
3137 // in the same block. The "simple" but wrong lowering would be:
3138 //
3139 // t2 = PHI t1(BB1), f1(BB2)
3140 // t3 = PHI t2(BB1), f2(BB2)
3141 //
3142 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
3143 // renaming is to note that on the path through BB1, t2 is really just a
3144 // copy of t1, and do that renaming, properly generating:
3145 //
3146 // t2 = PHI t1(BB1), f1(BB2)
3147 // t3 = PHI t1(BB1), f2(BB2)
3148 //
3149 // Case 2, we lower cascaded CMOVs such as
3150 //
3151 // (CMOV (CMOV F, T, cc1), T, cc2)
3152 //
3153 // to two successives branches.
3154 MachineInstr *CascadedCMOV = nullptr;
3155 MachineInstr *LastCMOV = &MI;
3156 M68k::CondCode CC = M68k::CondCode(MI.getOperand(3).getImm());
3157 M68k::CondCode OppCC = M68k::GetOppositeBranchCondition(CC);
3158 MachineBasicBlock::iterator NextMIIt =
3159 std::next(MachineBasicBlock::iterator(MI));
3160
3161 // Check for case 1, where there are multiple CMOVs with the same condition
3162 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
3163 // number of jumps the most.
3164
3165 if (isCMOVPseudo(MI)) {
3166 // See if we have a string of CMOVS with the same condition.
3167 while (NextMIIt != MBB->end() && isCMOVPseudo(*NextMIIt) &&
3168 (NextMIIt->getOperand(3).getImm() == CC ||
3169 NextMIIt->getOperand(3).getImm() == OppCC)) {
3170 LastCMOV = &*NextMIIt;
3171 ++NextMIIt;
3172 }
3173 }
3174
3175 // This checks for case 2, but only do this if we didn't already find
3176 // case 1, as indicated by LastCMOV == MI.
3177 if (LastCMOV == &MI && NextMIIt != MBB->end() &&
3178 NextMIIt->getOpcode() == MI.getOpcode() &&
3179 NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() &&
3180 NextMIIt->getOperand(1).getReg() == MI.getOperand(0).getReg() &&
3181 NextMIIt->getOperand(1).isKill()) {
3182 CascadedCMOV = &*NextMIIt;
3183 }
3184
3185 MachineBasicBlock *Jcc1MBB = nullptr;
3186
3187 // If we have a cascaded CMOV, we lower it to two successive branches to
3188 // the same block. CCR is used by both, so mark it as live in the second.
3189 if (CascadedCMOV) {
3190 Jcc1MBB = F->CreateMachineBasicBlock(BB);
3191 F->insert(It, Jcc1MBB);
3192 Jcc1MBB->addLiveIn(M68k::CCR);
3193 }
3194
3195 MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(BB);
3196 MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(BB);
3197 F->insert(It, Copy0MBB);
3198 F->insert(It, SinkMBB);
3199
3200 // Set the call frame size on entry to the new basic blocks.
3201 unsigned CallFrameSize = TII->getCallFrameSizeAt(MI);
3202 Copy0MBB->setCallFrameSize(CallFrameSize);
3203 SinkMBB->setCallFrameSize(CallFrameSize);
3204
3205 // If the CCR register isn't dead in the terminator, then claim that it's
3206 // live into the sink and copy blocks.
3207 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3208
3209 MachineInstr *LastCCRSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
3210 if (!LastCCRSUser->killsRegister(M68k::CCR) &&
3211 !checkAndUpdateCCRKill(LastCCRSUser, MBB, TRI)) {
3212 Copy0MBB->addLiveIn(M68k::CCR);
3213 SinkMBB->addLiveIn(M68k::CCR);
3214 }
3215
3216 // Transfer the remainder of MBB and its successor edges to SinkMBB.
3217 SinkMBB->splice(SinkMBB->begin(), MBB,
3218 std::next(MachineBasicBlock::iterator(LastCMOV)), MBB->end());
3219 SinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
3220
3221 // Add the true and fallthrough blocks as its successors.
3222 if (CascadedCMOV) {
3223 // The fallthrough block may be Jcc1MBB, if we have a cascaded CMOV.
3224 MBB->addSuccessor(Jcc1MBB);
3225
3226 // In that case, Jcc1MBB will itself fallthrough the Copy0MBB, and
3227 // jump to the SinkMBB.
3228 Jcc1MBB->addSuccessor(Copy0MBB);
3229 Jcc1MBB->addSuccessor(SinkMBB);
3230 } else {
3231 MBB->addSuccessor(Copy0MBB);
3232 }
3233
3234 // The true block target of the first (or only) branch is always SinkMBB.
3235 MBB->addSuccessor(SinkMBB);
3236
3237 // Create the conditional branch instruction.
3238 unsigned Opc = M68k::GetCondBranchFromCond(CC);
3239 BuildMI(MBB, DL, TII->get(Opc)).addMBB(SinkMBB);
3240
3241 if (CascadedCMOV) {
3242 unsigned Opc2 = M68k::GetCondBranchFromCond(
3243 (M68k::CondCode)CascadedCMOV->getOperand(3).getImm());
3244 BuildMI(Jcc1MBB, DL, TII->get(Opc2)).addMBB(SinkMBB);
3245 }
3246
3247 // Copy0MBB:
3248 // %FalseValue = ...
3249 // # fallthrough to SinkMBB
3250 Copy0MBB->addSuccessor(SinkMBB);
3251
3252 // SinkMBB:
3253 // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ]
3254 // ...
3255 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
3256 MachineBasicBlock::iterator MIItEnd =
3257 std::next(MachineBasicBlock::iterator(LastCMOV));
3258 MachineBasicBlock::iterator SinkInsertionPoint = SinkMBB->begin();
3259 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
3260 MachineInstrBuilder MIB;
3261
3262 // As we are creating the PHIs, we have to be careful if there is more than
3263 // one. Later CMOVs may reference the results of earlier CMOVs, but later
3264 // PHIs have to reference the individual true/false inputs from earlier PHIs.
3265 // That also means that PHI construction must work forward from earlier to
3266 // later, and that the code must maintain a mapping from earlier PHI's
3267 // destination registers, and the registers that went into the PHI.
3268
3269 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
3270 Register DestReg = MIIt->getOperand(0).getReg();
3271 Register Op1Reg = MIIt->getOperand(1).getReg();
3272 Register Op2Reg = MIIt->getOperand(2).getReg();
3273
3274 // If this CMOV we are generating is the opposite condition from
3275 // the jump we generated, then we have to swap the operands for the
3276 // PHI that is going to be generated.
3277 if (MIIt->getOperand(3).getImm() == OppCC)
3278 std::swap(Op1Reg, Op2Reg);
3279
3280 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
3281 Op1Reg = RegRewriteTable[Op1Reg].first;
3282
3283 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
3284 Op2Reg = RegRewriteTable[Op2Reg].second;
3285
3286 MIB =
3287 BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(M68k::PHI), DestReg)
3288 .addReg(Op1Reg)
3289 .addMBB(Copy0MBB)
3290 .addReg(Op2Reg)
3291 .addMBB(ThisMBB);
3292
3293 // Add this PHI to the rewrite table.
3294 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
3295 }
3296
3297 // If we have a cascaded CMOV, the second Jcc provides the same incoming
3298 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
3299 if (CascadedCMOV) {
3300 MIB.addReg(MI.getOperand(2).getReg()).addMBB(Jcc1MBB);
3301 // Copy the PHI result to the register defined by the second CMOV.
3302 BuildMI(*SinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
3303 DL, TII->get(TargetOpcode::COPY),
3304 CascadedCMOV->getOperand(0).getReg())
3305 .addReg(MI.getOperand(0).getReg());
3306 CascadedCMOV->eraseFromParent();
3307 }
3308
3309 // Now remove the CMOV(s).
3310 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd;)
3311 (MIIt++)->eraseFromParent();
3312
3313 return SinkMBB;
3314 }
3315
3316 MachineBasicBlock *
EmitLoweredSegAlloca(MachineInstr & MI,MachineBasicBlock * BB) const3317 M68kTargetLowering::EmitLoweredSegAlloca(MachineInstr &MI,
3318 MachineBasicBlock *BB) const {
3319 llvm_unreachable("Cannot lower Segmented Stack Alloca with stack-split on");
3320 }
3321
3322 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr & MI,MachineBasicBlock * BB) const3323 M68kTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3324 MachineBasicBlock *BB) const {
3325 switch (MI.getOpcode()) {
3326 default:
3327 llvm_unreachable("Unexpected instr type to insert");
3328 case M68k::CMOV8d:
3329 case M68k::CMOV16d:
3330 case M68k::CMOV32r:
3331 return EmitLoweredSelect(MI, BB);
3332 case M68k::SALLOCA:
3333 return EmitLoweredSegAlloca(MI, BB);
3334 }
3335 }
3336
LowerVASTART(SDValue Op,SelectionDAG & DAG) const3337 SDValue M68kTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3338 MachineFunction &MF = DAG.getMachineFunction();
3339 auto PtrVT = getPointerTy(MF.getDataLayout());
3340 M68kMachineFunctionInfo *FuncInfo = MF.getInfo<M68kMachineFunctionInfo>();
3341
3342 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3343 SDLoc DL(Op);
3344
3345 // vastart just stores the address of the VarArgsFrameIndex slot into the
3346 // memory location argument.
3347 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3348 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3349 MachinePointerInfo(SV));
3350 }
3351
LowerATOMICFENCE(SDValue Op,SelectionDAG & DAG) const3352 SDValue M68kTargetLowering::LowerATOMICFENCE(SDValue Op,
3353 SelectionDAG &DAG) const {
3354 // Lower to a memory barrier created from inline asm.
3355 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3356 LLVMContext &Ctx = *DAG.getContext();
3357
3358 const unsigned Flags = InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore |
3359 InlineAsm::Extra_HasSideEffects;
3360 const SDValue AsmOperands[4] = {
3361 Op.getOperand(0), // Input chain
3362 DAG.getTargetExternalSymbol(
3363 "", TLI.getProgramPointerTy(
3364 DAG.getDataLayout())), // Empty inline asm string
3365 DAG.getMDNode(MDNode::get(Ctx, {})), // (empty) srcloc
3366 DAG.getTargetConstant(Flags, SDLoc(Op),
3367 TLI.getPointerTy(DAG.getDataLayout())), // Flags
3368 };
3369
3370 return DAG.getNode(ISD::INLINEASM, SDLoc(Op),
3371 DAG.getVTList(MVT::Other, MVT::Glue), AsmOperands);
3372 }
3373
3374 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
3375 // Calls to _alloca are needed to probe the stack when allocating more than 4k
3376 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
3377 // that the guard pages used by the OS virtual memory manager are allocated in
3378 // correct sequence.
LowerDYNAMIC_STACKALLOC(SDValue Op,SelectionDAG & DAG) const3379 SDValue M68kTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3380 SelectionDAG &DAG) const {
3381 MachineFunction &MF = DAG.getMachineFunction();
3382 bool SplitStack = MF.shouldSplitStack();
3383
3384 SDLoc DL(Op);
3385
3386 // Get the inputs.
3387 SDNode *Node = Op.getNode();
3388 SDValue Chain = Op.getOperand(0);
3389 SDValue Size = Op.getOperand(1);
3390 unsigned Align = Op.getConstantOperandVal(2);
3391 EVT VT = Node->getValueType(0);
3392
3393 // Chain the dynamic stack allocation so that it doesn't modify the stack
3394 // pointer when other instructions are using the stack.
3395 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
3396
3397 SDValue Result;
3398 if (SplitStack) {
3399 auto &MRI = MF.getRegInfo();
3400 auto SPTy = getPointerTy(DAG.getDataLayout());
3401 auto *ARClass = getRegClassFor(SPTy);
3402 Register Vreg = MRI.createVirtualRegister(ARClass);
3403 Chain = DAG.getCopyToReg(Chain, DL, Vreg, Size);
3404 Result = DAG.getNode(M68kISD::SEG_ALLOCA, DL, SPTy, Chain,
3405 DAG.getRegister(Vreg, SPTy));
3406 } else {
3407 auto &TLI = DAG.getTargetLoweringInfo();
3408 Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
3409 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
3410 " not tell us which reg is the stack pointer!");
3411
3412 SDValue SP = DAG.getCopyFromReg(Chain, DL, SPReg, VT);
3413 Chain = SP.getValue(1);
3414 const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
3415 unsigned StackAlign = TFI.getStackAlignment();
3416 Result = DAG.getNode(ISD::SUB, DL, VT, SP, Size); // Value
3417 if (Align > StackAlign)
3418 Result = DAG.getNode(ISD::AND, DL, VT, Result,
3419 DAG.getConstant(-(uint64_t)Align, DL, VT));
3420 Chain = DAG.getCopyToReg(Chain, DL, SPReg, Result); // Output chain
3421 }
3422
3423 Chain = DAG.getCALLSEQ_END(Chain, 0, 0, SDValue(), DL);
3424
3425 SDValue Ops[2] = {Result, Chain};
3426 return DAG.getMergeValues(Ops, DL);
3427 }
3428
LowerShiftLeftParts(SDValue Op,SelectionDAG & DAG) const3429 SDValue M68kTargetLowering::LowerShiftLeftParts(SDValue Op,
3430 SelectionDAG &DAG) const {
3431 SDLoc DL(Op);
3432 SDValue Lo = Op.getOperand(0);
3433 SDValue Hi = Op.getOperand(1);
3434 SDValue Shamt = Op.getOperand(2);
3435 EVT VT = Lo.getValueType();
3436
3437 // if Shamt - register size < 0: // Shamt < register size
3438 // Lo = Lo << Shamt
3439 // Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (register size - 1 ^ Shamt))
3440 // else:
3441 // Lo = 0
3442 // Hi = Lo << (Shamt - register size)
3443
3444 SDValue Zero = DAG.getConstant(0, DL, VT);
3445 SDValue One = DAG.getConstant(1, DL, VT);
3446 SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);
3447 SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);
3448 SDValue ShamtMinusRegisterSize =
3449 DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);
3450 SDValue RegisterSizeMinus1Shamt =
3451 DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);
3452
3453 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
3454 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One);
3455 SDValue ShiftRightLo =
3456 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, RegisterSizeMinus1Shamt);
3457 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
3458 SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
3459 SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusRegisterSize);
3460
3461 SDValue CC =
3462 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);
3463
3464 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
3465 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
3466
3467 return DAG.getMergeValues({Lo, Hi}, DL);
3468 }
3469
LowerShiftRightParts(SDValue Op,SelectionDAG & DAG,bool IsSRA) const3470 SDValue M68kTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
3471 bool IsSRA) const {
3472 SDLoc DL(Op);
3473 SDValue Lo = Op.getOperand(0);
3474 SDValue Hi = Op.getOperand(1);
3475 SDValue Shamt = Op.getOperand(2);
3476 EVT VT = Lo.getValueType();
3477
3478 // SRA expansion:
3479 // if Shamt - register size < 0: // Shamt < register size
3480 // Lo = (Lo >>u Shamt) | ((Hi << 1) << (register size - 1 ^ Shamt))
3481 // Hi = Hi >>s Shamt
3482 // else:
3483 // Lo = Hi >>s (Shamt - register size);
3484 // Hi = Hi >>s (register size - 1)
3485 //
3486 // SRL expansion:
3487 // if Shamt - register size < 0: // Shamt < register size
3488 // Lo = (Lo >>u Shamt) | ((Hi << 1) << (register size - 1 ^ Shamt))
3489 // Hi = Hi >>u Shamt
3490 // else:
3491 // Lo = Hi >>u (Shamt - register size);
3492 // Hi = 0;
3493
3494 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;
3495
3496 SDValue Zero = DAG.getConstant(0, DL, VT);
3497 SDValue One = DAG.getConstant(1, DL, VT);
3498 SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);
3499 SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);
3500 SDValue ShamtMinusRegisterSize =
3501 DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);
3502 SDValue RegisterSizeMinus1Shamt =
3503 DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);
3504
3505 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
3506 SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
3507 SDValue ShiftLeftHi =
3508 DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, RegisterSizeMinus1Shamt);
3509 SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);
3510 SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);
3511 SDValue LoFalse =
3512 DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusRegisterSize);
3513 SDValue HiFalse =
3514 IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, RegisterSizeMinus1) : Zero;
3515
3516 SDValue CC =
3517 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);
3518
3519 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
3520 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
3521
3522 return DAG.getMergeValues({Lo, Hi}, DL);
3523 }
3524
3525 //===----------------------------------------------------------------------===//
3526 // DAG Combine
3527 //===----------------------------------------------------------------------===//
3528
getSETCC(M68k::CondCode Cond,SDValue CCR,const SDLoc & dl,SelectionDAG & DAG)3529 static SDValue getSETCC(M68k::CondCode Cond, SDValue CCR, const SDLoc &dl,
3530 SelectionDAG &DAG) {
3531 return DAG.getNode(M68kISD::SETCC, dl, MVT::i8,
3532 DAG.getConstant(Cond, dl, MVT::i8), CCR);
3533 }
3534 // When legalizing carry, we create carries via add X, -1
3535 // If that comes from an actual carry, via setcc, we use the
3536 // carry directly.
combineCarryThroughADD(SDValue CCR)3537 static SDValue combineCarryThroughADD(SDValue CCR) {
3538 if (CCR.getOpcode() == M68kISD::ADD) {
3539 if (isAllOnesConstant(CCR.getOperand(1))) {
3540 SDValue Carry = CCR.getOperand(0);
3541 while (Carry.getOpcode() == ISD::TRUNCATE ||
3542 Carry.getOpcode() == ISD::ZERO_EXTEND ||
3543 Carry.getOpcode() == ISD::SIGN_EXTEND ||
3544 Carry.getOpcode() == ISD::ANY_EXTEND ||
3545 (Carry.getOpcode() == ISD::AND &&
3546 isOneConstant(Carry.getOperand(1))))
3547 Carry = Carry.getOperand(0);
3548 if (Carry.getOpcode() == M68kISD::SETCC ||
3549 Carry.getOpcode() == M68kISD::SETCC_CARRY) {
3550 if (Carry.getConstantOperandVal(0) == M68k::COND_CS)
3551 return Carry.getOperand(1);
3552 }
3553 }
3554 }
3555
3556 return SDValue();
3557 }
3558
3559 /// Optimize a CCR definition used according to the condition code \p CC into
3560 /// a simpler CCR value, potentially returning a new \p CC and replacing uses
3561 /// of chain values.
combineSetCCCCR(SDValue CCR,M68k::CondCode & CC,SelectionDAG & DAG,const M68kSubtarget & Subtarget)3562 static SDValue combineSetCCCCR(SDValue CCR, M68k::CondCode &CC,
3563 SelectionDAG &DAG,
3564 const M68kSubtarget &Subtarget) {
3565 if (CC == M68k::COND_CS)
3566 if (SDValue Flags = combineCarryThroughADD(CCR))
3567 return Flags;
3568
3569 return SDValue();
3570 }
3571
3572 // Optimize RES = M68kISD::SETCC CONDCODE, CCR_INPUT
combineM68kSetCC(SDNode * N,SelectionDAG & DAG,const M68kSubtarget & Subtarget)3573 static SDValue combineM68kSetCC(SDNode *N, SelectionDAG &DAG,
3574 const M68kSubtarget &Subtarget) {
3575 SDLoc DL(N);
3576 M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(0));
3577 SDValue CCR = N->getOperand(1);
3578
3579 // Try to simplify the CCR and condition code operands.
3580 if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget))
3581 return getSETCC(CC, Flags, DL, DAG);
3582
3583 return SDValue();
3584 }
combineM68kBrCond(SDNode * N,SelectionDAG & DAG,const M68kSubtarget & Subtarget)3585 static SDValue combineM68kBrCond(SDNode *N, SelectionDAG &DAG,
3586 const M68kSubtarget &Subtarget) {
3587 SDLoc DL(N);
3588 M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(2));
3589 SDValue CCR = N->getOperand(3);
3590
3591 // Try to simplify the CCR and condition code operands.
3592 // Make sure to not keep references to operands, as combineSetCCCCR can
3593 // RAUW them under us.
3594 if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget)) {
3595 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
3596 return DAG.getNode(M68kISD::BRCOND, DL, N->getVTList(), N->getOperand(0),
3597 N->getOperand(1), Cond, Flags);
3598 }
3599
3600 return SDValue();
3601 }
3602
combineSUBX(SDNode * N,SelectionDAG & DAG)3603 static SDValue combineSUBX(SDNode *N, SelectionDAG &DAG) {
3604 if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
3605 MVT VT = N->getSimpleValueType(0);
3606 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
3607 return DAG.getNode(M68kISD::SUBX, SDLoc(N), VTs, N->getOperand(0),
3608 N->getOperand(1), Flags);
3609 }
3610
3611 return SDValue();
3612 }
3613
3614 // Optimize RES, CCR = M68kISD::ADDX LHS, RHS, CCR
combineADDX(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI)3615 static SDValue combineADDX(SDNode *N, SelectionDAG &DAG,
3616 TargetLowering::DAGCombinerInfo &DCI) {
3617 if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
3618 MVT VT = N->getSimpleValueType(0);
3619 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
3620 return DAG.getNode(M68kISD::ADDX, SDLoc(N), VTs, N->getOperand(0),
3621 N->getOperand(1), Flags);
3622 }
3623
3624 return SDValue();
3625 }
3626
PerformDAGCombine(SDNode * N,DAGCombinerInfo & DCI) const3627 SDValue M68kTargetLowering::PerformDAGCombine(SDNode *N,
3628 DAGCombinerInfo &DCI) const {
3629 SelectionDAG &DAG = DCI.DAG;
3630 switch (N->getOpcode()) {
3631 case M68kISD::SUBX:
3632 return combineSUBX(N, DAG);
3633 case M68kISD::ADDX:
3634 return combineADDX(N, DAG, DCI);
3635 case M68kISD::SETCC:
3636 return combineM68kSetCC(N, DAG, Subtarget);
3637 case M68kISD::BRCOND:
3638 return combineM68kBrCond(N, DAG, Subtarget);
3639 }
3640
3641 return SDValue();
3642 }
3643
3644 //===----------------------------------------------------------------------===//
3645 // M68kISD Node Names
3646 //===----------------------------------------------------------------------===//
getTargetNodeName(unsigned Opcode) const3647 const char *M68kTargetLowering::getTargetNodeName(unsigned Opcode) const {
3648 switch (Opcode) {
3649 case M68kISD::CALL:
3650 return "M68kISD::CALL";
3651 case M68kISD::TAIL_CALL:
3652 return "M68kISD::TAIL_CALL";
3653 case M68kISD::RET:
3654 return "M68kISD::RET";
3655 case M68kISD::TC_RETURN:
3656 return "M68kISD::TC_RETURN";
3657 case M68kISD::ADD:
3658 return "M68kISD::ADD";
3659 case M68kISD::SUB:
3660 return "M68kISD::SUB";
3661 case M68kISD::ADDX:
3662 return "M68kISD::ADDX";
3663 case M68kISD::SUBX:
3664 return "M68kISD::SUBX";
3665 case M68kISD::SMUL:
3666 return "M68kISD::SMUL";
3667 case M68kISD::UMUL:
3668 return "M68kISD::UMUL";
3669 case M68kISD::OR:
3670 return "M68kISD::OR";
3671 case M68kISD::XOR:
3672 return "M68kISD::XOR";
3673 case M68kISD::AND:
3674 return "M68kISD::AND";
3675 case M68kISD::CMP:
3676 return "M68kISD::CMP";
3677 case M68kISD::BTST:
3678 return "M68kISD::BTST";
3679 case M68kISD::SELECT:
3680 return "M68kISD::SELECT";
3681 case M68kISD::CMOV:
3682 return "M68kISD::CMOV";
3683 case M68kISD::BRCOND:
3684 return "M68kISD::BRCOND";
3685 case M68kISD::SETCC:
3686 return "M68kISD::SETCC";
3687 case M68kISD::SETCC_CARRY:
3688 return "M68kISD::SETCC_CARRY";
3689 case M68kISD::GLOBAL_BASE_REG:
3690 return "M68kISD::GLOBAL_BASE_REG";
3691 case M68kISD::Wrapper:
3692 return "M68kISD::Wrapper";
3693 case M68kISD::WrapperPC:
3694 return "M68kISD::WrapperPC";
3695 case M68kISD::SEG_ALLOCA:
3696 return "M68kISD::SEG_ALLOCA";
3697 default:
3698 return NULL;
3699 }
3700 }
3701
getCCAssignFn(CallingConv::ID CC,bool Return,bool IsVarArg) const3702 CCAssignFn *M68kTargetLowering::getCCAssignFn(CallingConv::ID CC, bool Return,
3703 bool IsVarArg) const {
3704 if (Return)
3705 return RetCC_M68k_C;
3706 else
3707 return CC_M68k_C;
3708 }
3709