1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2024 Racktop Systems, Inc. 14 */ 15 #ifndef _LMRC_REG_H 16 #define _LMRC_REG_H 17 18 #include <sys/bitext.h> 19 #include <sys/debug.h> 20 #include <sys/stddef.h> 21 22 #include <sys/scsi/adapters/mfi/mfi.h> 23 24 typedef struct lmrc_raid_mfa_io_req_desc lmrc_raid_mfa_io_req_desc_t; 25 typedef union lmrc_atomic_req_desc lmrc_atomic_req_desc_t; 26 typedef union lmrc_req_desc lmrc_req_desc_t; 27 28 #include "lmrc_raid.h" 29 30 /* PCI device IDs of Gen 3.5 Controllers */ 31 #define LMRC_VENTURA 0x0014 32 #define LMRC_CRUSADER 0x0015 33 #define LMRC_HARPOON 0x0016 34 #define LMRC_TOMCAT 0x0017 35 #define LMRC_VENTURA_4PORT 0x001B 36 #define LMRC_CRUSADER_4PORT 0x001C 37 #define LMRC_AERO_10E0 0x10E0 38 #define LMRC_AERO_10E1 0x10E1 39 #define LMRC_AERO_10E2 0x10E2 40 #define LMRC_AERO_10E3 0x10E3 41 #define LMRC_AERO_10E4 0x10E4 42 #define LMRC_AERO_10E5 0x10E5 43 #define LMRC_AERO_10E6 0x10E6 44 #define LMRC_AERO_10E7 0x10E7 45 46 /* 47 * Message Frame Defines 48 */ 49 #define LMRC_SENSE_LEN 96 50 51 #define LMRC_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 52 53 #define LMRC_SPECIFIC_MPI2_FUNCTION(x) \ 54 (MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC + (x)) 55 #define LMRC_MPI2_FUNCTION_PASSTHRU_IO_REQUEST LMRC_SPECIFIC_MPI2_FUNCTION(0) 56 #define LMRC_MPI2_FUNCTION_LD_IO_REQUEST LMRC_SPECIFIC_MPI2_FUNCTION(1) 57 58 59 #define LMRC_MAX_MFI_CMDS 16 60 #define LMRC_MAX_IOCTL_CMDS 3 61 62 /* 63 * Firmware Status Register 64 * For Ventura and Aero controllers, this is outbound scratch pad register 0. 65 */ 66 #define LMRC_FW_RESET_REQUIRED(reg) (bitx32((reg), 0, 0) != 0) 67 #define LMRC_FW_RESET_ADAPTER(reg) (bitx32((reg), 1, 1) != 0) 68 #define LMRC_FW_MAX_CMD(reg) bitx32((reg), 15, 0) 69 #define LMRC_FW_MSIX_ENABLED(reg) (bitx32((reg), 26, 26) != 0) 70 #define LMRC_FW_STATE(reg) bitx32((reg), 31, 28) 71 72 /* outbound scratch pad register 1 */ 73 #define LMRC_MAX_CHAIN_SIZE(reg) bitx32((reg), 9, 5) 74 #define LMRC_MAX_REPLY_QUEUES_EXT(reg) bitx32((reg), 21, 14) 75 #define LMRC_EXT_CHAIN_SIZE_SUPPORT(reg) (bitx32((reg), 22, 22) != 0) 76 #define LMRC_RDPQ_MODE_SUPPORT(reg) (bitx32((reg), 23, 23) != 0) 77 #define LMRC_SYNC_CACHE_SUPPORT(reg) (bitx32((reg), 24, 24) != 0) 78 #define LMRC_ATOMIC_DESCRIPTOR_SUPPORT(reg) (bitx32((reg), 24, 24) != 0) 79 #define LMRC_64BIT_DMA_SUPPORT(reg) (bitx32((reg), 25, 25) != 0) 80 #define LMRC_INTR_COALESCING_SUPPORT(reg) (bitx32((reg), 26, 26) != 0) 81 82 #define LMRC_256K_IO 128 83 #define LMRC_1MB_IO (LMRC_256K_IO * 4) 84 85 /* outbound scratch pad register 2 */ 86 #define LMRC_MAX_RAID_MAP_SZ(reg) bitx32((reg), 24, 16) 87 88 /* outbound scratch pad register 3 */ 89 #define LMRC_NVME_PAGE_SHIFT(reg) bitx32((reg), 7, 0) 90 #define LMRC_DEFAULT_NVME_PAGE_SHIFT 12 91 92 /* 93 * FW posts its state in the upper 4 bits of the status register, extracted 94 * with LMRC_FW_STATE(reg). 95 */ 96 #define LMRC_FW_STATE_UNDEFINED 0x0 97 #define LMRC_FW_STATE_BB_INIT 0x1 98 #define LMRC_FW_STATE_FW_INIT 0x4 99 #define LMRC_FW_STATE_WAIT_HANDSHAKE 0x6 100 #define LMRC_FW_STATE_FW_INIT_2 0x7 101 #define LMRC_FW_STATE_DEVICE_SCAN 0x8 102 #define LMRC_FW_STATE_BOOT_MSG_PENDING 0x9 103 #define LMRC_FW_STATE_FLUSH_CACHE 0xa 104 #define LMRC_FW_STATE_READY 0xb 105 #define LMRC_FW_STATE_OPERATIONAL 0xc 106 #define LMRC_FW_STATE_FAULT 0xf 107 108 #define LMRC_MAX_PD_CHANNELS 1 109 #define LMRC_MAX_LD_CHANNELS 1 110 #define LMRC_MAX_DEV_PER_CHANNEL 256 111 #define LMRC_MAX_PD \ 112 (LMRC_MAX_PD_CHANNELS * LMRC_MAX_DEV_PER_CHANNEL) 113 #define LMRC_MAX_LD \ 114 (LMRC_MAX_LD_CHANNELS * LMRC_MAX_DEV_PER_CHANNEL) 115 #define LMRC_MAX_TM_TARGETS (LMRC_MAX_PD + LMRC_MAX_LD) 116 117 #define LMRC_DEFAULT_INIT_ID -1 118 #define LMRC_MAX_LUN 8 119 #define LMRC_DEFAULT_CMD_PER_LUN 256 120 121 #define LMRC_MAX_REPLY_POST_HOST_INDEX 16 122 123 124 /* By default, the firmware programs for 8k of memory */ 125 #define LMRC_MFI_MIN_MEM 4096 126 #define LMRC_MFI_DEF_MEM 8192 127 #define LMRC_MFI_MAX_CMD 16 128 129 130 #pragma pack(1) 131 132 /* 133 * MPT RAID MFA IO Descriptor. 134 * 135 * Note: The use of the lowest 8 bits for flags implies that an alignment 136 * of 256 bytes is required for the physical address. 137 */ 138 struct lmrc_raid_mfa_io_req_desc { 139 uint32_t RequestFlags:8; 140 uint32_t MessageAddress1:24; /* bits 31:8 */ 141 uint32_t MessageAddress2; /* bits 61:32 */ 142 }; 143 144 /* 145 * unions of Request Descriptors 146 */ 147 union lmrc_atomic_req_desc { 148 Mpi26AtomicRequestDescriptor_t rd_atomic; 149 uint32_t rd_reg; 150 }; 151 152 union lmrc_req_desc { 153 uint64_t rd_reg; 154 155 struct { 156 uint32_t rd_reg_lo; 157 uint32_t rd_reg_hi; 158 }; 159 160 lmrc_atomic_req_desc_t rd_atomic; 161 lmrc_raid_mfa_io_req_desc_t rd_mfa_io; 162 }; 163 164 #pragma pack(0) 165 166 /* 167 * Request descriptor types, in addition to those defined by mpi2.h 168 * 169 * FreeBSD and Linux drivers shift these, while mpi2.h defines them 170 * pre-shifted. The latter seems more sensible. 171 * 172 * XXX: LMRC_REQ_DESCRIPT_FLAGS_MFA has the same value as 173 * MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET. Why? 174 */ 175 #define LMRC_REQ_DESCRIPT_FLAGS_MFA 0x02 176 #define LMRC_REQ_DESCRIPT_FLAGS_NO_LOCK 0x04 177 #define LMRC_REQ_DESCRIPT_FLAGS_LD_IO 0x0e 178 179 #define MPI2_TYPE_CUDA 0x2 180 181 #endif /* _LMRC_REG_H */ 182