1 /****************************************************************************** 2 3 Project: Portable command line ISP for NXP LPC1000 / LPC2000 family 4 and Analog Devices ADUC70xx 5 6 Filename: lpcprog.h 7 8 Compiler: Microsoft VC 6/7, Microsoft VS2008, Microsoft VS2010, 9 GCC Cygwin, GCC Linux, GCC ARM ELF 10 11 Author: Martin Maurer (Martin.Maurer@clibb.de) 12 13 Copyright: (c) Martin Maurer 2003-2014, All rights reserved 14 Portions Copyright (c) by Aeolus Development 2004 http://www.aeolusdevelopment.com 15 16 This file is part of lpc21isp. 17 18 lpc21isp is free software: you can redistribute it and/or modify 19 it under the terms of the GNU Lesser General Public License as published by 20 the Free Software Foundation, either version 3 of the License, or 21 any later version. 22 23 lpc21isp is distributed in the hope that it will be useful, 24 but WITHOUT ANY WARRANTY; without even the implied warranty of 25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 GNU Lesser General Public License for more details. 27 28 You should have received a copy of the GNU Lesser General Public License 29 and GNU General Public License along with lpc21isp. 30 If not, see <http://www.gnu.org/licenses/>. 31 */ 32 33 /* LPC_RAMSTART, LPC_RAMBASE 34 * 35 * Used in NxpDownload() to decide whether to Flash code or just place in in RAM 36 * (works for .hex files only) 37 * 38 * LPC_RAMSTART - the Physical start address of the SRAM 39 * LPC_RAMBASE - the base address where downloading starts. 40 * Note that any code in the .hex file that resides in 0x4000,0000 ~ 0x4000,0200 41 * will _not_ be written to the LPCs SRAM. 42 * This is due to the fact that 0x4000,0040 - 0x4000,0200 is used by the bootrom. 43 * Any interrupt vectors must be copied to 0x4000,0000 and remapped to 0x0000,0000 44 * by the startup code. 45 */ 46 #define LPC_RAMSTART_LPC43XX 0x10000000L 47 #define LPC_RAMBASE_LPC43XX 0x10000200L 48 49 #define LPC_RAMSTART_LPC2XXX 0x40000000L 50 #define LPC_RAMBASE_LPC2XXX 0x40000200L 51 52 #define LPC_RAMSTART_LPC18XX 0x10000000L 53 #define LPC_RAMBASE_LPC18XX 0x10000200L 54 55 #define LPC_RAMSTART_LPC17XX 0x10000000L 56 #define LPC_RAMBASE_LPC17XX 0x10000200L 57 58 #define LPC_RAMSTART_LPC13XX 0x10000000L 59 #define LPC_RAMBASE_LPC13XX 0x10000300L 60 61 #define LPC_RAMSTART_LPC11XX 0x10000000L 62 #define LPC_RAMBASE_LPC11XX 0x10000300L 63 64 #define LPC_RAMSTART_LPC8XX 0x10000000L 65 #define LPC_RAMBASE_LPC8XX 0x10000270L 66 67 /* Return values used by NxpDownload(): reserving all values from 0x1000 to 0x1FFF */ 68 69 #define NO_ANSWER_WDT 0x1000 70 #define NO_ANSWER_QM 0x1001 71 #define NO_ANSWER_SYNC 0x1002 72 #define NO_ANSWER_OSC 0x1003 73 #define NO_ANSWER_RBV 0x1004 74 #define NO_ANSWER_RPID 0x1005 75 #define ERROR_WRITE_DATA 0x1006 76 #define ERROR_WRITE_CRC 0x1007 77 #define ERROR_WRITE_CRC2 0x1008 78 #define PROGRAM_TOO_LARGE 0x1009 79 80 #define USER_ABORT_SYNC 0x100A /* User aborted synchronisation process */ 81 82 #define UNKNOWN_LPC 0x100B /* Unknown LPC detected */ 83 84 #define UNLOCK_ERROR 0x1100 /* return value is 0x1100 + NXP ISP returned value (0 to 255) */ 85 #define WRONG_ANSWER_PREP 0x1200 /* return value is 0x1200 + NXP ISP returned value (0 to 255) */ 86 #define WRONG_ANSWER_ERAS 0x1300 /* return value is 0x1300 + NXP ISP returned value (0 to 255) */ 87 #define WRONG_ANSWER_WRIT 0x1400 /* return value is 0x1400 + NXP ISP returned value (0 to 255) */ 88 #define WRONG_ANSWER_PREP2 0x1500 /* return value is 0x1500 + NXP ISP returned value (0 to 255) */ 89 #define WRONG_ANSWER_COPY 0x1600 /* return value is 0x1600 + NXP ISP returned value (0 to 255) */ 90 #define FAILED_RUN 0x1700 /* return value is 0x1700 + NXP ISP returned value (0 to 255) */ 91 #define WRONG_ANSWER_BTBNK 0x1800 /* return value is 0x1800 + NXP ISP returned value (0 to 255) */ 92 93 #if defined COMPILE_FOR_LPC21 94 #ifndef WIN32 95 #define LPC_BSL_PIN 13 96 #define LPC_RESET_PIN 47 97 #define LPC_RESET(in) NAsetGPIOpin(LPC_RESET_PIN, (in)) 98 #define LPC_BSL(in) NAsetGPIOpin(LPC_BSL_PIN, (in)) 99 #endif // WIN32 100 #endif // COMPILE_FOR_LPC21 101 102 103 /* LPC_FLASHMASK 104 * 105 * LPC_FLASHMASK - bitmask to define the maximum size of the Filesize to download. 106 * LoadFile() will check any new segment address record (03) or extended linear 107 * address record (04) to see if the addressed 64 kByte data block still falls 108 * in the max. flash size. 109 * LoadFile() will not load any files that are larger than this size. 110 */ 111 #define LPC_FLASHMASK 0xFFC00000 /* 22 bits = 4 MB */ 112 113 typedef enum 114 { 115 CHIP_VARIANT_NONE, 116 CHIP_VARIANT_LPC43XX, 117 CHIP_VARIANT_LPC2XXX, 118 CHIP_VARIANT_LPC18XX, 119 CHIP_VARIANT_LPC17XX, 120 CHIP_VARIANT_LPC13XX, 121 CHIP_VARIANT_LPC11XX, 122 CHIP_VARIANT_LPC8XX 123 } CHIP_VARIANT; 124 125 typedef struct 126 { 127 const unsigned long id; 128 const unsigned long id2; 129 const unsigned int EvalId2; 130 const char *Product; 131 const unsigned int FlashSize; /* in kiB, for informational purposes only */ 132 const unsigned int RAMSize; /* in kiB, for informational purposes only */ 133 unsigned int FlashSectors; /* total number of sectors */ 134 unsigned int MaxCopySize; /* maximum size that can be copied to Flash in a single command */ 135 const unsigned int *SectorTable; /* pointer to a sector table with constant the sector sizes */ 136 const CHIP_VARIANT ChipVariant; 137 } LPC_DEVICE_TYPE; 138 139 int NxpDownload(ISP_ENVIRONMENT *IspEnvironment); 140 141 unsigned long ReturnValueLpcRamStart(ISP_ENVIRONMENT *IspEnvironment); 142 143 unsigned long ReturnValueLpcRamBase(ISP_ENVIRONMENT *IspEnvironment); 144 145