1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2017-2023 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
7 * EMULEX and SLI are trademarks of Emulex. *
8 * www.broadcom.com *
9 * *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
22
23 #define FDMI_DID 0xfffffaU
24 #define NameServer_DID 0xfffffcU
25 #define Fabric_Cntl_DID 0xfffffdU
26 #define Fabric_DID 0xfffffeU
27 #define Bcast_DID 0xffffffU
28 #define Mask_DID 0xffffffU
29 #define CT_DID_MASK 0xffff00U
30 #define Fabric_DID_MASK 0xfff000U
31 #define WELL_KNOWN_DID_MASK 0xfffff0U
32
33 #define PT2PT_LocalID 1
34 #define PT2PT_RemoteID 2
35
36 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
37 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
38 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */
39 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
40
41 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
42 0 */
43
44 #define FCELSSIZE 1024 /* maximum ELS transfer size */
45
46 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
47 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
48 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
49
50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
58 #define SLI2_IOCB_CMD_R3_ENTRIES 0
59 #define SLI2_IOCB_RSP_R3_ENTRIES 0
60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62
63 #define SLI2_IOCB_CMD_SIZE 32
64 #define SLI2_IOCB_RSP_SIZE 32
65 #define SLI3_IOCB_CMD_SIZE 128
66 #define SLI3_IOCB_RSP_SIZE 64
67
68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
70
71 /* vendor ID used in SCSI netlink calls */
72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73
74 #define FW_REV_STR_SIZE 32
75 /* Common Transport structures and definitions */
76
77 union CtRevisionId {
78 /* Structure is in Big Endian format */
79 struct {
80 uint32_t Revision:8;
81 uint32_t InId:24;
82 } bits;
83 uint32_t word;
84 };
85
86 union CtCommandResponse {
87 /* Structure is in Big Endian format */
88 struct {
89 __be16 CmdRsp;
90 __be16 Size;
91 } bits;
92 uint32_t word;
93 };
94
95 /* FC4 Feature bits for RFF_ID */
96 #define FC4_FEATURE_TARGET 0x1
97 #define FC4_FEATURE_INIT 0x2
98 #define FC4_FEATURE_NVME_DISC 0x4
99
100 enum rft_word0 {
101 RFT_FCP_REG = (0x1 << 8),
102 };
103
104 enum rft_word1 {
105 RFT_NVME_REG = (0x1 << 8),
106 };
107
108 enum rft_word3 {
109 RFT_APP_SERV_REG = (0x1 << 0),
110 };
111
112 struct lpfc_sli_ct_request {
113 /* Structure is in Big Endian format */
114 union CtRevisionId RevisionId;
115 uint8_t FsType;
116 uint8_t FsSubType;
117 uint8_t Options;
118 uint8_t Rsrvd1;
119 union CtCommandResponse CommandResponse;
120 uint8_t Rsrvd2;
121 uint8_t ReasonCode;
122 uint8_t Explanation;
123 uint8_t VendorUnique;
124 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */
125
126 union {
127 __be32 PortID;
128 struct gid {
129 uint8_t PortType; /* for GID_PT requests */
130 #define GID_PT_N_PORT 1
131 uint8_t DomainScope;
132 uint8_t AreaScope;
133 uint8_t Fc4Type; /* for GID_FT requests */
134 } gid;
135 struct gid_ff {
136 uint8_t Flags;
137 uint8_t DomainScope;
138 uint8_t AreaScope;
139 uint8_t rsvd1;
140 uint8_t rsvd2;
141 uint8_t rsvd3;
142 uint8_t Fc4FBits;
143 uint8_t Fc4Type;
144 } gid_ff;
145 struct rft {
146 __be32 port_id; /* For RFT_ID requests */
147
148 __be32 fcp_reg; /* rsvd 31:9, fcp_reg 8, rsvd 7:0 */
149 __be32 nvme_reg; /* rsvd 31:9, nvme_reg 8, rsvd 7:0 */
150 __be32 word2;
151 __be32 app_serv_reg; /* rsvd 31:1, app_serv_reg 0 */
152 __be32 word[4];
153 } rft;
154 struct rnn {
155 uint32_t PortId; /* For RNN_ID requests */
156 uint8_t wwnn[8];
157 } rnn;
158 struct rsnn { /* For RSNN_ID requests */
159 uint8_t wwnn[8];
160 uint8_t len;
161 uint8_t symbname[255];
162 } rsnn;
163 struct da_id { /* For DA_ID requests */
164 uint32_t port_id;
165 } da_id;
166 struct rspn { /* For RSPN_ID requests */
167 uint32_t PortId;
168 uint8_t len;
169 uint8_t symbname[255];
170 } rspn;
171 struct gff {
172 uint32_t PortId;
173 } gff;
174 struct gff_acc {
175 uint8_t fbits[128];
176 } gff_acc;
177 struct gft {
178 uint32_t PortId;
179 } gft;
180 struct gft_acc {
181 uint32_t fc4_types[8];
182 } gft_acc;
183 #define FCP_TYPE_FEATURE_OFFSET 7
184 struct rff {
185 uint32_t PortId;
186 uint8_t reserved[2];
187 uint8_t fbits;
188 uint8_t type_code; /* type=8 for FCP */
189 } rff;
190 } un;
191 };
192
193 #define LPFC_MAX_CT_SIZE (60 * 4096)
194
195 #define SLI_CT_REVISION 1
196 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
197 sizeof(struct gid))
198 #define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
199 sizeof(struct gid_ff))
200 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
201 sizeof(struct gff))
202 #define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
203 sizeof(struct gft))
204 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
205 sizeof(struct rft))
206 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
207 sizeof(struct rff))
208 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
209 sizeof(struct rnn))
210 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
211 sizeof(struct rsnn))
212 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
213 sizeof(struct da_id))
214 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
215 sizeof(struct rspn))
216
217 /*
218 * FsType Definitions
219 */
220
221 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
222 #define SLI_CT_TIME_SERVICE 0xFB
223 #define SLI_CT_DIRECTORY_SERVICE 0xFC
224 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
225
226 /*
227 * Directory Service Subtypes
228 */
229
230 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
231
232 /*
233 * Response Codes
234 */
235
236 #define SLI_CT_RESPONSE_FS_RJT 0x8001
237 #define SLI_CT_RESPONSE_FS_ACC 0x8002
238
239 /*
240 * Reason Codes
241 */
242
243 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
244 #define SLI_CT_INVALID_COMMAND 0x01
245 #define SLI_CT_INVALID_VERSION 0x02
246 #define SLI_CT_LOGICAL_ERROR 0x03
247 #define SLI_CT_INVALID_IU_SIZE 0x04
248 #define SLI_CT_LOGICAL_BUSY 0x05
249 #define SLI_CT_PROTOCOL_ERROR 0x07
250 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
251 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
252 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
253 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
254 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
255 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
256 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
257 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
258 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
259 #define SLI_CT_VENDOR_UNIQUE 0xff
260
261 /*
262 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
263 */
264
265 #define SLI_CT_NO_PORT_ID 0x01
266 #define SLI_CT_NO_PORT_NAME 0x02
267 #define SLI_CT_NO_NODE_NAME 0x03
268 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
269 #define SLI_CT_NO_IP_ADDRESS 0x05
270 #define SLI_CT_NO_IPA 0x06
271 #define SLI_CT_NO_FC4_TYPES 0x07
272 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
273 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
274 #define SLI_CT_NO_PORT_TYPE 0x0A
275 #define SLI_CT_ACCESS_DENIED 0x10
276 #define SLI_CT_INVALID_PORT_ID 0x11
277 #define SLI_CT_DATABASE_EMPTY 0x12
278 #define SLI_CT_APP_ID_NOT_AVAILABLE 0x40
279
280 /*
281 * Name Server Command Codes
282 */
283
284 #define SLI_CTNS_GA_NXT 0x0100
285 #define SLI_CTNS_GPN_ID 0x0112
286 #define SLI_CTNS_GNN_ID 0x0113
287 #define SLI_CTNS_GCS_ID 0x0114
288 #define SLI_CTNS_GFT_ID 0x0117
289 #define SLI_CTNS_GSPN_ID 0x0118
290 #define SLI_CTNS_GPT_ID 0x011A
291 #define SLI_CTNS_GFF_ID 0x011F
292 #define SLI_CTNS_GID_PN 0x0121
293 #define SLI_CTNS_GID_NN 0x0131
294 #define SLI_CTNS_GIP_NN 0x0135
295 #define SLI_CTNS_GIPA_NN 0x0136
296 #define SLI_CTNS_GSNN_NN 0x0139
297 #define SLI_CTNS_GNN_IP 0x0153
298 #define SLI_CTNS_GIPA_IP 0x0156
299 #define SLI_CTNS_GID_FT 0x0171
300 #define SLI_CTNS_GID_FF 0x01F1
301 #define SLI_CTNS_GID_PT 0x01A1
302 #define SLI_CTNS_RPN_ID 0x0212
303 #define SLI_CTNS_RNN_ID 0x0213
304 #define SLI_CTNS_RCS_ID 0x0214
305 #define SLI_CTNS_RFT_ID 0x0217
306 #define SLI_CTNS_RSPN_ID 0x0218
307 #define SLI_CTNS_RPT_ID 0x021A
308 #define SLI_CTNS_RFF_ID 0x021F
309 #define SLI_CTNS_RIP_NN 0x0235
310 #define SLI_CTNS_RIPA_NN 0x0236
311 #define SLI_CTNS_RSNN_NN 0x0239
312 #define SLI_CTNS_DA_ID 0x0300
313
314 /*
315 * Port Types
316 */
317
318 #define SLI_CTPT_N_PORT 0x01
319 #define SLI_CTPT_NL_PORT 0x02
320 #define SLI_CTPT_FNL_PORT 0x03
321 #define SLI_CTPT_IP 0x04
322 #define SLI_CTPT_FCP 0x08
323 #define SLI_CTPT_NVME 0x28
324 #define SLI_CTPT_NX_PORT 0x7F
325 #define SLI_CTPT_F_PORT 0x81
326 #define SLI_CTPT_FL_PORT 0x82
327 #define SLI_CTPT_E_PORT 0x84
328
329 #define SLI_CT_LAST_ENTRY 0x80000000
330
331 /* Fibre Channel Service Parameter definitions */
332
333 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
334 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
335 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
336 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
337
338 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
339 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
340 #define FC_PH3 0x20 /* FC-PH-3 version */
341
342 #define FF_FRAME_SIZE 2048
343
344 struct lpfc_name {
345 union {
346 struct {
347 #ifdef __BIG_ENDIAN_BITFIELD
348 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
349 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
350 8:11 of IEEE ext */
351 #else /* __LITTLE_ENDIAN_BITFIELD */
352 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
353 8:11 of IEEE ext */
354 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
355 #endif
356
357 #define NAME_IEEE 0x1 /* IEEE name - nameType */
358 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
359 #define NAME_FC_TYPE 0x3 /* FC native name type */
360 #define NAME_IP_TYPE 0x4 /* IP address */
361 #define NAME_CCITT_TYPE 0xC
362 #define NAME_CCITT_GR_TYPE 0xE
363 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
364 extended Lsb */
365 uint8_t IEEE[6]; /* FC IEEE address */
366 } s;
367 uint8_t wwn[8];
368 uint64_t name __packed __aligned(4);
369 } u;
370 };
371
372 struct csp {
373 uint8_t fcphHigh; /* FC Word 0, byte 0 */
374 uint8_t fcphLow;
375 uint8_t bbCreditMsb;
376 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */
377
378 /*
379 * Word 1 Bit 31 in common service parameter is overloaded.
380 * Word 1 Bit 31 in FLOGI request is multiple NPort request
381 * Word 1 Bit 31 in FLOGI response is clean address bit
382 */
383 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
384 /*
385 * Word 1 Bit 30 in common service parameter is overloaded.
386 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
387 * Word 1 Bit 30 in PLOGI request is random offset
388 */
389 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
390 /*
391 * Word 1 Bit 29 in common service parameter is overloaded.
392 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
393 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
394 */
395 #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
396 #ifdef __BIG_ENDIAN_BITFIELD
397 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
398 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
399 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
400 uint16_t fPort:1; /* FC Word 1, bit 28 */
401 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
402 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
403 uint16_t multicast:1; /* FC Word 1, bit 25 */
404 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */
405
406 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */
407 uint16_t simplex:1; /* FC Word 1, bit 22 */
408 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
409 uint16_t dhd:1; /* FC Word 1, bit 18 */
410 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
411 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
412 #else /* __LITTLE_ENDIAN_BITFIELD */
413 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */
414 uint16_t multicast:1; /* FC Word 1, bit 25 */
415 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
416 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
417 uint16_t fPort:1; /* FC Word 1, bit 28 */
418 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
419 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
420 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
421
422 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
423 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
424 uint16_t dhd:1; /* FC Word 1, bit 18 */
425 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
426 uint16_t simplex:1; /* FC Word 1, bit 22 */
427 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */
428 #endif
429
430 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
431 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
432 union {
433 struct {
434 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
435
436 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
437 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
438
439 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
440 } nPort;
441 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
442 } w2;
443
444 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
445 };
446
447 struct class_parms {
448 #ifdef __BIG_ENDIAN_BITFIELD
449 uint8_t classValid:1; /* FC Word 0, bit 31 */
450 uint8_t intermix:1; /* FC Word 0, bit 30 */
451 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
452 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
453 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
454 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
455 #else /* __LITTLE_ENDIAN_BITFIELD */
456 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
457 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
458 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
459 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
460 uint8_t intermix:1; /* FC Word 0, bit 30 */
461 uint8_t classValid:1; /* FC Word 0, bit 31 */
462
463 #endif
464
465 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
466
467 #ifdef __BIG_ENDIAN_BITFIELD
468 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
469 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
470 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
471 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
472 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
473 #else /* __LITTLE_ENDIAN_BITFIELD */
474 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
475 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
476 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
477 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
478 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
479 #endif
480
481 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
482
483 #ifdef __BIG_ENDIAN_BITFIELD
484 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
485 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
486 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
487 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
488 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
489 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
490 #else /* __LITTLE_ENDIAN_BITFIELD */
491 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
492 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
493 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
494 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
495 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
496 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
497 #endif
498
499 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
500 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
501 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
502
503 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
504 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
505 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
506 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
507
508 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
509 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
510 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
511 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
512 };
513
514 struct serv_parm { /* Structure is in Big Endian format */
515 struct csp cmn;
516 struct lpfc_name portName;
517 struct lpfc_name nodeName;
518 struct class_parms cls1;
519 struct class_parms cls2;
520 struct class_parms cls3;
521 struct class_parms cls4;
522 union {
523 uint8_t vendorVersion[16];
524 struct {
525 uint32_t vid;
526 #define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */
527 uint32_t flags;
528 #define LPFC_VV_SUPPRESS_RSP 1
529 } vv;
530 } un;
531 };
532
533 /*
534 * Virtual Fabric Tagging Header
535 */
536 struct fc_vft_header {
537 uint32_t word0;
538 #define fc_vft_hdr_r_ctl_SHIFT 24
539 #define fc_vft_hdr_r_ctl_MASK 0xFF
540 #define fc_vft_hdr_r_ctl_WORD word0
541 #define fc_vft_hdr_ver_SHIFT 22
542 #define fc_vft_hdr_ver_MASK 0x3
543 #define fc_vft_hdr_ver_WORD word0
544 #define fc_vft_hdr_type_SHIFT 18
545 #define fc_vft_hdr_type_MASK 0xF
546 #define fc_vft_hdr_type_WORD word0
547 #define fc_vft_hdr_e_SHIFT 16
548 #define fc_vft_hdr_e_MASK 0x1
549 #define fc_vft_hdr_e_WORD word0
550 #define fc_vft_hdr_priority_SHIFT 13
551 #define fc_vft_hdr_priority_MASK 0x7
552 #define fc_vft_hdr_priority_WORD word0
553 #define fc_vft_hdr_vf_id_SHIFT 1
554 #define fc_vft_hdr_vf_id_MASK 0xFFF
555 #define fc_vft_hdr_vf_id_WORD word0
556 uint32_t word1;
557 #define fc_vft_hdr_hopct_SHIFT 24
558 #define fc_vft_hdr_hopct_MASK 0xFF
559 #define fc_vft_hdr_hopct_WORD word1
560 };
561
562 #include <uapi/scsi/fc/fc_els.h>
563
564 /*
565 * Application Header
566 */
567 struct fc_app_header {
568 uint32_t dst_app_id;
569 uint32_t src_app_id;
570 #define LOOPBACK_SRC_APPID 0x4321
571 uint32_t word2;
572 uint32_t word3;
573 };
574
575 /*
576 * dfctl optional header definition
577 */
578 enum lpfc_fc_dfctl {
579 LPFC_FC_NO_DEVICE_HEADER,
580 LPFC_FC_16B_DEVICE_HEADER,
581 LPFC_FC_32B_DEVICE_HEADER,
582 LPFC_FC_64B_DEVICE_HEADER,
583 };
584
585 /*
586 * Extended Link Service LS_COMMAND codes (Payload Word 0)
587 */
588 #ifdef __BIG_ENDIAN_BITFIELD
589 #define ELS_CMD_MASK 0xffff0000
590 #define ELS_RSP_MASK 0xff000000
591 #define ELS_CMD_LS_RJT 0x01000000
592 #define ELS_CMD_ACC 0x02000000
593 #define ELS_CMD_PLOGI 0x03000000
594 #define ELS_CMD_FLOGI 0x04000000
595 #define ELS_CMD_LOGO 0x05000000
596 #define ELS_CMD_ABTX 0x06000000
597 #define ELS_CMD_RCS 0x07000000
598 #define ELS_CMD_RES 0x08000000
599 #define ELS_CMD_RSS 0x09000000
600 #define ELS_CMD_RSI 0x0A000000
601 #define ELS_CMD_ESTS 0x0B000000
602 #define ELS_CMD_ESTC 0x0C000000
603 #define ELS_CMD_ADVC 0x0D000000
604 #define ELS_CMD_RTV 0x0E000000
605 #define ELS_CMD_RLS 0x0F000000
606 #define ELS_CMD_ECHO 0x10000000
607 #define ELS_CMD_TEST 0x11000000
608 #define ELS_CMD_RRQ 0x12000000
609 #define ELS_CMD_REC 0x13000000
610 #define ELS_CMD_RDP 0x18000000
611 #define ELS_CMD_RDF 0x19000000
612 #define ELS_CMD_PRLI 0x20100014
613 #define ELS_CMD_NVMEPRLI 0x20140018
614 #define ELS_CMD_PRLO 0x21100014
615 #define ELS_CMD_PRLO_ACC 0x02100014
616 #define ELS_CMD_PDISC 0x50000000
617 #define ELS_CMD_FDISC 0x51000000
618 #define ELS_CMD_ADISC 0x52000000
619 #define ELS_CMD_FARP 0x54000000
620 #define ELS_CMD_FARPR 0x55000000
621 #define ELS_CMD_RPL 0x57000000
622 #define ELS_CMD_FAN 0x60000000
623 #define ELS_CMD_RSCN 0x61040000
624 #define ELS_CMD_RSCN_XMT 0x61040008
625 #define ELS_CMD_SCR 0x62000000
626 #define ELS_CMD_RNID 0x78000000
627 #define ELS_CMD_LIRR 0x7A000000
628 #define ELS_CMD_LCB 0x81000000
629 #define ELS_CMD_FPIN 0x16000000
630 #define ELS_CMD_EDC 0x17000000
631 #define ELS_CMD_QFPA 0xB0000000
632 #define ELS_CMD_UVEM 0xB1000000
633 #else /* __LITTLE_ENDIAN_BITFIELD */
634 #define ELS_CMD_MASK 0xffff
635 #define ELS_RSP_MASK 0xff
636 #define ELS_CMD_LS_RJT 0x01
637 #define ELS_CMD_ACC 0x02
638 #define ELS_CMD_PLOGI 0x03
639 #define ELS_CMD_FLOGI 0x04
640 #define ELS_CMD_LOGO 0x05
641 #define ELS_CMD_ABTX 0x06
642 #define ELS_CMD_RCS 0x07
643 #define ELS_CMD_RES 0x08
644 #define ELS_CMD_RSS 0x09
645 #define ELS_CMD_RSI 0x0A
646 #define ELS_CMD_ESTS 0x0B
647 #define ELS_CMD_ESTC 0x0C
648 #define ELS_CMD_ADVC 0x0D
649 #define ELS_CMD_RTV 0x0E
650 #define ELS_CMD_RLS 0x0F
651 #define ELS_CMD_ECHO 0x10
652 #define ELS_CMD_TEST 0x11
653 #define ELS_CMD_RRQ 0x12
654 #define ELS_CMD_REC 0x13
655 #define ELS_CMD_RDP 0x18
656 #define ELS_CMD_RDF 0x19
657 #define ELS_CMD_PRLI 0x14001020
658 #define ELS_CMD_NVMEPRLI 0x18001420
659 #define ELS_CMD_PRLO 0x14001021
660 #define ELS_CMD_PRLO_ACC 0x14001002
661 #define ELS_CMD_PDISC 0x50
662 #define ELS_CMD_FDISC 0x51
663 #define ELS_CMD_ADISC 0x52
664 #define ELS_CMD_FARP 0x54
665 #define ELS_CMD_FARPR 0x55
666 #define ELS_CMD_RPL 0x57
667 #define ELS_CMD_FAN 0x60
668 #define ELS_CMD_RSCN 0x0461
669 #define ELS_CMD_RSCN_XMT 0x08000461
670 #define ELS_CMD_SCR 0x62
671 #define ELS_CMD_RNID 0x78
672 #define ELS_CMD_LIRR 0x7A
673 #define ELS_CMD_LCB 0x81
674 #define ELS_CMD_FPIN ELS_FPIN
675 #define ELS_CMD_EDC ELS_EDC
676 #define ELS_CMD_QFPA 0xB0
677 #define ELS_CMD_UVEM 0xB1
678 #endif
679
680 /*
681 * LS_RJT Payload Definition
682 */
683
684 struct ls_rjt { /* Structure is in Big Endian format */
685 union {
686 __be32 ls_rjt_error_be;
687 uint32_t lsRjtError;
688 struct {
689 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
690
691 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
692 /* LS_RJT reason codes */
693 #define LSRJT_INVALID_CMD 0x01
694 #define LSRJT_LOGICAL_ERR 0x03
695 #define LSRJT_LOGICAL_BSY 0x05
696 #define LSRJT_PROTOCOL_ERR 0x07
697 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
698 #define LSRJT_CMD_UNSUPPORTED 0x0B
699 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
700
701 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
702 /* LS_RJT reason explanation */
703 #define LSEXP_NOTHING_MORE 0x00
704 #define LSEXP_SPARM_OPTIONS 0x01
705 #define LSEXP_SPARM_ICTL 0x03
706 #define LSEXP_SPARM_RCTL 0x05
707 #define LSEXP_SPARM_RCV_SIZE 0x07
708 #define LSEXP_SPARM_CONCUR_SEQ 0x09
709 #define LSEXP_SPARM_CREDIT 0x0B
710 #define LSEXP_INVALID_PNAME 0x0D
711 #define LSEXP_INVALID_NNAME 0x0E
712 #define LSEXP_INVALID_CSP 0x0F
713 #define LSEXP_INVALID_ASSOC_HDR 0x11
714 #define LSEXP_ASSOC_HDR_REQ 0x13
715 #define LSEXP_INVALID_O_SID 0x15
716 #define LSEXP_INVALID_OX_RX 0x17
717 #define LSEXP_CMD_IN_PROGRESS 0x19
718 #define LSEXP_PORT_LOGIN_REQ 0x1E
719 #define LSEXP_INVALID_NPORT_ID 0x1F
720 #define LSEXP_INVALID_SEQ_ID 0x21
721 #define LSEXP_INVALID_XCHG 0x23
722 #define LSEXP_INACTIVE_XCHG 0x25
723 #define LSEXP_RQ_REQUIRED 0x27
724 #define LSEXP_OUT_OF_RESOURCE 0x29
725 #define LSEXP_CANT_GIVE_DATA 0x2A
726 #define LSEXP_REQ_UNSUPPORTED 0x2C
727 #define LSEXP_NO_RSRC_ASSIGN 0x52
728 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
729 } b;
730 } un;
731 };
732
733 /*
734 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
735 */
736
737 typedef struct _LOGO { /* Structure is in Big Endian format */
738 union {
739 uint32_t nPortId32; /* Access nPortId as a word */
740 struct {
741 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
742 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
743 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
744 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
745 } b;
746 } un;
747 struct lpfc_name portName; /* N_port name field */
748 } LOGO;
749
750 /*
751 * FCP Login (PRLI Request / ACC) Payload Definition
752 */
753
754 #define PRLX_PAGE_LEN 0x10
755 #define TPRLO_PAGE_LEN 0x14
756
757 typedef struct _PRLI { /* Structure is in Big Endian format */
758 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
759
760 #define PRLI_FCP_TYPE 0x08
761 #define PRLI_NVME_TYPE 0x28
762 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
763
764 #ifdef __BIG_ENDIAN_BITFIELD
765 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
766 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
767 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
768
769 /* ACC = imagePairEstablished */
770 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
771 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
772 #else /* __LITTLE_ENDIAN_BITFIELD */
773 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
774 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
775 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
776 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
777 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
778 /* ACC = imagePairEstablished */
779 #endif
780
781 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
782 #define PRLI_NO_RESOURCES 0x2
783 #define PRLI_INIT_INCOMPLETE 0x3
784 #define PRLI_NO_SUCH_PA 0x4
785 #define PRLI_PREDEF_CONFIG 0x5
786 #define PRLI_PARTIAL_SUCCESS 0x6
787 #define PRLI_INVALID_PAGE_CNT 0x7
788 #define PRLI_INV_SRV_PARM 0x8
789
790 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
791
792 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
793
794 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
795
796 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
797 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
798
799 #ifdef __BIG_ENDIAN_BITFIELD
800 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
801 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
802 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
803 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
804 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
805 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
806 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
807 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
808 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
809 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
810 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
811 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
812 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
813 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
814 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
815 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
816 #else /* __LITTLE_ENDIAN_BITFIELD */
817 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
818 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
819 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
820 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
821 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
822 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
823 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
824 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
825 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
826 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
827 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
828 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
829 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
830 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
831 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
832 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
833 #endif
834 } PRLI;
835
836 /*
837 * FCP Logout (PRLO Request / ACC) Payload Definition
838 */
839
840 typedef struct _PRLO { /* Structure is in Big Endian format */
841 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
842
843 #define PRLO_FCP_TYPE 0x08
844 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
845
846 #ifdef __BIG_ENDIAN_BITFIELD
847 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
848 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
849 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
850 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
851 #else /* __LITTLE_ENDIAN_BITFIELD */
852 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
853 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
854 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
855 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
856 #endif
857
858 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
859 #define PRLO_NO_SUCH_IMAGE 0x4
860 #define PRLO_INVALID_PAGE_CNT 0x7
861
862 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
863
864 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
865
866 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
867
868 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
869 } PRLO;
870
871 typedef struct _ADISC { /* Structure is in Big Endian format */
872 uint32_t hardAL_PA;
873 struct lpfc_name portName;
874 struct lpfc_name nodeName;
875 uint32_t DID;
876 } ADISC;
877
878 typedef struct _FARP { /* Structure is in Big Endian format */
879 uint32_t Mflags:8;
880 uint32_t Odid:24;
881 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
882 action */
883 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
884 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
885 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
886 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
887 supported */
888 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
889 supported */
890 uint32_t Rflags:8;
891 uint32_t Rdid:24;
892 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
893 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
894 struct lpfc_name OportName;
895 struct lpfc_name OnodeName;
896 struct lpfc_name RportName;
897 struct lpfc_name RnodeName;
898 uint8_t Oipaddr[16];
899 uint8_t Ripaddr[16];
900 } FARP;
901
902 typedef struct _FAN { /* Structure is in Big Endian format */
903 uint32_t Fdid;
904 struct lpfc_name FportName;
905 struct lpfc_name FnodeName;
906 } FAN;
907
908 typedef struct _SCR { /* Structure is in Big Endian format */
909 uint8_t resvd1;
910 uint8_t resvd2;
911 uint8_t resvd3;
912 uint8_t Function;
913 #define SCR_FUNC_FABRIC 0x01
914 #define SCR_FUNC_NPORT 0x02
915 #define SCR_FUNC_FULL 0x03
916 #define SCR_CLEAR 0xff
917 } SCR;
918
919 typedef struct _RNID_TOP_DISC {
920 struct lpfc_name portName;
921 uint8_t resvd[8];
922 uint32_t unitType;
923 #define RNID_HBA 0x7
924 #define RNID_HOST 0xa
925 #define RNID_DRIVER 0xd
926 uint32_t physPort;
927 uint32_t attachedNodes;
928 uint16_t ipVersion;
929 #define RNID_IPV4 0x1
930 #define RNID_IPV6 0x2
931 uint16_t UDPport;
932 uint8_t ipAddr[16];
933 uint16_t resvd1;
934 uint16_t flags;
935 #define RNID_TD_SUPPORT 0x1
936 #define RNID_LP_VALID 0x2
937 } RNID_TOP_DISC;
938
939 typedef struct _RNID { /* Structure is in Big Endian format */
940 uint8_t Format;
941 #define RNID_TOPOLOGY_DISC 0xdf
942 uint8_t CommonLen;
943 uint8_t resvd1;
944 uint8_t SpecificLen;
945 struct lpfc_name portName;
946 struct lpfc_name nodeName;
947 union {
948 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
949 } un;
950 } RNID;
951
952 struct RLS { /* Structure is in Big Endian format */
953 uint32_t rls;
954 #define rls_rsvd_SHIFT 24
955 #define rls_rsvd_MASK 0x000000ff
956 #define rls_rsvd_WORD rls
957 #define rls_did_SHIFT 0
958 #define rls_did_MASK 0x00ffffff
959 #define rls_did_WORD rls
960 };
961
962 struct RLS_RSP { /* Structure is in Big Endian format */
963 uint32_t linkFailureCnt;
964 uint32_t lossSyncCnt;
965 uint32_t lossSignalCnt;
966 uint32_t primSeqErrCnt;
967 uint32_t invalidXmitWord;
968 uint32_t crcCnt;
969 };
970
971 struct RRQ { /* Structure is in Big Endian format */
972 uint32_t rrq;
973 #define rrq_rsvd_SHIFT 24
974 #define rrq_rsvd_MASK 0x000000ff
975 #define rrq_rsvd_WORD rrq
976 #define rrq_did_SHIFT 0
977 #define rrq_did_MASK 0x00ffffff
978 #define rrq_did_WORD rrq
979 uint32_t rrq_exchg;
980 #define rrq_oxid_SHIFT 16
981 #define rrq_oxid_MASK 0xffff
982 #define rrq_oxid_WORD rrq_exchg
983 #define rrq_rxid_SHIFT 0
984 #define rrq_rxid_MASK 0xffff
985 #define rrq_rxid_WORD rrq_exchg
986 };
987
988 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
989 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
990
991 struct RTV_RSP { /* Structure is in Big Endian format */
992 uint32_t ratov;
993 uint32_t edtov;
994 uint32_t qtov;
995 #define qtov_rsvd0_SHIFT 28
996 #define qtov_rsvd0_MASK 0x0000000f
997 #define qtov_rsvd0_WORD qtov /* reserved */
998 #define qtov_edtovres_SHIFT 27
999 #define qtov_edtovres_MASK 0x00000001
1000 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
1001 #define qtov__rsvd1_SHIFT 19
1002 #define qtov_rsvd1_MASK 0x0000003f
1003 #define qtov_rsvd1_WORD qtov /* reserved */
1004 #define qtov_rttov_SHIFT 18
1005 #define qtov_rttov_MASK 0x00000001
1006 #define qtov_rttov_WORD qtov /* R_T_TOV value */
1007 #define qtov_rsvd2_SHIFT 0
1008 #define qtov_rsvd2_MASK 0x0003ffff
1009 #define qtov_rsvd2_WORD qtov /* reserved */
1010 };
1011
1012
1013 typedef struct _RPL { /* Structure is in Big Endian format */
1014 uint32_t maxsize;
1015 uint32_t index;
1016 } RPL;
1017
1018 typedef struct _PORT_NUM_BLK {
1019 uint32_t portNum;
1020 uint32_t portID;
1021 struct lpfc_name portName;
1022 } PORT_NUM_BLK;
1023
1024 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
1025 uint32_t listLen;
1026 uint32_t index;
1027 PORT_NUM_BLK port_num_blk;
1028 } RPL_RSP;
1029
1030 /* This is used for RSCN command */
1031 typedef struct _D_ID { /* Structure is in Big Endian format */
1032 union {
1033 uint32_t word;
1034 struct {
1035 #ifdef __BIG_ENDIAN_BITFIELD
1036 uint8_t resv;
1037 uint8_t domain;
1038 uint8_t area;
1039 uint8_t id;
1040 #else /* __LITTLE_ENDIAN_BITFIELD */
1041 uint8_t id;
1042 uint8_t area;
1043 uint8_t domain;
1044 uint8_t resv;
1045 #endif
1046 } b;
1047 } un;
1048 } D_ID;
1049
1050 #define RSCN_ADDRESS_FORMAT_PORT 0x0
1051 #define RSCN_ADDRESS_FORMAT_AREA 0x1
1052 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
1053 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
1054 #define RSCN_ADDRESS_FORMAT_MASK 0x3
1055
1056 /*
1057 * Structure to define all ELS Payload types
1058 */
1059
1060 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
1061 uint8_t elsCode; /* FC Word 0, bit 24:31 */
1062 uint8_t elsByte1;
1063 uint8_t elsByte2;
1064 uint8_t elsByte3;
1065 union {
1066 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
1067 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
1068 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
1069 PRLI prli; /* Payload for PRLI/ACC */
1070 PRLO prlo; /* Payload for PRLO/ACC */
1071 ADISC adisc; /* Payload for ADISC/ACC */
1072 FARP farp; /* Payload for FARP/ACC */
1073 FAN fan; /* Payload for FAN */
1074 SCR scr; /* Payload for SCR/ACC */
1075 RNID rnid; /* Payload for RNID */
1076 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
1077 } un;
1078 } ELS_PKT;
1079
1080 /*
1081 * Link Cable Beacon (LCB) ELS Frame
1082 */
1083
1084 struct fc_lcb_request_frame {
1085 uint32_t lcb_command; /* ELS command opcode (0x81) */
1086 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1087 #define LPFC_LCB_ON 0x1
1088 #define LPFC_LCB_OFF 0x2
1089 uint8_t reserved[2];
1090 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
1091 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1092 #define LPFC_LCB_GREEN 0x1
1093 #define LPFC_LCB_AMBER 0x2
1094 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1095 #define LCB_CAPABILITY_DURATION 1
1096 #define BEACON_VERSION_V1 1
1097 #define BEACON_VERSION_V0 0
1098 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1099 };
1100
1101 /*
1102 * Link Cable Beacon (LCB) ELS Response Frame
1103 */
1104 struct fc_lcb_res_frame {
1105 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */
1106 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1107 uint8_t reserved[2];
1108 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
1109 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1110 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1111 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1112 };
1113
1114 /*
1115 * Read Diagnostic Parameters (RDP) ELS frame.
1116 */
1117 #define SFF_PG0_IDENT_SFP 0x3
1118
1119 #define SFP_FLAG_PT_OPTICAL 0x0
1120 #define SFP_FLAG_PT_SWLASER 0x01
1121 #define SFP_FLAG_PT_LWLASER_LC1310 0x02
1122 #define SFP_FLAG_PT_LWLASER_LL1550 0x03
1123 #define SFP_FLAG_PT_MASK 0x0F
1124 #define SFP_FLAG_PT_SHIFT 0
1125
1126 #define SFP_FLAG_IS_OPTICAL_PORT 0x01
1127 #define SFP_FLAG_IS_OPTICAL_MASK 0x010
1128 #define SFP_FLAG_IS_OPTICAL_SHIFT 4
1129
1130 #define SFP_FLAG_IS_DESC_VALID 0x01
1131 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020
1132 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5
1133
1134 #define SFP_FLAG_CT_UNKNOWN 0x0
1135 #define SFP_FLAG_CT_SFP_PLUS 0x01
1136 #define SFP_FLAG_CT_MASK 0x3C
1137 #define SFP_FLAG_CT_SHIFT 6
1138
1139 struct fc_rdp_port_name_info {
1140 uint8_t wwnn[8];
1141 uint8_t wwpn[8];
1142 };
1143
1144
1145 /*
1146 * Link Error Status Block Structure (FC-FS-3) for RDP
1147 * This similar to RPS ELS
1148 */
1149 struct fc_link_status {
1150 uint32_t link_failure_cnt;
1151 uint32_t loss_of_synch_cnt;
1152 uint32_t loss_of_signal_cnt;
1153 uint32_t primitive_seq_proto_err;
1154 uint32_t invalid_trans_word;
1155 uint32_t invalid_crc_cnt;
1156
1157 };
1158
1159 #define RDP_PORT_NAMES_DESC_TAG 0x00010003
1160 struct fc_rdp_port_name_desc {
1161 uint32_t tag; /* 0001 0003h */
1162 uint32_t length; /* set to size of payload struct */
1163 struct fc_rdp_port_name_info port_names;
1164 };
1165
1166
1167 struct fc_rdp_fec_info {
1168 uint32_t CorrectedBlocks;
1169 uint32_t UncorrectableBlocks;
1170 };
1171
1172 #define RDP_FEC_DESC_TAG 0x00010005
1173 struct fc_fec_rdp_desc {
1174 uint32_t tag;
1175 uint32_t length;
1176 struct fc_rdp_fec_info info;
1177 };
1178
1179 struct fc_rdp_link_error_status_payload_info {
1180 struct fc_link_status link_status; /* 24 bytes */
1181 uint32_t port_type; /* bits 31-30 only */
1182 };
1183
1184 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
1185 struct fc_rdp_link_error_status_desc {
1186 uint32_t tag; /* 0001 0002h */
1187 uint32_t length; /* set to size of payload struct */
1188 struct fc_rdp_link_error_status_payload_info info;
1189 };
1190
1191 #define VN_PT_PHY_UNKNOWN 0x00
1192 #define VN_PT_PHY_PF_PORT 0x01
1193 #define VN_PT_PHY_ETH_MAC 0x10
1194 #define VN_PT_PHY_SHIFT 30
1195
1196 #define RDP_PS_1GB 0x8000
1197 #define RDP_PS_2GB 0x4000
1198 #define RDP_PS_4GB 0x2000
1199 #define RDP_PS_10GB 0x1000
1200 #define RDP_PS_8GB 0x0800
1201 #define RDP_PS_16GB 0x0400
1202 #define RDP_PS_32GB 0x0200
1203 #define RDP_PS_64GB 0x0100
1204 #define RDP_PS_128GB 0x0080
1205 #define RDP_PS_256GB 0x0040
1206
1207 #define RDP_CAP_USER_CONFIGURED 0x0002
1208 #define RDP_CAP_UNKNOWN 0x0001
1209 #define RDP_PS_UNKNOWN 0x0002
1210 #define RDP_PS_NOT_ESTABLISHED 0x0001
1211
1212 struct fc_rdp_port_speed {
1213 uint16_t capabilities;
1214 uint16_t speed;
1215 };
1216
1217 struct fc_rdp_port_speed_info {
1218 struct fc_rdp_port_speed port_speed;
1219 };
1220
1221 #define RDP_PORT_SPEED_DESC_TAG 0x00010001
1222 struct fc_rdp_port_speed_desc {
1223 uint32_t tag; /* 00010001h */
1224 uint32_t length; /* set to size of payload struct */
1225 struct fc_rdp_port_speed_info info;
1226 };
1227
1228 #define RDP_NPORT_ID_SIZE 4
1229 #define RDP_N_PORT_DESC_TAG 0x00000003
1230 struct fc_rdp_nport_desc {
1231 uint32_t tag; /* 0000 0003h, big endian */
1232 uint32_t length; /* size of RDP_N_PORT_ID struct */
1233 uint32_t nport_id : 12;
1234 uint32_t reserved : 8;
1235 };
1236
1237
1238 struct fc_rdp_link_service_info {
1239 uint32_t els_req; /* Request payload word 0 value.*/
1240 };
1241
1242 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001
1243 struct fc_rdp_link_service_desc {
1244 uint32_t tag; /* Descriptor tag 1 */
1245 uint32_t length; /* set to size of payload struct. */
1246 struct fc_rdp_link_service_info payload;
1247 /* must be ELS req Word 0(0x18) */
1248 };
1249
1250 struct fc_rdp_sfp_info {
1251 uint16_t temperature;
1252 uint16_t vcc;
1253 uint16_t tx_bias;
1254 uint16_t tx_power;
1255 uint16_t rx_power;
1256 uint16_t flags;
1257 };
1258
1259 #define RDP_SFP_DESC_TAG 0x00010000
1260 struct fc_rdp_sfp_desc {
1261 uint32_t tag;
1262 uint32_t length; /* set to size of sfp_info struct */
1263 struct fc_rdp_sfp_info sfp_info;
1264 };
1265
1266 /* Buffer Credit Descriptor */
1267 struct fc_rdp_bbc_info {
1268 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */
1269 uint32_t attached_port_bbc;
1270 uint32_t rtt; /* Round trip time */
1271 };
1272 #define RDP_BBC_DESC_TAG 0x00010006
1273 struct fc_rdp_bbc_desc {
1274 uint32_t tag;
1275 uint32_t length;
1276 struct fc_rdp_bbc_info bbc_info;
1277 };
1278
1279 /* Optical Element Type Transgression Flags */
1280 #define RDP_OET_LOW_WARNING 0x1
1281 #define RDP_OET_HIGH_WARNING 0x2
1282 #define RDP_OET_LOW_ALARM 0x4
1283 #define RDP_OET_HIGH_ALARM 0x8
1284
1285 #define RDP_OED_TEMPERATURE 0x1
1286 #define RDP_OED_VOLTAGE 0x2
1287 #define RDP_OED_TXBIAS 0x3
1288 #define RDP_OED_TXPOWER 0x4
1289 #define RDP_OED_RXPOWER 0x5
1290
1291 #define RDP_OED_TYPE_SHIFT 28
1292 /* Optical Element Data descriptor */
1293 struct fc_rdp_oed_info {
1294 uint16_t hi_alarm;
1295 uint16_t lo_alarm;
1296 uint16_t hi_warning;
1297 uint16_t lo_warning;
1298 uint32_t function_flags;
1299 };
1300 #define RDP_OED_DESC_TAG 0x00010007
1301 struct fc_rdp_oed_sfp_desc {
1302 uint32_t tag;
1303 uint32_t length;
1304 struct fc_rdp_oed_info oed_info;
1305 };
1306
1307 /* Optical Product Data descriptor */
1308 struct fc_rdp_opd_sfp_info {
1309 uint8_t vendor_name[16];
1310 uint8_t model_number[16];
1311 uint8_t serial_number[16];
1312 uint8_t revision[4];
1313 uint8_t date[8];
1314 };
1315
1316 #define RDP_OPD_DESC_TAG 0x00010008
1317 struct fc_rdp_opd_sfp_desc {
1318 uint32_t tag;
1319 uint32_t length;
1320 struct fc_rdp_opd_sfp_info opd_info;
1321 };
1322
1323 struct fc_rdp_req_frame {
1324 uint32_t rdp_command; /* ELS command opcode (0x18)*/
1325 uint32_t rdp_des_length; /* RDP Payload Word 1 */
1326 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1327 };
1328
1329
1330 struct fc_rdp_res_frame {
1331 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */
1332 uint32_t length; /* FC Word 1 */
1333 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */
1334 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */
1335 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */
1336 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */
1337 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */
1338 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */
1339 struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/
1340 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/
1341 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/
1342 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/
1343 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/
1344 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/
1345 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/
1346 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/
1347 };
1348
1349
1350 /* UVEM */
1351
1352 #define LPFC_UVEM_SIZE 60
1353 #define LPFC_UVEM_VEM_ID_DESC_SIZE 16
1354 #define LPFC_UVEM_VE_MAP_DESC_SIZE 20
1355
1356 #define VEM_ID_DESC_TAG 0x0001000A
1357 struct lpfc_vem_id_desc {
1358 uint32_t tag;
1359 uint32_t length;
1360 uint8_t vem_id[16];
1361 };
1362
1363 #define LPFC_QFPA_SIZE 4
1364
1365 #define INSTANTIATED_VE_DESC_TAG 0x0001000B
1366 struct instantiated_ve_desc {
1367 uint32_t tag;
1368 uint32_t length;
1369 uint8_t global_vem_id[16];
1370 uint32_t word6;
1371 #define lpfc_instantiated_local_id_SHIFT 0
1372 #define lpfc_instantiated_local_id_MASK 0x000000ff
1373 #define lpfc_instantiated_local_id_WORD word6
1374 #define lpfc_instantiated_nport_id_SHIFT 8
1375 #define lpfc_instantiated_nport_id_MASK 0x00ffffff
1376 #define lpfc_instantiated_nport_id_WORD word6
1377 };
1378
1379 #define DEINSTANTIATED_VE_DESC_TAG 0x0001000C
1380 struct deinstantiated_ve_desc {
1381 uint32_t tag;
1382 uint32_t length;
1383 uint8_t global_vem_id[16];
1384 uint32_t word6;
1385 #define lpfc_deinstantiated_nport_id_SHIFT 0
1386 #define lpfc_deinstantiated_nport_id_MASK 0x000000ff
1387 #define lpfc_deinstantiated_nport_id_WORD word6
1388 #define lpfc_deinstantiated_local_id_SHIFT 24
1389 #define lpfc_deinstantiated_local_id_MASK 0x00ffffff
1390 #define lpfc_deinstantiated_local_id_WORD word6
1391 };
1392
1393 /* Query Fabric Priority Allocation Response */
1394 #define LPFC_PRIORITY_RANGE_DESC_SIZE 12
1395
1396 struct priority_range_desc {
1397 uint32_t tag;
1398 uint32_t length;
1399 uint8_t lo_range;
1400 uint8_t hi_range;
1401 uint8_t qos_priority;
1402 uint8_t local_ve_id;
1403 };
1404
1405 struct fc_qfpa_res {
1406 uint32_t reply_sequence; /* LS_ACC or LS_RJT */
1407 uint32_t length; /* FC Word 1 */
1408 struct priority_range_desc desc[1];
1409 };
1410
1411 /* Application Server command code */
1412 /* VMID */
1413
1414 #define SLI_CT_APP_SEV_Subtypes 0x20 /* Application Server subtype */
1415
1416 #define SLI_CTAS_GAPPIA_ENT 0x0100 /* Get Application Identifier */
1417 #define SLI_CTAS_GALLAPPIA 0x0101 /* Get All Application Identifier */
1418 #define SLI_CTAS_GALLAPPIA_ID 0x0102 /* Get All Application Identifier */
1419 /* for Nport */
1420 #define SLI_CTAS_GAPPIA_IDAPP 0x0103 /* Get Application Identifier */
1421 /* for Nport */
1422 #define SLI_CTAS_RAPP_IDENT 0x0200 /* Register Application Identifier */
1423 #define SLI_CTAS_DAPP_IDENT 0x0300 /* Deregister Application */
1424 /* Identifier */
1425 #define SLI_CTAS_DALLAPP_ID 0x0301 /* Deregister All Application */
1426 /* Identifier */
1427
1428 struct entity_id_object {
1429 uint8_t entity_id_len;
1430 uint8_t entity_id[255]; /* VM UUID */
1431 };
1432
1433 struct app_id_object {
1434 __be32 port_id;
1435 __be32 app_id;
1436 struct entity_id_object obj;
1437 };
1438
1439 struct lpfc_vmid_rapp_ident_list {
1440 __be32 no_of_objects;
1441 struct entity_id_object obj[];
1442 };
1443
1444 struct lpfc_vmid_dapp_ident_list {
1445 __be32 no_of_objects;
1446 struct entity_id_object obj[];
1447 };
1448
1449 #define GALLAPPIA_ID_LAST 0x80
1450 struct lpfc_vmid_gallapp_ident_list {
1451 uint8_t control;
1452 uint8_t reserved[3];
1453 struct app_id_object app_id;
1454 };
1455
1456 #define RAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4)
1457 #define DAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4)
1458 #define GALLAPPIA_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4)
1459 #define DALLAPP_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4)
1460
1461 /******** FDMI ********/
1462
1463 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1464 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */
1465
1466 /* Definitions for HBA / Port attribute entries */
1467
1468 /* Attribute Entry Structures */
1469
1470 struct lpfc_fdmi_attr_u32 {
1471 __be16 type;
1472 __be16 len;
1473 __be32 value_u32;
1474 };
1475
1476 struct lpfc_fdmi_attr_wwn {
1477 __be16 type;
1478 __be16 len;
1479
1480 /* Keep as u8[8] instead of __be64 to avoid accidental zero padding
1481 * by compiler
1482 */
1483 u8 name[8];
1484 };
1485
1486 struct lpfc_fdmi_attr_fullwwn {
1487 __be16 type;
1488 __be16 len;
1489
1490 /* Keep as u8[8] instead of __be64 to avoid accidental zero padding
1491 * by compiler
1492 */
1493 u8 nname[8];
1494 u8 pname[8];
1495 };
1496
1497 struct lpfc_fdmi_attr_fc4types {
1498 __be16 type;
1499 __be16 len;
1500 u8 value_types[32];
1501 };
1502
1503 struct lpfc_fdmi_attr_string {
1504 __be16 type;
1505 __be16 len;
1506 char value_string[256];
1507 };
1508
1509 /* Maximum FDMI attribute length is Type+Len (4 bytes) + 256 byte string */
1510 #define FDMI_MAX_ATTRLEN sizeof(struct lpfc_fdmi_attr_string)
1511
1512 /*
1513 * HBA Attribute Block
1514 */
1515 struct lpfc_fdmi_attr_block {
1516 uint32_t EntryCnt; /* Number of HBA attribute entries */
1517 /* Variable Length Attribute Entry TLV's follow */
1518 };
1519
1520 /*
1521 * Port Entry
1522 */
1523 struct lpfc_fdmi_port_entry {
1524 struct lpfc_name PortName;
1525 };
1526
1527 /*
1528 * HBA Identifier
1529 */
1530 struct lpfc_fdmi_hba_ident {
1531 struct lpfc_name PortName;
1532 };
1533
1534 /*
1535 * Registered Port List Format
1536 */
1537 struct lpfc_fdmi_reg_port_list {
1538 __be32 EntryCnt;
1539 struct lpfc_fdmi_port_entry pe;
1540 };
1541
1542 /*
1543 * Register HBA(RHBA)
1544 */
1545 struct lpfc_fdmi_reg_hba {
1546 struct lpfc_fdmi_hba_ident hi;
1547 struct lpfc_fdmi_reg_port_list rpl;
1548 };
1549
1550 /******** MI MIB ********/
1551 #define SLI_CT_MIB_Subtypes 0x11
1552
1553 /*
1554 * Register HBA Attributes (RHAT)
1555 */
1556 struct lpfc_fdmi_reg_hbaattr {
1557 struct lpfc_name HBA_PortName;
1558 struct lpfc_fdmi_attr_block ab;
1559 };
1560
1561 /*
1562 * Register Port Attributes (RPA)
1563 */
1564 struct lpfc_fdmi_reg_portattr {
1565 struct lpfc_name PortName;
1566 struct lpfc_fdmi_attr_block ab;
1567 };
1568
1569 /*
1570 * HBA MAnagement Operations Command Codes
1571 */
1572 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1573 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1574 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1575 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1576 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */
1577 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
1578 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
1579 #define SLI_MGMT_RPRT 0x210 /* Register Port */
1580 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1581 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1582 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */
1583 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
1584 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */
1585
1586 #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */
1587
1588 /*
1589 * HBA Attribute Types
1590 */
1591 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */
1592 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */
1593 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */
1594 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */
1595 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */
1596 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */
1597 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */
1598 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1599 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */
1600 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */
1601 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1602 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */
1603 #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */
1604 #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */
1605 #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */
1606 #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */
1607 #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */
1608 #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */
1609
1610 /* Bit mask for all individual HBA attributes */
1611 #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001
1612 #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002
1613 #define LPFC_FDMI_HBA_ATTR_sn 0x00000004
1614 #define LPFC_FDMI_HBA_ATTR_model 0x00000008
1615 #define LPFC_FDMI_HBA_ATTR_description 0x00000010
1616 #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020
1617 #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040
1618 #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080
1619 #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100
1620 #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200
1621 #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400
1622 #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800
1623 #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */
1624 #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000
1625 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000
1626 #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000
1627 #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */
1628 #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000
1629
1630 /* Bit mask for FDMI-1 defined HBA attributes */
1631 #define LPFC_FDMI1_HBA_ATTR 0x000007ff
1632
1633 /* Bit mask for FDMI-2 defined HBA attributes */
1634 /* Skip vendor_info and bios_state */
1635 #define LPFC_FDMI2_HBA_ATTR 0x0002efff
1636
1637 /*
1638 * Port Attribute Types
1639 */
1640 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */
1641 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */
1642 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */
1643 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */
1644 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */
1645 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */
1646 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */
1647 #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */
1648 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */
1649 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */
1650 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */
1651 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */
1652 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */
1653 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */
1654 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */
1655 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */
1656 #define RPRT_VENDOR_MI 0xf047 /* vendor ascii string */
1657 #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */
1658 #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */
1659 #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */
1660 #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */
1661 #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */
1662 #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */
1663 #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */
1664
1665 /* Bit mask for all individual PORT attributes */
1666 #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001
1667 #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002
1668 #define LPFC_FDMI_PORT_ATTR_speed 0x00000004
1669 #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008
1670 #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010
1671 #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020
1672 #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040
1673 #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080
1674 #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100
1675 #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200
1676 #define LPFC_FDMI_PORT_ATTR_class 0x00000400
1677 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800
1678 #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000
1679 #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000
1680 #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000
1681 #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000
1682 #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */
1683 #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */
1684 #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */
1685 #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */
1686 #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */
1687 #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */
1688 #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */
1689 #define LPFC_FDMI_VENDOR_ATTR_mi 0x00800000 /* Vendor specific */
1690
1691 /* Bit mask for FDMI-1 defined PORT attributes */
1692 #define LPFC_FDMI1_PORT_ATTR 0x0000003f
1693
1694 /* Bit mask for FDMI-2 defined PORT attributes */
1695 #define LPFC_FDMI2_PORT_ATTR 0x0000ffff
1696
1697 /* Bit mask for Smart SAN defined PORT attributes */
1698 #define LPFC_FDMI2_SMART_ATTR 0x007fffff
1699
1700 /* Defines for PORT port state attribute */
1701 #define LPFC_FDMI_PORTSTATE_UNKNOWN 1
1702 #define LPFC_FDMI_PORTSTATE_ONLINE 2
1703
1704 /* Defines for PORT port type attribute */
1705 #define LPFC_FDMI_PORTTYPE_UNKNOWN 0
1706 #define LPFC_FDMI_PORTTYPE_NPORT 1
1707 #define LPFC_FDMI_PORTTYPE_NLPORT 2
1708
1709 /*
1710 * Begin HBA configuration parameters.
1711 * The PCI configuration register BAR assignments are:
1712 * BAR0, offset 0x10 - SLIM base memory address
1713 * BAR1, offset 0x14 - SLIM base memory high address
1714 * BAR2, offset 0x18 - REGISTER base memory address
1715 * BAR3, offset 0x1c - REGISTER base memory high address
1716 * BAR4, offset 0x20 - BIU I/O registers
1717 * BAR5, offset 0x24 - REGISTER base io high address
1718 */
1719
1720 /* Number of rings currently used and available. */
1721 #define MAX_SLI3_CONFIGURED_RINGS 3
1722 #define MAX_SLI3_RINGS 4
1723
1724 /* IOCB / Mailbox is owned by FireFly */
1725 #define OWN_CHIP 1
1726
1727 /* IOCB / Mailbox is owned by Host */
1728 #define OWN_HOST 0
1729
1730 /* Number of 4-byte words in an IOCB. */
1731 #define IOCB_WORD_SZ 8
1732
1733 /* network headers for Dfctl field */
1734 #define FC_NET_HDR 0x20
1735
1736 /* Start FireFly Register definitions */
1737 #define PCI_VENDOR_ID_EMULEX 0x10df
1738 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1739 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1740 #define PCI_DEVICE_ID_BALIUS 0xe131
1741 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1742 #define PCI_DEVICE_ID_LANCER_FC 0xe200
1743 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1744 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1745 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1746 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
1747 #define PCI_DEVICE_ID_LANCER_G7_FC 0xf400
1748 #define PCI_DEVICE_ID_LANCER_G7P_FC 0xf500
1749 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1750 #define PCI_DEVICE_ID_SAT_MID 0xf015
1751 #define PCI_DEVICE_ID_RFLY 0xf095
1752 #define PCI_DEVICE_ID_PFLY 0xf098
1753 #define PCI_DEVICE_ID_LP101 0xf0a1
1754 #define PCI_DEVICE_ID_TFLY 0xf0a5
1755 #define PCI_DEVICE_ID_BSMB 0xf0d1
1756 #define PCI_DEVICE_ID_BMID 0xf0d5
1757 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1758 #define PCI_DEVICE_ID_ZMID 0xf0e5
1759 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1760 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1761 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1762 #define PCI_DEVICE_ID_SAT 0xf100
1763 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1764 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1765 #define PCI_DEVICE_ID_FALCON 0xf180
1766 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1767 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1768 #define PCI_DEVICE_ID_CENTAUR 0xf900
1769 #define PCI_DEVICE_ID_PEGASUS 0xf980
1770 #define PCI_DEVICE_ID_THOR 0xfa00
1771 #define PCI_DEVICE_ID_VIPER 0xfb00
1772 #define PCI_DEVICE_ID_LP10000S 0xfc00
1773 #define PCI_DEVICE_ID_LP11000S 0xfc10
1774 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1775 #define PCI_DEVICE_ID_SAT_S 0xfc40
1776 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1777 #define PCI_DEVICE_ID_HELIOS 0xfd00
1778 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1779 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1780 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1781 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1782 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1783 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1784 #define PCI_DEVICE_ID_TIGERSHARK 0x0704
1785 #define PCI_DEVICE_ID_TOMCAT 0x0714
1786 #define PCI_DEVICE_ID_SKYHAWK 0x0724
1787 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1788 #define PCI_VENDOR_ID_ATTO 0x117c
1789 #define PCI_DEVICE_ID_CLRY_16XE 0x0064
1790 #define PCI_DEVICE_ID_CLRY_161E 0x0063
1791 #define PCI_DEVICE_ID_CLRY_162E 0x0064
1792 #define PCI_DEVICE_ID_CLRY_164E 0x0065
1793 #define PCI_DEVICE_ID_CLRY_16XP 0x0094
1794 #define PCI_DEVICE_ID_CLRY_161P 0x00a0
1795 #define PCI_DEVICE_ID_CLRY_162P 0x0094
1796 #define PCI_DEVICE_ID_CLRY_164P 0x00a1
1797 #define PCI_DEVICE_ID_CLRY_32XE 0x0094
1798 #define PCI_DEVICE_ID_CLRY_321E 0x00a2
1799 #define PCI_DEVICE_ID_CLRY_322E 0x00a3
1800 #define PCI_DEVICE_ID_CLRY_324E 0x00ac
1801 #define PCI_DEVICE_ID_CLRY_32XP 0x00bb
1802 #define PCI_DEVICE_ID_CLRY_321P 0x00bc
1803 #define PCI_DEVICE_ID_CLRY_322P 0x00bd
1804 #define PCI_DEVICE_ID_CLRY_324P 0x00be
1805 #define PCI_DEVICE_ID_TLFC_2 0x0064
1806 #define PCI_DEVICE_ID_TLFC_2XX2 0x4064
1807 #define PCI_DEVICE_ID_TLFC_3 0x0094
1808 #define PCI_DEVICE_ID_TLFC_3162 0x40a6
1809 #define PCI_DEVICE_ID_TLFC_3322 0x40a7
1810
1811 #define JEDEC_ID_ADDRESS 0x0080001c
1812 #define FIREFLY_JEDEC_ID 0x1ACC
1813 #define SUPERFLY_JEDEC_ID 0x0020
1814 #define DRAGONFLY_JEDEC_ID 0x0021
1815 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1816 #define CENTAUR_2G_JEDEC_ID 0x0026
1817 #define CENTAUR_1G_JEDEC_ID 0x0028
1818 #define PEGASUS_ORION_JEDEC_ID 0x0036
1819 #define PEGASUS_JEDEC_ID 0x0038
1820 #define THOR_JEDEC_ID 0x0012
1821 #define HELIOS_JEDEC_ID 0x0364
1822 #define ZEPHYR_JEDEC_ID 0x0577
1823 #define VIPER_JEDEC_ID 0x4838
1824 #define SATURN_JEDEC_ID 0x1004
1825
1826 #define JEDEC_ID_MASK 0x0FFFF000
1827 #define JEDEC_ID_SHIFT 12
1828 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1829
1830 typedef struct { /* FireFly BIU registers */
1831 uint32_t hostAtt; /* See definitions for Host Attention
1832 register */
1833 uint32_t chipAtt; /* See definitions for Chip Attention
1834 register */
1835 uint32_t hostStatus; /* See definitions for Host Status register */
1836 uint32_t hostControl; /* See definitions for Host Control register */
1837 uint32_t buiConfig; /* See definitions for BIU configuration
1838 register */
1839 } FF_REGS;
1840
1841 /* IO Register size in bytes */
1842 #define FF_REG_AREA_SIZE 256
1843
1844 /* Host Attention Register */
1845
1846 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1847
1848 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1849 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1850 #define HA_R0ATT 0x00000008 /* Bit 3 */
1851 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1852 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1853 #define HA_R1ATT 0x00000080 /* Bit 7 */
1854 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1855 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1856 #define HA_R2ATT 0x00000800 /* Bit 11 */
1857 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1858 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1859 #define HA_R3ATT 0x00008000 /* Bit 15 */
1860 #define HA_LATT 0x20000000 /* Bit 29 */
1861 #define HA_MBATT 0x40000000 /* Bit 30 */
1862 #define HA_ERATT 0x80000000 /* Bit 31 */
1863
1864 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1865 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1866 #define HA_RXATT 0x00000008 /* Bit 3 */
1867 #define HA_RXMASK 0x0000000f
1868
1869 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1870 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1871 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1872 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1873
1874 #define HA_R0_POS 3
1875 #define HA_R1_POS 7
1876 #define HA_R2_POS 11
1877 #define HA_R3_POS 15
1878 #define HA_LE_POS 29
1879 #define HA_MB_POS 30
1880 #define HA_ER_POS 31
1881 /* Chip Attention Register */
1882
1883 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1884
1885 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1886 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1887 #define CA_R0ATT 0x00000008 /* Bit 3 */
1888 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1889 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1890 #define CA_R1ATT 0x00000080 /* Bit 7 */
1891 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1892 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1893 #define CA_R2ATT 0x00000800 /* Bit 11 */
1894 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1895 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1896 #define CA_R3ATT 0x00008000 /* Bit 15 */
1897 #define CA_MBATT 0x40000000 /* Bit 30 */
1898
1899 /* Host Status Register */
1900
1901 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1902
1903 #define HS_MBRDY 0x00400000 /* Bit 22 */
1904 #define HS_FFRDY 0x00800000 /* Bit 23 */
1905 #define HS_FFER8 0x01000000 /* Bit 24 */
1906 #define HS_FFER7 0x02000000 /* Bit 25 */
1907 #define HS_FFER6 0x04000000 /* Bit 26 */
1908 #define HS_FFER5 0x08000000 /* Bit 27 */
1909 #define HS_FFER4 0x10000000 /* Bit 28 */
1910 #define HS_FFER3 0x20000000 /* Bit 29 */
1911 #define HS_FFER2 0x40000000 /* Bit 30 */
1912 #define HS_FFER1 0x80000000 /* Bit 31 */
1913 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1914 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1915 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
1916 /* Host Control Register */
1917
1918 #define HC_REG_OFFSET 12 /* Byte offset from register base address */
1919
1920 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1921 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1922 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1923 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1924 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1925 #define HC_INITHBI 0x02000000 /* Bit 25 */
1926 #define HC_INITMB 0x04000000 /* Bit 26 */
1927 #define HC_INITFF 0x08000000 /* Bit 27 */
1928 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1929 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1930
1931 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1932 #define MSIX_DFLT_ID 0
1933 #define MSIX_RNG0_ID 0
1934 #define MSIX_RNG1_ID 1
1935 #define MSIX_RNG2_ID 2
1936 #define MSIX_RNG3_ID 3
1937
1938 #define MSIX_LINK_ID 4
1939 #define MSIX_MBOX_ID 5
1940
1941 #define MSIX_SPARE0_ID 6
1942 #define MSIX_SPARE1_ID 7
1943
1944 /* Mailbox Commands */
1945 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1946 #define MBX_LOAD_SM 0x01
1947 #define MBX_READ_NV 0x02
1948 #define MBX_WRITE_NV 0x03
1949 #define MBX_RUN_BIU_DIAG 0x04
1950 #define MBX_INIT_LINK 0x05
1951 #define MBX_DOWN_LINK 0x06
1952 #define MBX_CONFIG_LINK 0x07
1953 #define MBX_CONFIG_RING 0x09
1954 #define MBX_RESET_RING 0x0A
1955 #define MBX_READ_CONFIG 0x0B
1956 #define MBX_READ_RCONFIG 0x0C
1957 #define MBX_READ_SPARM 0x0D
1958 #define MBX_READ_STATUS 0x0E
1959 #define MBX_READ_RPI 0x0F
1960 #define MBX_READ_XRI 0x10
1961 #define MBX_READ_REV 0x11
1962 #define MBX_READ_LNK_STAT 0x12
1963 #define MBX_REG_LOGIN 0x13
1964 #define MBX_UNREG_LOGIN 0x14
1965 #define MBX_CLEAR_LA 0x16
1966 #define MBX_DUMP_MEMORY 0x17
1967 #define MBX_DUMP_CONTEXT 0x18
1968 #define MBX_RUN_DIAGS 0x19
1969 #define MBX_RESTART 0x1A
1970 #define MBX_UPDATE_CFG 0x1B
1971 #define MBX_DOWN_LOAD 0x1C
1972 #define MBX_DEL_LD_ENTRY 0x1D
1973 #define MBX_RUN_PROGRAM 0x1E
1974 #define MBX_SET_MASK 0x20
1975 #define MBX_SET_VARIABLE 0x21
1976 #define MBX_UNREG_D_ID 0x23
1977 #define MBX_KILL_BOARD 0x24
1978 #define MBX_CONFIG_FARP 0x25
1979 #define MBX_BEACON 0x2A
1980 #define MBX_CONFIG_MSI 0x30
1981 #define MBX_HEARTBEAT 0x31
1982 #define MBX_WRITE_VPARMS 0x32
1983 #define MBX_ASYNCEVT_ENABLE 0x33
1984 #define MBX_READ_EVENT_LOG_STATUS 0x37
1985 #define MBX_READ_EVENT_LOG 0x38
1986 #define MBX_WRITE_EVENT_LOG 0x39
1987
1988 #define MBX_PORT_CAPABILITIES 0x3B
1989 #define MBX_PORT_IOV_CONTROL 0x3C
1990
1991 #define MBX_CONFIG_HBQ 0x7C
1992 #define MBX_LOAD_AREA 0x81
1993 #define MBX_RUN_BIU_DIAG64 0x84
1994 #define MBX_CONFIG_PORT 0x88
1995 #define MBX_READ_SPARM64 0x8D
1996 #define MBX_READ_RPI64 0x8F
1997 #define MBX_REG_LOGIN64 0x93
1998 #define MBX_READ_TOPOLOGY 0x95
1999 #define MBX_REG_VPI 0x96
2000 #define MBX_UNREG_VPI 0x97
2001
2002 #define MBX_WRITE_WWN 0x98
2003 #define MBX_SET_DEBUG 0x99
2004 #define MBX_LOAD_EXP_ROM 0x9C
2005 #define MBX_SLI4_CONFIG 0x9B
2006 #define MBX_SLI4_REQ_FTRS 0x9D
2007 #define MBX_MAX_CMDS 0x9E
2008 #define MBX_RESUME_RPI 0x9E
2009 #define MBX_SLI2_CMD_MASK 0x80
2010 #define MBX_REG_VFI 0x9F
2011 #define MBX_REG_FCFI 0xA0
2012 #define MBX_UNREG_VFI 0xA1
2013 #define MBX_UNREG_FCFI 0xA2
2014 #define MBX_INIT_VFI 0xA3
2015 #define MBX_INIT_VPI 0xA4
2016 #define MBX_ACCESS_VDATA 0xA5
2017 #define MBX_REG_FCFI_MRQ 0xAF
2018
2019 #define MBX_AUTH_PORT 0xF8
2020 #define MBX_SECURITY_MGMT 0xF9
2021
2022 /* IOCB Commands */
2023
2024 #define CMD_RCV_SEQUENCE_CX 0x01
2025 #define CMD_XMIT_SEQUENCE_CR 0x02
2026 #define CMD_XMIT_SEQUENCE_CX 0x03
2027 #define CMD_XMIT_BCAST_CN 0x04
2028 #define CMD_XMIT_BCAST_CX 0x05
2029 #define CMD_QUE_RING_BUF_CN 0x06
2030 #define CMD_QUE_XRI_BUF_CX 0x07
2031 #define CMD_IOCB_CONTINUE_CN 0x08
2032 #define CMD_RET_XRI_BUF_CX 0x09
2033 #define CMD_ELS_REQUEST_CR 0x0A
2034 #define CMD_ELS_REQUEST_CX 0x0B
2035 #define CMD_RCV_ELS_REQ_CX 0x0D
2036 #define CMD_ABORT_XRI_CN 0x0E
2037 #define CMD_ABORT_XRI_CX 0x0F
2038 #define CMD_CLOSE_XRI_CN 0x10
2039 #define CMD_CLOSE_XRI_CX 0x11
2040 #define CMD_CREATE_XRI_CR 0x12
2041 #define CMD_CREATE_XRI_CX 0x13
2042 #define CMD_GET_RPI_CN 0x14
2043 #define CMD_XMIT_ELS_RSP_CX 0x15
2044 #define CMD_GET_RPI_CR 0x16
2045 #define CMD_XRI_ABORTED_CX 0x17
2046 #define CMD_FCP_IWRITE_CR 0x18
2047 #define CMD_FCP_IWRITE_CX 0x19
2048 #define CMD_FCP_IREAD_CR 0x1A
2049 #define CMD_FCP_IREAD_CX 0x1B
2050 #define CMD_FCP_ICMND_CR 0x1C
2051 #define CMD_FCP_ICMND_CX 0x1D
2052 #define CMD_FCP_TSEND_CX 0x1F
2053 #define CMD_FCP_TRECEIVE_CX 0x21
2054 #define CMD_FCP_TRSP_CX 0x23
2055 #define CMD_FCP_AUTO_TRSP_CX 0x29
2056
2057 #define CMD_ADAPTER_MSG 0x20
2058 #define CMD_ADAPTER_DUMP 0x22
2059
2060 /* SLI_2 IOCB Command Set */
2061
2062 #define CMD_ASYNC_STATUS 0x7C
2063 #define CMD_RCV_SEQUENCE64_CX 0x81
2064 #define CMD_XMIT_SEQUENCE64_CR 0x82
2065 #define CMD_XMIT_SEQUENCE64_CX 0x83
2066 #define CMD_XMIT_BCAST64_CN 0x84
2067 #define CMD_XMIT_BCAST64_CX 0x85
2068 #define CMD_QUE_RING_BUF64_CN 0x86
2069 #define CMD_QUE_XRI_BUF64_CX 0x87
2070 #define CMD_IOCB_CONTINUE64_CN 0x88
2071 #define CMD_RET_XRI_BUF64_CX 0x89
2072 #define CMD_ELS_REQUEST64_CR 0x8A
2073 #define CMD_ELS_REQUEST64_CX 0x8B
2074 #define CMD_ABORT_MXRI64_CN 0x8C
2075 #define CMD_RCV_ELS_REQ64_CX 0x8D
2076 #define CMD_XMIT_ELS_RSP64_CX 0x95
2077 #define CMD_XMIT_BLS_RSP64_CX 0x97
2078 #define CMD_FCP_IWRITE64_CR 0x98
2079 #define CMD_FCP_IWRITE64_CX 0x99
2080 #define CMD_FCP_IREAD64_CR 0x9A
2081 #define CMD_FCP_IREAD64_CX 0x9B
2082 #define CMD_FCP_ICMND64_CR 0x9C
2083 #define CMD_FCP_ICMND64_CX 0x9D
2084 #define CMD_FCP_TSEND64_CX 0x9F
2085 #define CMD_FCP_TRECEIVE64_CX 0xA1
2086 #define CMD_FCP_TRSP64_CX 0xA3
2087
2088 #define CMD_QUE_XRI64_CX 0xB3
2089 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
2090 #define CMD_IOCB_RCV_ELS64_CX 0xB7
2091 #define CMD_IOCB_RET_XRI64_CX 0xB9
2092 #define CMD_IOCB_RCV_CONT64_CX 0xBB
2093
2094 #define CMD_GEN_REQUEST64_CR 0xC2
2095 #define CMD_GEN_REQUEST64_CX 0xC3
2096
2097 /* Unhandled SLI-3 Commands */
2098 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
2099 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
2100 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
2101 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
2102 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
2103 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
2104 #define CMD_IOCB_RET_HBQE64_CN 0xCA
2105 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
2106 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
2107 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
2108 #define CMD_IOCB_LOGENTRY_CN 0x94
2109 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
2110
2111 /* Data Security SLI Commands */
2112 #define DSSCMD_IWRITE64_CR 0xF8
2113 #define DSSCMD_IWRITE64_CX 0xF9
2114 #define DSSCMD_IREAD64_CR 0xFA
2115 #define DSSCMD_IREAD64_CX 0xFB
2116
2117 #define CMD_MAX_IOCB_CMD 0xFB
2118 #define CMD_IOCB_MASK 0xff
2119
2120 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
2121 iocb */
2122 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
2123 /*
2124 * Define Status
2125 */
2126 #define MBX_SUCCESS 0
2127 #define MBXERR_NUM_RINGS 1
2128 #define MBXERR_NUM_IOCBS 2
2129 #define MBXERR_IOCBS_EXCEEDED 3
2130 #define MBXERR_BAD_RING_NUMBER 4
2131 #define MBXERR_MASK_ENTRIES_RANGE 5
2132 #define MBXERR_MASKS_EXCEEDED 6
2133 #define MBXERR_BAD_PROFILE 7
2134 #define MBXERR_BAD_DEF_CLASS 8
2135 #define MBXERR_BAD_MAX_RESPONDER 9
2136 #define MBXERR_BAD_MAX_ORIGINATOR 10
2137 #define MBXERR_RPI_REGISTERED 11
2138 #define MBXERR_RPI_FULL 12
2139 #define MBXERR_NO_RESOURCES 13
2140 #define MBXERR_BAD_RCV_LENGTH 14
2141 #define MBXERR_DMA_ERROR 15
2142 #define MBXERR_ERROR 16
2143 #define MBXERR_LINK_DOWN 0x33
2144 #define MBXERR_SEC_NO_PERMISSION 0xF02
2145 #define MBX_NOT_FINISHED 255
2146
2147 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
2148 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
2149
2150 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
2151
2152 /*
2153 * return code Fail
2154 */
2155 #define FAILURE 1
2156
2157 /*
2158 * Begin Structure Definitions for Mailbox Commands
2159 */
2160
2161 typedef struct {
2162 #ifdef __BIG_ENDIAN_BITFIELD
2163 uint8_t tval;
2164 uint8_t tmask;
2165 uint8_t rval;
2166 uint8_t rmask;
2167 #else /* __LITTLE_ENDIAN_BITFIELD */
2168 uint8_t rmask;
2169 uint8_t rval;
2170 uint8_t tmask;
2171 uint8_t tval;
2172 #endif
2173 } RR_REG;
2174
2175 struct ulp_bde {
2176 uint32_t bdeAddress;
2177 #ifdef __BIG_ENDIAN_BITFIELD
2178 uint32_t bdeReserved:4;
2179 uint32_t bdeAddrHigh:4;
2180 uint32_t bdeSize:24;
2181 #else /* __LITTLE_ENDIAN_BITFIELD */
2182 uint32_t bdeSize:24;
2183 uint32_t bdeAddrHigh:4;
2184 uint32_t bdeReserved:4;
2185 #endif
2186 };
2187
2188 typedef struct ULP_BDL { /* SLI-2 */
2189 #ifdef __BIG_ENDIAN_BITFIELD
2190 uint32_t bdeFlags:8; /* BDL Flags */
2191 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
2192 #else /* __LITTLE_ENDIAN_BITFIELD */
2193 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
2194 uint32_t bdeFlags:8; /* BDL Flags */
2195 #endif
2196
2197 uint32_t addrLow; /* Address 0:31 */
2198 uint32_t addrHigh; /* Address 32:63 */
2199 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
2200 } ULP_BDL;
2201
2202 /*
2203 * BlockGuard Definitions
2204 */
2205
2206 enum lpfc_protgrp_type {
2207 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
2208 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
2209 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
2210 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
2211 };
2212
2213 /* PDE Descriptors */
2214 #define LPFC_PDE5_DESCRIPTOR 0x85
2215 #define LPFC_PDE6_DESCRIPTOR 0x86
2216 #define LPFC_PDE7_DESCRIPTOR 0x87
2217
2218 /* BlockGuard Opcodes */
2219 #define BG_OP_IN_NODIF_OUT_CRC 0x0
2220 #define BG_OP_IN_CRC_OUT_NODIF 0x1
2221 #define BG_OP_IN_NODIF_OUT_CSUM 0x2
2222 #define BG_OP_IN_CSUM_OUT_NODIF 0x3
2223 #define BG_OP_IN_CRC_OUT_CRC 0x4
2224 #define BG_OP_IN_CSUM_OUT_CSUM 0x5
2225 #define BG_OP_IN_CRC_OUT_CSUM 0x6
2226 #define BG_OP_IN_CSUM_OUT_CRC 0x7
2227 #define BG_OP_RAW_MODE 0x8
2228
2229 struct lpfc_pde5 {
2230 uint32_t word0;
2231 #define pde5_type_SHIFT 24
2232 #define pde5_type_MASK 0x000000ff
2233 #define pde5_type_WORD word0
2234 #define pde5_rsvd0_SHIFT 0
2235 #define pde5_rsvd0_MASK 0x00ffffff
2236 #define pde5_rsvd0_WORD word0
2237 uint32_t reftag; /* Reference Tag Value */
2238 uint32_t reftagtr; /* Reference Tag Translation Value */
2239 };
2240
2241 struct lpfc_pde6 {
2242 uint32_t word0;
2243 #define pde6_type_SHIFT 24
2244 #define pde6_type_MASK 0x000000ff
2245 #define pde6_type_WORD word0
2246 #define pde6_rsvd0_SHIFT 0
2247 #define pde6_rsvd0_MASK 0x00ffffff
2248 #define pde6_rsvd0_WORD word0
2249 uint32_t word1;
2250 #define pde6_rsvd1_SHIFT 26
2251 #define pde6_rsvd1_MASK 0x0000003f
2252 #define pde6_rsvd1_WORD word1
2253 #define pde6_na_SHIFT 25
2254 #define pde6_na_MASK 0x00000001
2255 #define pde6_na_WORD word1
2256 #define pde6_rsvd2_SHIFT 16
2257 #define pde6_rsvd2_MASK 0x000001FF
2258 #define pde6_rsvd2_WORD word1
2259 #define pde6_apptagtr_SHIFT 0
2260 #define pde6_apptagtr_MASK 0x0000ffff
2261 #define pde6_apptagtr_WORD word1
2262 uint32_t word2;
2263 #define pde6_optx_SHIFT 28
2264 #define pde6_optx_MASK 0x0000000f
2265 #define pde6_optx_WORD word2
2266 #define pde6_oprx_SHIFT 24
2267 #define pde6_oprx_MASK 0x0000000f
2268 #define pde6_oprx_WORD word2
2269 #define pde6_nr_SHIFT 23
2270 #define pde6_nr_MASK 0x00000001
2271 #define pde6_nr_WORD word2
2272 #define pde6_ce_SHIFT 22
2273 #define pde6_ce_MASK 0x00000001
2274 #define pde6_ce_WORD word2
2275 #define pde6_re_SHIFT 21
2276 #define pde6_re_MASK 0x00000001
2277 #define pde6_re_WORD word2
2278 #define pde6_ae_SHIFT 20
2279 #define pde6_ae_MASK 0x00000001
2280 #define pde6_ae_WORD word2
2281 #define pde6_ai_SHIFT 19
2282 #define pde6_ai_MASK 0x00000001
2283 #define pde6_ai_WORD word2
2284 #define pde6_bs_SHIFT 16
2285 #define pde6_bs_MASK 0x00000007
2286 #define pde6_bs_WORD word2
2287 #define pde6_apptagval_SHIFT 0
2288 #define pde6_apptagval_MASK 0x0000ffff
2289 #define pde6_apptagval_WORD word2
2290 };
2291
2292 struct lpfc_pde7 {
2293 uint32_t word0;
2294 #define pde7_type_SHIFT 24
2295 #define pde7_type_MASK 0x000000ff
2296 #define pde7_type_WORD word0
2297 #define pde7_rsvd0_SHIFT 0
2298 #define pde7_rsvd0_MASK 0x00ffffff
2299 #define pde7_rsvd0_WORD word0
2300 uint32_t addrHigh;
2301 uint32_t addrLow;
2302 };
2303
2304 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
2305
2306 typedef struct {
2307 #ifdef __BIG_ENDIAN_BITFIELD
2308 uint32_t rsvd2:25;
2309 uint32_t acknowledgment:1;
2310 uint32_t version:1;
2311 uint32_t erase_or_prog:1;
2312 uint32_t update_flash:1;
2313 uint32_t update_ram:1;
2314 uint32_t method:1;
2315 uint32_t load_cmplt:1;
2316 #else /* __LITTLE_ENDIAN_BITFIELD */
2317 uint32_t load_cmplt:1;
2318 uint32_t method:1;
2319 uint32_t update_ram:1;
2320 uint32_t update_flash:1;
2321 uint32_t erase_or_prog:1;
2322 uint32_t version:1;
2323 uint32_t acknowledgment:1;
2324 uint32_t rsvd2:25;
2325 #endif
2326
2327 uint32_t dl_to_adr_low;
2328 uint32_t dl_to_adr_high;
2329 uint32_t dl_len;
2330 union {
2331 uint32_t dl_from_mbx_offset;
2332 struct ulp_bde dl_from_bde;
2333 struct ulp_bde64 dl_from_bde64;
2334 } un;
2335
2336 } LOAD_SM_VAR;
2337
2338 /* Structure for MB Command READ_NVPARM (02) */
2339
2340 typedef struct {
2341 uint32_t rsvd1[3]; /* Read as all one's */
2342 uint32_t rsvd2; /* Read as all zero's */
2343 uint32_t portname[2]; /* N_PORT name */
2344 uint32_t nodename[2]; /* NODE name */
2345
2346 #ifdef __BIG_ENDIAN_BITFIELD
2347 uint32_t pref_DID:24;
2348 uint32_t hardAL_PA:8;
2349 #else /* __LITTLE_ENDIAN_BITFIELD */
2350 uint32_t hardAL_PA:8;
2351 uint32_t pref_DID:24;
2352 #endif
2353
2354 uint32_t rsvd3[21]; /* Read as all one's */
2355 } READ_NV_VAR;
2356
2357 /* Structure for MB Command WRITE_NVPARMS (03) */
2358
2359 typedef struct {
2360 uint32_t rsvd1[3]; /* Must be all one's */
2361 uint32_t rsvd2; /* Must be all zero's */
2362 uint32_t portname[2]; /* N_PORT name */
2363 uint32_t nodename[2]; /* NODE name */
2364
2365 #ifdef __BIG_ENDIAN_BITFIELD
2366 uint32_t pref_DID:24;
2367 uint32_t hardAL_PA:8;
2368 #else /* __LITTLE_ENDIAN_BITFIELD */
2369 uint32_t hardAL_PA:8;
2370 uint32_t pref_DID:24;
2371 #endif
2372
2373 uint32_t rsvd3[21]; /* Must be all one's */
2374 } WRITE_NV_VAR;
2375
2376 /* Structure for MB Command RUN_BIU_DIAG (04) */
2377 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2378
2379 typedef struct {
2380 uint32_t rsvd1;
2381 union {
2382 struct {
2383 struct ulp_bde xmit_bde;
2384 struct ulp_bde rcv_bde;
2385 } s1;
2386 struct {
2387 struct ulp_bde64 xmit_bde64;
2388 struct ulp_bde64 rcv_bde64;
2389 } s2;
2390 } un;
2391 } BIU_DIAG_VAR;
2392
2393 /* Structure for MB command READ_EVENT_LOG (0x38) */
2394 struct READ_EVENT_LOG_VAR {
2395 uint32_t word1;
2396 #define lpfc_event_log_SHIFT 29
2397 #define lpfc_event_log_MASK 0x00000001
2398 #define lpfc_event_log_WORD word1
2399 #define USE_MAILBOX_RESPONSE 1
2400 uint32_t offset;
2401 struct ulp_bde64 rcv_bde64;
2402 };
2403
2404 /* Structure for MB Command INIT_LINK (05) */
2405
2406 typedef struct {
2407 #ifdef __BIG_ENDIAN_BITFIELD
2408 uint32_t rsvd1:24;
2409 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2410 #else /* __LITTLE_ENDIAN_BITFIELD */
2411 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2412 uint32_t rsvd1:24;
2413 #endif
2414
2415 #ifdef __BIG_ENDIAN_BITFIELD
2416 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2417 uint8_t rsvd2;
2418 uint16_t link_flags;
2419 #else /* __LITTLE_ENDIAN_BITFIELD */
2420 uint16_t link_flags;
2421 uint8_t rsvd2;
2422 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2423 #endif
2424
2425 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
2426 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
2427 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
2428 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
2429 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
2430 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
2431 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
2432
2433 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
2434 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
2435 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
2436
2437 uint32_t link_speed;
2438 #define LINK_SPEED_AUTO 0x0 /* Auto selection */
2439 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
2440 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
2441 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
2442 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
2443 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
2444 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
2445 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */
2446 #define LINK_SPEED_64G 0x17 /* 64 Gigabaud */
2447 #define LINK_SPEED_128G 0x1A /* 128 Gigabaud */
2448 #define LINK_SPEED_256G 0x1D /* 256 Gigabaud */
2449
2450 } INIT_LINK_VAR;
2451
2452 /* Structure for MB Command DOWN_LINK (06) */
2453
2454 typedef struct {
2455 uint32_t rsvd1;
2456 } DOWN_LINK_VAR;
2457
2458 /* Structure for MB Command CONFIG_LINK (07) */
2459
2460 typedef struct {
2461 #ifdef __BIG_ENDIAN_BITFIELD
2462 uint32_t cr:1;
2463 uint32_t ci:1;
2464 uint32_t cr_delay:6;
2465 uint32_t cr_count:8;
2466 uint32_t rsvd1:8;
2467 uint32_t MaxBBC:8;
2468 #else /* __LITTLE_ENDIAN_BITFIELD */
2469 uint32_t MaxBBC:8;
2470 uint32_t rsvd1:8;
2471 uint32_t cr_count:8;
2472 uint32_t cr_delay:6;
2473 uint32_t ci:1;
2474 uint32_t cr:1;
2475 #endif
2476
2477 uint32_t myId;
2478 uint32_t rsvd2;
2479 uint32_t edtov;
2480 uint32_t arbtov;
2481 uint32_t ratov;
2482 uint32_t rttov;
2483 uint32_t altov;
2484 uint32_t crtov;
2485
2486 #ifdef __BIG_ENDIAN_BITFIELD
2487 uint32_t rsvd4:19;
2488 uint32_t cscn:1;
2489 uint32_t bbscn:4;
2490 uint32_t rsvd3:8;
2491 #else /* __LITTLE_ENDIAN_BITFIELD */
2492 uint32_t rsvd3:8;
2493 uint32_t bbscn:4;
2494 uint32_t cscn:1;
2495 uint32_t rsvd4:19;
2496 #endif
2497
2498 #ifdef __BIG_ENDIAN_BITFIELD
2499 uint32_t rrq_enable:1;
2500 uint32_t rrq_immed:1;
2501 uint32_t rsvd5:29;
2502 uint32_t ack0_enable:1;
2503 #else /* __LITTLE_ENDIAN_BITFIELD */
2504 uint32_t ack0_enable:1;
2505 uint32_t rsvd5:29;
2506 uint32_t rrq_immed:1;
2507 uint32_t rrq_enable:1;
2508 #endif
2509 } CONFIG_LINK;
2510
2511 /* Structure for MB Command PART_SLIM (08)
2512 * will be removed since SLI1 is no longer supported!
2513 */
2514 typedef struct {
2515 #ifdef __BIG_ENDIAN_BITFIELD
2516 uint16_t offCiocb;
2517 uint16_t numCiocb;
2518 uint16_t offRiocb;
2519 uint16_t numRiocb;
2520 #else /* __LITTLE_ENDIAN_BITFIELD */
2521 uint16_t numCiocb;
2522 uint16_t offCiocb;
2523 uint16_t numRiocb;
2524 uint16_t offRiocb;
2525 #endif
2526 } RING_DEF;
2527
2528 typedef struct {
2529 #ifdef __BIG_ENDIAN_BITFIELD
2530 uint32_t unused1:24;
2531 uint32_t numRing:8;
2532 #else /* __LITTLE_ENDIAN_BITFIELD */
2533 uint32_t numRing:8;
2534 uint32_t unused1:24;
2535 #endif
2536
2537 RING_DEF ringdef[4];
2538 uint32_t hbainit;
2539 } PART_SLIM_VAR;
2540
2541 /* Structure for MB Command CONFIG_RING (09) */
2542
2543 typedef struct {
2544 #ifdef __BIG_ENDIAN_BITFIELD
2545 uint32_t unused2:6;
2546 uint32_t recvSeq:1;
2547 uint32_t recvNotify:1;
2548 uint32_t numMask:8;
2549 uint32_t profile:8;
2550 uint32_t unused1:4;
2551 uint32_t ring:4;
2552 #else /* __LITTLE_ENDIAN_BITFIELD */
2553 uint32_t ring:4;
2554 uint32_t unused1:4;
2555 uint32_t profile:8;
2556 uint32_t numMask:8;
2557 uint32_t recvNotify:1;
2558 uint32_t recvSeq:1;
2559 uint32_t unused2:6;
2560 #endif
2561
2562 #ifdef __BIG_ENDIAN_BITFIELD
2563 uint16_t maxRespXchg;
2564 uint16_t maxOrigXchg;
2565 #else /* __LITTLE_ENDIAN_BITFIELD */
2566 uint16_t maxOrigXchg;
2567 uint16_t maxRespXchg;
2568 #endif
2569
2570 RR_REG rrRegs[6];
2571 } CONFIG_RING_VAR;
2572
2573 /* Structure for MB Command RESET_RING (10) */
2574
2575 typedef struct {
2576 uint32_t ring_no;
2577 } RESET_RING_VAR;
2578
2579 /* Structure for MB Command READ_CONFIG (11) */
2580
2581 typedef struct {
2582 #ifdef __BIG_ENDIAN_BITFIELD
2583 uint32_t cr:1;
2584 uint32_t ci:1;
2585 uint32_t cr_delay:6;
2586 uint32_t cr_count:8;
2587 uint32_t InitBBC:8;
2588 uint32_t MaxBBC:8;
2589 #else /* __LITTLE_ENDIAN_BITFIELD */
2590 uint32_t MaxBBC:8;
2591 uint32_t InitBBC:8;
2592 uint32_t cr_count:8;
2593 uint32_t cr_delay:6;
2594 uint32_t ci:1;
2595 uint32_t cr:1;
2596 #endif
2597
2598 #ifdef __BIG_ENDIAN_BITFIELD
2599 uint32_t topology:8;
2600 uint32_t myDid:24;
2601 #else /* __LITTLE_ENDIAN_BITFIELD */
2602 uint32_t myDid:24;
2603 uint32_t topology:8;
2604 #endif
2605
2606 /* Defines for topology (defined previously) */
2607 #ifdef __BIG_ENDIAN_BITFIELD
2608 uint32_t AR:1;
2609 uint32_t IR:1;
2610 uint32_t rsvd1:29;
2611 uint32_t ack0:1;
2612 #else /* __LITTLE_ENDIAN_BITFIELD */
2613 uint32_t ack0:1;
2614 uint32_t rsvd1:29;
2615 uint32_t IR:1;
2616 uint32_t AR:1;
2617 #endif
2618
2619 uint32_t edtov;
2620 uint32_t arbtov;
2621 uint32_t ratov;
2622 uint32_t rttov;
2623 uint32_t altov;
2624 uint32_t lmt;
2625 #define LMT_RESERVED 0x000 /* Not used */
2626 #define LMT_1Gb 0x004
2627 #define LMT_2Gb 0x008
2628 #define LMT_4Gb 0x040
2629 #define LMT_8Gb 0x080
2630 #define LMT_10Gb 0x100
2631 #define LMT_16Gb 0x200
2632 #define LMT_32Gb 0x400
2633 #define LMT_64Gb 0x800
2634 #define LMT_128Gb 0x1000
2635 #define LMT_256Gb 0x2000
2636 uint32_t rsvd2;
2637 uint32_t rsvd3;
2638 uint32_t max_xri;
2639 uint32_t max_iocb;
2640 uint32_t max_rpi;
2641 uint32_t avail_xri;
2642 uint32_t avail_iocb;
2643 uint32_t avail_rpi;
2644 uint32_t max_vpi;
2645 uint32_t rsvd4;
2646 uint32_t rsvd5;
2647 uint32_t avail_vpi;
2648 } READ_CONFIG_VAR;
2649
2650 /* Structure for MB Command READ_RCONFIG (12) */
2651
2652 typedef struct {
2653 #ifdef __BIG_ENDIAN_BITFIELD
2654 uint32_t rsvd2:7;
2655 uint32_t recvNotify:1;
2656 uint32_t numMask:8;
2657 uint32_t profile:8;
2658 uint32_t rsvd1:4;
2659 uint32_t ring:4;
2660 #else /* __LITTLE_ENDIAN_BITFIELD */
2661 uint32_t ring:4;
2662 uint32_t rsvd1:4;
2663 uint32_t profile:8;
2664 uint32_t numMask:8;
2665 uint32_t recvNotify:1;
2666 uint32_t rsvd2:7;
2667 #endif
2668
2669 #ifdef __BIG_ENDIAN_BITFIELD
2670 uint16_t maxResp;
2671 uint16_t maxOrig;
2672 #else /* __LITTLE_ENDIAN_BITFIELD */
2673 uint16_t maxOrig;
2674 uint16_t maxResp;
2675 #endif
2676
2677 RR_REG rrRegs[6];
2678
2679 #ifdef __BIG_ENDIAN_BITFIELD
2680 uint16_t cmdRingOffset;
2681 uint16_t cmdEntryCnt;
2682 uint16_t rspRingOffset;
2683 uint16_t rspEntryCnt;
2684 uint16_t nextCmdOffset;
2685 uint16_t rsvd3;
2686 uint16_t nextRspOffset;
2687 uint16_t rsvd4;
2688 #else /* __LITTLE_ENDIAN_BITFIELD */
2689 uint16_t cmdEntryCnt;
2690 uint16_t cmdRingOffset;
2691 uint16_t rspEntryCnt;
2692 uint16_t rspRingOffset;
2693 uint16_t rsvd3;
2694 uint16_t nextCmdOffset;
2695 uint16_t rsvd4;
2696 uint16_t nextRspOffset;
2697 #endif
2698 } READ_RCONF_VAR;
2699
2700 /* Structure for MB Command READ_SPARM (13) */
2701 /* Structure for MB Command READ_SPARM64 (0x8D) */
2702
2703 typedef struct {
2704 uint32_t rsvd1;
2705 uint32_t rsvd2;
2706 union {
2707 struct ulp_bde sp; /* This BDE points to struct serv_parm
2708 structure */
2709 struct ulp_bde64 sp64;
2710 } un;
2711 #ifdef __BIG_ENDIAN_BITFIELD
2712 uint16_t rsvd3;
2713 uint16_t vpi;
2714 #else /* __LITTLE_ENDIAN_BITFIELD */
2715 uint16_t vpi;
2716 uint16_t rsvd3;
2717 #endif
2718 } READ_SPARM_VAR;
2719
2720 /* Structure for MB Command READ_STATUS (14) */
2721 enum read_status_word1 {
2722 RD_ST_CC = 0x01,
2723 RD_ST_XKB = 0x80,
2724 };
2725
2726 enum read_status_word17 {
2727 RD_ST_XMIT_XKB_MASK = 0x3fffff,
2728 };
2729
2730 enum read_status_word18 {
2731 RD_ST_RCV_XKB_MASK = 0x3fffff,
2732 };
2733
2734 typedef struct {
2735 u8 clear_counters; /* rsvd 7:1, cc 0 */
2736 u8 rsvd5;
2737 u8 rsvd6;
2738 u8 xkb; /* xkb 7, rsvd 6:0 */
2739
2740 u32 rsvd8;
2741
2742 uint32_t xmitByteCnt;
2743 uint32_t rcvByteCnt;
2744 uint32_t xmitFrameCnt;
2745 uint32_t rcvFrameCnt;
2746 uint32_t xmitSeqCnt;
2747 uint32_t rcvSeqCnt;
2748 uint32_t totalOrigExchanges;
2749 uint32_t totalRespExchanges;
2750 uint32_t rcvPbsyCnt;
2751 uint32_t rcvFbsyCnt;
2752
2753 u32 drop_frame_no_rq;
2754 u32 empty_rq;
2755 u32 drop_frame_no_xri;
2756 u32 empty_xri;
2757
2758 u32 xmit_xkb; /* rsvd 31:22, xmit_xkb 21:0 */
2759 u32 rcv_xkb; /* rsvd 31:22, rcv_xkb 21:0 */
2760 } READ_STATUS_VAR;
2761
2762 /* Structure for MB Command READ_RPI (15) */
2763 /* Structure for MB Command READ_RPI64 (0x8F) */
2764
2765 typedef struct {
2766 #ifdef __BIG_ENDIAN_BITFIELD
2767 uint16_t nextRpi;
2768 uint16_t reqRpi;
2769 uint32_t rsvd2:8;
2770 uint32_t DID:24;
2771 #else /* __LITTLE_ENDIAN_BITFIELD */
2772 uint16_t reqRpi;
2773 uint16_t nextRpi;
2774 uint32_t DID:24;
2775 uint32_t rsvd2:8;
2776 #endif
2777
2778 union {
2779 struct ulp_bde sp;
2780 struct ulp_bde64 sp64;
2781 } un;
2782
2783 } READ_RPI_VAR;
2784
2785 /* Structure for MB Command READ_XRI (16) */
2786
2787 typedef struct {
2788 #ifdef __BIG_ENDIAN_BITFIELD
2789 uint16_t nextXri;
2790 uint16_t reqXri;
2791 uint16_t rsvd1;
2792 uint16_t rpi;
2793 uint32_t rsvd2:8;
2794 uint32_t DID:24;
2795 uint32_t rsvd3:8;
2796 uint32_t SID:24;
2797 uint32_t rsvd4;
2798 uint8_t seqId;
2799 uint8_t rsvd5;
2800 uint16_t seqCount;
2801 uint16_t oxId;
2802 uint16_t rxId;
2803 uint32_t rsvd6:30;
2804 uint32_t si:1;
2805 uint32_t exchOrig:1;
2806 #else /* __LITTLE_ENDIAN_BITFIELD */
2807 uint16_t reqXri;
2808 uint16_t nextXri;
2809 uint16_t rpi;
2810 uint16_t rsvd1;
2811 uint32_t DID:24;
2812 uint32_t rsvd2:8;
2813 uint32_t SID:24;
2814 uint32_t rsvd3:8;
2815 uint32_t rsvd4;
2816 uint16_t seqCount;
2817 uint8_t rsvd5;
2818 uint8_t seqId;
2819 uint16_t rxId;
2820 uint16_t oxId;
2821 uint32_t exchOrig:1;
2822 uint32_t si:1;
2823 uint32_t rsvd6:30;
2824 #endif
2825 } READ_XRI_VAR;
2826
2827 /* Structure for MB Command READ_REV (17) */
2828
2829 typedef struct {
2830 #ifdef __BIG_ENDIAN_BITFIELD
2831 uint32_t cv:1;
2832 uint32_t rr:1;
2833 uint32_t rsvd2:2;
2834 uint32_t v3req:1;
2835 uint32_t v3rsp:1;
2836 uint32_t rsvd1:25;
2837 uint32_t rv:1;
2838 #else /* __LITTLE_ENDIAN_BITFIELD */
2839 uint32_t rv:1;
2840 uint32_t rsvd1:25;
2841 uint32_t v3rsp:1;
2842 uint32_t v3req:1;
2843 uint32_t rsvd2:2;
2844 uint32_t rr:1;
2845 uint32_t cv:1;
2846 #endif
2847
2848 uint32_t biuRev;
2849 uint32_t smRev;
2850 union {
2851 uint32_t smFwRev;
2852 struct {
2853 #ifdef __BIG_ENDIAN_BITFIELD
2854 uint8_t ProgType;
2855 uint8_t ProgId;
2856 uint16_t ProgVer:4;
2857 uint16_t ProgRev:4;
2858 uint16_t ProgFixLvl:2;
2859 uint16_t ProgDistType:2;
2860 uint16_t DistCnt:4;
2861 #else /* __LITTLE_ENDIAN_BITFIELD */
2862 uint16_t DistCnt:4;
2863 uint16_t ProgDistType:2;
2864 uint16_t ProgFixLvl:2;
2865 uint16_t ProgRev:4;
2866 uint16_t ProgVer:4;
2867 uint8_t ProgId;
2868 uint8_t ProgType;
2869 #endif
2870
2871 } b;
2872 } un;
2873 uint32_t endecRev;
2874 #ifdef __BIG_ENDIAN_BITFIELD
2875 uint8_t feaLevelHigh;
2876 uint8_t feaLevelLow;
2877 uint8_t fcphHigh;
2878 uint8_t fcphLow;
2879 #else /* __LITTLE_ENDIAN_BITFIELD */
2880 uint8_t fcphLow;
2881 uint8_t fcphHigh;
2882 uint8_t feaLevelLow;
2883 uint8_t feaLevelHigh;
2884 #endif
2885
2886 uint32_t postKernRev;
2887 uint32_t opFwRev;
2888 uint8_t opFwName[16];
2889 uint32_t sli1FwRev;
2890 uint8_t sli1FwName[16];
2891 uint32_t sli2FwRev;
2892 uint8_t sli2FwName[16];
2893 uint32_t sli3Feat;
2894 uint32_t RandomData[6];
2895 } READ_REV_VAR;
2896
2897 /* Structure for MB Command READ_LINK_STAT (18) */
2898
2899 typedef struct {
2900 uint32_t word0;
2901
2902 #define lpfc_read_link_stat_rec_SHIFT 0
2903 #define lpfc_read_link_stat_rec_MASK 0x1
2904 #define lpfc_read_link_stat_rec_WORD word0
2905
2906 #define lpfc_read_link_stat_gec_SHIFT 1
2907 #define lpfc_read_link_stat_gec_MASK 0x1
2908 #define lpfc_read_link_stat_gec_WORD word0
2909
2910 #define lpfc_read_link_stat_w02oftow23of_SHIFT 2
2911 #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF
2912 #define lpfc_read_link_stat_w02oftow23of_WORD word0
2913
2914 #define lpfc_read_link_stat_rsvd_SHIFT 24
2915 #define lpfc_read_link_stat_rsvd_MASK 0x1F
2916 #define lpfc_read_link_stat_rsvd_WORD word0
2917
2918 #define lpfc_read_link_stat_gec2_SHIFT 29
2919 #define lpfc_read_link_stat_gec2_MASK 0x1
2920 #define lpfc_read_link_stat_gec2_WORD word0
2921
2922 #define lpfc_read_link_stat_clrc_SHIFT 30
2923 #define lpfc_read_link_stat_clrc_MASK 0x1
2924 #define lpfc_read_link_stat_clrc_WORD word0
2925
2926 #define lpfc_read_link_stat_clof_SHIFT 31
2927 #define lpfc_read_link_stat_clof_MASK 0x1
2928 #define lpfc_read_link_stat_clof_WORD word0
2929
2930 uint32_t linkFailureCnt;
2931 uint32_t lossSyncCnt;
2932 uint32_t lossSignalCnt;
2933 uint32_t primSeqErrCnt;
2934 uint32_t invalidXmitWord;
2935 uint32_t crcCnt;
2936 uint32_t primSeqTimeout;
2937 uint32_t elasticOverrun;
2938 uint32_t arbTimeout;
2939 uint32_t advRecBufCredit;
2940 uint32_t curRecBufCredit;
2941 uint32_t advTransBufCredit;
2942 uint32_t curTransBufCredit;
2943 uint32_t recEofCount;
2944 uint32_t recEofdtiCount;
2945 uint32_t recEofniCount;
2946 uint32_t recSofcount;
2947 uint32_t rsvd1;
2948 uint32_t rsvd2;
2949 uint32_t recDrpXriCount;
2950 uint32_t fecCorrBlkCount;
2951 uint32_t fecUncorrBlkCount;
2952 } READ_LNK_VAR;
2953
2954 /* Structure for MB Command REG_LOGIN (19) */
2955 /* Structure for MB Command REG_LOGIN64 (0x93) */
2956
2957 typedef struct {
2958 #ifdef __BIG_ENDIAN_BITFIELD
2959 uint16_t rsvd1;
2960 uint16_t rpi;
2961 uint32_t rsvd2:8;
2962 uint32_t did:24;
2963 #else /* __LITTLE_ENDIAN_BITFIELD */
2964 uint16_t rpi;
2965 uint16_t rsvd1;
2966 uint32_t did:24;
2967 uint32_t rsvd2:8;
2968 #endif
2969
2970 union {
2971 struct ulp_bde sp;
2972 struct ulp_bde64 sp64;
2973 } un;
2974
2975 #ifdef __BIG_ENDIAN_BITFIELD
2976 uint16_t rsvd6;
2977 uint16_t vpi;
2978 #else /* __LITTLE_ENDIAN_BITFIELD */
2979 uint16_t vpi;
2980 uint16_t rsvd6;
2981 #endif
2982
2983 } REG_LOGIN_VAR;
2984
2985 /* Word 30 contents for REG_LOGIN */
2986 typedef union {
2987 struct {
2988 #ifdef __BIG_ENDIAN_BITFIELD
2989 uint16_t rsvd1:12;
2990 uint16_t wd30_class:4;
2991 uint16_t xri;
2992 #else /* __LITTLE_ENDIAN_BITFIELD */
2993 uint16_t xri;
2994 uint16_t wd30_class:4;
2995 uint16_t rsvd1:12;
2996 #endif
2997 } f;
2998 uint32_t word;
2999 } REG_WD30;
3000
3001 /* Structure for MB Command UNREG_LOGIN (20) */
3002
3003 typedef struct {
3004 #ifdef __BIG_ENDIAN_BITFIELD
3005 uint16_t rsvd1;
3006 uint16_t rpi;
3007 uint32_t rsvd2;
3008 uint32_t rsvd3;
3009 uint32_t rsvd4;
3010 uint32_t rsvd5;
3011 uint16_t rsvd6;
3012 uint16_t vpi;
3013 #else /* __LITTLE_ENDIAN_BITFIELD */
3014 uint16_t rpi;
3015 uint16_t rsvd1;
3016 uint32_t rsvd2;
3017 uint32_t rsvd3;
3018 uint32_t rsvd4;
3019 uint32_t rsvd5;
3020 uint16_t vpi;
3021 uint16_t rsvd6;
3022 #endif
3023 } UNREG_LOGIN_VAR;
3024
3025 /* Structure for MB Command REG_VPI (0x96) */
3026 typedef struct {
3027 #ifdef __BIG_ENDIAN_BITFIELD
3028 uint32_t rsvd1;
3029 uint32_t rsvd2:7;
3030 uint32_t upd:1;
3031 uint32_t sid:24;
3032 uint32_t wwn[2];
3033 uint32_t rsvd5;
3034 uint16_t vfi;
3035 uint16_t vpi;
3036 #else /* __LITTLE_ENDIAN */
3037 uint32_t rsvd1;
3038 uint32_t sid:24;
3039 uint32_t upd:1;
3040 uint32_t rsvd2:7;
3041 uint32_t wwn[2];
3042 uint32_t rsvd5;
3043 uint16_t vpi;
3044 uint16_t vfi;
3045 #endif
3046 } REG_VPI_VAR;
3047
3048 /* Structure for MB Command UNREG_VPI (0x97) */
3049 typedef struct {
3050 uint32_t rsvd1;
3051 #ifdef __BIG_ENDIAN_BITFIELD
3052 uint16_t rsvd2;
3053 uint16_t sli4_vpi;
3054 #else /* __LITTLE_ENDIAN */
3055 uint16_t sli4_vpi;
3056 uint16_t rsvd2;
3057 #endif
3058 uint32_t rsvd3;
3059 uint32_t rsvd4;
3060 uint32_t rsvd5;
3061 #ifdef __BIG_ENDIAN_BITFIELD
3062 uint16_t rsvd6;
3063 uint16_t vpi;
3064 #else /* __LITTLE_ENDIAN */
3065 uint16_t vpi;
3066 uint16_t rsvd6;
3067 #endif
3068 } UNREG_VPI_VAR;
3069
3070 /* Structure for MB Command UNREG_D_ID (0x23) */
3071
3072 typedef struct {
3073 uint32_t did;
3074 uint32_t rsvd2;
3075 uint32_t rsvd3;
3076 uint32_t rsvd4;
3077 uint32_t rsvd5;
3078 #ifdef __BIG_ENDIAN_BITFIELD
3079 uint16_t rsvd6;
3080 uint16_t vpi;
3081 #else
3082 uint16_t vpi;
3083 uint16_t rsvd6;
3084 #endif
3085 } UNREG_D_ID_VAR;
3086
3087 /* Structure for MB Command READ_TOPOLOGY (0x95) */
3088 struct lpfc_mbx_read_top {
3089 uint32_t eventTag; /* Event tag */
3090 uint32_t word2;
3091 #define lpfc_mbx_read_top_fa_SHIFT 12
3092 #define lpfc_mbx_read_top_fa_MASK 0x00000001
3093 #define lpfc_mbx_read_top_fa_WORD word2
3094 #define lpfc_mbx_read_top_mm_SHIFT 11
3095 #define lpfc_mbx_read_top_mm_MASK 0x00000001
3096 #define lpfc_mbx_read_top_mm_WORD word2
3097 #define lpfc_mbx_read_top_pb_SHIFT 9
3098 #define lpfc_mbx_read_top_pb_MASK 0X00000001
3099 #define lpfc_mbx_read_top_pb_WORD word2
3100 #define lpfc_mbx_read_top_il_SHIFT 8
3101 #define lpfc_mbx_read_top_il_MASK 0x00000001
3102 #define lpfc_mbx_read_top_il_WORD word2
3103 #define lpfc_mbx_read_top_att_type_SHIFT 0
3104 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF
3105 #define lpfc_mbx_read_top_att_type_WORD word2
3106 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
3107 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */
3108 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
3109 #define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */
3110 uint32_t word3;
3111 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24
3112 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
3113 #define lpfc_mbx_read_top_alpa_granted_WORD word3
3114 #define lpfc_mbx_read_top_lip_alps_SHIFT 16
3115 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
3116 #define lpfc_mbx_read_top_lip_alps_WORD word3
3117 #define lpfc_mbx_read_top_lip_type_SHIFT 8
3118 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
3119 #define lpfc_mbx_read_top_lip_type_WORD word3
3120 #define lpfc_mbx_read_top_topology_SHIFT 0
3121 #define lpfc_mbx_read_top_topology_MASK 0x000000FF
3122 #define lpfc_mbx_read_top_topology_WORD word3
3123 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
3124 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
3125 /* store the LILP AL_PA position map into */
3126 struct ulp_bde64 lilpBde64;
3127 #define LPFC_ALPA_MAP_SIZE 128
3128 uint32_t word7;
3129 #define lpfc_mbx_read_top_ld_lu_SHIFT 31
3130 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
3131 #define lpfc_mbx_read_top_ld_lu_WORD word7
3132 #define lpfc_mbx_read_top_ld_tf_SHIFT 30
3133 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
3134 #define lpfc_mbx_read_top_ld_tf_WORD word7
3135 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
3136 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
3137 #define lpfc_mbx_read_top_ld_link_spd_WORD word7
3138 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
3139 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
3140 #define lpfc_mbx_read_top_ld_nl_port_WORD word7
3141 #define lpfc_mbx_read_top_ld_tx_SHIFT 2
3142 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
3143 #define lpfc_mbx_read_top_ld_tx_WORD word7
3144 #define lpfc_mbx_read_top_ld_rx_SHIFT 0
3145 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
3146 #define lpfc_mbx_read_top_ld_rx_WORD word7
3147 uint32_t word8;
3148 #define lpfc_mbx_read_top_lu_SHIFT 31
3149 #define lpfc_mbx_read_top_lu_MASK 0x00000001
3150 #define lpfc_mbx_read_top_lu_WORD word8
3151 #define lpfc_mbx_read_top_tf_SHIFT 30
3152 #define lpfc_mbx_read_top_tf_MASK 0x00000001
3153 #define lpfc_mbx_read_top_tf_WORD word8
3154 #define lpfc_mbx_read_top_link_spd_SHIFT 8
3155 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
3156 #define lpfc_mbx_read_top_link_spd_WORD word8
3157 #define lpfc_mbx_read_top_nl_port_SHIFT 4
3158 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
3159 #define lpfc_mbx_read_top_nl_port_WORD word8
3160 #define lpfc_mbx_read_top_tx_SHIFT 2
3161 #define lpfc_mbx_read_top_tx_MASK 0x00000003
3162 #define lpfc_mbx_read_top_tx_WORD word8
3163 #define lpfc_mbx_read_top_rx_SHIFT 0
3164 #define lpfc_mbx_read_top_rx_MASK 0x00000003
3165 #define lpfc_mbx_read_top_rx_WORD word8
3166 #define LPFC_LINK_SPEED_UNKNOWN 0x0
3167 #define LPFC_LINK_SPEED_1GHZ 0x04
3168 #define LPFC_LINK_SPEED_2GHZ 0x08
3169 #define LPFC_LINK_SPEED_4GHZ 0x10
3170 #define LPFC_LINK_SPEED_8GHZ 0x20
3171 #define LPFC_LINK_SPEED_10GHZ 0x40
3172 #define LPFC_LINK_SPEED_16GHZ 0x80
3173 #define LPFC_LINK_SPEED_32GHZ 0x90
3174 #define LPFC_LINK_SPEED_64GHZ 0xA0
3175 #define LPFC_LINK_SPEED_128GHZ 0xB0
3176 #define LPFC_LINK_SPEED_256GHZ 0xC0
3177 };
3178
3179 /* Structure for MB Command CLEAR_LA (22) */
3180
3181 typedef struct {
3182 uint32_t eventTag; /* Event tag */
3183 uint32_t rsvd1;
3184 } CLEAR_LA_VAR;
3185
3186 /* Structure for MB Command DUMP */
3187
3188 typedef struct {
3189 #ifdef __BIG_ENDIAN_BITFIELD
3190 uint32_t rsvd:25;
3191 uint32_t ra:1;
3192 uint32_t co:1;
3193 uint32_t cv:1;
3194 uint32_t type:4;
3195 uint32_t entry_index:16;
3196 uint32_t region_id:16;
3197 #else /* __LITTLE_ENDIAN_BITFIELD */
3198 uint32_t type:4;
3199 uint32_t cv:1;
3200 uint32_t co:1;
3201 uint32_t ra:1;
3202 uint32_t rsvd:25;
3203 uint32_t region_id:16;
3204 uint32_t entry_index:16;
3205 #endif
3206
3207 uint32_t sli4_length;
3208 uint32_t word_cnt;
3209 uint32_t resp_offset;
3210 } DUMP_VAR;
3211
3212 #define DMP_MEM_REG 0x1
3213 #define DMP_NV_PARAMS 0x2
3214 #define DMP_LMSD 0x3 /* Link Module Serial Data */
3215 #define DMP_WELL_KNOWN 0x4
3216
3217 #define DMP_REGION_VPD 0xe
3218 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
3219 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
3220 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
3221
3222 #define DMP_REGION_VPORT 0x16 /* VPort info region */
3223 #define DMP_VPORT_REGION_SIZE 0x200
3224 #define DMP_MBOX_OFFSET_WORD 0x5
3225
3226 #define DMP_REGION_23 0x17 /* fcoe param and port state region */
3227 #define DMP_RGN23_SIZE 0x400
3228
3229 #define WAKE_UP_PARMS_REGION_ID 4
3230 #define WAKE_UP_PARMS_WORD_SIZE 15
3231
3232 struct vport_rec {
3233 uint8_t wwpn[8];
3234 uint8_t wwnn[8];
3235 };
3236
3237 #define VPORT_INFO_SIG 0x32324752
3238 #define VPORT_INFO_REV_MASK 0xff
3239 #define VPORT_INFO_REV 0x1
3240 #define MAX_STATIC_VPORT_COUNT 16
3241 struct static_vport_info {
3242 uint32_t signature;
3243 uint32_t rev;
3244 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
3245 uint32_t resvd[66];
3246 };
3247
3248 /* Option rom version structure */
3249 struct prog_id {
3250 #ifdef __BIG_ENDIAN_BITFIELD
3251 uint8_t type;
3252 uint8_t id;
3253 uint32_t ver:4; /* Major Version */
3254 uint32_t rev:4; /* Revision */
3255 uint32_t lev:2; /* Level */
3256 uint32_t dist:2; /* Dist Type */
3257 uint32_t num:4; /* number after dist type */
3258 #else /* __LITTLE_ENDIAN_BITFIELD */
3259 uint32_t num:4; /* number after dist type */
3260 uint32_t dist:2; /* Dist Type */
3261 uint32_t lev:2; /* Level */
3262 uint32_t rev:4; /* Revision */
3263 uint32_t ver:4; /* Major Version */
3264 uint8_t id;
3265 uint8_t type;
3266 #endif
3267 };
3268
3269 /* Structure for MB Command UPDATE_CFG (0x1B) */
3270
3271 struct update_cfg_var {
3272 #ifdef __BIG_ENDIAN_BITFIELD
3273 uint32_t rsvd2:16;
3274 uint32_t type:8;
3275 uint32_t rsvd:1;
3276 uint32_t ra:1;
3277 uint32_t co:1;
3278 uint32_t cv:1;
3279 uint32_t req:4;
3280 uint32_t entry_length:16;
3281 uint32_t region_id:16;
3282 #else /* __LITTLE_ENDIAN_BITFIELD */
3283 uint32_t req:4;
3284 uint32_t cv:1;
3285 uint32_t co:1;
3286 uint32_t ra:1;
3287 uint32_t rsvd:1;
3288 uint32_t type:8;
3289 uint32_t rsvd2:16;
3290 uint32_t region_id:16;
3291 uint32_t entry_length:16;
3292 #endif
3293
3294 uint32_t resp_info;
3295 uint32_t byte_cnt;
3296 uint32_t data_offset;
3297 };
3298
3299 struct hbq_mask {
3300 #ifdef __BIG_ENDIAN_BITFIELD
3301 uint8_t tmatch;
3302 uint8_t tmask;
3303 uint8_t rctlmatch;
3304 uint8_t rctlmask;
3305 #else /* __LITTLE_ENDIAN */
3306 uint8_t rctlmask;
3307 uint8_t rctlmatch;
3308 uint8_t tmask;
3309 uint8_t tmatch;
3310 #endif
3311 };
3312
3313
3314 /* Structure for MB Command CONFIG_HBQ (7c) */
3315
3316 struct config_hbq_var {
3317 #ifdef __BIG_ENDIAN_BITFIELD
3318 uint32_t rsvd1 :7;
3319 uint32_t recvNotify :1; /* Receive Notification */
3320 uint32_t numMask :8; /* # Mask Entries */
3321 uint32_t profile :8; /* Selection Profile */
3322 uint32_t rsvd2 :8;
3323 #else /* __LITTLE_ENDIAN */
3324 uint32_t rsvd2 :8;
3325 uint32_t profile :8; /* Selection Profile */
3326 uint32_t numMask :8; /* # Mask Entries */
3327 uint32_t recvNotify :1; /* Receive Notification */
3328 uint32_t rsvd1 :7;
3329 #endif
3330
3331 #ifdef __BIG_ENDIAN_BITFIELD
3332 uint32_t hbqId :16;
3333 uint32_t rsvd3 :12;
3334 uint32_t ringMask :4;
3335 #else /* __LITTLE_ENDIAN */
3336 uint32_t ringMask :4;
3337 uint32_t rsvd3 :12;
3338 uint32_t hbqId :16;
3339 #endif
3340
3341 #ifdef __BIG_ENDIAN_BITFIELD
3342 uint32_t entry_count :16;
3343 uint32_t rsvd4 :8;
3344 uint32_t headerLen :8;
3345 #else /* __LITTLE_ENDIAN */
3346 uint32_t headerLen :8;
3347 uint32_t rsvd4 :8;
3348 uint32_t entry_count :16;
3349 #endif
3350
3351 uint32_t hbqaddrLow;
3352 uint32_t hbqaddrHigh;
3353
3354 #ifdef __BIG_ENDIAN_BITFIELD
3355 uint32_t rsvd5 :31;
3356 uint32_t logEntry :1;
3357 #else /* __LITTLE_ENDIAN */
3358 uint32_t logEntry :1;
3359 uint32_t rsvd5 :31;
3360 #endif
3361
3362 uint32_t rsvd6; /* w7 */
3363 uint32_t rsvd7; /* w8 */
3364 uint32_t rsvd8; /* w9 */
3365
3366 struct hbq_mask hbqMasks[6];
3367
3368
3369 union {
3370 uint32_t allprofiles[12];
3371
3372 struct {
3373 #ifdef __BIG_ENDIAN_BITFIELD
3374 uint32_t seqlenoff :16;
3375 uint32_t maxlen :16;
3376 #else /* __LITTLE_ENDIAN */
3377 uint32_t maxlen :16;
3378 uint32_t seqlenoff :16;
3379 #endif
3380 #ifdef __BIG_ENDIAN_BITFIELD
3381 uint32_t rsvd1 :28;
3382 uint32_t seqlenbcnt :4;
3383 #else /* __LITTLE_ENDIAN */
3384 uint32_t seqlenbcnt :4;
3385 uint32_t rsvd1 :28;
3386 #endif
3387 uint32_t rsvd[10];
3388 } profile2;
3389
3390 struct {
3391 #ifdef __BIG_ENDIAN_BITFIELD
3392 uint32_t seqlenoff :16;
3393 uint32_t maxlen :16;
3394 #else /* __LITTLE_ENDIAN */
3395 uint32_t maxlen :16;
3396 uint32_t seqlenoff :16;
3397 #endif
3398 #ifdef __BIG_ENDIAN_BITFIELD
3399 uint32_t cmdcodeoff :28;
3400 uint32_t rsvd1 :12;
3401 uint32_t seqlenbcnt :4;
3402 #else /* __LITTLE_ENDIAN */
3403 uint32_t seqlenbcnt :4;
3404 uint32_t rsvd1 :12;
3405 uint32_t cmdcodeoff :28;
3406 #endif
3407 uint32_t cmdmatch[8];
3408
3409 uint32_t rsvd[2];
3410 } profile3;
3411
3412 struct {
3413 #ifdef __BIG_ENDIAN_BITFIELD
3414 uint32_t seqlenoff :16;
3415 uint32_t maxlen :16;
3416 #else /* __LITTLE_ENDIAN */
3417 uint32_t maxlen :16;
3418 uint32_t seqlenoff :16;
3419 #endif
3420 #ifdef __BIG_ENDIAN_BITFIELD
3421 uint32_t cmdcodeoff :28;
3422 uint32_t rsvd1 :12;
3423 uint32_t seqlenbcnt :4;
3424 #else /* __LITTLE_ENDIAN */
3425 uint32_t seqlenbcnt :4;
3426 uint32_t rsvd1 :12;
3427 uint32_t cmdcodeoff :28;
3428 #endif
3429 uint32_t cmdmatch[8];
3430
3431 uint32_t rsvd[2];
3432 } profile5;
3433
3434 } profiles;
3435
3436 };
3437
3438
3439
3440 /* Structure for MB Command CONFIG_PORT (0x88) */
3441 typedef struct {
3442 #ifdef __BIG_ENDIAN_BITFIELD
3443 uint32_t cBE : 1;
3444 uint32_t cET : 1;
3445 uint32_t cHpcb : 1;
3446 uint32_t cMA : 1;
3447 uint32_t sli_mode : 4;
3448 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3449 * config block */
3450 #else /* __LITTLE_ENDIAN */
3451 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3452 * config block */
3453 uint32_t sli_mode : 4;
3454 uint32_t cMA : 1;
3455 uint32_t cHpcb : 1;
3456 uint32_t cET : 1;
3457 uint32_t cBE : 1;
3458 #endif
3459
3460 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
3461 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
3462 uint32_t hbainit[5];
3463 #ifdef __BIG_ENDIAN_BITFIELD
3464 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3465 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3466 #else /* __LITTLE_ENDIAN */
3467 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3468 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3469 #endif
3470
3471 #ifdef __BIG_ENDIAN_BITFIELD
3472 uint32_t rsvd1 : 20; /* Reserved */
3473 uint32_t casabt : 1; /* Configure async abts status notice */
3474 uint32_t rsvd2 : 2; /* Reserved */
3475 uint32_t cbg : 1; /* Configure BlockGuard */
3476 uint32_t cmv : 1; /* Configure Max VPIs */
3477 uint32_t ccrp : 1; /* Config Command Ring Polling */
3478 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3479 uint32_t chbs : 1; /* Cofigure Host Backing store */
3480 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3481 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3482 uint32_t cmx : 1; /* Configure Max XRIs */
3483 uint32_t cmr : 1; /* Configure Max RPIs */
3484 #else /* __LITTLE_ENDIAN */
3485 uint32_t cmr : 1; /* Configure Max RPIs */
3486 uint32_t cmx : 1; /* Configure Max XRIs */
3487 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3488 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3489 uint32_t chbs : 1; /* Cofigure Host Backing store */
3490 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3491 uint32_t ccrp : 1; /* Config Command Ring Polling */
3492 uint32_t cmv : 1; /* Configure Max VPIs */
3493 uint32_t cbg : 1; /* Configure BlockGuard */
3494 uint32_t rsvd2 : 2; /* Reserved */
3495 uint32_t casabt : 1; /* Configure async abts status notice */
3496 uint32_t rsvd1 : 20; /* Reserved */
3497 #endif
3498 #ifdef __BIG_ENDIAN_BITFIELD
3499 uint32_t rsvd3 : 20; /* Reserved */
3500 uint32_t gasabt : 1; /* Grant async abts status notice */
3501 uint32_t rsvd4 : 2; /* Reserved */
3502 uint32_t gbg : 1; /* Grant BlockGuard */
3503 uint32_t gmv : 1; /* Grant Max VPIs */
3504 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3505 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3506 uint32_t ghbs : 1; /* Grant Host Backing Store */
3507 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3508 uint32_t gerbm : 1; /* Grant ERBM Request */
3509 uint32_t gmx : 1; /* Grant Max XRIs */
3510 uint32_t gmr : 1; /* Grant Max RPIs */
3511 #else /* __LITTLE_ENDIAN */
3512 uint32_t gmr : 1; /* Grant Max RPIs */
3513 uint32_t gmx : 1; /* Grant Max XRIs */
3514 uint32_t gerbm : 1; /* Grant ERBM Request */
3515 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3516 uint32_t ghbs : 1; /* Grant Host Backing Store */
3517 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3518 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3519 uint32_t gmv : 1; /* Grant Max VPIs */
3520 uint32_t gbg : 1; /* Grant BlockGuard */
3521 uint32_t rsvd4 : 2; /* Reserved */
3522 uint32_t gasabt : 1; /* Grant async abts status notice */
3523 uint32_t rsvd3 : 20; /* Reserved */
3524 #endif
3525
3526 #ifdef __BIG_ENDIAN_BITFIELD
3527 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3528 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3529 #else /* __LITTLE_ENDIAN */
3530 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3531 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3532 #endif
3533
3534 #ifdef __BIG_ENDIAN_BITFIELD
3535 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3536 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3537 #else /* __LITTLE_ENDIAN */
3538 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3539 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3540 #endif
3541
3542 uint32_t rsvd6; /* Reserved */
3543
3544 #ifdef __BIG_ENDIAN_BITFIELD
3545 uint32_t rsvd7 : 16;
3546 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3547 #else /* __LITTLE_ENDIAN */
3548 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3549 uint32_t rsvd7 : 16;
3550 #endif
3551
3552 } CONFIG_PORT_VAR;
3553
3554 /* Structure for MB Command CONFIG_MSI (0x30) */
3555 struct config_msi_var {
3556 #ifdef __BIG_ENDIAN_BITFIELD
3557 uint32_t dfltMsgNum:8; /* Default message number */
3558 uint32_t rsvd1:11; /* Reserved */
3559 uint32_t NID:5; /* Number of secondary attention IDs */
3560 uint32_t rsvd2:5; /* Reserved */
3561 uint32_t dfltPresent:1; /* Default message number present */
3562 uint32_t addFlag:1; /* Add association flag */
3563 uint32_t reportFlag:1; /* Report association flag */
3564 #else /* __LITTLE_ENDIAN_BITFIELD */
3565 uint32_t reportFlag:1; /* Report association flag */
3566 uint32_t addFlag:1; /* Add association flag */
3567 uint32_t dfltPresent:1; /* Default message number present */
3568 uint32_t rsvd2:5; /* Reserved */
3569 uint32_t NID:5; /* Number of secondary attention IDs */
3570 uint32_t rsvd1:11; /* Reserved */
3571 uint32_t dfltMsgNum:8; /* Default message number */
3572 #endif
3573 uint32_t attentionConditions[2];
3574 uint8_t attentionId[16];
3575 uint8_t messageNumberByHA[64];
3576 uint8_t messageNumberByID[16];
3577 uint32_t autoClearHA[2];
3578 #ifdef __BIG_ENDIAN_BITFIELD
3579 uint32_t rsvd3:16;
3580 uint32_t autoClearID:16;
3581 #else /* __LITTLE_ENDIAN_BITFIELD */
3582 uint32_t autoClearID:16;
3583 uint32_t rsvd3:16;
3584 #endif
3585 uint32_t rsvd4;
3586 };
3587
3588 /* SLI-2 Port Control Block */
3589
3590 /* SLIM POINTER */
3591 #define SLIMOFF 0x30 /* WORD */
3592
3593 typedef struct _SLI2_RDSC {
3594 uint32_t cmdEntries;
3595 uint32_t cmdAddrLow;
3596 uint32_t cmdAddrHigh;
3597
3598 uint32_t rspEntries;
3599 uint32_t rspAddrLow;
3600 uint32_t rspAddrHigh;
3601 } SLI2_RDSC;
3602
3603 typedef struct _PCB {
3604 #ifdef __BIG_ENDIAN_BITFIELD
3605 uint32_t type:8;
3606 #define TYPE_NATIVE_SLI2 0x01
3607 uint32_t feature:8;
3608 #define FEATURE_INITIAL_SLI2 0x01
3609 uint32_t rsvd:12;
3610 uint32_t maxRing:4;
3611 #else /* __LITTLE_ENDIAN_BITFIELD */
3612 uint32_t maxRing:4;
3613 uint32_t rsvd:12;
3614 uint32_t feature:8;
3615 #define FEATURE_INITIAL_SLI2 0x01
3616 uint32_t type:8;
3617 #define TYPE_NATIVE_SLI2 0x01
3618 #endif
3619
3620 uint32_t mailBoxSize;
3621 uint32_t mbAddrLow;
3622 uint32_t mbAddrHigh;
3623
3624 uint32_t hgpAddrLow;
3625 uint32_t hgpAddrHigh;
3626
3627 uint32_t pgpAddrLow;
3628 uint32_t pgpAddrHigh;
3629 SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3630 } PCB_t;
3631
3632 /* NEW_FEATURE */
3633 typedef struct {
3634 #ifdef __BIG_ENDIAN_BITFIELD
3635 uint32_t rsvd0:27;
3636 uint32_t discardFarp:1;
3637 uint32_t IPEnable:1;
3638 uint32_t nodeName:1;
3639 uint32_t portName:1;
3640 uint32_t filterEnable:1;
3641 #else /* __LITTLE_ENDIAN_BITFIELD */
3642 uint32_t filterEnable:1;
3643 uint32_t portName:1;
3644 uint32_t nodeName:1;
3645 uint32_t IPEnable:1;
3646 uint32_t discardFarp:1;
3647 uint32_t rsvd:27;
3648 #endif
3649
3650 uint8_t portname[8]; /* Used to be struct lpfc_name */
3651 uint8_t nodename[8];
3652 uint32_t rsvd1;
3653 uint32_t rsvd2;
3654 uint32_t rsvd3;
3655 uint32_t IPAddress;
3656 } CONFIG_FARP_VAR;
3657
3658 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3659
3660 typedef struct {
3661 #ifdef __BIG_ENDIAN_BITFIELD
3662 uint32_t rsvd:30;
3663 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3664 #else /* __LITTLE_ENDIAN */
3665 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3666 uint32_t rsvd:30;
3667 #endif
3668 } ASYNCEVT_ENABLE_VAR;
3669
3670 /* Union of all Mailbox Command types */
3671 #define MAILBOX_CMD_WSIZE 32
3672 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3673 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3674 #define MAILBOX_EXT_WSIZE 512
3675 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3676 #define MAILBOX_HBA_EXT_OFFSET 0x100
3677 /* max mbox xmit size is a page size for sysfs IO operations */
3678 #define MAILBOX_SYSFS_MAX 4096
3679
3680 typedef union {
3681 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3682 * feature/max ring number
3683 */
3684 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3685 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3686 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
3687 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3688 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
3689 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
3690 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3691 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
3692 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3693 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3694 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3695 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3696 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3697 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
3698 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3699 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3700 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3701 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
3702 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3703 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
3704 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
3705 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3706 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3707 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3708 * NEW_FEATURE
3709 */
3710 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3711 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3712 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3713 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3714 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3715 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3716 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3717 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3718 * (READ_EVENT_LOG)
3719 */
3720 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
3721 } MAILVARIANTS;
3722
3723 /*
3724 * SLI-2 specific structures
3725 */
3726
3727 struct lpfc_hgp {
3728 __le32 cmdPutInx;
3729 __le32 rspGetInx;
3730 };
3731
3732 struct lpfc_pgp {
3733 __le32 cmdGetInx;
3734 __le32 rspPutInx;
3735 };
3736
3737 struct sli2_desc {
3738 uint32_t unused1[16];
3739 struct lpfc_hgp host[MAX_SLI3_RINGS];
3740 struct lpfc_pgp port[MAX_SLI3_RINGS];
3741 };
3742
3743 struct sli3_desc {
3744 struct lpfc_hgp host[MAX_SLI3_RINGS];
3745 uint32_t reserved[8];
3746 uint32_t hbq_put[16];
3747 };
3748
3749 struct sli3_pgp {
3750 struct lpfc_pgp port[MAX_SLI3_RINGS];
3751 uint32_t hbq_get[16];
3752 };
3753
3754 union sli_var {
3755 struct sli2_desc s2;
3756 struct sli3_desc s3;
3757 struct sli3_pgp s3_pgp;
3758 };
3759
3760 typedef struct {
3761 struct_group_tagged(MAILBOX_word0, bits,
3762 union {
3763 struct {
3764 #ifdef __BIG_ENDIAN_BITFIELD
3765 uint16_t mbxStatus;
3766 uint8_t mbxCommand;
3767 uint8_t mbxReserved:6;
3768 uint8_t mbxHc:1;
3769 uint8_t mbxOwner:1; /* Low order bit first word */
3770 #else /* __LITTLE_ENDIAN_BITFIELD */
3771 uint8_t mbxOwner:1; /* Low order bit first word */
3772 uint8_t mbxHc:1;
3773 uint8_t mbxReserved:6;
3774 uint8_t mbxCommand;
3775 uint16_t mbxStatus;
3776 #endif
3777 };
3778 u32 word0;
3779 };
3780 );
3781
3782 MAILVARIANTS un;
3783 union sli_var us;
3784 } MAILBOX_t;
3785
3786 /*
3787 * Begin Structure Definitions for IOCB Commands
3788 */
3789
3790 typedef struct {
3791 #ifdef __BIG_ENDIAN_BITFIELD
3792 uint8_t statAction;
3793 uint8_t statRsn;
3794 uint8_t statBaExp;
3795 uint8_t statLocalError;
3796 #else /* __LITTLE_ENDIAN_BITFIELD */
3797 uint8_t statLocalError;
3798 uint8_t statBaExp;
3799 uint8_t statRsn;
3800 uint8_t statAction;
3801 #endif
3802 /* statRsn P/F_RJT reason codes */
3803 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3804 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3805 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3806 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3807 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3808 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3809 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3810 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3811 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3812 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3813 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3814 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3815 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3816 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3817 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3818 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
3819 #define RJT_XCHG_ERR 0x11 /* Exchange error */
3820 #define RJT_PROT_ERR 0x12 /* Protocol error */
3821 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3822 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3823 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3824 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3825 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3826 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3827 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3828 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3829
3830 #define IOERR_SUCCESS 0x00 /* statLocalError */
3831 #define IOERR_MISSING_CONTINUE 0x01
3832 #define IOERR_SEQUENCE_TIMEOUT 0x02
3833 #define IOERR_INTERNAL_ERROR 0x03
3834 #define IOERR_INVALID_RPI 0x04
3835 #define IOERR_NO_XRI 0x05
3836 #define IOERR_ILLEGAL_COMMAND 0x06
3837 #define IOERR_XCHG_DROPPED 0x07
3838 #define IOERR_ILLEGAL_FIELD 0x08
3839 #define IOERR_RPI_SUSPENDED 0x09
3840 #define IOERR_TOO_MANY_BUFFERS 0x0A
3841 #define IOERR_RCV_BUFFER_WAITING 0x0B
3842 #define IOERR_NO_CONNECTION 0x0C
3843 #define IOERR_TX_DMA_FAILED 0x0D
3844 #define IOERR_RX_DMA_FAILED 0x0E
3845 #define IOERR_ILLEGAL_FRAME 0x0F
3846 #define IOERR_EXTRA_DATA 0x10
3847 #define IOERR_NO_RESOURCES 0x11
3848 #define IOERR_RESERVED 0x12
3849 #define IOERR_ILLEGAL_LENGTH 0x13
3850 #define IOERR_UNSUPPORTED_FEATURE 0x14
3851 #define IOERR_ABORT_IN_PROGRESS 0x15
3852 #define IOERR_ABORT_REQUESTED 0x16
3853 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3854 #define IOERR_LOOP_OPEN_FAILURE 0x18
3855 #define IOERR_RING_RESET 0x19
3856 #define IOERR_LINK_DOWN 0x1A
3857 #define IOERR_CORRUPTED_DATA 0x1B
3858 #define IOERR_CORRUPTED_RPI 0x1C
3859 #define IOERR_OUT_OF_ORDER_DATA 0x1D
3860 #define IOERR_OUT_OF_ORDER_ACK 0x1E
3861 #define IOERR_DUP_FRAME 0x1F
3862 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3863 #define IOERR_BAD_HOST_ADDRESS 0x21
3864 #define IOERR_RCV_HDRBUF_WAITING 0x22
3865 #define IOERR_MISSING_HDR_BUFFER 0x23
3866 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3867 #define IOERR_ABORTMULT_REQUESTED 0x25
3868 #define IOERR_BUFFER_SHORTAGE 0x28
3869 #define IOERR_DEFAULT 0x29
3870 #define IOERR_CNT 0x2A
3871 #define IOERR_SLER_FAILURE 0x46
3872 #define IOERR_SLER_CMD_RCV_FAILURE 0x47
3873 #define IOERR_SLER_REC_RJT_ERR 0x48
3874 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3875 #define IOERR_SLER_SRR_RJT_ERR 0x4A
3876 #define IOERR_SLER_RRQ_RJT_ERR 0x4C
3877 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3878 #define IOERR_SLER_ABTS_ERR 0x4E
3879 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3880 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3881 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3882 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3883 #define IOERR_DRVR_MASK 0x100
3884 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3885 #define IOERR_SLI_BRESET 0x102
3886 #define IOERR_SLI_ABORTED 0x103
3887 #define IOERR_PARAM_MASK 0x1ff
3888 } PARM_ERR;
3889
3890 typedef union {
3891 struct {
3892 #ifdef __BIG_ENDIAN_BITFIELD
3893 uint8_t Rctl; /* R_CTL field */
3894 uint8_t Type; /* TYPE field */
3895 uint8_t Dfctl; /* DF_CTL field */
3896 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3897 #else /* __LITTLE_ENDIAN_BITFIELD */
3898 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3899 uint8_t Dfctl; /* DF_CTL field */
3900 uint8_t Type; /* TYPE field */
3901 uint8_t Rctl; /* R_CTL field */
3902 #endif
3903
3904 #define BC 0x02 /* Broadcast Received - Fctl */
3905 #define SI 0x04 /* Sequence Initiative */
3906 #define LA 0x08 /* Ignore Link Attention state */
3907 #define LS 0x80 /* Last Sequence */
3908 } hcsw;
3909 uint32_t reserved;
3910 } WORD5;
3911
3912 /* IOCB Command template for a generic response */
3913 typedef struct {
3914 uint32_t reserved[4];
3915 PARM_ERR perr;
3916 } GENERIC_RSP;
3917
3918 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3919 typedef struct {
3920 struct ulp_bde xrsqbde[2];
3921 uint32_t xrsqRo; /* Starting Relative Offset */
3922 WORD5 w5; /* Header control/status word */
3923 } XR_SEQ_FIELDS;
3924
3925 /* IOCB Command template for ELS_REQUEST */
3926 typedef struct {
3927 struct ulp_bde elsReq;
3928 struct ulp_bde elsRsp;
3929
3930 #ifdef __BIG_ENDIAN_BITFIELD
3931 uint32_t word4Rsvd:7;
3932 uint32_t fl:1;
3933 uint32_t myID:24;
3934 uint32_t word5Rsvd:8;
3935 uint32_t remoteID:24;
3936 #else /* __LITTLE_ENDIAN_BITFIELD */
3937 uint32_t myID:24;
3938 uint32_t fl:1;
3939 uint32_t word4Rsvd:7;
3940 uint32_t remoteID:24;
3941 uint32_t word5Rsvd:8;
3942 #endif
3943 } ELS_REQUEST;
3944
3945 /* IOCB Command template for RCV_ELS_REQ */
3946 typedef struct {
3947 struct ulp_bde elsReq[2];
3948 uint32_t parmRo;
3949
3950 #ifdef __BIG_ENDIAN_BITFIELD
3951 uint32_t word5Rsvd:8;
3952 uint32_t remoteID:24;
3953 #else /* __LITTLE_ENDIAN_BITFIELD */
3954 uint32_t remoteID:24;
3955 uint32_t word5Rsvd:8;
3956 #endif
3957 } RCV_ELS_REQ;
3958
3959 /* IOCB Command template for ABORT / CLOSE_XRI */
3960 typedef struct {
3961 uint32_t rsvd[3];
3962 uint32_t abortType;
3963 #define ABORT_TYPE_ABTX 0x00000000
3964 #define ABORT_TYPE_ABTS 0x00000001
3965 uint32_t parm;
3966 #ifdef __BIG_ENDIAN_BITFIELD
3967 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3968 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3969 #else /* __LITTLE_ENDIAN_BITFIELD */
3970 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3971 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3972 #endif
3973 } AC_XRI;
3974
3975 /* IOCB Command template for ABORT_MXRI64 */
3976 typedef struct {
3977 uint32_t rsvd[3];
3978 uint32_t abortType;
3979 uint32_t parm;
3980 uint32_t iotag32;
3981 } A_MXRI64;
3982
3983 /* IOCB Command template for GET_RPI */
3984 typedef struct {
3985 uint32_t rsvd[4];
3986 uint32_t parmRo;
3987 #ifdef __BIG_ENDIAN_BITFIELD
3988 uint32_t word5Rsvd:8;
3989 uint32_t remoteID:24;
3990 #else /* __LITTLE_ENDIAN_BITFIELD */
3991 uint32_t remoteID:24;
3992 uint32_t word5Rsvd:8;
3993 #endif
3994 } GET_RPI;
3995
3996 /* IOCB Command template for all FCP Initiator commands */
3997 typedef struct {
3998 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3999 struct ulp_bde fcpi_rsp; /* Rcv buffer */
4000 uint32_t fcpi_parm;
4001 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
4002 } FCPI_FIELDS;
4003
4004 /* IOCB Command template for all FCP Target commands */
4005 typedef struct {
4006 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
4007 uint32_t fcpt_Offset;
4008 uint32_t fcpt_Length; /* transfer ready for IWRITE */
4009 } FCPT_FIELDS;
4010
4011 /* SLI-2 IOCB structure definitions */
4012
4013 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
4014 typedef struct {
4015 ULP_BDL bdl;
4016 uint32_t xrsqRo; /* Starting Relative Offset */
4017 WORD5 w5; /* Header control/status word */
4018 } XMT_SEQ_FIELDS64;
4019
4020 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
4021 #define xmit_els_remoteID xrsqRo
4022
4023 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
4024 typedef struct {
4025 struct ulp_bde64 rcvBde;
4026 uint32_t rsvd1;
4027 uint32_t xrsqRo; /* Starting Relative Offset */
4028 WORD5 w5; /* Header control/status word */
4029 } RCV_SEQ_FIELDS64;
4030
4031 /* IOCB Command template for ELS_REQUEST64 */
4032 typedef struct {
4033 ULP_BDL bdl;
4034 #ifdef __BIG_ENDIAN_BITFIELD
4035 uint32_t word4Rsvd:7;
4036 uint32_t fl:1;
4037 uint32_t myID:24;
4038 uint32_t word5Rsvd:8;
4039 uint32_t remoteID:24;
4040 #else /* __LITTLE_ENDIAN_BITFIELD */
4041 uint32_t myID:24;
4042 uint32_t fl:1;
4043 uint32_t word4Rsvd:7;
4044 uint32_t remoteID:24;
4045 uint32_t word5Rsvd:8;
4046 #endif
4047 } ELS_REQUEST64;
4048
4049 /* IOCB Command template for GEN_REQUEST64 */
4050 typedef struct {
4051 ULP_BDL bdl;
4052 uint32_t xrsqRo; /* Starting Relative Offset */
4053 WORD5 w5; /* Header control/status word */
4054 } GEN_REQUEST64;
4055
4056 /* IOCB Command template for RCV_ELS_REQ64 */
4057 typedef struct {
4058 struct ulp_bde64 elsReq;
4059 uint32_t rcvd1;
4060 uint32_t parmRo;
4061
4062 #ifdef __BIG_ENDIAN_BITFIELD
4063 uint32_t word5Rsvd:8;
4064 uint32_t remoteID:24;
4065 #else /* __LITTLE_ENDIAN_BITFIELD */
4066 uint32_t remoteID:24;
4067 uint32_t word5Rsvd:8;
4068 #endif
4069 } RCV_ELS_REQ64;
4070
4071 /* IOCB Command template for RCV_SEQ64 */
4072 struct rcv_seq64 {
4073 struct ulp_bde64 elsReq;
4074 uint32_t hbq_1;
4075 uint32_t parmRo;
4076 #ifdef __BIG_ENDIAN_BITFIELD
4077 uint32_t rctl:8;
4078 uint32_t type:8;
4079 uint32_t dfctl:8;
4080 uint32_t ls:1;
4081 uint32_t fs:1;
4082 uint32_t rsvd2:3;
4083 uint32_t si:1;
4084 uint32_t bc:1;
4085 uint32_t rsvd3:1;
4086 #else /* __LITTLE_ENDIAN_BITFIELD */
4087 uint32_t rsvd3:1;
4088 uint32_t bc:1;
4089 uint32_t si:1;
4090 uint32_t rsvd2:3;
4091 uint32_t fs:1;
4092 uint32_t ls:1;
4093 uint32_t dfctl:8;
4094 uint32_t type:8;
4095 uint32_t rctl:8;
4096 #endif
4097 };
4098
4099 /* IOCB Command template for all 64 bit FCP Initiator commands */
4100 typedef struct {
4101 ULP_BDL bdl;
4102 uint32_t fcpi_parm;
4103 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
4104 } FCPI_FIELDS64;
4105
4106 /* IOCB Command template for all 64 bit FCP Target commands */
4107 typedef struct {
4108 ULP_BDL bdl;
4109 uint32_t fcpt_Offset;
4110 uint32_t fcpt_Length; /* transfer ready for IWRITE */
4111 } FCPT_FIELDS64;
4112
4113 /* IOCB Command template for Async Status iocb commands */
4114 typedef struct {
4115 uint32_t rsvd[4];
4116 uint32_t param;
4117 #ifdef __BIG_ENDIAN_BITFIELD
4118 uint16_t evt_code; /* High order bits word 5 */
4119 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
4120 #else /* __LITTLE_ENDIAN_BITFIELD */
4121 uint16_t sub_ctxt_tag; /* High order bits word 5 */
4122 uint16_t evt_code; /* Low order bits word 5 */
4123 #endif
4124 } ASYNCSTAT_FIELDS;
4125 #define ASYNC_TEMP_WARN 0x100
4126 #define ASYNC_TEMP_SAFE 0x101
4127 #define ASYNC_STATUS_CN 0x102
4128
4129 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
4130 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
4131
4132 struct rcv_sli3 {
4133 #ifdef __BIG_ENDIAN_BITFIELD
4134 uint16_t ox_id;
4135 uint16_t seq_cnt;
4136
4137 uint16_t vpi;
4138 uint16_t word9Rsvd;
4139 #else /* __LITTLE_ENDIAN */
4140 uint16_t seq_cnt;
4141 uint16_t ox_id;
4142
4143 uint16_t word9Rsvd;
4144 uint16_t vpi;
4145 #endif
4146 uint32_t word10Rsvd;
4147 uint32_t acc_len; /* accumulated length */
4148 struct ulp_bde64 bde2;
4149 };
4150
4151 /* Structure used for a single HBQ entry */
4152 struct lpfc_hbq_entry {
4153 struct ulp_bde64 bde;
4154 uint32_t buffer_tag;
4155 };
4156
4157 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
4158 typedef struct {
4159 struct lpfc_hbq_entry buff;
4160 uint32_t rsvd;
4161 uint32_t rsvd1;
4162 } QUE_XRI64_CX_FIELDS;
4163
4164 struct que_xri64cx_ext_fields {
4165 uint32_t iotag64_low;
4166 uint32_t iotag64_high;
4167 uint32_t ebde_count;
4168 uint32_t rsvd;
4169 struct lpfc_hbq_entry buff[5];
4170 };
4171
4172 struct sli3_bg_fields {
4173 uint32_t filler[6]; /* word 8-13 in IOCB */
4174 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
4175 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
4176 #define BGS_BIDIR_BG_PROF_MASK 0xff000000
4177 #define BGS_BIDIR_BG_PROF_SHIFT 24
4178 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
4179 #define BGS_BIDIR_ERR_COND_SHIFT 16
4180 #define BGS_BG_PROFILE_MASK 0x0000ff00
4181 #define BGS_BG_PROFILE_SHIFT 8
4182 #define BGS_INVALID_PROF_MASK 0x00000020
4183 #define BGS_INVALID_PROF_SHIFT 5
4184 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
4185 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4
4186 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
4187 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
4188 #define BGS_REFTAG_ERR_MASK 0x00000004
4189 #define BGS_REFTAG_ERR_SHIFT 2
4190 #define BGS_APPTAG_ERR_MASK 0x00000002
4191 #define BGS_APPTAG_ERR_SHIFT 1
4192 #define BGS_GUARD_ERR_MASK 0x00000001
4193 #define BGS_GUARD_ERR_SHIFT 0
4194 uint32_t bgstat; /* word 15 - BlockGuard Status */
4195 };
4196
4197 static inline uint32_t
lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)4198 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
4199 {
4200 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
4201 BGS_BIDIR_BG_PROF_SHIFT;
4202 }
4203
4204 static inline uint32_t
lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)4205 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
4206 {
4207 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
4208 BGS_BIDIR_ERR_COND_SHIFT;
4209 }
4210
4211 static inline uint32_t
lpfc_bgs_get_bg_prof(uint32_t bgstat)4212 lpfc_bgs_get_bg_prof(uint32_t bgstat)
4213 {
4214 return (bgstat & BGS_BG_PROFILE_MASK) >>
4215 BGS_BG_PROFILE_SHIFT;
4216 }
4217
4218 static inline uint32_t
lpfc_bgs_get_invalid_prof(uint32_t bgstat)4219 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
4220 {
4221 return (bgstat & BGS_INVALID_PROF_MASK) >>
4222 BGS_INVALID_PROF_SHIFT;
4223 }
4224
4225 static inline uint32_t
lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)4226 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
4227 {
4228 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
4229 BGS_UNINIT_DIF_BLOCK_SHIFT;
4230 }
4231
4232 static inline uint32_t
lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)4233 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
4234 {
4235 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
4236 BGS_HI_WATER_MARK_PRESENT_SHIFT;
4237 }
4238
4239 static inline uint32_t
lpfc_bgs_get_reftag_err(uint32_t bgstat)4240 lpfc_bgs_get_reftag_err(uint32_t bgstat)
4241 {
4242 return (bgstat & BGS_REFTAG_ERR_MASK) >>
4243 BGS_REFTAG_ERR_SHIFT;
4244 }
4245
4246 static inline uint32_t
lpfc_bgs_get_apptag_err(uint32_t bgstat)4247 lpfc_bgs_get_apptag_err(uint32_t bgstat)
4248 {
4249 return (bgstat & BGS_APPTAG_ERR_MASK) >>
4250 BGS_APPTAG_ERR_SHIFT;
4251 }
4252
4253 static inline uint32_t
lpfc_bgs_get_guard_err(uint32_t bgstat)4254 lpfc_bgs_get_guard_err(uint32_t bgstat)
4255 {
4256 return (bgstat & BGS_GUARD_ERR_MASK) >>
4257 BGS_GUARD_ERR_SHIFT;
4258 }
4259
4260 #define LPFC_EXT_DATA_BDE_COUNT 3
4261 struct fcp_irw_ext {
4262 uint32_t io_tag64_low;
4263 uint32_t io_tag64_high;
4264 #ifdef __BIG_ENDIAN_BITFIELD
4265 uint8_t reserved1;
4266 uint8_t reserved2;
4267 uint8_t reserved3;
4268 uint8_t ebde_count;
4269 #else /* __LITTLE_ENDIAN */
4270 uint8_t ebde_count;
4271 uint8_t reserved3;
4272 uint8_t reserved2;
4273 uint8_t reserved1;
4274 #endif
4275 uint32_t reserved4;
4276 struct ulp_bde64 rbde; /* response bde */
4277 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
4278 uint8_t icd[32]; /* immediate command data (32 bytes) */
4279 };
4280
4281 typedef struct _IOCB { /* IOCB structure */
4282 union {
4283 GENERIC_RSP grsp; /* Generic response */
4284 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
4285 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
4286 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
4287 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
4288 A_MXRI64 amxri; /* abort multiple xri command overlay */
4289 GET_RPI getrpi; /* GET_RPI template */
4290 FCPI_FIELDS fcpi; /* FCP Initiator template */
4291 FCPT_FIELDS fcpt; /* FCP target template */
4292
4293 /* SLI-2 structures */
4294
4295 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
4296 * bde_64s */
4297 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
4298 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
4299 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
4300 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
4301 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
4302 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
4303 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
4304 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
4305 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
4306 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
4307 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
4308 } un;
4309 union {
4310 struct {
4311 #ifdef __BIG_ENDIAN_BITFIELD
4312 uint16_t ulpContext; /* High order bits word 6 */
4313 uint16_t ulpIoTag; /* Low order bits word 6 */
4314 #else /* __LITTLE_ENDIAN_BITFIELD */
4315 uint16_t ulpIoTag; /* Low order bits word 6 */
4316 uint16_t ulpContext; /* High order bits word 6 */
4317 #endif
4318 } t1;
4319 struct {
4320 #ifdef __BIG_ENDIAN_BITFIELD
4321 uint16_t ulpContext; /* High order bits word 6 */
4322 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4323 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4324 #else /* __LITTLE_ENDIAN_BITFIELD */
4325 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4326 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4327 uint16_t ulpContext; /* High order bits word 6 */
4328 #endif
4329 } t2;
4330 } un1;
4331 #define ulpContext un1.t1.ulpContext
4332 #define ulpIoTag un1.t1.ulpIoTag
4333 #define ulpIoTag0 un1.t2.ulpIoTag0
4334
4335 #ifdef __BIG_ENDIAN_BITFIELD
4336 uint32_t ulpTimeout:8;
4337 uint32_t ulpXS:1;
4338 uint32_t ulpFCP2Rcvy:1;
4339 uint32_t ulpPU:2;
4340 uint32_t ulpIr:1;
4341 uint32_t ulpClass:3;
4342 uint32_t ulpCommand:8;
4343 uint32_t ulpStatus:4;
4344 uint32_t ulpBdeCount:2;
4345 uint32_t ulpLe:1;
4346 uint32_t ulpOwner:1; /* Low order bit word 7 */
4347 #else /* __LITTLE_ENDIAN_BITFIELD */
4348 uint32_t ulpOwner:1; /* Low order bit word 7 */
4349 uint32_t ulpLe:1;
4350 uint32_t ulpBdeCount:2;
4351 uint32_t ulpStatus:4;
4352 uint32_t ulpCommand:8;
4353 uint32_t ulpClass:3;
4354 uint32_t ulpIr:1;
4355 uint32_t ulpPU:2;
4356 uint32_t ulpFCP2Rcvy:1;
4357 uint32_t ulpXS:1;
4358 uint32_t ulpTimeout:8;
4359 #endif
4360
4361 union {
4362 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
4363
4364 /* words 8-31 used for que_xri_cx iocb */
4365 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4366 struct fcp_irw_ext fcp_ext;
4367 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
4368
4369 /* words 8-15 for BlockGuard */
4370 struct sli3_bg_fields sli3_bg;
4371 } unsli3;
4372
4373 #define ulpCt_h ulpXS
4374 #define ulpCt_l ulpFCP2Rcvy
4375
4376 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
4377 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
4378 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
4379 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
4380 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
4381 #define PARM_NPIV_DID 3
4382 #define CLASS1 0 /* Class 1 */
4383 #define CLASS2 1 /* Class 2 */
4384 #define CLASS3 2 /* Class 3 */
4385 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
4386
4387 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
4388 #define IOSTAT_FCP_RSP_ERROR 0x1
4389 #define IOSTAT_REMOTE_STOP 0x2
4390 #define IOSTAT_LOCAL_REJECT 0x3
4391 #define IOSTAT_NPORT_RJT 0x4
4392 #define IOSTAT_FABRIC_RJT 0x5
4393 #define IOSTAT_NPORT_BSY 0x6
4394 #define IOSTAT_FABRIC_BSY 0x7
4395 #define IOSTAT_INTERMED_RSP 0x8
4396 #define IOSTAT_LS_RJT 0x9
4397 #define IOSTAT_BA_RJT 0xA
4398 #define IOSTAT_RSVD1 0xB
4399 #define IOSTAT_RSVD2 0xC
4400 #define IOSTAT_RSVD3 0xD
4401 #define IOSTAT_RSVD4 0xE
4402 #define IOSTAT_NEED_BUFFER 0xF
4403 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
4404 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
4405 #define IOSTAT_CNT 0x11
4406
4407 } IOCB_t;
4408
4409
4410 #define SLI1_SLIM_SIZE (4 * 1024)
4411
4412 /* Up to 498 IOCBs will fit into 16k
4413 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
4414 */
4415 #define SLI2_SLIM_SIZE (64 * 1024)
4416
4417 /* Maximum IOCBs that will fit in SLI2 slim */
4418 #define MAX_SLI2_IOCB 498
4419 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4420 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4421 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4422
4423 /* HBQ entries are 4 words each = 4k */
4424 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
4425 lpfc_sli_hbq_count())
4426
4427 struct lpfc_sli2_slim {
4428 MAILBOX_t mbx;
4429 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
4430 PCB_t pcb;
4431 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4432 };
4433
4434 /*
4435 * This function checks PCI device to allow special handling for LC HBAs.
4436 *
4437 * Parameters:
4438 * device : struct pci_dev 's device field
4439 *
4440 * return 1 => TRUE
4441 * 0 => FALSE
4442 */
4443 static inline int
lpfc_is_LC_HBA(unsigned short device)4444 lpfc_is_LC_HBA(unsigned short device)
4445 {
4446 if ((device == PCI_DEVICE_ID_TFLY) ||
4447 (device == PCI_DEVICE_ID_PFLY) ||
4448 (device == PCI_DEVICE_ID_LP101) ||
4449 (device == PCI_DEVICE_ID_BMID) ||
4450 (device == PCI_DEVICE_ID_BSMB) ||
4451 (device == PCI_DEVICE_ID_ZMID) ||
4452 (device == PCI_DEVICE_ID_ZSMB) ||
4453 (device == PCI_DEVICE_ID_SAT_MID) ||
4454 (device == PCI_DEVICE_ID_SAT_SMB) ||
4455 (device == PCI_DEVICE_ID_RFLY))
4456 return 1;
4457 else
4458 return 0;
4459 }
4460
4461 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
4462