1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief This is the parent TargetLowering class for hardware code gen
12 /// targets.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "AMDGPUISelLowering.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
32
33 using namespace llvm;
34
35 namespace {
36
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
39 private:
40 const Twine &Description;
41 const Function &Fn;
42
43 static int KindID;
44
getKindID()45 static int getKindID() {
46 if (KindID == 0)
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
48 return KindID;
49 }
50
51 public:
DiagnosticInfoUnsupported(const Function & Fn,const Twine & Desc,DiagnosticSeverity Severity=DS_Error)52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
55 Description(Desc),
56 Fn(Fn) { }
57
getFunction() const58 const Function &getFunction() const { return Fn; }
getDescription() const59 const Twine &getDescription() const { return Description; }
60
print(DiagnosticPrinter & DP) const61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
63 }
64
classof(const DiagnosticInfo * DI)65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
67 }
68 };
69
70 int DiagnosticInfoUnsupported::KindID = 0;
71 }
72
73
allocateStack(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
80
81 return true;
82 }
83
84 #include "AMDGPUGenCallingConv.inc"
85
86 // Find a larger type to do a load / store of a vector with.
getEquivalentMemType(LLVMContext & Ctx,EVT VT)87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
89 if (StoreSize <= 32)
90 return EVT::getIntegerVT(Ctx, StoreSize);
91
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
94 }
95
96 // Type for a vector that will be loaded to.
getEquivalentLoadRegType(LLVMContext & Ctx,EVT VT)97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
99 if (StoreSize <= 32)
100 return EVT::getIntegerVT(Ctx, 32);
101
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
103 }
104
AMDGPUTargetLowering(TargetMachine & TM)105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
106 TargetLowering(TM) {
107
108 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
109
110 setOperationAction(ISD::Constant, MVT::i32, Legal);
111 setOperationAction(ISD::Constant, MVT::i64, Legal);
112 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
114
115 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
116 setOperationAction(ISD::BRIND, MVT::Other, Expand);
117
118 // We need to custom lower some of the intrinsics
119 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
120
121 // Library functions. These default to Expand, but we have instructions
122 // for them.
123 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
124 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
125 setOperationAction(ISD::FPOW, MVT::f32, Legal);
126 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
127 setOperationAction(ISD::FABS, MVT::f32, Legal);
128 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
129 setOperationAction(ISD::FRINT, MVT::f32, Legal);
130 setOperationAction(ISD::FROUND, MVT::f32, Legal);
131 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
132
133 setOperationAction(ISD::FREM, MVT::f32, Custom);
134 setOperationAction(ISD::FREM, MVT::f64, Custom);
135
136 // Lower floating point store/load to integer store/load to reduce the number
137 // of patterns in tablegen.
138 setOperationAction(ISD::STORE, MVT::f32, Promote);
139 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
140
141 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
142 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
143
144 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
145 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
146
147 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
149
150 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
152
153 setOperationAction(ISD::STORE, MVT::f64, Promote);
154 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
155
156 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
157 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
158
159 // Custom lowering of vector stores is required for local address space
160 // stores.
161 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
162
163 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
164 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
165 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
166
167 // XXX: This can be change to Custom, once ExpandVectorStores can
168 // handle 64-bit stores.
169 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
170
171 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
172 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
173 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
174 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
175 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
176
177
178 setOperationAction(ISD::LOAD, MVT::f32, Promote);
179 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
180
181 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
182 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
183
184 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
185 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
186
187 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
189
190 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
192
193 setOperationAction(ISD::LOAD, MVT::f64, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
195
196 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
198
199 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
200 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
201 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
202 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
203 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
204 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
205 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
206 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
207 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
208 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
209
210 // There are no 64-bit extloads. These should be done as a 32-bit extload and
211 // an extension to 64-bit.
212 for (MVT VT : MVT::integer_valuetypes()) {
213 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
214 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
215 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
216 }
217
218 for (MVT VT : MVT::integer_vector_valuetypes()) {
219 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
220 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
221 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
222 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
223 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
224 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
225 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
226 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
227 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
228 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
229 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
230 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
231 }
232
233 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
234
235 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
236 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
237 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
238 setOperationAction(ISD::FRINT, MVT::f64, Custom);
239 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
240 }
241
242 if (!Subtarget->hasBFI()) {
243 // fcopysign can be done in a single instruction with BFI.
244 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
245 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
246 }
247
248 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
249
250 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
251 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
252 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
253 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
254
255 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
256 for (MVT VT : ScalarIntVTs) {
257 setOperationAction(ISD::SREM, VT, Expand);
258 setOperationAction(ISD::SDIV, VT, Expand);
259
260 // GPU does not have divrem function for signed or unsigned.
261 setOperationAction(ISD::SDIVREM, VT, Custom);
262 setOperationAction(ISD::UDIVREM, VT, Custom);
263
264 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
265 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
266 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
267
268 setOperationAction(ISD::BSWAP, VT, Expand);
269 setOperationAction(ISD::CTTZ, VT, Expand);
270 setOperationAction(ISD::CTLZ, VT, Expand);
271 }
272
273 if (!Subtarget->hasBCNT(32))
274 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
275
276 if (!Subtarget->hasBCNT(64))
277 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
278
279 // The hardware supports 32-bit ROTR, but not ROTL.
280 setOperationAction(ISD::ROTL, MVT::i32, Expand);
281 setOperationAction(ISD::ROTL, MVT::i64, Expand);
282 setOperationAction(ISD::ROTR, MVT::i64, Expand);
283
284 setOperationAction(ISD::MUL, MVT::i64, Expand);
285 setOperationAction(ISD::MULHU, MVT::i64, Expand);
286 setOperationAction(ISD::MULHS, MVT::i64, Expand);
287 setOperationAction(ISD::UDIV, MVT::i32, Expand);
288 setOperationAction(ISD::UREM, MVT::i32, Expand);
289 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
290 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
291 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
292 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
293 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
294
295 if (!Subtarget->hasFFBH())
296 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
297
298 if (!Subtarget->hasFFBL())
299 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
300
301 static const MVT::SimpleValueType VectorIntTypes[] = {
302 MVT::v2i32, MVT::v4i32
303 };
304
305 for (MVT VT : VectorIntTypes) {
306 // Expand the following operations for the current type by default.
307 setOperationAction(ISD::ADD, VT, Expand);
308 setOperationAction(ISD::AND, VT, Expand);
309 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
310 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
311 setOperationAction(ISD::MUL, VT, Expand);
312 setOperationAction(ISD::OR, VT, Expand);
313 setOperationAction(ISD::SHL, VT, Expand);
314 setOperationAction(ISD::SRA, VT, Expand);
315 setOperationAction(ISD::SRL, VT, Expand);
316 setOperationAction(ISD::ROTL, VT, Expand);
317 setOperationAction(ISD::ROTR, VT, Expand);
318 setOperationAction(ISD::SUB, VT, Expand);
319 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
320 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
321 setOperationAction(ISD::SDIV, VT, Expand);
322 setOperationAction(ISD::UDIV, VT, Expand);
323 setOperationAction(ISD::SREM, VT, Expand);
324 setOperationAction(ISD::UREM, VT, Expand);
325 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
326 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
327 setOperationAction(ISD::SDIVREM, VT, Custom);
328 setOperationAction(ISD::UDIVREM, VT, Custom);
329 setOperationAction(ISD::ADDC, VT, Expand);
330 setOperationAction(ISD::SUBC, VT, Expand);
331 setOperationAction(ISD::ADDE, VT, Expand);
332 setOperationAction(ISD::SUBE, VT, Expand);
333 setOperationAction(ISD::SELECT, VT, Expand);
334 setOperationAction(ISD::VSELECT, VT, Expand);
335 setOperationAction(ISD::SELECT_CC, VT, Expand);
336 setOperationAction(ISD::XOR, VT, Expand);
337 setOperationAction(ISD::BSWAP, VT, Expand);
338 setOperationAction(ISD::CTPOP, VT, Expand);
339 setOperationAction(ISD::CTTZ, VT, Expand);
340 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
341 setOperationAction(ISD::CTLZ, VT, Expand);
342 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
343 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
344 }
345
346 static const MVT::SimpleValueType FloatVectorTypes[] = {
347 MVT::v2f32, MVT::v4f32
348 };
349
350 for (MVT VT : FloatVectorTypes) {
351 setOperationAction(ISD::FABS, VT, Expand);
352 setOperationAction(ISD::FMINNUM, VT, Expand);
353 setOperationAction(ISD::FMAXNUM, VT, Expand);
354 setOperationAction(ISD::FADD, VT, Expand);
355 setOperationAction(ISD::FCEIL, VT, Expand);
356 setOperationAction(ISD::FCOS, VT, Expand);
357 setOperationAction(ISD::FDIV, VT, Expand);
358 setOperationAction(ISD::FEXP2, VT, Expand);
359 setOperationAction(ISD::FLOG2, VT, Expand);
360 setOperationAction(ISD::FREM, VT, Expand);
361 setOperationAction(ISD::FPOW, VT, Expand);
362 setOperationAction(ISD::FFLOOR, VT, Expand);
363 setOperationAction(ISD::FTRUNC, VT, Expand);
364 setOperationAction(ISD::FMUL, VT, Expand);
365 setOperationAction(ISD::FMA, VT, Expand);
366 setOperationAction(ISD::FRINT, VT, Expand);
367 setOperationAction(ISD::FNEARBYINT, VT, Expand);
368 setOperationAction(ISD::FSQRT, VT, Expand);
369 setOperationAction(ISD::FSIN, VT, Expand);
370 setOperationAction(ISD::FSUB, VT, Expand);
371 setOperationAction(ISD::FNEG, VT, Expand);
372 setOperationAction(ISD::SELECT, VT, Expand);
373 setOperationAction(ISD::VSELECT, VT, Expand);
374 setOperationAction(ISD::SELECT_CC, VT, Expand);
375 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
376 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
377 }
378
379 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
380 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
381
382 setTargetDAGCombine(ISD::MUL);
383 setTargetDAGCombine(ISD::SELECT);
384 setTargetDAGCombine(ISD::SELECT_CC);
385 setTargetDAGCombine(ISD::STORE);
386
387 setBooleanContents(ZeroOrNegativeOneBooleanContent);
388 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
389
390 setSchedulingPreference(Sched::RegPressure);
391 setJumpIsExpensive(true);
392
393 // SI at least has hardware support for floating point exceptions, but no way
394 // of using or handling them is implemented. They are also optional in OpenCL
395 // (Section 7.3)
396 setHasFloatingPointExceptions(false);
397
398 setSelectIsExpensive(false);
399 PredictableSelectIsExpensive = false;
400
401 // There are no integer divide instructions, and these expand to a pretty
402 // large sequence of instructions.
403 setIntDivIsCheap(false);
404 setPow2SDivIsCheap(false);
405 setFsqrtIsCheap(true);
406
407 // FIXME: Need to really handle these.
408 MaxStoresPerMemcpy = 4096;
409 MaxStoresPerMemmove = 4096;
410 MaxStoresPerMemset = 4096;
411 }
412
413 //===----------------------------------------------------------------------===//
414 // Target Information
415 //===----------------------------------------------------------------------===//
416
getVectorIdxTy() const417 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
418 return MVT::i32;
419 }
420
isSelectSupported(SelectSupportKind SelType) const421 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
422 return true;
423 }
424
425 // The backend supports 32 and 64 bit floating point immediates.
426 // FIXME: Why are we reporting vectors of FP immediates as legal?
isFPImmLegal(const APFloat & Imm,EVT VT) const427 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
428 EVT ScalarVT = VT.getScalarType();
429 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
430 }
431
432 // We don't want to shrink f64 / f32 constants.
ShouldShrinkFPConstant(EVT VT) const433 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
434 EVT ScalarVT = VT.getScalarType();
435 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
436 }
437
shouldReduceLoadWidth(SDNode * N,ISD::LoadExtType,EVT NewVT) const438 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
439 ISD::LoadExtType,
440 EVT NewVT) const {
441
442 unsigned NewSize = NewVT.getStoreSizeInBits();
443
444 // If we are reducing to a 32-bit load, this is always better.
445 if (NewSize == 32)
446 return true;
447
448 EVT OldVT = N->getValueType(0);
449 unsigned OldSize = OldVT.getStoreSizeInBits();
450
451 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
452 // extloads, so doing one requires using a buffer_load. In cases where we
453 // still couldn't use a scalar load, using the wider load shouldn't really
454 // hurt anything.
455
456 // If the old size already had to be an extload, there's no harm in continuing
457 // to reduce the width.
458 return (OldSize < 32);
459 }
460
isLoadBitCastBeneficial(EVT LoadTy,EVT CastTy) const461 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
462 EVT CastTy) const {
463 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
464 return true;
465
466 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
467 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
468
469 return ((LScalarSize <= CastScalarSize) ||
470 (CastScalarSize >= 32) ||
471 (LScalarSize < 32));
472 }
473
474 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
475 // profitable with the expansion for 64-bit since it's generally good to
476 // speculate things.
477 // FIXME: These should really have the size as a parameter.
isCheapToSpeculateCttz() const478 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
479 return true;
480 }
481
isCheapToSpeculateCtlz() const482 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
483 return true;
484 }
485
486 //===---------------------------------------------------------------------===//
487 // Target Properties
488 //===---------------------------------------------------------------------===//
489
isFAbsFree(EVT VT) const490 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
491 assert(VT.isFloatingPoint());
492 return VT == MVT::f32 || VT == MVT::f64;
493 }
494
isFNegFree(EVT VT) const495 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
496 assert(VT.isFloatingPoint());
497 return VT == MVT::f32 || VT == MVT::f64;
498 }
499
isTruncateFree(EVT Source,EVT Dest) const500 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
501 // Truncate is just accessing a subregister.
502 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
503 }
504
isTruncateFree(Type * Source,Type * Dest) const505 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
506 // Truncate is just accessing a subregister.
507 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
508 (Dest->getPrimitiveSizeInBits() % 32 == 0);
509 }
510
isZExtFree(Type * Src,Type * Dest) const511 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
512 const DataLayout *DL = getDataLayout();
513 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
514 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
515
516 return SrcSize == 32 && DestSize == 64;
517 }
518
isZExtFree(EVT Src,EVT Dest) const519 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
520 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
521 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
522 // this will enable reducing 64-bit operations the 32-bit, which is always
523 // good.
524 return Src == MVT::i32 && Dest == MVT::i64;
525 }
526
isZExtFree(SDValue Val,EVT VT2) const527 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
528 return isZExtFree(Val.getValueType(), VT2);
529 }
530
isNarrowingProfitable(EVT SrcVT,EVT DestVT) const531 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
532 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
533 // limited number of native 64-bit operations. Shrinking an operation to fit
534 // in a single 32-bit register should always be helpful. As currently used,
535 // this is much less general than the name suggests, and is only used in
536 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
537 // not profitable, and may actually be harmful.
538 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
539 }
540
541 //===---------------------------------------------------------------------===//
542 // TargetLowering Callbacks
543 //===---------------------------------------------------------------------===//
544
AnalyzeFormalArguments(CCState & State,const SmallVectorImpl<ISD::InputArg> & Ins) const545 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
546 const SmallVectorImpl<ISD::InputArg> &Ins) const {
547
548 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
549 }
550
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,SDLoc DL,SelectionDAG & DAG) const551 SDValue AMDGPUTargetLowering::LowerReturn(
552 SDValue Chain,
553 CallingConv::ID CallConv,
554 bool isVarArg,
555 const SmallVectorImpl<ISD::OutputArg> &Outs,
556 const SmallVectorImpl<SDValue> &OutVals,
557 SDLoc DL, SelectionDAG &DAG) const {
558 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
559 }
560
561 //===---------------------------------------------------------------------===//
562 // Target specific lowering
563 //===---------------------------------------------------------------------===//
564
LowerCall(CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const565 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
566 SmallVectorImpl<SDValue> &InVals) const {
567 SDValue Callee = CLI.Callee;
568 SelectionDAG &DAG = CLI.DAG;
569
570 const Function &Fn = *DAG.getMachineFunction().getFunction();
571
572 StringRef FuncName("<unknown>");
573
574 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
575 FuncName = G->getSymbol();
576 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
577 FuncName = G->getGlobal()->getName();
578
579 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
580 DAG.getContext()->diagnose(NoCalls);
581 return SDValue();
582 }
583
LowerOperation(SDValue Op,SelectionDAG & DAG) const584 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
585 SelectionDAG &DAG) const {
586 switch (Op.getOpcode()) {
587 default:
588 Op.getNode()->dump();
589 llvm_unreachable("Custom lowering code for this"
590 "instruction is not implemented yet!");
591 break;
592 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
593 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
594 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
595 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
596 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
597 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
598 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
599 case ISD::FREM: return LowerFREM(Op, DAG);
600 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
601 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
602 case ISD::FRINT: return LowerFRINT(Op, DAG);
603 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
604 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
605 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
606 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
607 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
608 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
609 }
610 return Op;
611 }
612
ReplaceNodeResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const613 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
614 SmallVectorImpl<SDValue> &Results,
615 SelectionDAG &DAG) const {
616 switch (N->getOpcode()) {
617 case ISD::SIGN_EXTEND_INREG:
618 // Different parts of legalization seem to interpret which type of
619 // sign_extend_inreg is the one to check for custom lowering. The extended
620 // from type is what really matters, but some places check for custom
621 // lowering of the result type. This results in trying to use
622 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
623 // nothing here and let the illegal result integer be handled normally.
624 return;
625 case ISD::LOAD: {
626 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
627 if (!Node)
628 return;
629
630 Results.push_back(SDValue(Node, 0));
631 Results.push_back(SDValue(Node, 1));
632 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
633 // function
634 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
635 return;
636 }
637 case ISD::STORE: {
638 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
639 if (Lowered.getNode())
640 Results.push_back(Lowered);
641 return;
642 }
643 default:
644 return;
645 }
646 }
647
648 // FIXME: This implements accesses to initialized globals in the constant
649 // address space by copying them to private and accessing that. It does not
650 // properly handle illegal types or vectors. The private vector loads are not
651 // scalarized, and the illegal scalars hit an assertion. This technique will not
652 // work well with large initializers, and this should eventually be
653 // removed. Initialized globals should be placed into a data section that the
654 // runtime will load into a buffer before the kernel is executed. Uses of the
655 // global need to be replaced with a pointer loaded from an implicit kernel
656 // argument into this buffer holding the copy of the data, which will remove the
657 // need for any of this.
LowerConstantInitializer(const Constant * Init,const GlobalValue * GV,const SDValue & InitPtr,SDValue Chain,SelectionDAG & DAG) const658 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
659 const GlobalValue *GV,
660 const SDValue &InitPtr,
661 SDValue Chain,
662 SelectionDAG &DAG) const {
663 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
664 SDLoc DL(InitPtr);
665 Type *InitTy = Init->getType();
666
667 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
668 EVT VT = EVT::getEVT(InitTy);
669 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
670 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
671 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
672 TD->getPrefTypeAlignment(InitTy));
673 }
674
675 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
676 EVT VT = EVT::getEVT(CFP->getType());
677 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
678 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
679 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
680 TD->getPrefTypeAlignment(CFP->getType()));
681 }
682
683 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
684 const StructLayout *SL = TD->getStructLayout(ST);
685
686 EVT PtrVT = InitPtr.getValueType();
687 SmallVector<SDValue, 8> Chains;
688
689 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
690 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
691 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
692
693 Constant *Elt = Init->getAggregateElement(I);
694 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
695 }
696
697 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
698 }
699
700 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
701 EVT PtrVT = InitPtr.getValueType();
702
703 unsigned NumElements;
704 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
705 NumElements = AT->getNumElements();
706 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
707 NumElements = VT->getNumElements();
708 else
709 llvm_unreachable("Unexpected type");
710
711 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
712 SmallVector<SDValue, 8> Chains;
713 for (unsigned i = 0; i < NumElements; ++i) {
714 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
715 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
716
717 Constant *Elt = Init->getAggregateElement(i);
718 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
719 }
720
721 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
722 }
723
724 if (isa<UndefValue>(Init)) {
725 EVT VT = EVT::getEVT(InitTy);
726 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
727 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
728 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
729 TD->getPrefTypeAlignment(InitTy));
730 }
731
732 Init->dump();
733 llvm_unreachable("Unhandled constant initializer");
734 }
735
hasDefinedInitializer(const GlobalValue * GV)736 static bool hasDefinedInitializer(const GlobalValue *GV) {
737 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
738 if (!GVar || !GVar->hasInitializer())
739 return false;
740
741 if (isa<UndefValue>(GVar->getInitializer()))
742 return false;
743
744 return true;
745 }
746
LowerGlobalAddress(AMDGPUMachineFunction * MFI,SDValue Op,SelectionDAG & DAG) const747 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
748 SDValue Op,
749 SelectionDAG &DAG) const {
750
751 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
752 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
753 const GlobalValue *GV = G->getGlobal();
754
755 switch (G->getAddressSpace()) {
756 case AMDGPUAS::LOCAL_ADDRESS: {
757 // XXX: What does the value of G->getOffset() mean?
758 assert(G->getOffset() == 0 &&
759 "Do not know what to do with an non-zero offset");
760
761 // TODO: We could emit code to handle the initialization somewhere.
762 if (hasDefinedInitializer(GV))
763 break;
764
765 unsigned Offset;
766 if (MFI->LocalMemoryObjects.count(GV) == 0) {
767 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
768 Offset = MFI->LDSSize;
769 MFI->LocalMemoryObjects[GV] = Offset;
770 // XXX: Account for alignment?
771 MFI->LDSSize += Size;
772 } else {
773 Offset = MFI->LocalMemoryObjects[GV];
774 }
775
776 return DAG.getConstant(Offset, getPointerTy(AMDGPUAS::LOCAL_ADDRESS));
777 }
778 case AMDGPUAS::CONSTANT_ADDRESS: {
779 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
780 Type *EltType = GV->getType()->getElementType();
781 unsigned Size = TD->getTypeAllocSize(EltType);
782 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
783
784 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
785 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
786
787 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
788 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
789
790 const GlobalVariable *Var = cast<GlobalVariable>(GV);
791 if (!Var->hasInitializer()) {
792 // This has no use, but bugpoint will hit it.
793 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
794 }
795
796 const Constant *Init = Var->getInitializer();
797 SmallVector<SDNode*, 8> WorkList;
798
799 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
800 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
801 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
802 continue;
803 WorkList.push_back(*I);
804 }
805 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
806 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
807 E = WorkList.end(); I != E; ++I) {
808 SmallVector<SDValue, 8> Ops;
809 Ops.push_back(Chain);
810 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
811 Ops.push_back((*I)->getOperand(i));
812 }
813 DAG.UpdateNodeOperands(*I, Ops);
814 }
815 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
816 }
817 }
818
819 const Function &Fn = *DAG.getMachineFunction().getFunction();
820 DiagnosticInfoUnsupported BadInit(Fn,
821 "initializer for address space");
822 DAG.getContext()->diagnose(BadInit);
823 return SDValue();
824 }
825
LowerCONCAT_VECTORS(SDValue Op,SelectionDAG & DAG) const826 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
827 SelectionDAG &DAG) const {
828 SmallVector<SDValue, 8> Args;
829
830 for (const SDUse &U : Op->ops())
831 DAG.ExtractVectorElements(U.get(), Args);
832
833 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
834 }
835
LowerEXTRACT_SUBVECTOR(SDValue Op,SelectionDAG & DAG) const836 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
837 SelectionDAG &DAG) const {
838
839 SmallVector<SDValue, 8> Args;
840 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
841 EVT VT = Op.getValueType();
842 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
843 VT.getVectorNumElements());
844
845 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
846 }
847
LowerFrameIndex(SDValue Op,SelectionDAG & DAG) const848 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
849 SelectionDAG &DAG) const {
850
851 MachineFunction &MF = DAG.getMachineFunction();
852 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
853 getTargetMachine().getSubtargetImpl()->getFrameLowering());
854
855 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
856
857 unsigned FrameIndex = FIN->getIndex();
858 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
859 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
860 Op.getValueType());
861 }
862
LowerINTRINSIC_WO_CHAIN(SDValue Op,SelectionDAG & DAG) const863 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
864 SelectionDAG &DAG) const {
865 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
866 SDLoc DL(Op);
867 EVT VT = Op.getValueType();
868
869 switch (IntrinsicID) {
870 default: return Op;
871 case AMDGPUIntrinsic::AMDGPU_abs:
872 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
873 return LowerIntrinsicIABS(Op, DAG);
874 case AMDGPUIntrinsic::AMDGPU_lrp:
875 return LowerIntrinsicLRP(Op, DAG);
876
877 case AMDGPUIntrinsic::AMDGPU_clamp:
878 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
879 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
880 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
881
882 case Intrinsic::AMDGPU_div_scale: {
883 // 3rd parameter required to be a constant.
884 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
885 if (!Param)
886 return DAG.getUNDEF(VT);
887
888 // Translate to the operands expected by the machine instruction. The
889 // first parameter must be the same as the first instruction.
890 SDValue Numerator = Op.getOperand(1);
891 SDValue Denominator = Op.getOperand(2);
892
893 // Note this order is opposite of the machine instruction's operations,
894 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
895 // intrinsic has the numerator as the first operand to match a normal
896 // division operation.
897
898 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
899
900 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
901 Denominator, Numerator);
902 }
903
904 case Intrinsic::AMDGPU_div_fmas:
905 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
906 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
907 Op.getOperand(4));
908
909 case Intrinsic::AMDGPU_div_fixup:
910 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
911 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
912
913 case Intrinsic::AMDGPU_trig_preop:
914 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
915 Op.getOperand(1), Op.getOperand(2));
916
917 case Intrinsic::AMDGPU_rcp:
918 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
919
920 case Intrinsic::AMDGPU_rsq:
921 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
922
923 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
924 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
925
926 case Intrinsic::AMDGPU_rsq_clamped:
927 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
928 Type *Type = VT.getTypeForEVT(*DAG.getContext());
929 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
930 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
931
932 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
933 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
934 DAG.getConstantFP(Max, VT));
935 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
936 DAG.getConstantFP(Min, VT));
937 } else {
938 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
939 }
940
941 case Intrinsic::AMDGPU_ldexp:
942 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
943 Op.getOperand(2));
944
945 case AMDGPUIntrinsic::AMDGPU_imax:
946 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
947 Op.getOperand(2));
948 case AMDGPUIntrinsic::AMDGPU_umax:
949 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
950 Op.getOperand(2));
951 case AMDGPUIntrinsic::AMDGPU_imin:
952 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
953 Op.getOperand(2));
954 case AMDGPUIntrinsic::AMDGPU_umin:
955 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
956 Op.getOperand(2));
957
958 case AMDGPUIntrinsic::AMDGPU_umul24:
959 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
960 Op.getOperand(1), Op.getOperand(2));
961
962 case AMDGPUIntrinsic::AMDGPU_imul24:
963 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
964 Op.getOperand(1), Op.getOperand(2));
965
966 case AMDGPUIntrinsic::AMDGPU_umad24:
967 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
968 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
969
970 case AMDGPUIntrinsic::AMDGPU_imad24:
971 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
972 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
973
974 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
975 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
976
977 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
978 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
979
980 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
981 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
982
983 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
984 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
985
986 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
987 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
988 Op.getOperand(1),
989 Op.getOperand(2),
990 Op.getOperand(3));
991
992 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
993 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
994 Op.getOperand(1),
995 Op.getOperand(2),
996 Op.getOperand(3));
997
998 case AMDGPUIntrinsic::AMDGPU_bfi:
999 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
1000 Op.getOperand(1),
1001 Op.getOperand(2),
1002 Op.getOperand(3));
1003
1004 case AMDGPUIntrinsic::AMDGPU_bfm:
1005 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1006 Op.getOperand(1),
1007 Op.getOperand(2));
1008
1009 case AMDGPUIntrinsic::AMDGPU_brev:
1010 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
1011
1012 case Intrinsic::AMDGPU_class:
1013 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1014 Op.getOperand(1), Op.getOperand(2));
1015
1016 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1017 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1018
1019 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1020 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1021 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1022 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1023 }
1024 }
1025
1026 ///IABS(a) = SMAX(sub(0, a), a)
LowerIntrinsicIABS(SDValue Op,SelectionDAG & DAG) const1027 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1028 SelectionDAG &DAG) const {
1029 SDLoc DL(Op);
1030 EVT VT = Op.getValueType();
1031 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1032 Op.getOperand(1));
1033
1034 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1035 }
1036
1037 /// Linear Interpolation
1038 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
LowerIntrinsicLRP(SDValue Op,SelectionDAG & DAG) const1039 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1040 SelectionDAG &DAG) const {
1041 SDLoc DL(Op);
1042 EVT VT = Op.getValueType();
1043 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1044 DAG.getConstantFP(1.0f, MVT::f32),
1045 Op.getOperand(1));
1046 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1047 Op.getOperand(3));
1048 return DAG.getNode(ISD::FADD, DL, VT,
1049 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1050 OneSubAC);
1051 }
1052
1053 /// \brief Generate Min/Max node
CombineFMinMaxLegacy(SDLoc DL,EVT VT,SDValue LHS,SDValue RHS,SDValue True,SDValue False,SDValue CC,DAGCombinerInfo & DCI) const1054 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1055 EVT VT,
1056 SDValue LHS,
1057 SDValue RHS,
1058 SDValue True,
1059 SDValue False,
1060 SDValue CC,
1061 DAGCombinerInfo &DCI) const {
1062 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1063 return SDValue();
1064
1065 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1066 return SDValue();
1067
1068 SelectionDAG &DAG = DCI.DAG;
1069 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1070 switch (CCOpcode) {
1071 case ISD::SETOEQ:
1072 case ISD::SETONE:
1073 case ISD::SETUNE:
1074 case ISD::SETNE:
1075 case ISD::SETUEQ:
1076 case ISD::SETEQ:
1077 case ISD::SETFALSE:
1078 case ISD::SETFALSE2:
1079 case ISD::SETTRUE:
1080 case ISD::SETTRUE2:
1081 case ISD::SETUO:
1082 case ISD::SETO:
1083 break;
1084 case ISD::SETULE:
1085 case ISD::SETULT: {
1086 if (LHS == True)
1087 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1088 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1089 }
1090 case ISD::SETOLE:
1091 case ISD::SETOLT:
1092 case ISD::SETLE:
1093 case ISD::SETLT: {
1094 // Ordered. Assume ordered for undefined.
1095
1096 // Only do this after legalization to avoid interfering with other combines
1097 // which might occur.
1098 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1099 !DCI.isCalledByLegalizer())
1100 return SDValue();
1101
1102 // We need to permute the operands to get the correct NaN behavior. The
1103 // selected operand is the second one based on the failing compare with NaN,
1104 // so permute it based on the compare type the hardware uses.
1105 if (LHS == True)
1106 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1107 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1108 }
1109 case ISD::SETUGE:
1110 case ISD::SETUGT: {
1111 if (LHS == True)
1112 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1113 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1114 }
1115 case ISD::SETGT:
1116 case ISD::SETGE:
1117 case ISD::SETOGE:
1118 case ISD::SETOGT: {
1119 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1120 !DCI.isCalledByLegalizer())
1121 return SDValue();
1122
1123 if (LHS == True)
1124 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1125 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1126 }
1127 case ISD::SETCC_INVALID:
1128 llvm_unreachable("Invalid setcc condcode!");
1129 }
1130 return SDValue();
1131 }
1132
1133 /// \brief Generate Min/Max node
CombineIMinMax(SDLoc DL,EVT VT,SDValue LHS,SDValue RHS,SDValue True,SDValue False,SDValue CC,SelectionDAG & DAG) const1134 SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL,
1135 EVT VT,
1136 SDValue LHS,
1137 SDValue RHS,
1138 SDValue True,
1139 SDValue False,
1140 SDValue CC,
1141 SelectionDAG &DAG) const {
1142 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1143 return SDValue();
1144
1145 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1146 switch (CCOpcode) {
1147 case ISD::SETULE:
1148 case ISD::SETULT: {
1149 unsigned Opc = (LHS == True) ? AMDGPUISD::UMIN : AMDGPUISD::UMAX;
1150 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1151 }
1152 case ISD::SETLE:
1153 case ISD::SETLT: {
1154 unsigned Opc = (LHS == True) ? AMDGPUISD::SMIN : AMDGPUISD::SMAX;
1155 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1156 }
1157 case ISD::SETGT:
1158 case ISD::SETGE: {
1159 unsigned Opc = (LHS == True) ? AMDGPUISD::SMAX : AMDGPUISD::SMIN;
1160 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1161 }
1162 case ISD::SETUGE:
1163 case ISD::SETUGT: {
1164 unsigned Opc = (LHS == True) ? AMDGPUISD::UMAX : AMDGPUISD::UMIN;
1165 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1166 }
1167 default:
1168 return SDValue();
1169 }
1170 }
1171
ScalarizeVectorLoad(const SDValue Op,SelectionDAG & DAG) const1172 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1173 SelectionDAG &DAG) const {
1174 LoadSDNode *Load = cast<LoadSDNode>(Op);
1175 EVT MemVT = Load->getMemoryVT();
1176 EVT MemEltVT = MemVT.getVectorElementType();
1177
1178 EVT LoadVT = Op.getValueType();
1179 EVT EltVT = LoadVT.getVectorElementType();
1180 EVT PtrVT = Load->getBasePtr().getValueType();
1181
1182 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1183 SmallVector<SDValue, 8> Loads;
1184 SmallVector<SDValue, 8> Chains;
1185
1186 SDLoc SL(Op);
1187 unsigned MemEltSize = MemEltVT.getStoreSize();
1188 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1189
1190 for (unsigned i = 0; i < NumElts; ++i) {
1191 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1192 DAG.getConstant(i * MemEltSize, PtrVT));
1193
1194 SDValue NewLoad
1195 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1196 Load->getChain(), Ptr,
1197 SrcValue.getWithOffset(i * MemEltSize),
1198 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1199 Load->isInvariant(), Load->getAlignment());
1200 Loads.push_back(NewLoad.getValue(0));
1201 Chains.push_back(NewLoad.getValue(1));
1202 }
1203
1204 SDValue Ops[] = {
1205 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1206 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1207 };
1208
1209 return DAG.getMergeValues(Ops, SL);
1210 }
1211
SplitVectorLoad(const SDValue Op,SelectionDAG & DAG) const1212 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1213 SelectionDAG &DAG) const {
1214 EVT VT = Op.getValueType();
1215
1216 // If this is a 2 element vector, we really want to scalarize and not create
1217 // weird 1 element vectors.
1218 if (VT.getVectorNumElements() == 2)
1219 return ScalarizeVectorLoad(Op, DAG);
1220
1221 LoadSDNode *Load = cast<LoadSDNode>(Op);
1222 SDValue BasePtr = Load->getBasePtr();
1223 EVT PtrVT = BasePtr.getValueType();
1224 EVT MemVT = Load->getMemoryVT();
1225 SDLoc SL(Op);
1226 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1227
1228 EVT LoVT, HiVT;
1229 EVT LoMemVT, HiMemVT;
1230 SDValue Lo, Hi;
1231
1232 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1233 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1234 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1235 SDValue LoLoad
1236 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1237 Load->getChain(), BasePtr,
1238 SrcValue,
1239 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1240 Load->isInvariant(), Load->getAlignment());
1241
1242 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1243 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1244
1245 SDValue HiLoad
1246 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1247 Load->getChain(), HiPtr,
1248 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1249 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1250 Load->isInvariant(), Load->getAlignment());
1251
1252 SDValue Ops[] = {
1253 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1254 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1255 LoLoad.getValue(1), HiLoad.getValue(1))
1256 };
1257
1258 return DAG.getMergeValues(Ops, SL);
1259 }
1260
MergeVectorStore(const SDValue & Op,SelectionDAG & DAG) const1261 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1262 SelectionDAG &DAG) const {
1263 StoreSDNode *Store = cast<StoreSDNode>(Op);
1264 EVT MemVT = Store->getMemoryVT();
1265 unsigned MemBits = MemVT.getSizeInBits();
1266
1267 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1268 // truncating store into an i32 store.
1269 // XXX: We could also handle optimize other vector bitwidths.
1270 if (!MemVT.isVector() || MemBits > 32) {
1271 return SDValue();
1272 }
1273
1274 SDLoc DL(Op);
1275 SDValue Value = Store->getValue();
1276 EVT VT = Value.getValueType();
1277 EVT ElemVT = VT.getVectorElementType();
1278 SDValue Ptr = Store->getBasePtr();
1279 EVT MemEltVT = MemVT.getVectorElementType();
1280 unsigned MemEltBits = MemEltVT.getSizeInBits();
1281 unsigned MemNumElements = MemVT.getVectorNumElements();
1282 unsigned PackedSize = MemVT.getStoreSizeInBits();
1283 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1284
1285 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1286
1287 SDValue PackedValue;
1288 for (unsigned i = 0; i < MemNumElements; ++i) {
1289 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1290 DAG.getConstant(i, MVT::i32));
1291 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1292 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1293
1294 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1295 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1296
1297 if (i == 0) {
1298 PackedValue = Elt;
1299 } else {
1300 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1301 }
1302 }
1303
1304 if (PackedSize < 32) {
1305 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1306 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1307 Store->getMemOperand()->getPointerInfo(),
1308 PackedVT,
1309 Store->isNonTemporal(), Store->isVolatile(),
1310 Store->getAlignment());
1311 }
1312
1313 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1314 Store->getMemOperand()->getPointerInfo(),
1315 Store->isVolatile(), Store->isNonTemporal(),
1316 Store->getAlignment());
1317 }
1318
ScalarizeVectorStore(SDValue Op,SelectionDAG & DAG) const1319 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1320 SelectionDAG &DAG) const {
1321 StoreSDNode *Store = cast<StoreSDNode>(Op);
1322 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1323 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1324 EVT PtrVT = Store->getBasePtr().getValueType();
1325 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1326 SDLoc SL(Op);
1327
1328 SmallVector<SDValue, 8> Chains;
1329
1330 unsigned EltSize = MemEltVT.getStoreSize();
1331 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1332
1333 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1334 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1335 Store->getValue(),
1336 DAG.getConstant(i, MVT::i32));
1337
1338 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), PtrVT);
1339 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1340 SDValue NewStore =
1341 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1342 SrcValue.getWithOffset(i * EltSize),
1343 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1344 Store->getAlignment());
1345 Chains.push_back(NewStore);
1346 }
1347
1348 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1349 }
1350
SplitVectorStore(SDValue Op,SelectionDAG & DAG) const1351 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1352 SelectionDAG &DAG) const {
1353 StoreSDNode *Store = cast<StoreSDNode>(Op);
1354 SDValue Val = Store->getValue();
1355 EVT VT = Val.getValueType();
1356
1357 // If this is a 2 element vector, we really want to scalarize and not create
1358 // weird 1 element vectors.
1359 if (VT.getVectorNumElements() == 2)
1360 return ScalarizeVectorStore(Op, DAG);
1361
1362 EVT MemVT = Store->getMemoryVT();
1363 SDValue Chain = Store->getChain();
1364 SDValue BasePtr = Store->getBasePtr();
1365 SDLoc SL(Op);
1366
1367 EVT LoVT, HiVT;
1368 EVT LoMemVT, HiMemVT;
1369 SDValue Lo, Hi;
1370
1371 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1372 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1373 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1374
1375 EVT PtrVT = BasePtr.getValueType();
1376 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1377 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1378
1379 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1380 SDValue LoStore
1381 = DAG.getTruncStore(Chain, SL, Lo,
1382 BasePtr,
1383 SrcValue,
1384 LoMemVT,
1385 Store->isNonTemporal(),
1386 Store->isVolatile(),
1387 Store->getAlignment());
1388 SDValue HiStore
1389 = DAG.getTruncStore(Chain, SL, Hi,
1390 HiPtr,
1391 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1392 HiMemVT,
1393 Store->isNonTemporal(),
1394 Store->isVolatile(),
1395 Store->getAlignment());
1396
1397 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1398 }
1399
1400
LowerLOAD(SDValue Op,SelectionDAG & DAG) const1401 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1402 SDLoc DL(Op);
1403 LoadSDNode *Load = cast<LoadSDNode>(Op);
1404 ISD::LoadExtType ExtType = Load->getExtensionType();
1405 EVT VT = Op.getValueType();
1406 EVT MemVT = Load->getMemoryVT();
1407
1408 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1409 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1410 // FIXME: Copied from PPC
1411 // First, load into 32 bits, then truncate to 1 bit.
1412
1413 SDValue Chain = Load->getChain();
1414 SDValue BasePtr = Load->getBasePtr();
1415 MachineMemOperand *MMO = Load->getMemOperand();
1416
1417 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1418 BasePtr, MVT::i8, MMO);
1419
1420 SDValue Ops[] = {
1421 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1422 NewLD.getValue(1)
1423 };
1424
1425 return DAG.getMergeValues(Ops, DL);
1426 }
1427
1428 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1429 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1430 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1431 return SDValue();
1432
1433
1434 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1435 DAG.getConstant(2, MVT::i32));
1436 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1437 Load->getChain(), Ptr,
1438 DAG.getTargetConstant(0, MVT::i32),
1439 Op.getOperand(2));
1440 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1441 Load->getBasePtr(),
1442 DAG.getConstant(0x3, MVT::i32));
1443 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1444 DAG.getConstant(3, MVT::i32));
1445
1446 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1447
1448 EVT MemEltVT = MemVT.getScalarType();
1449 if (ExtType == ISD::SEXTLOAD) {
1450 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1451
1452 SDValue Ops[] = {
1453 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1454 Load->getChain()
1455 };
1456
1457 return DAG.getMergeValues(Ops, DL);
1458 }
1459
1460 SDValue Ops[] = {
1461 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1462 Load->getChain()
1463 };
1464
1465 return DAG.getMergeValues(Ops, DL);
1466 }
1467
LowerSTORE(SDValue Op,SelectionDAG & DAG) const1468 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1469 SDLoc DL(Op);
1470 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1471 if (Result.getNode()) {
1472 return Result;
1473 }
1474
1475 StoreSDNode *Store = cast<StoreSDNode>(Op);
1476 SDValue Chain = Store->getChain();
1477 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1478 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1479 Store->getValue().getValueType().isVector()) {
1480 return ScalarizeVectorStore(Op, DAG);
1481 }
1482
1483 EVT MemVT = Store->getMemoryVT();
1484 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1485 MemVT.bitsLT(MVT::i32)) {
1486 unsigned Mask = 0;
1487 if (Store->getMemoryVT() == MVT::i8) {
1488 Mask = 0xff;
1489 } else if (Store->getMemoryVT() == MVT::i16) {
1490 Mask = 0xffff;
1491 }
1492 SDValue BasePtr = Store->getBasePtr();
1493 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1494 DAG.getConstant(2, MVT::i32));
1495 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1496 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1497
1498 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1499 DAG.getConstant(0x3, MVT::i32));
1500
1501 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1502 DAG.getConstant(3, MVT::i32));
1503
1504 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1505 Store->getValue());
1506
1507 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1508
1509 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1510 MaskedValue, ShiftAmt);
1511
1512 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1513 ShiftAmt);
1514 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1515 DAG.getConstant(0xffffffff, MVT::i32));
1516 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1517
1518 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1519 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1520 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1521 }
1522 return SDValue();
1523 }
1524
1525 // This is a shortcut for integer division because we have fast i32<->f32
1526 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1527 // float is enough to accurately represent up to a 24-bit integer.
LowerDIVREM24(SDValue Op,SelectionDAG & DAG,bool sign) const1528 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1529 SDLoc DL(Op);
1530 EVT VT = Op.getValueType();
1531 SDValue LHS = Op.getOperand(0);
1532 SDValue RHS = Op.getOperand(1);
1533 MVT IntVT = MVT::i32;
1534 MVT FltVT = MVT::f32;
1535
1536 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1537 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1538
1539 if (VT.isVector()) {
1540 unsigned NElts = VT.getVectorNumElements();
1541 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1542 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1543 }
1544
1545 unsigned BitSize = VT.getScalarType().getSizeInBits();
1546
1547 SDValue jq = DAG.getConstant(1, IntVT);
1548
1549 if (sign) {
1550 // char|short jq = ia ^ ib;
1551 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1552
1553 // jq = jq >> (bitsize - 2)
1554 jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
1555
1556 // jq = jq | 0x1
1557 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
1558
1559 // jq = (int)jq
1560 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1561 }
1562
1563 // int ia = (int)LHS;
1564 SDValue ia = sign ?
1565 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1566
1567 // int ib, (int)RHS;
1568 SDValue ib = sign ?
1569 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1570
1571 // float fa = (float)ia;
1572 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1573
1574 // float fb = (float)ib;
1575 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1576
1577 // float fq = native_divide(fa, fb);
1578 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1579 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1580
1581 // fq = trunc(fq);
1582 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1583
1584 // float fqneg = -fq;
1585 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1586
1587 // float fr = mad(fqneg, fb, fa);
1588 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1589 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1590
1591 // int iq = (int)fq;
1592 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1593
1594 // fr = fabs(fr);
1595 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1596
1597 // fb = fabs(fb);
1598 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1599
1600 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), VT);
1601
1602 // int cv = fr >= fb;
1603 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1604
1605 // jq = (cv ? jq : 0);
1606 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
1607
1608 // dst = trunc/extend to legal type
1609 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1610
1611 // dst = iq + jq;
1612 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1613
1614 // Rem needs compensation, it's easier to recompute it
1615 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1616 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1617
1618 SDValue Res[2] = {
1619 Div,
1620 Rem
1621 };
1622 return DAG.getMergeValues(Res, DL);
1623 }
1624
LowerUDIVREM64(SDValue Op,SelectionDAG & DAG,SmallVectorImpl<SDValue> & Results) const1625 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1626 SelectionDAG &DAG,
1627 SmallVectorImpl<SDValue> &Results) const {
1628 assert(Op.getValueType() == MVT::i64);
1629
1630 SDLoc DL(Op);
1631 EVT VT = Op.getValueType();
1632 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1633
1634 SDValue one = DAG.getConstant(1, HalfVT);
1635 SDValue zero = DAG.getConstant(0, HalfVT);
1636
1637 //HiLo split
1638 SDValue LHS = Op.getOperand(0);
1639 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1640 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1641
1642 SDValue RHS = Op.getOperand(1);
1643 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1644 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1645
1646 // Get Speculative values
1647 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1648 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1649
1650 SDValue REM_Hi = zero;
1651 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1652
1653 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1654 SDValue DIV_Lo = zero;
1655
1656 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1657
1658 for (unsigned i = 0; i < halfBitWidth; ++i) {
1659 SDValue POS = DAG.getConstant(halfBitWidth - i - 1, HalfVT);
1660 // Get Value of high bit
1661 SDValue HBit;
1662 if (halfBitWidth == 32 && Subtarget->hasBFE()) {
1663 HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
1664 } else {
1665 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1666 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1667 }
1668
1669 SDValue Carry = DAG.getNode(ISD::SRL, DL, HalfVT, REM_Lo,
1670 DAG.getConstant(halfBitWidth - 1, HalfVT));
1671 REM_Hi = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Hi, one);
1672 REM_Hi = DAG.getNode(ISD::OR, DL, HalfVT, REM_Hi, Carry);
1673
1674 REM_Lo = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Lo, one);
1675 REM_Lo = DAG.getNode(ISD::OR, DL, HalfVT, REM_Lo, HBit);
1676
1677
1678 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
1679
1680 SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
1681 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1682
1683 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1684
1685 // Update REM
1686
1687 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1688
1689 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1690 REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
1691 REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
1692 }
1693
1694 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
1695 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1696 Results.push_back(DIV);
1697 Results.push_back(REM);
1698 }
1699
LowerUDIVREM(SDValue Op,SelectionDAG & DAG) const1700 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1701 SelectionDAG &DAG) const {
1702 SDLoc DL(Op);
1703 EVT VT = Op.getValueType();
1704
1705 if (VT == MVT::i64) {
1706 SmallVector<SDValue, 2> Results;
1707 LowerUDIVREM64(Op, DAG, Results);
1708 return DAG.getMergeValues(Results, DL);
1709 }
1710
1711 SDValue Num = Op.getOperand(0);
1712 SDValue Den = Op.getOperand(1);
1713
1714 if (VT == MVT::i32) {
1715 if (DAG.MaskedValueIsZero(Op.getOperand(0), APInt(32, 0xff << 24)) &&
1716 DAG.MaskedValueIsZero(Op.getOperand(1), APInt(32, 0xff << 24))) {
1717 // TODO: We technically could do this for i64, but shouldn't that just be
1718 // handled by something generally reducing 64-bit division on 32-bit
1719 // values to 32-bit?
1720 return LowerDIVREM24(Op, DAG, false);
1721 }
1722 }
1723
1724 // RCP = URECIP(Den) = 2^32 / Den + e
1725 // e is rounding error.
1726 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1727
1728 // RCP_LO = mul(RCP, Den) */
1729 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1730
1731 // RCP_HI = mulhu (RCP, Den) */
1732 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1733
1734 // NEG_RCP_LO = -RCP_LO
1735 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1736 RCP_LO);
1737
1738 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1739 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1740 NEG_RCP_LO, RCP_LO,
1741 ISD::SETEQ);
1742 // Calculate the rounding error from the URECIP instruction
1743 // E = mulhu(ABS_RCP_LO, RCP)
1744 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1745
1746 // RCP_A_E = RCP + E
1747 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1748
1749 // RCP_S_E = RCP - E
1750 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1751
1752 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1753 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1754 RCP_A_E, RCP_S_E,
1755 ISD::SETEQ);
1756 // Quotient = mulhu(Tmp0, Num)
1757 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1758
1759 // Num_S_Remainder = Quotient * Den
1760 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1761
1762 // Remainder = Num - Num_S_Remainder
1763 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1764
1765 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1766 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1767 DAG.getConstant(-1, VT),
1768 DAG.getConstant(0, VT),
1769 ISD::SETUGE);
1770 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1771 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1772 Num_S_Remainder,
1773 DAG.getConstant(-1, VT),
1774 DAG.getConstant(0, VT),
1775 ISD::SETUGE);
1776 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1777 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1778 Remainder_GE_Zero);
1779
1780 // Calculate Division result:
1781
1782 // Quotient_A_One = Quotient + 1
1783 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1784 DAG.getConstant(1, VT));
1785
1786 // Quotient_S_One = Quotient - 1
1787 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1788 DAG.getConstant(1, VT));
1789
1790 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1791 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1792 Quotient, Quotient_A_One, ISD::SETEQ);
1793
1794 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1795 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1796 Quotient_S_One, Div, ISD::SETEQ);
1797
1798 // Calculate Rem result:
1799
1800 // Remainder_S_Den = Remainder - Den
1801 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1802
1803 // Remainder_A_Den = Remainder + Den
1804 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1805
1806 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1807 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1808 Remainder, Remainder_S_Den, ISD::SETEQ);
1809
1810 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1811 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1812 Remainder_A_Den, Rem, ISD::SETEQ);
1813 SDValue Ops[2] = {
1814 Div,
1815 Rem
1816 };
1817 return DAG.getMergeValues(Ops, DL);
1818 }
1819
LowerSDIVREM(SDValue Op,SelectionDAG & DAG) const1820 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1821 SelectionDAG &DAG) const {
1822 SDLoc DL(Op);
1823 EVT VT = Op.getValueType();
1824
1825 SDValue LHS = Op.getOperand(0);
1826 SDValue RHS = Op.getOperand(1);
1827
1828 if (VT == MVT::i32) {
1829 if (DAG.ComputeNumSignBits(Op.getOperand(0)) > 8 &&
1830 DAG.ComputeNumSignBits(Op.getOperand(1)) > 8) {
1831 // TODO: We technically could do this for i64, but shouldn't that just be
1832 // handled by something generally reducing 64-bit division on 32-bit
1833 // values to 32-bit?
1834 return LowerDIVREM24(Op, DAG, true);
1835 }
1836 }
1837
1838 SDValue Zero = DAG.getConstant(0, VT);
1839 SDValue NegOne = DAG.getConstant(-1, VT);
1840
1841 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1842 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1843 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1844 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1845
1846 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1847 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1848
1849 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1850 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1851
1852 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1853 SDValue Rem = Div.getValue(1);
1854
1855 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1856 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1857
1858 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1859 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1860
1861 SDValue Res[2] = {
1862 Div,
1863 Rem
1864 };
1865 return DAG.getMergeValues(Res, DL);
1866 }
1867
1868 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
LowerFREM(SDValue Op,SelectionDAG & DAG) const1869 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1870 SDLoc SL(Op);
1871 EVT VT = Op.getValueType();
1872 SDValue X = Op.getOperand(0);
1873 SDValue Y = Op.getOperand(1);
1874
1875 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1876 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1877 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1878
1879 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1880 }
1881
LowerFCEIL(SDValue Op,SelectionDAG & DAG) const1882 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1883 SDLoc SL(Op);
1884 SDValue Src = Op.getOperand(0);
1885
1886 // result = trunc(src)
1887 // if (src > 0.0 && src != result)
1888 // result += 1.0
1889
1890 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1891
1892 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1893 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1894
1895 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1896
1897 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1898 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1899 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1900
1901 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1902 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1903 }
1904
LowerFTRUNC(SDValue Op,SelectionDAG & DAG) const1905 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1906 SDLoc SL(Op);
1907 SDValue Src = Op.getOperand(0);
1908
1909 assert(Op.getValueType() == MVT::f64);
1910
1911 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1912 const SDValue One = DAG.getConstant(1, MVT::i32);
1913
1914 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1915
1916 // Extract the upper half, since this is where we will find the sign and
1917 // exponent.
1918 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1919
1920 const unsigned FractBits = 52;
1921 const unsigned ExpBits = 11;
1922
1923 // Extract the exponent.
1924 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1925 Hi,
1926 DAG.getConstant(FractBits - 32, MVT::i32),
1927 DAG.getConstant(ExpBits, MVT::i32));
1928 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1929 DAG.getConstant(1023, MVT::i32));
1930
1931 // Extract the sign bit.
1932 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1933 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1934
1935 // Extend back to to 64-bits.
1936 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1937 Zero, SignBit);
1938 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1939
1940 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1941 const SDValue FractMask
1942 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1943
1944 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1945 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1946 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1947
1948 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1949
1950 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1951
1952 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1953 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1954
1955 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1956 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1957
1958 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1959 }
1960
LowerFRINT(SDValue Op,SelectionDAG & DAG) const1961 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1962 SDLoc SL(Op);
1963 SDValue Src = Op.getOperand(0);
1964
1965 assert(Op.getValueType() == MVT::f64);
1966
1967 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1968 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1969 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1970
1971 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1972 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1973
1974 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1975
1976 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1977 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
1978
1979 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1980 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1981
1982 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1983 }
1984
LowerFNEARBYINT(SDValue Op,SelectionDAG & DAG) const1985 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1986 // FNEARBYINT and FRINT are the same, except in their handling of FP
1987 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1988 // rint, so just treat them as equivalent.
1989 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1990 }
1991
LowerFFLOOR(SDValue Op,SelectionDAG & DAG) const1992 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1993 SDLoc SL(Op);
1994 SDValue Src = Op.getOperand(0);
1995
1996 // result = trunc(src);
1997 // if (src < 0.0 && src != result)
1998 // result += -1.0.
1999
2000 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2001
2002 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
2003 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
2004
2005 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
2006
2007 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2008 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2009 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2010
2011 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2012 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2013 }
2014
LowerINT_TO_FP64(SDValue Op,SelectionDAG & DAG,bool Signed) const2015 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2016 bool Signed) const {
2017 SDLoc SL(Op);
2018 SDValue Src = Op.getOperand(0);
2019
2020 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2021
2022 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2023 DAG.getConstant(0, MVT::i32));
2024 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2025 DAG.getConstant(1, MVT::i32));
2026
2027 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2028 SL, MVT::f64, Hi);
2029
2030 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2031
2032 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2033 DAG.getConstant(32, MVT::i32));
2034
2035 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2036 }
2037
LowerUINT_TO_FP(SDValue Op,SelectionDAG & DAG) const2038 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2039 SelectionDAG &DAG) const {
2040 SDValue S0 = Op.getOperand(0);
2041 if (S0.getValueType() != MVT::i64)
2042 return SDValue();
2043
2044 EVT DestVT = Op.getValueType();
2045 if (DestVT == MVT::f64)
2046 return LowerINT_TO_FP64(Op, DAG, false);
2047
2048 assert(DestVT == MVT::f32);
2049
2050 SDLoc DL(Op);
2051
2052 // f32 uint_to_fp i64
2053 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2054 DAG.getConstant(0, MVT::i32));
2055 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
2056 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2057 DAG.getConstant(1, MVT::i32));
2058 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
2059 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
2060 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
2061 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
2062 }
2063
LowerSINT_TO_FP(SDValue Op,SelectionDAG & DAG) const2064 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2065 SelectionDAG &DAG) const {
2066 SDValue Src = Op.getOperand(0);
2067 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
2068 return LowerINT_TO_FP64(Op, DAG, true);
2069
2070 return SDValue();
2071 }
2072
LowerFP64_TO_INT(SDValue Op,SelectionDAG & DAG,bool Signed) const2073 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2074 bool Signed) const {
2075 SDLoc SL(Op);
2076
2077 SDValue Src = Op.getOperand(0);
2078
2079 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2080
2081 SDValue K0
2082 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), MVT::f64);
2083 SDValue K1
2084 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), MVT::f64);
2085
2086 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2087
2088 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2089
2090
2091 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2092
2093 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2094 MVT::i32, FloorMul);
2095 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2096
2097 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2098
2099 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2100 }
2101
LowerFP_TO_SINT(SDValue Op,SelectionDAG & DAG) const2102 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2103 SelectionDAG &DAG) const {
2104 SDValue Src = Op.getOperand(0);
2105
2106 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2107 return LowerFP64_TO_INT(Op, DAG, true);
2108
2109 return SDValue();
2110 }
2111
LowerFP_TO_UINT(SDValue Op,SelectionDAG & DAG) const2112 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2113 SelectionDAG &DAG) const {
2114 SDValue Src = Op.getOperand(0);
2115
2116 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2117 return LowerFP64_TO_INT(Op, DAG, false);
2118
2119 return SDValue();
2120 }
2121
LowerSIGN_EXTEND_INREG(SDValue Op,SelectionDAG & DAG) const2122 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2123 SelectionDAG &DAG) const {
2124 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2125 MVT VT = Op.getSimpleValueType();
2126 MVT ScalarVT = VT.getScalarType();
2127
2128 if (!VT.isVector())
2129 return SDValue();
2130
2131 SDValue Src = Op.getOperand(0);
2132 SDLoc DL(Op);
2133
2134 // TODO: Don't scalarize on Evergreen?
2135 unsigned NElts = VT.getVectorNumElements();
2136 SmallVector<SDValue, 8> Args;
2137 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2138
2139 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2140 for (unsigned I = 0; I < NElts; ++I)
2141 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2142
2143 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2144 }
2145
2146 //===----------------------------------------------------------------------===//
2147 // Custom DAG optimizations
2148 //===----------------------------------------------------------------------===//
2149
isU24(SDValue Op,SelectionDAG & DAG)2150 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2151 APInt KnownZero, KnownOne;
2152 EVT VT = Op.getValueType();
2153 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2154
2155 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2156 }
2157
isI24(SDValue Op,SelectionDAG & DAG)2158 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2159 EVT VT = Op.getValueType();
2160
2161 // In order for this to be a signed 24-bit value, bit 23, must
2162 // be a sign bit.
2163 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2164 // as unsigned 24-bit values.
2165 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2166 }
2167
simplifyI24(SDValue Op,TargetLowering::DAGCombinerInfo & DCI)2168 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2169
2170 SelectionDAG &DAG = DCI.DAG;
2171 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2172 EVT VT = Op.getValueType();
2173
2174 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2175 APInt KnownZero, KnownOne;
2176 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2177 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2178 DCI.CommitTargetLoweringOpt(TLO);
2179 }
2180
2181 template <typename IntTy>
constantFoldBFE(SelectionDAG & DAG,IntTy Src0,uint32_t Offset,uint32_t Width)2182 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2183 uint32_t Offset, uint32_t Width) {
2184 if (Width + Offset < 32) {
2185 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2186 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2187 return DAG.getConstant(Result, MVT::i32);
2188 }
2189
2190 return DAG.getConstant(Src0 >> Offset, MVT::i32);
2191 }
2192
usesAllNormalStores(SDNode * LoadVal)2193 static bool usesAllNormalStores(SDNode *LoadVal) {
2194 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2195 if (!ISD::isNormalStore(*I))
2196 return false;
2197 }
2198
2199 return true;
2200 }
2201
2202 // If we have a copy of an illegal type, replace it with a load / store of an
2203 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2204 // instructions emitted when handling extloads and truncstores. Ideally we could
2205 // recognize the pack / unpack pattern to eliminate it.
performStoreCombine(SDNode * N,DAGCombinerInfo & DCI) const2206 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2207 DAGCombinerInfo &DCI) const {
2208 if (!DCI.isBeforeLegalize())
2209 return SDValue();
2210
2211 StoreSDNode *SN = cast<StoreSDNode>(N);
2212 SDValue Value = SN->getValue();
2213 EVT VT = Value.getValueType();
2214
2215 if (isTypeLegal(VT) || SN->isVolatile() ||
2216 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2217 return SDValue();
2218
2219 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2220 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2221 return SDValue();
2222
2223 EVT MemVT = LoadVal->getMemoryVT();
2224
2225 SDLoc SL(N);
2226 SelectionDAG &DAG = DCI.DAG;
2227 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2228
2229 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2230 LoadVT, SL,
2231 LoadVal->getChain(),
2232 LoadVal->getBasePtr(),
2233 LoadVal->getOffset(),
2234 LoadVT,
2235 LoadVal->getMemOperand());
2236
2237 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2238 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2239
2240 return DAG.getStore(SN->getChain(), SL, NewLoad,
2241 SN->getBasePtr(), SN->getMemOperand());
2242 }
2243
performMulCombine(SDNode * N,DAGCombinerInfo & DCI) const2244 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2245 DAGCombinerInfo &DCI) const {
2246 EVT VT = N->getValueType(0);
2247
2248 if (VT.isVector() || VT.getSizeInBits() > 32)
2249 return SDValue();
2250
2251 SelectionDAG &DAG = DCI.DAG;
2252 SDLoc DL(N);
2253
2254 SDValue N0 = N->getOperand(0);
2255 SDValue N1 = N->getOperand(1);
2256 SDValue Mul;
2257
2258 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2259 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2260 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2261 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2262 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2263 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2264 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2265 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2266 } else {
2267 return SDValue();
2268 }
2269
2270 // We need to use sext even for MUL_U24, because MUL_U24 is used
2271 // for signed multiply of 8 and 16-bit types.
2272 return DAG.getSExtOrTrunc(Mul, DL, VT);
2273 }
2274
PerformDAGCombine(SDNode * N,DAGCombinerInfo & DCI) const2275 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2276 DAGCombinerInfo &DCI) const {
2277 SelectionDAG &DAG = DCI.DAG;
2278 SDLoc DL(N);
2279
2280 switch(N->getOpcode()) {
2281 default: break;
2282 case ISD::MUL:
2283 return performMulCombine(N, DCI);
2284 case AMDGPUISD::MUL_I24:
2285 case AMDGPUISD::MUL_U24: {
2286 SDValue N0 = N->getOperand(0);
2287 SDValue N1 = N->getOperand(1);
2288 simplifyI24(N0, DCI);
2289 simplifyI24(N1, DCI);
2290 return SDValue();
2291 }
2292 case ISD::SELECT: {
2293 SDValue Cond = N->getOperand(0);
2294 if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) {
2295 SDLoc DL(N);
2296 EVT VT = N->getValueType(0);
2297 SDValue LHS = Cond.getOperand(0);
2298 SDValue RHS = Cond.getOperand(1);
2299 SDValue CC = Cond.getOperand(2);
2300
2301 SDValue True = N->getOperand(1);
2302 SDValue False = N->getOperand(2);
2303
2304 if (VT == MVT::f32)
2305 return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
2306
2307 // TODO: Implement min / max Evergreen instructions.
2308 if (VT == MVT::i32 &&
2309 Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
2310 return CombineIMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
2311 }
2312 }
2313
2314 break;
2315 }
2316 case AMDGPUISD::BFE_I32:
2317 case AMDGPUISD::BFE_U32: {
2318 assert(!N->getValueType(0).isVector() &&
2319 "Vector handling of BFE not implemented");
2320 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2321 if (!Width)
2322 break;
2323
2324 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2325 if (WidthVal == 0)
2326 return DAG.getConstant(0, MVT::i32);
2327
2328 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2329 if (!Offset)
2330 break;
2331
2332 SDValue BitsFrom = N->getOperand(0);
2333 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2334
2335 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2336
2337 if (OffsetVal == 0) {
2338 // This is already sign / zero extended, so try to fold away extra BFEs.
2339 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2340
2341 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2342 if (OpSignBits >= SignBits)
2343 return BitsFrom;
2344
2345 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2346 if (Signed) {
2347 // This is a sign_extend_inreg. Replace it to take advantage of existing
2348 // DAG Combines. If not eliminated, we will match back to BFE during
2349 // selection.
2350
2351 // TODO: The sext_inreg of extended types ends, although we can could
2352 // handle them in a single BFE.
2353 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2354 DAG.getValueType(SmallVT));
2355 }
2356
2357 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2358 }
2359
2360 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2361 if (Signed) {
2362 return constantFoldBFE<int32_t>(DAG,
2363 CVal->getSExtValue(),
2364 OffsetVal,
2365 WidthVal);
2366 }
2367
2368 return constantFoldBFE<uint32_t>(DAG,
2369 CVal->getZExtValue(),
2370 OffsetVal,
2371 WidthVal);
2372 }
2373
2374 if ((OffsetVal + WidthVal) >= 32) {
2375 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
2376 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2377 BitsFrom, ShiftVal);
2378 }
2379
2380 if (BitsFrom.hasOneUse()) {
2381 APInt Demanded = APInt::getBitsSet(32,
2382 OffsetVal,
2383 OffsetVal + WidthVal);
2384
2385 APInt KnownZero, KnownOne;
2386 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2387 !DCI.isBeforeLegalizeOps());
2388 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2389 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2390 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2391 KnownZero, KnownOne, TLO)) {
2392 DCI.CommitTargetLoweringOpt(TLO);
2393 }
2394 }
2395
2396 break;
2397 }
2398
2399 case ISD::STORE:
2400 return performStoreCombine(N, DCI);
2401 }
2402 return SDValue();
2403 }
2404
2405 //===----------------------------------------------------------------------===//
2406 // Helper functions
2407 //===----------------------------------------------------------------------===//
2408
getOriginalFunctionArgs(SelectionDAG & DAG,const Function * F,const SmallVectorImpl<ISD::InputArg> & Ins,SmallVectorImpl<ISD::InputArg> & OrigIns) const2409 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2410 SelectionDAG &DAG,
2411 const Function *F,
2412 const SmallVectorImpl<ISD::InputArg> &Ins,
2413 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2414
2415 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2416 if (Ins[i].ArgVT == Ins[i].VT) {
2417 OrigIns.push_back(Ins[i]);
2418 continue;
2419 }
2420
2421 EVT VT;
2422 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2423 // Vector has been split into scalars.
2424 VT = Ins[i].ArgVT.getVectorElementType();
2425 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2426 Ins[i].ArgVT.getVectorElementType() !=
2427 Ins[i].VT.getVectorElementType()) {
2428 // Vector elements have been promoted
2429 VT = Ins[i].ArgVT;
2430 } else {
2431 // Vector has been spilt into smaller vectors.
2432 VT = Ins[i].VT;
2433 }
2434
2435 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2436 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2437 OrigIns.push_back(Arg);
2438 }
2439 }
2440
isHWTrueValue(SDValue Op) const2441 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2442 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2443 return CFP->isExactlyValue(1.0);
2444 }
2445 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2446 return C->isAllOnesValue();
2447 }
2448 return false;
2449 }
2450
isHWFalseValue(SDValue Op) const2451 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2452 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2453 return CFP->getValueAPF().isZero();
2454 }
2455 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2456 return C->isNullValue();
2457 }
2458 return false;
2459 }
2460
CreateLiveInRegister(SelectionDAG & DAG,const TargetRegisterClass * RC,unsigned Reg,EVT VT) const2461 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2462 const TargetRegisterClass *RC,
2463 unsigned Reg, EVT VT) const {
2464 MachineFunction &MF = DAG.getMachineFunction();
2465 MachineRegisterInfo &MRI = MF.getRegInfo();
2466 unsigned VirtualRegister;
2467 if (!MRI.isLiveIn(Reg)) {
2468 VirtualRegister = MRI.createVirtualRegister(RC);
2469 MRI.addLiveIn(Reg, VirtualRegister);
2470 } else {
2471 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2472 }
2473 return DAG.getRegister(VirtualRegister, VT);
2474 }
2475
2476 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2477
getTargetNodeName(unsigned Opcode) const2478 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2479 switch (Opcode) {
2480 default: return nullptr;
2481 // AMDIL DAG nodes
2482 NODE_NAME_CASE(CALL);
2483 NODE_NAME_CASE(UMUL);
2484 NODE_NAME_CASE(RET_FLAG);
2485 NODE_NAME_CASE(BRANCH_COND);
2486
2487 // AMDGPU DAG nodes
2488 NODE_NAME_CASE(DWORDADDR)
2489 NODE_NAME_CASE(FRACT)
2490 NODE_NAME_CASE(CLAMP)
2491 NODE_NAME_CASE(MAD)
2492 NODE_NAME_CASE(FMAX_LEGACY)
2493 NODE_NAME_CASE(SMAX)
2494 NODE_NAME_CASE(UMAX)
2495 NODE_NAME_CASE(FMIN_LEGACY)
2496 NODE_NAME_CASE(SMIN)
2497 NODE_NAME_CASE(UMIN)
2498 NODE_NAME_CASE(FMAX3)
2499 NODE_NAME_CASE(SMAX3)
2500 NODE_NAME_CASE(UMAX3)
2501 NODE_NAME_CASE(FMIN3)
2502 NODE_NAME_CASE(SMIN3)
2503 NODE_NAME_CASE(UMIN3)
2504 NODE_NAME_CASE(URECIP)
2505 NODE_NAME_CASE(DIV_SCALE)
2506 NODE_NAME_CASE(DIV_FMAS)
2507 NODE_NAME_CASE(DIV_FIXUP)
2508 NODE_NAME_CASE(TRIG_PREOP)
2509 NODE_NAME_CASE(RCP)
2510 NODE_NAME_CASE(RSQ)
2511 NODE_NAME_CASE(RSQ_LEGACY)
2512 NODE_NAME_CASE(RSQ_CLAMPED)
2513 NODE_NAME_CASE(LDEXP)
2514 NODE_NAME_CASE(FP_CLASS)
2515 NODE_NAME_CASE(DOT4)
2516 NODE_NAME_CASE(BFE_U32)
2517 NODE_NAME_CASE(BFE_I32)
2518 NODE_NAME_CASE(BFI)
2519 NODE_NAME_CASE(BFM)
2520 NODE_NAME_CASE(BREV)
2521 NODE_NAME_CASE(MUL_U24)
2522 NODE_NAME_CASE(MUL_I24)
2523 NODE_NAME_CASE(MAD_U24)
2524 NODE_NAME_CASE(MAD_I24)
2525 NODE_NAME_CASE(EXPORT)
2526 NODE_NAME_CASE(CONST_ADDRESS)
2527 NODE_NAME_CASE(REGISTER_LOAD)
2528 NODE_NAME_CASE(REGISTER_STORE)
2529 NODE_NAME_CASE(LOAD_CONSTANT)
2530 NODE_NAME_CASE(LOAD_INPUT)
2531 NODE_NAME_CASE(SAMPLE)
2532 NODE_NAME_CASE(SAMPLEB)
2533 NODE_NAME_CASE(SAMPLED)
2534 NODE_NAME_CASE(SAMPLEL)
2535 NODE_NAME_CASE(CVT_F32_UBYTE0)
2536 NODE_NAME_CASE(CVT_F32_UBYTE1)
2537 NODE_NAME_CASE(CVT_F32_UBYTE2)
2538 NODE_NAME_CASE(CVT_F32_UBYTE3)
2539 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2540 NODE_NAME_CASE(CONST_DATA_PTR)
2541 NODE_NAME_CASE(STORE_MSKOR)
2542 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2543 }
2544 }
2545
getRsqrtEstimate(SDValue Operand,DAGCombinerInfo & DCI,unsigned & RefinementSteps,bool & UseOneConstNR) const2546 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2547 DAGCombinerInfo &DCI,
2548 unsigned &RefinementSteps,
2549 bool &UseOneConstNR) const {
2550 SelectionDAG &DAG = DCI.DAG;
2551 EVT VT = Operand.getValueType();
2552
2553 if (VT == MVT::f32) {
2554 RefinementSteps = 0;
2555 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2556 }
2557
2558 // TODO: There is also f64 rsq instruction, but the documentation is less
2559 // clear on its precision.
2560
2561 return SDValue();
2562 }
2563
getRecipEstimate(SDValue Operand,DAGCombinerInfo & DCI,unsigned & RefinementSteps) const2564 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2565 DAGCombinerInfo &DCI,
2566 unsigned &RefinementSteps) const {
2567 SelectionDAG &DAG = DCI.DAG;
2568 EVT VT = Operand.getValueType();
2569
2570 if (VT == MVT::f32) {
2571 // Reciprocal, < 1 ulp error.
2572 //
2573 // This reciprocal approximation converges to < 0.5 ulp error with one
2574 // newton rhapson performed with two fused multiple adds (FMAs).
2575
2576 RefinementSteps = 0;
2577 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2578 }
2579
2580 // TODO: There is also f64 rcp instruction, but the documentation is less
2581 // clear on its precision.
2582
2583 return SDValue();
2584 }
2585
computeKnownBitsForMinMax(const SDValue Op0,const SDValue Op1,APInt & KnownZero,APInt & KnownOne,const SelectionDAG & DAG,unsigned Depth)2586 static void computeKnownBitsForMinMax(const SDValue Op0,
2587 const SDValue Op1,
2588 APInt &KnownZero,
2589 APInt &KnownOne,
2590 const SelectionDAG &DAG,
2591 unsigned Depth) {
2592 APInt Op0Zero, Op0One;
2593 APInt Op1Zero, Op1One;
2594 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2595 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2596
2597 KnownZero = Op0Zero & Op1Zero;
2598 KnownOne = Op0One & Op1One;
2599 }
2600
computeKnownBitsForTargetNode(const SDValue Op,APInt & KnownZero,APInt & KnownOne,const SelectionDAG & DAG,unsigned Depth) const2601 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2602 const SDValue Op,
2603 APInt &KnownZero,
2604 APInt &KnownOne,
2605 const SelectionDAG &DAG,
2606 unsigned Depth) const {
2607
2608 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2609
2610 APInt KnownZero2;
2611 APInt KnownOne2;
2612 unsigned Opc = Op.getOpcode();
2613
2614 switch (Opc) {
2615 default:
2616 break;
2617 case ISD::INTRINSIC_WO_CHAIN: {
2618 // FIXME: The intrinsic should just use the node.
2619 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2620 case AMDGPUIntrinsic::AMDGPU_imax:
2621 case AMDGPUIntrinsic::AMDGPU_umax:
2622 case AMDGPUIntrinsic::AMDGPU_imin:
2623 case AMDGPUIntrinsic::AMDGPU_umin:
2624 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2625 KnownZero, KnownOne, DAG, Depth);
2626 break;
2627 default:
2628 break;
2629 }
2630
2631 break;
2632 }
2633 case AMDGPUISD::SMAX:
2634 case AMDGPUISD::UMAX:
2635 case AMDGPUISD::SMIN:
2636 case AMDGPUISD::UMIN:
2637 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2638 KnownZero, KnownOne, DAG, Depth);
2639 break;
2640
2641 case AMDGPUISD::BFE_I32:
2642 case AMDGPUISD::BFE_U32: {
2643 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2644 if (!CWidth)
2645 return;
2646
2647 unsigned BitWidth = 32;
2648 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2649
2650 if (Opc == AMDGPUISD::BFE_U32)
2651 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2652
2653 break;
2654 }
2655 }
2656 }
2657
ComputeNumSignBitsForTargetNode(SDValue Op,const SelectionDAG & DAG,unsigned Depth) const2658 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2659 SDValue Op,
2660 const SelectionDAG &DAG,
2661 unsigned Depth) const {
2662 switch (Op.getOpcode()) {
2663 case AMDGPUISD::BFE_I32: {
2664 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2665 if (!Width)
2666 return 1;
2667
2668 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2669 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2670 if (!Offset || !Offset->isNullValue())
2671 return SignBits;
2672
2673 // TODO: Could probably figure something out with non-0 offsets.
2674 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2675 return std::max(SignBits, Op0SignBits);
2676 }
2677
2678 case AMDGPUISD::BFE_U32: {
2679 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2680 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
2681 }
2682
2683 default:
2684 return 1;
2685 }
2686 }
2687