1 //===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler. 10 // It contains common definitions used by both the disassembler and the table 11 // generator. 12 // Documentation for the disassembler can be found in X86Disassembler.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_SUPPORT_X86DISASSEMBLERDECODERCOMMON_H 17 #define LLVM_SUPPORT_X86DISASSEMBLERDECODERCOMMON_H 18 19 #include "llvm/Support/DataTypes.h" 20 21 namespace llvm { 22 namespace X86Disassembler { 23 24 #define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers 25 #define CONTEXTS_SYM x86DisassemblerContexts 26 #define ONEBYTE_SYM x86DisassemblerOneByteOpcodes 27 #define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes 28 #define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes 29 #define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes 30 #define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes 31 #define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes 32 #define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes 33 #define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes 34 #define MAP4_SYM x86DisassemblerMap4Opcodes 35 #define MAP5_SYM x86DisassemblerMap5Opcodes 36 #define MAP6_SYM x86DisassemblerMap6Opcodes 37 #define MAP7_SYM x86DisassemblerMap7Opcodes 38 39 #define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers" 40 #define CONTEXTS_STR "x86DisassemblerContexts" 41 #define ONEBYTE_STR "x86DisassemblerOneByteOpcodes" 42 #define TWOBYTE_STR "x86DisassemblerTwoByteOpcodes" 43 #define THREEBYTE38_STR "x86DisassemblerThreeByte38Opcodes" 44 #define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes" 45 #define XOP8_MAP_STR "x86DisassemblerXOP8Opcodes" 46 #define XOP9_MAP_STR "x86DisassemblerXOP9Opcodes" 47 #define XOPA_MAP_STR "x86DisassemblerXOPAOpcodes" 48 #define THREEDNOW_MAP_STR "x86Disassembler3DNowOpcodes" 49 #define MAP4_STR "x86DisassemblerMap4Opcodes" 50 #define MAP5_STR "x86DisassemblerMap5Opcodes" 51 #define MAP6_STR "x86DisassemblerMap6Opcodes" 52 #define MAP7_STR "x86DisassemblerMap7Opcodes" 53 54 // Attributes of an instruction that must be known before the opcode can be 55 // processed correctly. Most of these indicate the presence of particular 56 // prefixes, but ATTR_64BIT is simply an attribute of the decoding context. 57 enum attributeBits { 58 ATTR_NONE = 0x00, 59 ATTR_64BIT = 0x1 << 0, 60 ATTR_XS = 0x1 << 1, 61 ATTR_XD = 0x1 << 2, 62 ATTR_REXW = 0x1 << 3, 63 ATTR_OPSIZE = 0x1 << 4, 64 ATTR_ADSIZE = 0x1 << 5, 65 ATTR_VEX = 0x1 << 6, 66 ATTR_VEXL = 0x1 << 7, 67 ATTR_EVEX = 0x1 << 8, 68 ATTR_EVEXL2 = 0x1 << 9, 69 ATTR_EVEXK = 0x1 << 10, 70 ATTR_EVEXKZ = 0x1 << 11, 71 ATTR_EVEXB = 0x1 << 12, 72 ATTR_REX2 = 0x1 << 13, 73 ATTR_EVEXNF = 0x1 << 14, 74 ATTR_max = 0x1 << 15, 75 }; 76 77 // Combinations of the above attributes that are relevant to instruction 78 // decode. Although other combinations are possible, they can be reduced to 79 // these without affecting the ultimately decoded instruction. 80 81 // Class name Rank Rationale for rank assignment 82 #define INSTRUCTION_CONTEXTS \ 83 ENUM_ENTRY(IC, 0, "says nothing about the instruction") \ 84 ENUM_ENTRY(IC_64BIT, 1, \ 85 "says the instruction applies in 64-bit mode but no more") \ 86 ENUM_ENTRY(IC_OPSIZE, 3, \ 87 "requires an OPSIZE prefix, so operands change width") \ 88 ENUM_ENTRY(IC_ADSIZE, 3, \ 89 "requires an ADSIZE prefix, so operands change width") \ 90 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \ 91 ENUM_ENTRY(IC_XD, 2, \ 92 "may say something about the opcode but not the operands") \ 93 ENUM_ENTRY(IC_XS, 2, \ 94 "may say something about the opcode but not the operands") \ 95 ENUM_ENTRY(IC_XD_OPSIZE, 3, \ 96 "requires an OPSIZE prefix, so operands change width") \ 97 ENUM_ENTRY(IC_XS_OPSIZE, 3, \ 98 "requires an OPSIZE prefix, so operands change width") \ 99 ENUM_ENTRY(IC_XD_ADSIZE, 3, \ 100 "requires an ADSIZE prefix, so operands change width") \ 101 ENUM_ENTRY(IC_XS_ADSIZE, 3, \ 102 "requires an ADSIZE prefix, so operands change width") \ 103 ENUM_ENTRY(IC_64BIT_REXW, 5, \ 104 "requires a REX.W prefix, so operands change width; overrides " \ 105 "IC_OPSIZE") \ 106 ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, \ 107 "requires a REX.W prefix and 0x67 prefix") \ 108 ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \ 109 ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \ 110 ENUM_ENTRY(IC_64BIT_OPSIZE_ADSIZE, 4, \ 111 "Just as meaningful as IC_OPSIZE/IC_ADSIZE") \ 112 ENUM_ENTRY(IC_64BIT_XD, 6, "XD instructions are SSE; REX.W is secondary") \ 113 ENUM_ENTRY(IC_64BIT_XS, 6, "Just as meaningful as IC_64BIT_XD") \ 114 ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \ 115 ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \ 116 ENUM_ENTRY(IC_64BIT_XD_ADSIZE, 3, "Just as meaningful as IC_XD_ADSIZE") \ 117 ENUM_ENTRY(IC_64BIT_XS_ADSIZE, 3, "Just as meaningful as IC_XS_ADSIZE") \ 118 ENUM_ENTRY(IC_64BIT_REXW_XS, 7, "OPSIZE could mean a different opcode") \ 119 ENUM_ENTRY(IC_64BIT_REXW_XD, 7, "Just as meaningful as IC_64BIT_REXW_XS") \ 120 ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 8, \ 121 "The Dynamic Duo! Prefer over all else because this changes " \ 122 "most operands' meaning") \ 123 ENUM_ENTRY(IC_64BIT_REX2, 2, "requires a REX2 prefix") \ 124 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \ 125 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \ 126 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \ 127 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \ 128 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \ 129 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \ 130 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \ 131 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \ 132 ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \ 133 ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix") \ 134 ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix") \ 135 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \ 136 ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \ 137 ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \ 138 ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \ 139 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \ 140 ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \ 141 ENUM_ENTRY(IC_EVEX_NF, 2, "requires EVEX and NF prefix") \ 142 ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \ 143 ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \ 144 ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \ 145 ENUM_ENTRY(IC_EVEX_OPSIZE_NF, 3, "requires EVEX, NF and the OpSize prefix") \ 146 ENUM_ENTRY(IC_EVEX_OPSIZE_ADSIZE, 3, \ 147 "requires EVEX, OPSIZE and the ADSIZE prefix") \ 148 ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \ 149 ENUM_ENTRY(IC_EVEX_W_NF, 4, "requires EVEX, W and NF prefix") \ 150 ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \ 151 ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \ 152 ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \ 153 ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \ 154 ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix") \ 155 ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix") \ 156 ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \ 157 ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \ 158 ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \ 159 ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \ 160 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \ 161 ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \ 162 ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix") \ 163 ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix") \ 164 ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \ 165 ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \ 166 ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \ 167 ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \ 168 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \ 169 ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \ 170 ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \ 171 ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \ 172 ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \ 173 ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \ 174 ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \ 175 ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \ 176 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \ 177 ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \ 178 ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix") \ 179 ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix") \ 180 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \ 181 ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \ 182 ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \ 183 ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \ 184 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \ 185 ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \ 186 ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix") \ 187 ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix") \ 188 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \ 189 ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \ 190 ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \ 191 ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \ 192 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \ 193 ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \ 194 ENUM_ENTRY(IC_EVEX_B_NF, 2, "requires EVEX_NF and EVEX_B prefix") \ 195 ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \ 196 ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \ 197 ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \ 198 ENUM_ENTRY(IC_EVEX_OPSIZE_B_NF, 3, "requires EVEX_B, NF and Opsize prefix") \ 199 ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \ 200 ENUM_ENTRY(IC_EVEX_W_B_NF, 4, "requires EVEX_NF, EVEX_B and the W prefix") \ 201 ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \ 202 ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \ 203 ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \ 204 ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \ 205 ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix") \ 206 ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix") \ 207 ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \ 208 ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \ 209 ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \ 210 ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \ 211 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \ 212 ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \ 213 ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix") \ 214 ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix") \ 215 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \ 216 ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \ 217 ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \ 218 ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \ 219 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \ 220 ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \ 221 ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \ 222 ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \ 223 ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, \ 224 "requires EVEX_B, EVEX_K and the OpSize prefix") \ 225 ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \ 226 ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \ 227 ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \ 228 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, \ 229 "requires EVEX_B, EVEX_K, W, and OpSize") \ 230 ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \ 231 ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, \ 232 "requires EVEX_B, EVEX_K and the L and XS prefix") \ 233 ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, \ 234 "requires EVEX_B, EVEX_K and the L and XD prefix") \ 235 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, \ 236 "requires EVEX_B, EVEX_K, L, and OpSize") \ 237 ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \ 238 ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, \ 239 "requires EVEX_B, EVEX_K, L, W and XS prefix") \ 240 ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, \ 241 "requires EVEX_B, EVEX_K, L, W and XD prefix") \ 242 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B, 4, \ 243 "requires EVEX_B, EVEX_K, L, W and OpSize") \ 244 ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \ 245 ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, \ 246 "requires EVEX_B, EVEX_K and the L2 and XS prefix") \ 247 ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, \ 248 "requires EVEX_B, EVEX_K and the L2 and XD prefix") \ 249 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, \ 250 "requires EVEX_B, EVEX_K, L2, and OpSize") \ 251 ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \ 252 ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, \ 253 "requires EVEX_B, EVEX_K, L2, W and XS prefix") \ 254 ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, \ 255 "requires EVEX_B, EVEX_K, L2, W and XD prefix") \ 256 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B, 4, \ 257 "requires EVEX_B, EVEX_K, L2, W and OpSize") \ 258 ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \ 259 ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \ 260 ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \ 261 ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, \ 262 "requires EVEX_B, EVEX_KZ and the OpSize prefix") \ 263 ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \ 264 ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, \ 265 "requires EVEX_B, EVEX_KZ, W, and XS prefix") \ 266 ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, \ 267 "requires EVEX_B, EVEX_KZ, W, and XD prefix") \ 268 ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, \ 269 "requires EVEX_B, EVEX_KZ, W, and OpSize") \ 270 ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \ 271 ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, \ 272 "requires EVEX_B, EVEX_KZ and the L and XS prefix") \ 273 ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, \ 274 "requires EVEX_B, EVEX_KZ and the L and XD prefix") \ 275 ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, \ 276 "requires EVEX_B, EVEX_KZ, L, and OpSize") \ 277 ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \ 278 ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, \ 279 "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \ 280 ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, \ 281 "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \ 282 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, \ 283 "requires EVEX_B, EVEX_KZ, L, W and OpSize") \ 284 ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \ 285 ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, \ 286 "requires EVEX_B, EVEX_KZ and the L2 and XS prefix") \ 287 ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, \ 288 "requires EVEX_B, EVEX_KZ and the L2 and XD prefix") \ 289 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, \ 290 "requires EVEX_B, EVEX_KZ, L2, and OpSize") \ 291 ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \ 292 ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, \ 293 "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \ 294 ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, \ 295 "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \ 296 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, \ 297 "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \ 298 ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \ 299 ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \ 300 ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \ 301 ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \ 302 ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \ 303 ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \ 304 ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \ 305 ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \ 306 ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \ 307 ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix") \ 308 ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix") \ 309 ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \ 310 ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \ 311 ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \ 312 ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \ 313 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \ 314 ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \ 315 ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix") \ 316 ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix") \ 317 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \ 318 ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \ 319 ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \ 320 ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \ 321 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize") 322 323 #define ENUM_ENTRY(n, r, d) n, 324 enum InstructionContext { INSTRUCTION_CONTEXTS IC_max }; 325 #undef ENUM_ENTRY 326 327 // Opcode types, which determine which decode table to use, both in the Intel 328 // manual and also for the decoder. 329 enum OpcodeType { 330 ONEBYTE = 0, 331 TWOBYTE = 1, 332 THREEBYTE_38 = 2, 333 THREEBYTE_3A = 3, 334 XOP8_MAP = 4, 335 XOP9_MAP = 5, 336 XOPA_MAP = 6, 337 THREEDNOW_MAP = 7, 338 MAP4 = 8, 339 MAP5 = 9, 340 MAP6 = 10, 341 MAP7 = 11 342 }; 343 344 // The following structs are used for the hierarchical decode table. After 345 // determining the instruction's class (i.e., which IC_* constant applies to 346 // it), the decoder reads the opcode. Some instructions require specific 347 // values of the ModR/M byte, so the ModR/M byte indexes into the final table. 348 // 349 // If a ModR/M byte is not required, "required" is left unset, and the values 350 // for each instructionID are identical. 351 typedef uint16_t InstrUID; 352 353 // ModRMDecisionType - describes the type of ModR/M decision, allowing the 354 // consumer to determine the number of entries in it. 355 // 356 // MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded 357 // instruction is the same. 358 // MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode 359 // corresponds to one instruction; otherwise, it corresponds to 360 // a different instruction. 361 // MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte 362 // divided by 8 is used to select instruction; otherwise, each 363 // value of the ModR/M byte could correspond to a different 364 // instruction. 365 // MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This 366 // corresponds to instructions that use reg field as opcode 367 // MODRM_FULL - Potentially, each value of the ModR/M byte could correspond 368 // to a different instruction. 369 #define MODRMTYPES \ 370 ENUM_ENTRY(MODRM_ONEENTRY) \ 371 ENUM_ENTRY(MODRM_SPLITRM) \ 372 ENUM_ENTRY(MODRM_SPLITMISC) \ 373 ENUM_ENTRY(MODRM_SPLITREG) \ 374 ENUM_ENTRY(MODRM_FULL) 375 376 #define ENUM_ENTRY(n) n, 377 enum ModRMDecisionType { MODRMTYPES MODRM_max }; 378 #undef ENUM_ENTRY 379 380 #define CASE_ENCODING_RM \ 381 case ENCODING_RM: \ 382 case ENCODING_RM_CD2: \ 383 case ENCODING_RM_CD4: \ 384 case ENCODING_RM_CD8: \ 385 case ENCODING_RM_CD16: \ 386 case ENCODING_RM_CD32: \ 387 case ENCODING_RM_CD64 388 389 #define CASE_ENCODING_VSIB \ 390 case ENCODING_VSIB: \ 391 case ENCODING_VSIB_CD2: \ 392 case ENCODING_VSIB_CD4: \ 393 case ENCODING_VSIB_CD8: \ 394 case ENCODING_VSIB_CD16: \ 395 case ENCODING_VSIB_CD32: \ 396 case ENCODING_VSIB_CD64 397 398 // Physical encodings of instruction operands. 399 #define ENCODINGS \ 400 ENUM_ENTRY(ENCODING_NONE, "") \ 401 ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \ 402 ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \ 403 ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2") \ 404 ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4") \ 405 ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8") \ 406 ENUM_ENTRY(ENCODING_RM_CD16, "R/M operand with CDisp scaling of 16") \ 407 ENUM_ENTRY(ENCODING_RM_CD32, "R/M operand with CDisp scaling of 32") \ 408 ENUM_ENTRY(ENCODING_RM_CD64, "R/M operand with CDisp scaling of 64") \ 409 ENUM_ENTRY(ENCODING_SIB, "Force SIB operand in ModR/M byte.") \ 410 ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \ 411 ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \ 412 ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \ 413 ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8") \ 414 ENUM_ENTRY(ENCODING_VSIB_CD16, "VSIB operand with CDisp scaling of 16") \ 415 ENUM_ENTRY(ENCODING_VSIB_CD32, "VSIB operand with CDisp scaling of 32") \ 416 ENUM_ENTRY(ENCODING_VSIB_CD64, "VSIB operand with CDisp scaling of 64") \ 417 ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \ 418 ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \ 419 ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \ 420 ENUM_ENTRY(ENCODING_IW, "2-byte") \ 421 ENUM_ENTRY(ENCODING_ID, "4-byte") \ 422 ENUM_ENTRY(ENCODING_IO, "8-byte") \ 423 ENUM_ENTRY(ENCODING_RB, \ 424 "(AL..DIL, R8B..R15B) Register code added to the opcode byte") \ 425 ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \ 426 ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \ 427 ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \ 428 ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M byte.") \ 429 ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \ 430 ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \ 431 ENUM_ENTRY(ENCODING_IRC, "Immediate for static rounding control") \ 432 ENUM_ENTRY(ENCODING_Rv, \ 433 "Register code of operand size added to the opcode byte") \ 434 ENUM_ENTRY(ENCODING_CC, "Condition code encoded in opcode") \ 435 ENUM_ENTRY(ENCODING_DUP, \ 436 "Duplicate of another operand; ID is encoded in type") \ 437 ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \ 438 ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes") 439 440 #define ENUM_ENTRY(n, d) n, 441 enum OperandEncoding { ENCODINGS ENCODING_max }; 442 #undef ENUM_ENTRY 443 444 // Semantic interpretations of instruction operands. 445 #define TYPES \ 446 ENUM_ENTRY(TYPE_NONE, "") \ 447 ENUM_ENTRY(TYPE_REL, "immediate address") \ 448 ENUM_ENTRY(TYPE_R8, "1-byte register operand") \ 449 ENUM_ENTRY(TYPE_R16, "2-byte") \ 450 ENUM_ENTRY(TYPE_R32, "4-byte") \ 451 ENUM_ENTRY(TYPE_R64, "8-byte") \ 452 ENUM_ENTRY(TYPE_IMM, "immediate operand") \ 453 ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \ 454 ENUM_ENTRY(TYPE_M, "Memory operand") \ 455 ENUM_ENTRY(TYPE_MSIB, "Memory operand force sib encoding") \ 456 ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \ 457 ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \ 458 ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \ 459 ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \ 460 ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \ 461 ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \ 462 ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \ 463 ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \ 464 ENUM_ENTRY(TYPE_XMM, "16-byte") \ 465 ENUM_ENTRY(TYPE_YMM, "32-byte") \ 466 ENUM_ENTRY(TYPE_ZMM, "64-byte") \ 467 ENUM_ENTRY(TYPE_VK, "mask register") \ 468 ENUM_ENTRY(TYPE_VK_PAIR, "mask register pair") \ 469 ENUM_ENTRY(TYPE_TMM, "tile") \ 470 ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \ 471 ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ 472 ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \ 473 ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \ 474 ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \ 475 ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \ 476 ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \ 477 ENUM_ENTRY(TYPE_DUP1, "operand 1") \ 478 ENUM_ENTRY(TYPE_DUP2, "operand 2") \ 479 ENUM_ENTRY(TYPE_DUP3, "operand 3") \ 480 ENUM_ENTRY(TYPE_DUP4, "operand 4") 481 482 #define ENUM_ENTRY(n, d) n, 483 enum OperandType { TYPES TYPE_max }; 484 #undef ENUM_ENTRY 485 486 /// The specification for how to extract and interpret one operand. 487 struct OperandSpecifier { 488 uint8_t encoding; 489 uint8_t type; 490 }; 491 492 static const unsigned X86_MAX_OPERANDS = 6; 493 494 /// Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode 495 /// are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode, 496 /// respectively. 497 enum DisassemblerMode { MODE_16BIT, MODE_32BIT, MODE_64BIT }; 498 499 } // namespace X86Disassembler 500 } // namespace llvm 501 502 #endif 503