1 /* 2 * Copyright 2007-2012, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 #ifndef _HDA_H_ 10 #define _HDA_H_ 11 12 #ifndef __REACTOS__ 13 #include <KernelExport.h> 14 #include <Drivers.h> 15 #include <PCI.h> 16 #include <PCI_x86.h> 17 18 #include <string.h> 19 #include <stdlib.h> 20 21 #ifndef HAIKU_TARGET_PLATFORM_HAIKU 22 # define DEVFS_PATH_FORMAT "audio/multi/hda/%lu" 23 # include <multi_audio.h> 24 #else 25 # define DEVFS_PATH_FORMAT "audio/hmulti/hda/%lu" 26 # include <hmulti_audio.h> 27 #endif 28 #endif 29 30 #include "hda_controller_defs.h" 31 #include "hda_codec_defs.h" 32 33 #define MAX_CARDS 4 34 35 /* values for the class_sub field for class_base = 0x04 (multimedia device) */ 36 #ifndef __HAIKU__ 37 # define PCI_hd_audio 3 38 #endif 39 40 #define HDA_MAX_AUDIO_GROUPS 15 41 #define HDA_MAX_CODECS 15 42 #define HDA_MAX_STREAMS 16 43 #define MAX_CODEC_RESPONSES 16 44 #define MAX_CODEC_UNSOL_RESPONSES 16 45 #define MAX_INPUTS 32 46 #define MAX_IO_WIDGETS 8 47 #define MAX_ASSOCIATIONS 16 48 #define MAX_ASSOCIATION_PINS 16 49 50 #define STREAM_MAX_BUFFERS 10 51 #define STREAM_MIN_BUFFERS 2 52 53 54 enum { 55 STREAM_PLAYBACK, 56 STREAM_RECORD 57 }; 58 59 struct hda_codec; 60 struct hda_stream; 61 struct hda_multi; 62 63 /*! This structure describes a single HDA compliant 64 controller. It contains a list of available streams 65 for use by the codecs contained, and the messaging queue 66 (verb/response) buffers for communication. 67 */ 68 #ifndef __REACTOS__ 69 struct hda_controller { 70 struct pci_info pci_info; 71 int32 opened; 72 const char* devfs_path; 73 74 area_id regs_area; 75 vuint8* regs; 76 uint32 irq; 77 bool msi; 78 bool dma_snooping; 79 80 uint16 codec_status; 81 uint32 num_input_streams; 82 uint32 num_output_streams; 83 uint32 num_bidir_streams; 84 85 uint32 corb_length; 86 uint32 rirb_length; 87 uint32 rirb_read_pos; 88 uint32 corb_write_pos; 89 area_id corb_rirb_pos_area; 90 corb_t* corb; 91 rirb_t* rirb; 92 uint32* stream_positions; 93 94 hda_codec* codecs[HDA_MAX_CODECS + 1]; 95 hda_codec* active_codec; 96 uint32 num_codecs; 97 98 hda_stream* streams[HDA_MAX_STREAMS]; 99 sem_id buffer_ready_sem; 100 Read8hda_controller101 uint8 Read8(uint32 reg) 102 { 103 return *(regs + reg); 104 } 105 Read16hda_controller106 uint16 Read16(uint32 reg) 107 { 108 return *(vuint16*)(regs + reg); 109 } 110 Read32hda_controller111 uint32 Read32(uint32 reg) 112 { 113 return *(vuint32*)(regs + reg); 114 } 115 Write8hda_controller116 void Write8(uint32 reg, uint8 value) 117 { 118 *(regs + reg) = value; 119 } 120 Write16hda_controller121 void Write16(uint32 reg, uint16 value) 122 { 123 *(vuint16*)(regs + reg) = value; 124 } 125 Write32hda_controller126 void Write32(uint32 reg, uint32 value) 127 { 128 *(vuint32*)(regs + reg) = value; 129 } 130 ReadModifyWrite8hda_controller131 void ReadModifyWrite8(uint32 reg, uint8 mask, uint8 value) 132 { 133 uint8 temp = Read8(reg); 134 temp &= ~mask; 135 temp |= value; 136 Write8(reg, temp); 137 } 138 ReadModifyWrite16hda_controller139 void ReadModifyWrite16(uint32 reg, uint16 mask, uint16 value) 140 { 141 uint16 temp = Read16(reg); 142 temp &= ~mask; 143 temp |= value; 144 Write16(reg, temp); 145 } 146 ReadModifyWrite32hda_controller147 void ReadModifyWrite32(uint32 reg, uint32 mask, uint32 value) 148 { 149 uint32 temp = Read32(reg); 150 temp &= ~mask; 151 temp |= value; 152 Write32(reg, temp); 153 } 154 }; 155 156 /*! This structure describes a single stream of audio data, 157 which is can have multiple channels (for stereo or better). 158 */ 159 struct hda_stream { 160 uint32 id; /* HDA controller stream # */ 161 uint32 offset; /* HDA I/O/B descriptor offset */ 162 bool running; 163 spinlock lock; /* Write lock */ 164 uint32 type; 165 166 hda_controller* controller; 167 168 uint32 pin_widget; /* PIN Widget ID */ 169 uint32 io_widgets[MAX_IO_WIDGETS]; /* Input/Output Converter Widget ID */ 170 uint32 num_io_widgets; 171 172 uint32 sample_rate; 173 uint32 sample_format; 174 175 uint32 num_buffers; 176 uint32 num_channels; 177 uint32 buffer_length; /* size of buffer in samples */ 178 uint32 buffer_size; /* actual (aligned) size of buffer in bytes */ 179 uint32 sample_size; 180 uint8* buffers[STREAM_MAX_BUFFERS]; 181 /* Virtual addresses for buffer */ 182 phys_addr_t physical_buffers[STREAM_MAX_BUFFERS]; 183 /* Physical addresses for buffer */ 184 185 volatile bigtime_t real_time; 186 volatile uint64 frames_count; 187 uint32 last_link_frame_position; 188 volatile int32 buffer_cycle; 189 190 uint32 rate, bps; /* Samplerate & bits per sample */ 191 192 area_id buffer_area; 193 area_id buffer_descriptors_area; 194 phys_addr_t physical_buffer_descriptors; /* BDL physical address */ 195 196 int32 incorrect_position_count; 197 bool use_dma_position; 198 Read8hda_stream199 uint8 Read8(uint32 reg) 200 { 201 return controller->Read8(HDAC_STREAM_BASE + offset + reg); 202 } 203 Read16hda_stream204 uint16 Read16(uint32 reg) 205 { 206 return controller->Read16(HDAC_STREAM_BASE + offset + reg); 207 } 208 Read32hda_stream209 uint32 Read32(uint32 reg) 210 { 211 return controller->Read32(HDAC_STREAM_BASE + offset + reg); 212 } 213 Write8hda_stream214 void Write8(uint32 reg, uint8 value) 215 { 216 *(controller->regs + HDAC_STREAM_BASE + offset + reg) = value; 217 } 218 Write16hda_stream219 void Write16(uint32 reg, uint16 value) 220 { 221 *(vuint16*)(controller->regs + HDAC_STREAM_BASE + offset + reg) = value; 222 } 223 Write32hda_stream224 void Write32(uint32 reg, uint32 value) 225 { 226 *(vuint32*)(controller->regs + HDAC_STREAM_BASE + offset + reg) = value; 227 } 228 }; 229 230 struct hda_widget { 231 uint32 node_id; 232 233 uint32 num_inputs; 234 int32 active_input; 235 uint32 inputs[MAX_INPUTS]; 236 uint32 flags; 237 238 hda_widget_type type; 239 uint32 pm; 240 241 struct { 242 uint32 audio; 243 uint32 output_amplifier; 244 uint32 input_amplifier; 245 } capabilities; 246 247 union { 248 struct { 249 uint32 formats; 250 uint32 rates; 251 } io; 252 struct { 253 } mixer; 254 struct { 255 uint32 capabilities; 256 uint32 config; 257 } pin; 258 } d; 259 }; 260 261 struct hda_association { 262 uint32 index; 263 bool enabled; 264 uint32 pin_count; 265 uint32 pins[MAX_ASSOCIATION_PINS]; 266 }; 267 #endif 268 269 #define WIDGET_FLAG_OUTPUT_PATH 0x01 270 #define WIDGET_FLAG_INPUT_PATH 0x02 271 #define WIDGET_FLAG_WIDGET_PATH 0x04 272 273 /*! This structure describes a single Audio Function Group. An AFG 274 is a group of audio widgets which can be used to configure multiple 275 streams of audio either from the HDA Link to an output device (= playback) 276 or from an input device to the HDA link (= recording). 277 */ 278 #ifndef __REACTOS__ 279 struct hda_audio_group { 280 hda_codec* codec; 281 hda_widget widget; 282 283 /* Multi Audio API data */ 284 hda_stream* playback_stream; 285 hda_stream* record_stream; 286 287 uint32 widget_start; 288 uint32 widget_count; 289 290 uint32 association_count; 291 uint32 gpio; 292 293 hda_widget* widgets; 294 hda_association associations[MAX_ASSOCIATIONS]; 295 296 hda_multi* multi; 297 }; 298 299 /*! This structure describes a single codec module in the 300 HDA compliant device. This is a discrete component, which 301 can contain both Audio Function Groups, Modem Function Groups, 302 and other customized (vendor specific) Function Groups. 303 304 NOTE: ATM, only Audio Function Groups are supported. 305 */ 306 struct hda_codec { 307 uint16 vendor_id; 308 uint16 product_id; 309 uint8 major; 310 uint8 minor; 311 uint8 revision; 312 uint8 stepping; 313 uint8 addr; 314 315 uint32 quirks; 316 317 sem_id response_sem; 318 uint32 responses[MAX_CODEC_RESPONSES]; 319 uint32 response_count; 320 321 sem_id unsol_response_sem; 322 thread_id unsol_response_thread; 323 uint32 unsol_responses[MAX_CODEC_UNSOL_RESPONSES]; 324 uint32 unsol_response_read, unsol_response_write; 325 326 hda_audio_group* audio_groups[HDA_MAX_AUDIO_GROUPS]; 327 uint32 num_audio_groups; 328 329 struct hda_controller* controller; 330 }; 331 332 333 #define MULTI_CONTROL_FIRSTID 1024 334 #define MULTI_CONTROL_MASTERID 0 335 #define MULTI_MAX_CONTROLS 128 336 #define MULTI_MAX_CHANNELS 128 337 338 struct hda_multi_mixer_control { 339 hda_multi *multi; 340 int32 nid; 341 int32 type; 342 bool input; 343 uint32 mute; 344 uint32 gain; 345 uint32 capabilities; 346 int32 index; 347 multi_mix_control mix_control; 348 }; 349 350 351 struct hda_multi { 352 hda_audio_group *group; 353 hda_multi_mixer_control controls[MULTI_MAX_CONTROLS]; 354 uint32 control_count; 355 356 multi_channel_info chans[MULTI_MAX_CHANNELS]; 357 uint32 output_channel_count; 358 uint32 input_channel_count; 359 uint32 output_bus_channel_count; 360 uint32 input_bus_channel_count; 361 uint32 aux_bus_channel_count; 362 }; 363 364 365 /* driver.c */ 366 extern device_hooks gDriverHooks; 367 extern pci_module_info* gPci; 368 extern pci_x86_module_info* gPCIx86Module; 369 extern hda_controller gCards[MAX_CARDS]; 370 extern uint32 gNumCards; 371 372 /* hda_codec.c */ 373 const char* get_widget_location(uint32 location); 374 hda_widget* hda_audio_group_get_widget(hda_audio_group* audioGroup, uint32 nodeID); 375 376 status_t hda_audio_group_get_widgets(hda_audio_group* audioGroup, 377 hda_stream* stream); 378 hda_codec* hda_codec_new(hda_controller* controller, uint32 cad); 379 void hda_codec_delete(hda_codec* codec); 380 381 /* hda_multi_audio.c */ 382 status_t multi_audio_control(void* cookie, uint32 op, void* arg, size_t length); 383 384 /* hda_controller.c: Basic controller support */ 385 status_t hda_hw_init(hda_controller* controller); 386 void hda_hw_stop(hda_controller* controller); 387 void hda_hw_uninit(hda_controller* controller); 388 status_t hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, 389 uint32 count); 390 status_t hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload); 391 status_t hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32 *response); 392 393 /* hda_controller.c: Stream support */ 394 hda_stream* hda_stream_new(hda_audio_group* audioGroup, int type); 395 void hda_stream_delete(hda_stream* stream); 396 status_t hda_stream_setup_buffers(hda_audio_group* audioGroup, 397 hda_stream* stream, const char* desc); 398 status_t hda_stream_start(hda_controller* controller, hda_stream* stream); 399 status_t hda_stream_stop(hda_controller* controller, hda_stream* stream); 400 #endif 401 402 #endif /* _HDA_H_ */ 403