1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s 3 4define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 5; CHECK-LABEL: cmpeqz_v4i1: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vpt.i32 eq, q1, zr 8; CHECK-NEXT: vcmpt.i32 ne, q2, zr 9; CHECK-NEXT: vmrs r0, p0 10; CHECK-NEXT: vpt.i32 eq, q0, zr 11; CHECK-NEXT: vcmpt.i32 eq, q2, zr 12; CHECK-NEXT: vmrs r1, p0 13; CHECK-NEXT: orrs r0, r1 14; CHECK-NEXT: vmsr p0, r0 15; CHECK-NEXT: vpsel q0, q0, q1 16; CHECK-NEXT: bx lr 17entry: 18 %c1 = icmp eq <4 x i32> %a, zeroinitializer 19 %c2 = icmp eq <4 x i32> %b, zeroinitializer 20 %c3 = icmp eq <4 x i32> %c, zeroinitializer 21 %c4 = select <4 x i1> %c3, <4 x i1> %c1, <4 x i1> %c2 22 %s = select <4 x i1> %c4, <4 x i32> %a, <4 x i32> %b 23 ret <4 x i32> %s 24} 25 26define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 27; CHECK-LABEL: cmpeqz_v8i1: 28; CHECK: @ %bb.0: @ %entry 29; CHECK-NEXT: vpt.i16 eq, q1, zr 30; CHECK-NEXT: vcmpt.i16 ne, q2, zr 31; CHECK-NEXT: vmrs r0, p0 32; CHECK-NEXT: vpt.i16 eq, q0, zr 33; CHECK-NEXT: vcmpt.i16 eq, q2, zr 34; CHECK-NEXT: vmrs r1, p0 35; CHECK-NEXT: orrs r0, r1 36; CHECK-NEXT: vmsr p0, r0 37; CHECK-NEXT: vpsel q0, q0, q1 38; CHECK-NEXT: bx lr 39entry: 40 %c1 = icmp eq <8 x i16> %a, zeroinitializer 41 %c2 = icmp eq <8 x i16> %b, zeroinitializer 42 %c3 = icmp eq <8 x i16> %c, zeroinitializer 43 %c4 = select <8 x i1> %c3, <8 x i1> %c1, <8 x i1> %c2 44 %s = select <8 x i1> %c4, <8 x i16> %a, <8 x i16> %b 45 ret <8 x i16> %s 46} 47 48define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 49; CHECK-LABEL: cmpeqz_v16i1: 50; CHECK: @ %bb.0: @ %entry 51; CHECK-NEXT: vpt.i8 eq, q1, zr 52; CHECK-NEXT: vcmpt.i8 ne, q2, zr 53; CHECK-NEXT: vmrs r0, p0 54; CHECK-NEXT: vpt.i8 eq, q0, zr 55; CHECK-NEXT: vcmpt.i8 eq, q2, zr 56; CHECK-NEXT: vmrs r1, p0 57; CHECK-NEXT: orrs r0, r1 58; CHECK-NEXT: vmsr p0, r0 59; CHECK-NEXT: vpsel q0, q0, q1 60; CHECK-NEXT: bx lr 61entry: 62 %c1 = icmp eq <16 x i8> %a, zeroinitializer 63 %c2 = icmp eq <16 x i8> %b, zeroinitializer 64 %c3 = icmp eq <16 x i8> %c, zeroinitializer 65 %c4 = select <16 x i1> %c3, <16 x i1> %c1, <16 x i1> %c2 66 %s = select <16 x i1> %c4, <16 x i8> %a, <16 x i8> %b 67 ret <16 x i8> %s 68} 69 70define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { 71; CHECK-LABEL: cmpeqz_v2i1: 72; CHECK: @ %bb.0: @ %entry 73; CHECK-NEXT: .vsave {d8, d9} 74; CHECK-NEXT: vpush {d8, d9} 75; CHECK-NEXT: vmov r0, r1, d5 76; CHECK-NEXT: orrs r0, r1 77; CHECK-NEXT: vmov r1, r2, d4 78; CHECK-NEXT: cset r0, eq 79; CHECK-NEXT: cmp r0, #0 80; CHECK-NEXT: csetm r0, ne 81; CHECK-NEXT: orrs r1, r2 82; CHECK-NEXT: cset r1, eq 83; CHECK-NEXT: cmp r1, #0 84; CHECK-NEXT: csetm r1, ne 85; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 86; CHECK-NEXT: vmov q2[3], q2[1], r1, r0 87; CHECK-NEXT: vmov r0, r1, d3 88; CHECK-NEXT: orrs r0, r1 89; CHECK-NEXT: vmov r1, r2, d2 90; CHECK-NEXT: cset r0, eq 91; CHECK-NEXT: cmp r0, #0 92; CHECK-NEXT: csetm r0, ne 93; CHECK-NEXT: orrs r1, r2 94; CHECK-NEXT: cset r1, eq 95; CHECK-NEXT: cmp r1, #0 96; CHECK-NEXT: csetm r1, ne 97; CHECK-NEXT: vmov q3[2], q3[0], r1, r0 98; CHECK-NEXT: vmov q3[3], q3[1], r1, r0 99; CHECK-NEXT: vmov r0, r1, d1 100; CHECK-NEXT: vbic q3, q3, q2 101; CHECK-NEXT: orrs r0, r1 102; CHECK-NEXT: vmov r1, r2, d0 103; CHECK-NEXT: cset r0, eq 104; CHECK-NEXT: cmp r0, #0 105; CHECK-NEXT: csetm r0, ne 106; CHECK-NEXT: orrs r1, r2 107; CHECK-NEXT: cset r1, eq 108; CHECK-NEXT: cmp r1, #0 109; CHECK-NEXT: csetm r1, ne 110; CHECK-NEXT: vmov q4[2], q4[0], r1, r0 111; CHECK-NEXT: vmov q4[3], q4[1], r1, r0 112; CHECK-NEXT: vand q2, q4, q2 113; CHECK-NEXT: vorr q2, q2, q3 114; CHECK-NEXT: vbic q1, q1, q2 115; CHECK-NEXT: vand q0, q0, q2 116; CHECK-NEXT: vorr q0, q0, q1 117; CHECK-NEXT: vpop {d8, d9} 118; CHECK-NEXT: bx lr 119entry: 120 %c1 = icmp eq <2 x i64> %a, zeroinitializer 121 %c2 = icmp eq <2 x i64> %b, zeroinitializer 122 %c3 = icmp eq <2 x i64> %c, zeroinitializer 123 %c4 = select <2 x i1> %c3, <2 x i1> %c1, <2 x i1> %c2 124 %s = select <2 x i1> %c4, <2 x i64> %a, <2 x i64> %b 125 ret <2 x i64> %s 126} 127 128define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 129; CHECK-LABEL: cmpnez_v4i1: 130; CHECK: @ %bb.0: @ %entry 131; CHECK-NEXT: vpt.i32 ne, q1, zr 132; CHECK-NEXT: vcmpt.i32 eq, q2, zr 133; CHECK-NEXT: vmrs r0, p0 134; CHECK-NEXT: vpt.i32 ne, q0, zr 135; CHECK-NEXT: vcmpt.i32 ne, q2, zr 136; CHECK-NEXT: vmrs r1, p0 137; CHECK-NEXT: orrs r0, r1 138; CHECK-NEXT: vmsr p0, r0 139; CHECK-NEXT: vpsel q0, q0, q1 140; CHECK-NEXT: bx lr 141entry: 142 %c1 = icmp ne <4 x i32> %a, zeroinitializer 143 %c2 = icmp ne <4 x i32> %b, zeroinitializer 144 %c3 = icmp ne <4 x i32> %c, zeroinitializer 145 %c4 = select <4 x i1> %c3, <4 x i1> %c1, <4 x i1> %c2 146 %s = select <4 x i1> %c4, <4 x i32> %a, <4 x i32> %b 147 ret <4 x i32> %s 148} 149 150define arm_aapcs_vfpcc <8 x i16> @cmpnez_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 151; CHECK-LABEL: cmpnez_v8i1: 152; CHECK: @ %bb.0: @ %entry 153; CHECK-NEXT: vpt.i16 ne, q1, zr 154; CHECK-NEXT: vcmpt.i16 eq, q2, zr 155; CHECK-NEXT: vmrs r0, p0 156; CHECK-NEXT: vpt.i16 ne, q0, zr 157; CHECK-NEXT: vcmpt.i16 ne, q2, zr 158; CHECK-NEXT: vmrs r1, p0 159; CHECK-NEXT: orrs r0, r1 160; CHECK-NEXT: vmsr p0, r0 161; CHECK-NEXT: vpsel q0, q0, q1 162; CHECK-NEXT: bx lr 163entry: 164 %c1 = icmp ne <8 x i16> %a, zeroinitializer 165 %c2 = icmp ne <8 x i16> %b, zeroinitializer 166 %c3 = icmp ne <8 x i16> %c, zeroinitializer 167 %c4 = select <8 x i1> %c3, <8 x i1> %c1, <8 x i1> %c2 168 %s = select <8 x i1> %c4, <8 x i16> %a, <8 x i16> %b 169 ret <8 x i16> %s 170} 171 172define arm_aapcs_vfpcc <16 x i8> @cmpnez_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 173; CHECK-LABEL: cmpnez_v16i1: 174; CHECK: @ %bb.0: @ %entry 175; CHECK-NEXT: vpt.i8 ne, q1, zr 176; CHECK-NEXT: vcmpt.i8 eq, q2, zr 177; CHECK-NEXT: vmrs r0, p0 178; CHECK-NEXT: vpt.i8 ne, q0, zr 179; CHECK-NEXT: vcmpt.i8 ne, q2, zr 180; CHECK-NEXT: vmrs r1, p0 181; CHECK-NEXT: orrs r0, r1 182; CHECK-NEXT: vmsr p0, r0 183; CHECK-NEXT: vpsel q0, q0, q1 184; CHECK-NEXT: bx lr 185entry: 186 %c1 = icmp ne <16 x i8> %a, zeroinitializer 187 %c2 = icmp ne <16 x i8> %b, zeroinitializer 188 %c3 = icmp ne <16 x i8> %c, zeroinitializer 189 %c4 = select <16 x i1> %c3, <16 x i1> %c1, <16 x i1> %c2 190 %s = select <16 x i1> %c4, <16 x i8> %a, <16 x i8> %b 191 ret <16 x i8> %s 192} 193 194define arm_aapcs_vfpcc <2 x i64> @cmpnez_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { 195; CHECK-LABEL: cmpnez_v2i1: 196; CHECK: @ %bb.0: @ %entry 197; CHECK-NEXT: .vsave {d8, d9} 198; CHECK-NEXT: vpush {d8, d9} 199; CHECK-NEXT: vmov r0, r1, d5 200; CHECK-NEXT: orrs r0, r1 201; CHECK-NEXT: vmov r1, r2, d4 202; CHECK-NEXT: cset r0, ne 203; CHECK-NEXT: cmp r0, #0 204; CHECK-NEXT: csetm r0, ne 205; CHECK-NEXT: orrs r1, r2 206; CHECK-NEXT: cset r1, ne 207; CHECK-NEXT: cmp r1, #0 208; CHECK-NEXT: csetm r1, ne 209; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 210; CHECK-NEXT: vmov q2[3], q2[1], r1, r0 211; CHECK-NEXT: vmov r0, r1, d3 212; CHECK-NEXT: orrs r0, r1 213; CHECK-NEXT: vmov r1, r2, d2 214; CHECK-NEXT: cset r0, ne 215; CHECK-NEXT: cmp r0, #0 216; CHECK-NEXT: csetm r0, ne 217; CHECK-NEXT: orrs r1, r2 218; CHECK-NEXT: cset r1, ne 219; CHECK-NEXT: cmp r1, #0 220; CHECK-NEXT: csetm r1, ne 221; CHECK-NEXT: vmov q3[2], q3[0], r1, r0 222; CHECK-NEXT: vmov q3[3], q3[1], r1, r0 223; CHECK-NEXT: vmov r0, r1, d1 224; CHECK-NEXT: vbic q3, q3, q2 225; CHECK-NEXT: orrs r0, r1 226; CHECK-NEXT: vmov r1, r2, d0 227; CHECK-NEXT: cset r0, ne 228; CHECK-NEXT: cmp r0, #0 229; CHECK-NEXT: csetm r0, ne 230; CHECK-NEXT: orrs r1, r2 231; CHECK-NEXT: cset r1, ne 232; CHECK-NEXT: cmp r1, #0 233; CHECK-NEXT: csetm r1, ne 234; CHECK-NEXT: vmov q4[2], q4[0], r1, r0 235; CHECK-NEXT: vmov q4[3], q4[1], r1, r0 236; CHECK-NEXT: vand q2, q4, q2 237; CHECK-NEXT: vorr q2, q2, q3 238; CHECK-NEXT: vbic q1, q1, q2 239; CHECK-NEXT: vand q0, q0, q2 240; CHECK-NEXT: vorr q0, q0, q1 241; CHECK-NEXT: vpop {d8, d9} 242; CHECK-NEXT: bx lr 243entry: 244 %c1 = icmp ne <2 x i64> %a, zeroinitializer 245 %c2 = icmp ne <2 x i64> %b, zeroinitializer 246 %c3 = icmp ne <2 x i64> %c, zeroinitializer 247 %c4 = select <2 x i1> %c3, <2 x i1> %c1, <2 x i1> %c2 248 %s = select <2 x i1> %c4, <2 x i64> %a, <2 x i64> %b 249 ret <2 x i64> %s 250} 251 252 253 254define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 255; CHECK-LABEL: cmpsltz_v4i1: 256; CHECK: @ %bb.0: @ %entry 257; CHECK-NEXT: vpt.s32 lt, q1, zr 258; CHECK-NEXT: vcmpt.s32 ge, q2, zr 259; CHECK-NEXT: vmrs r0, p0 260; CHECK-NEXT: vpt.s32 lt, q0, zr 261; CHECK-NEXT: vcmpt.s32 lt, q2, zr 262; CHECK-NEXT: vmrs r1, p0 263; CHECK-NEXT: orrs r0, r1 264; CHECK-NEXT: vmsr p0, r0 265; CHECK-NEXT: vpsel q0, q0, q1 266; CHECK-NEXT: bx lr 267entry: 268 %c1 = icmp slt <4 x i32> %a, zeroinitializer 269 %c2 = icmp slt <4 x i32> %b, zeroinitializer 270 %c3 = icmp slt <4 x i32> %c, zeroinitializer 271 %c4 = select <4 x i1> %c3, <4 x i1> %c1, <4 x i1> %c2 272 %s = select <4 x i1> %c4, <4 x i32> %a, <4 x i32> %b 273 ret <4 x i32> %s 274} 275 276define arm_aapcs_vfpcc <8 x i16> @cmpsltz_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 277; CHECK-LABEL: cmpsltz_v8i1: 278; CHECK: @ %bb.0: @ %entry 279; CHECK-NEXT: vpt.s16 lt, q1, zr 280; CHECK-NEXT: vcmpt.s16 ge, q2, zr 281; CHECK-NEXT: vmrs r0, p0 282; CHECK-NEXT: vpt.s16 lt, q0, zr 283; CHECK-NEXT: vcmpt.s16 lt, q2, zr 284; CHECK-NEXT: vmrs r1, p0 285; CHECK-NEXT: orrs r0, r1 286; CHECK-NEXT: vmsr p0, r0 287; CHECK-NEXT: vpsel q0, q0, q1 288; CHECK-NEXT: bx lr 289entry: 290 %c1 = icmp slt <8 x i16> %a, zeroinitializer 291 %c2 = icmp slt <8 x i16> %b, zeroinitializer 292 %c3 = icmp slt <8 x i16> %c, zeroinitializer 293 %c4 = select <8 x i1> %c3, <8 x i1> %c1, <8 x i1> %c2 294 %s = select <8 x i1> %c4, <8 x i16> %a, <8 x i16> %b 295 ret <8 x i16> %s 296} 297 298define arm_aapcs_vfpcc <16 x i8> @cmpsltz_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 299; CHECK-LABEL: cmpsltz_v16i1: 300; CHECK: @ %bb.0: @ %entry 301; CHECK-NEXT: vpt.s8 lt, q1, zr 302; CHECK-NEXT: vcmpt.s8 ge, q2, zr 303; CHECK-NEXT: vmrs r0, p0 304; CHECK-NEXT: vpt.s8 lt, q0, zr 305; CHECK-NEXT: vcmpt.s8 lt, q2, zr 306; CHECK-NEXT: vmrs r1, p0 307; CHECK-NEXT: orrs r0, r1 308; CHECK-NEXT: vmsr p0, r0 309; CHECK-NEXT: vpsel q0, q0, q1 310; CHECK-NEXT: bx lr 311entry: 312 %c1 = icmp slt <16 x i8> %a, zeroinitializer 313 %c2 = icmp slt <16 x i8> %b, zeroinitializer 314 %c3 = icmp slt <16 x i8> %c, zeroinitializer 315 %c4 = select <16 x i1> %c3, <16 x i1> %c1, <16 x i1> %c2 316 %s = select <16 x i1> %c4, <16 x i8> %a, <16 x i8> %b 317 ret <16 x i8> %s 318} 319 320define arm_aapcs_vfpcc <2 x i64> @cmpsltz_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { 321; CHECK-LABEL: cmpsltz_v2i1: 322; CHECK: @ %bb.0: @ %entry 323; CHECK-NEXT: .vsave {d8, d9} 324; CHECK-NEXT: vpush {d8, d9} 325; CHECK-NEXT: vmov r0, s11 326; CHECK-NEXT: vmov r1, s9 327; CHECK-NEXT: asrs r0, r0, #31 328; CHECK-NEXT: asrs r1, r1, #31 329; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 330; CHECK-NEXT: vmov q2[3], q2[1], r1, r0 331; CHECK-NEXT: vmov r0, s7 332; CHECK-NEXT: vmov r1, s5 333; CHECK-NEXT: asrs r0, r0, #31 334; CHECK-NEXT: asrs r1, r1, #31 335; CHECK-NEXT: vmov q3[2], q3[0], r1, r0 336; CHECK-NEXT: vmov q3[3], q3[1], r1, r0 337; CHECK-NEXT: vmov r0, s3 338; CHECK-NEXT: vmov r1, s1 339; CHECK-NEXT: vbic q3, q3, q2 340; CHECK-NEXT: asrs r0, r0, #31 341; CHECK-NEXT: asrs r1, r1, #31 342; CHECK-NEXT: vmov q4[2], q4[0], r1, r0 343; CHECK-NEXT: vmov q4[3], q4[1], r1, r0 344; CHECK-NEXT: vand q2, q4, q2 345; CHECK-NEXT: vorr q2, q2, q3 346; CHECK-NEXT: vbic q1, q1, q2 347; CHECK-NEXT: vand q0, q0, q2 348; CHECK-NEXT: vorr q0, q0, q1 349; CHECK-NEXT: vpop {d8, d9} 350; CHECK-NEXT: bx lr 351entry: 352 %c1 = icmp slt <2 x i64> %a, zeroinitializer 353 %c2 = icmp slt <2 x i64> %b, zeroinitializer 354 %c3 = icmp slt <2 x i64> %c, zeroinitializer 355 %c4 = select <2 x i1> %c3, <2 x i1> %c1, <2 x i1> %c2 356 %s = select <2 x i1> %c4, <2 x i64> %a, <2 x i64> %b 357 ret <2 x i64> %s 358} 359 360 361 362define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1_i1(<4 x i32> %a, <4 x i32> %b, i32 %c) { 363; CHECK-LABEL: cmpeqz_v4i1_i1: 364; CHECK: @ %bb.0: @ %entry 365; CHECK-NEXT: cbz r0, .LBB12_2 366; CHECK-NEXT: @ %bb.1: @ %select.false 367; CHECK-NEXT: vcmp.i32 eq, q1, zr 368; CHECK-NEXT: vpsel q0, q0, q1 369; CHECK-NEXT: bx lr 370; CHECK-NEXT: .LBB12_2: 371; CHECK-NEXT: vcmp.i32 eq, q0, zr 372; CHECK-NEXT: vpsel q0, q0, q1 373; CHECK-NEXT: bx lr 374entry: 375 %c1 = icmp eq <4 x i32> %a, zeroinitializer 376 %c2 = icmp eq <4 x i32> %b, zeroinitializer 377 %c3 = icmp eq i32 %c, 0 378 %c4 = select i1 %c3, <4 x i1> %c1, <4 x i1> %c2 379 %s = select <4 x i1> %c4, <4 x i32> %a, <4 x i32> %b 380 ret <4 x i32> %s 381} 382 383define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1_i1(<8 x i16> %a, <8 x i16> %b, i16 %c) { 384; CHECK-LABEL: cmpeqz_v8i1_i1: 385; CHECK: @ %bb.0: @ %entry 386; CHECK-NEXT: lsls r0, r0, #16 387; CHECK-NEXT: beq .LBB13_2 388; CHECK-NEXT: @ %bb.1: @ %select.false 389; CHECK-NEXT: vcmp.i16 eq, q1, zr 390; CHECK-NEXT: vpsel q0, q0, q1 391; CHECK-NEXT: bx lr 392; CHECK-NEXT: .LBB13_2: 393; CHECK-NEXT: vcmp.i16 eq, q0, zr 394; CHECK-NEXT: vpsel q0, q0, q1 395; CHECK-NEXT: bx lr 396entry: 397 %c1 = icmp eq <8 x i16> %a, zeroinitializer 398 %c2 = icmp eq <8 x i16> %b, zeroinitializer 399 %c3 = icmp eq i16 %c, 0 400 %c4 = select i1 %c3, <8 x i1> %c1, <8 x i1> %c2 401 %s = select <8 x i1> %c4, <8 x i16> %a, <8 x i16> %b 402 ret <8 x i16> %s 403} 404 405define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1_i1(<16 x i8> %a, <16 x i8> %b, i8 %c) { 406; CHECK-LABEL: cmpeqz_v16i1_i1: 407; CHECK: @ %bb.0: @ %entry 408; CHECK-NEXT: lsls r0, r0, #24 409; CHECK-NEXT: beq .LBB14_2 410; CHECK-NEXT: @ %bb.1: @ %select.false 411; CHECK-NEXT: vcmp.i8 eq, q1, zr 412; CHECK-NEXT: vpsel q0, q0, q1 413; CHECK-NEXT: bx lr 414; CHECK-NEXT: .LBB14_2: 415; CHECK-NEXT: vcmp.i8 eq, q0, zr 416; CHECK-NEXT: vpsel q0, q0, q1 417; CHECK-NEXT: bx lr 418entry: 419 %c1 = icmp eq <16 x i8> %a, zeroinitializer 420 %c2 = icmp eq <16 x i8> %b, zeroinitializer 421 %c3 = icmp eq i8 %c, 0 422 %c4 = select i1 %c3, <16 x i1> %c1, <16 x i1> %c2 423 %s = select <16 x i1> %c4, <16 x i8> %a, <16 x i8> %b 424 ret <16 x i8> %s 425} 426 427define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1_i1(<2 x i64> %a, <2 x i64> %b, i64 %c) { 428; CHECK-LABEL: cmpeqz_v2i1_i1: 429; CHECK: @ %bb.0: @ %entry 430; CHECK-NEXT: .save {r4, lr} 431; CHECK-NEXT: push {r4, lr} 432; CHECK-NEXT: vmov r2, r3, d3 433; CHECK-NEXT: orrs r2, r3 434; CHECK-NEXT: cset r2, eq 435; CHECK-NEXT: cmp r2, #0 436; CHECK-NEXT: vmov r2, r3, d2 437; CHECK-NEXT: csetm r12, ne 438; CHECK-NEXT: orrs r2, r3 439; CHECK-NEXT: cset r2, eq 440; CHECK-NEXT: cmp r2, #0 441; CHECK-NEXT: vmov r2, r3, d1 442; CHECK-NEXT: csetm r4, ne 443; CHECK-NEXT: orrs r2, r3 444; CHECK-NEXT: cset r2, eq 445; CHECK-NEXT: cmp r2, #0 446; CHECK-NEXT: vmov r2, r3, d0 447; CHECK-NEXT: csetm lr, ne 448; CHECK-NEXT: orrs r2, r3 449; CHECK-NEXT: cset r2, eq 450; CHECK-NEXT: cmp r2, #0 451; CHECK-NEXT: csetm r2, ne 452; CHECK-NEXT: orrs r0, r1 453; CHECK-NEXT: beq .LBB15_2 454; CHECK-NEXT: @ %bb.1: @ %select.false 455; CHECK-NEXT: vmov q2[2], q2[0], r4, r12 456; CHECK-NEXT: vmov q2[3], q2[1], r4, r12 457; CHECK-NEXT: b .LBB15_3 458; CHECK-NEXT: .LBB15_2: 459; CHECK-NEXT: vmov q2[2], q2[0], r2, lr 460; CHECK-NEXT: vmov q2[3], q2[1], r2, lr 461; CHECK-NEXT: .LBB15_3: @ %select.end 462; CHECK-NEXT: vmov r0, s10 463; CHECK-NEXT: vmov r1, s8 464; CHECK-NEXT: and r0, r0, #1 465; CHECK-NEXT: and r1, r1, #1 466; CHECK-NEXT: rsbs r0, r0, #0 467; CHECK-NEXT: rsbs r1, r1, #0 468; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 469; CHECK-NEXT: vmov q2[3], q2[1], r1, r0 470; CHECK-NEXT: vbic q1, q1, q2 471; CHECK-NEXT: vand q0, q0, q2 472; CHECK-NEXT: vorr q0, q0, q1 473; CHECK-NEXT: pop {r4, pc} 474entry: 475 %c1 = icmp eq <2 x i64> %a, zeroinitializer 476 %c2 = icmp eq <2 x i64> %b, zeroinitializer 477 %c3 = icmp eq i64 %c, zeroinitializer 478 %c4 = select i1 %c3, <2 x i1> %c1, <2 x i1> %c2 479 %s = select <2 x i1> %c4, <2 x i64> %a, <2 x i64> %b 480 ret <2 x i64> %s 481} 482