1 //===- FunctionLoweringInfo.h - Lower functions from LLVM IR ---*- C++ -*--===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This implements routines for translating functions from LLVM IR into 10 // Machine IR. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H 15 #define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H 16 17 #include "llvm/ADT/BitVector.h" 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/ADT/IndexedMap.h" 20 #include "llvm/ADT/Optional.h" 21 #include "llvm/ADT/SmallPtrSet.h" 22 #include "llvm/ADT/SmallVector.h" 23 #include "llvm/CodeGen/ISDOpcodes.h" 24 #include "llvm/CodeGen/MachineBasicBlock.h" 25 #include "llvm/CodeGen/TargetRegisterInfo.h" 26 #include "llvm/IR/Instructions.h" 27 #include "llvm/IR/Type.h" 28 #include "llvm/IR/Value.h" 29 #include "llvm/Support/KnownBits.h" 30 #include <cassert> 31 #include <utility> 32 #include <vector> 33 34 namespace llvm { 35 36 class Argument; 37 class BasicBlock; 38 class BranchProbabilityInfo; 39 class LegacyDivergenceAnalysis; 40 class Function; 41 class Instruction; 42 class MachineFunction; 43 class MachineInstr; 44 class MachineRegisterInfo; 45 class MVT; 46 class SelectionDAG; 47 class TargetLowering; 48 49 //===--------------------------------------------------------------------===// 50 /// FunctionLoweringInfo - This contains information that is global to a 51 /// function that is used when lowering a region of the function. 52 /// 53 class FunctionLoweringInfo { 54 public: 55 const Function *Fn; 56 MachineFunction *MF; 57 const TargetLowering *TLI; 58 MachineRegisterInfo *RegInfo; 59 BranchProbabilityInfo *BPI; 60 const LegacyDivergenceAnalysis *DA; 61 /// CanLowerReturn - true iff the function's return value can be lowered to 62 /// registers. 63 bool CanLowerReturn; 64 65 /// True if part of the CSRs will be handled via explicit copies. 66 bool SplitCSR; 67 68 /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg 69 /// allocated to hold a pointer to the hidden sret parameter. 70 Register DemoteRegister; 71 72 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry. 73 DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap; 74 75 /// ValueMap - Since we emit code for the function a basic block at a time, 76 /// we must remember which virtual registers hold the values for 77 /// cross-basic-block values. 78 DenseMap<const Value *, Register> ValueMap; 79 80 /// VirtReg2Value map is needed by the Divergence Analysis driven 81 /// instruction selection. It is reverted ValueMap. It is computed 82 /// in lazy style - on demand. It is used to get the Value corresponding 83 /// to the live in virtual register and is called from the 84 /// TargetLowerinInfo::isSDNodeSourceOfDivergence. 85 DenseMap<Register, const Value*> VirtReg2Value; 86 87 /// This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence 88 /// to get the Value corresponding to the live-in virtual register. 89 const Value *getValueFromVirtualReg(Register Vreg); 90 91 /// Track virtual registers created for exception pointers. 92 DenseMap<const Value *, Register> CatchPadExceptionPointers; 93 94 /// Helper object to track which of three possible relocation mechanisms are 95 /// used for a particular value being relocated over a statepoint. 96 struct StatepointRelocationRecord { 97 enum RelocType { 98 // Value did not need to be relocated and can be used directly. 99 NoRelocate, 100 // Value was spilled to stack and needs filled at the gc.relocate. 101 Spill, 102 // Value was lowered to tied def and gc.relocate should be replaced with 103 // copy from vreg. 104 VReg, 105 } type = NoRelocate; 106 // Payload contains either frame index of the stack slot in which the value 107 // was spilled, or virtual register which contains the re-definition. 108 union payload_t { payload_t()109 payload_t() : FI(-1) {} 110 int FI; 111 Register Reg; 112 } payload; 113 }; 114 115 /// Keep track of each value which was relocated and the strategy used to 116 /// relocate that value. This information is required when visiting 117 /// gc.relocates which may appear in following blocks. 118 using StatepointSpillMapTy = 119 DenseMap<const Value *, StatepointRelocationRecord>; 120 DenseMap<const Instruction *, StatepointSpillMapTy> StatepointRelocationMaps; 121 122 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in 123 /// the entry block. This allows the allocas to be efficiently referenced 124 /// anywhere in the function. 125 DenseMap<const AllocaInst*, int> StaticAllocaMap; 126 127 /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments. 128 DenseMap<const Argument*, int> ByValArgFrameIndexMap; 129 130 /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for 131 /// function arguments that are inserted after scheduling is completed. 132 SmallVector<MachineInstr*, 8> ArgDbgValues; 133 134 /// Bitvector with a bit set if corresponding argument is described in 135 /// ArgDbgValues. Using arg numbers according to Argument numbering. 136 BitVector DescribedArgs; 137 138 /// RegFixups - Registers which need to be replaced after isel is done. 139 DenseMap<Register, Register> RegFixups; 140 141 DenseSet<Register> RegsWithFixups; 142 143 /// StatepointStackSlots - A list of temporary stack slots (frame indices) 144 /// used to spill values at a statepoint. We store them here to enable 145 /// reuse of the same stack slots across different statepoints in different 146 /// basic blocks. 147 SmallVector<unsigned, 50> StatepointStackSlots; 148 149 /// MBB - The current block. 150 MachineBasicBlock *MBB; 151 152 /// MBB - The current insert position inside the current block. 153 MachineBasicBlock::iterator InsertPt; 154 155 struct LiveOutInfo { 156 unsigned NumSignBits : 31; 157 unsigned IsValid : 1; 158 KnownBits Known = 1; 159 LiveOutInfoLiveOutInfo160 LiveOutInfo() : NumSignBits(0), IsValid(true) {} 161 }; 162 163 /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND) 164 /// for a value. 165 DenseMap<const Value *, ISD::NodeType> PreferredExtendType; 166 167 /// VisitedBBs - The set of basic blocks visited thus far by instruction 168 /// selection. 169 SmallPtrSet<const BasicBlock*, 4> VisitedBBs; 170 171 /// PHINodesToUpdate - A list of phi instructions whose operand list will 172 /// be updated after processing the current basic block. 173 /// TODO: This isn't per-function state, it's per-basic-block state. But 174 /// there's no other convenient place for it to live right now. 175 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; 176 unsigned OrigNumPHINodesToUpdate; 177 178 /// If the current MBB is a landing pad, the exception pointer and exception 179 /// selector registers are copied into these virtual registers by 180 /// SelectionDAGISel::PrepareEHLandingPad(). 181 unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg; 182 183 /// set - Initialize this FunctionLoweringInfo with the given Function 184 /// and its associated MachineFunction. 185 /// 186 void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG); 187 188 /// clear - Clear out all the function-specific state. This returns this 189 /// FunctionLoweringInfo to an empty state, ready to be used for a 190 /// different function. 191 void clear(); 192 193 /// isExportedInst - Return true if the specified value is an instruction 194 /// exported from its block. isExportedInst(const Value * V)195 bool isExportedInst(const Value *V) const { 196 return ValueMap.count(V); 197 } 198 199 Register CreateReg(MVT VT, bool isDivergent = false); 200 201 Register CreateRegs(const Value *V); 202 203 Register CreateRegs(Type *Ty, bool isDivergent = false); 204 InitializeRegForValue(const Value * V)205 Register InitializeRegForValue(const Value *V) { 206 // Tokens never live in vregs. 207 if (V->getType()->isTokenTy()) 208 return 0; 209 Register &R = ValueMap[V]; 210 assert(R == 0 && "Already initialized this value register!"); 211 assert(VirtReg2Value.empty()); 212 return R = CreateRegs(V); 213 } 214 215 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the 216 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. GetLiveOutRegInfo(Register Reg)217 const LiveOutInfo *GetLiveOutRegInfo(Register Reg) { 218 if (!LiveOutRegInfo.inBounds(Reg)) 219 return nullptr; 220 221 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg]; 222 if (!LOI->IsValid) 223 return nullptr; 224 225 return LOI; 226 } 227 228 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the 229 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If 230 /// the register's LiveOutInfo is for a smaller bit width, it is extended to 231 /// the larger bit width by zero extension. The bit width must be no smaller 232 /// than the LiveOutInfo's existing bit width. 233 const LiveOutInfo *GetLiveOutRegInfo(Register Reg, unsigned BitWidth); 234 235 /// AddLiveOutRegInfo - Adds LiveOutInfo for a register. AddLiveOutRegInfo(Register Reg,unsigned NumSignBits,const KnownBits & Known)236 void AddLiveOutRegInfo(Register Reg, unsigned NumSignBits, 237 const KnownBits &Known) { 238 // Only install this information if it tells us something. 239 if (NumSignBits == 1 && Known.isUnknown()) 240 return; 241 242 LiveOutRegInfo.grow(Reg); 243 LiveOutInfo &LOI = LiveOutRegInfo[Reg]; 244 LOI.NumSignBits = NumSignBits; 245 LOI.Known.One = Known.One; 246 LOI.Known.Zero = Known.Zero; 247 } 248 249 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination 250 /// register based on the LiveOutInfo of its operands. 251 void ComputePHILiveOutRegInfo(const PHINode*); 252 253 /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be 254 /// called when a block is visited before all of its predecessors. InvalidatePHILiveOutRegInfo(const PHINode * PN)255 void InvalidatePHILiveOutRegInfo(const PHINode *PN) { 256 // PHIs with no uses have no ValueMap entry. 257 DenseMap<const Value*, Register>::const_iterator It = ValueMap.find(PN); 258 if (It == ValueMap.end()) 259 return; 260 261 Register Reg = It->second; 262 if (Reg == 0) 263 return; 264 265 LiveOutRegInfo.grow(Reg); 266 LiveOutRegInfo[Reg].IsValid = false; 267 } 268 269 /// setArgumentFrameIndex - Record frame index for the byval 270 /// argument. 271 void setArgumentFrameIndex(const Argument *A, int FI); 272 273 /// getArgumentFrameIndex - Get frame index for the byval argument. 274 int getArgumentFrameIndex(const Argument *A); 275 276 Register getCatchPadExceptionPointerVReg(const Value *CPI, 277 const TargetRegisterClass *RC); 278 279 private: 280 /// LiveOutRegInfo - Information about live out vregs. 281 IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo; 282 }; 283 284 } // end namespace llvm 285 286 #endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H 287