1 /* $OpenBSD: mb89352reg.h,v 1.5 2021/03/11 11:16:58 jsg Exp $ */ 2 /* $NetBSD: mb89352reg.h,v 1.3 2003/08/07 16:31:02 agc Exp $ */ 3 /* NecBSD: mb89352reg.h,v 1.3 1998/03/14 07:04:34 kmatsuda Exp */ 4 5 /*- 6 * Copyright (c) 1990, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda. 11 * 12 * This code is derived from software contributed to Berkeley by 13 * Van Jacobson of Lawrence Berkeley Laboratory. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsireg.h 8.1 (Berkeley) 6/10/93 40 */ 41 42 /*- 43 * Copyright (c) 1996,97,98,99 The NetBSD Foundation, Inc. 44 * All rights reserved. 45 * 46 * This code is derived from software contributed to The NetBSD Foundation 47 * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda. 48 * 49 * This code is derived from software contributed to Berkeley by 50 * Van Jacobson of Lawrence Berkeley Laboratory. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)scsireg.h 8.1 (Berkeley) 6/10/93 74 */ 75 /* 76 * [NetBSD for NEC PC-98 series] 77 * Copyright (c) 1996, 1997, 1998 78 * NetBSD/pc98 porting staff. All rights reserved. 79 * Copyright (c) 1996, 1997, 1998 80 * Kouichi Matsuda. All rights reserved. 81 */ 82 83 /* 84 * FUJITSU MB89352A SCSI Protocol Controller Hardware Description. 85 */ 86 87 /* Definitions, most of them have turned out to be unnecessary, but here they 88 * are anyway. 89 */ 90 91 #define BDID 0x00 /* Bus Device ID (R/W) */ 92 #define SCTL 0x01 /* SPC Control register (R/W) */ 93 #define SCMD 0x02 /* Command Register (R/W) */ 94 #define TMOD 0x03 /* Transmit Mode Register (synch models) */ 95 #define INTS 0x04 /* Interrupt sense (R); Interrupt Reset (W) */ 96 #define PSNS 0x05 /* Phase Sense (R); SPC Diagnostic Control (W) */ 97 #define SSTS 0x06 /* SPC status (R/O) */ 98 #define SERR 0x07 /* SPC error status (R/O) */ 99 #define PCTL 0x08 /* Phase Control (R/W) */ 100 #define MBC 0x09 /* Modified Byte Counter (R/O) */ 101 #define DREG 0x0a /* Data Register (R/W) */ 102 #define TEMP 0x0b /* Temporary Register (R/W) */ 103 #define TCH 0x0c /* Transfer Counter High (R/W) */ 104 #define TCM 0x0d /* Transfer Counter Middle (R/W) */ 105 #define TCL 0x0e /* Transfer Counter Low (R/W) */ 106 #define EXBF 0x0f /* External Buffer (synch models) */ 107 108 /* What all the bits do */ 109 110 /* SCSI_BDID */ 111 /* SCSI selection/reselection ID (both target *and* initiator) */ 112 #define SELID7 0x80 113 #define SELID6 0x40 114 #define SELID5 0x20 115 #define SELID4 0x10 116 #define SELID3 0x08 117 #define SELID2 0x04 118 #define SELID1 0x02 119 #define SELID0 0x01 120 121 /* SCSI_SCTL */ 122 #define SCTL_DISABLE 0x80 123 #define SCTL_CTRLRST 0x40 124 #define SCTL_DIAG 0x20 125 #define SCTL_ABRT_ENAB 0x10 126 #define SCTL_PARITY_ENAB 0x08 127 #define SCTL_SEL_ENAB 0x04 128 #define SCTL_RESEL_ENAB 0x02 129 #define SCTL_INTR_ENAB 0x01 130 131 /* SCSI_SCMD */ 132 #define SCMD_RST 0x10 133 #define SCMD_ICPT_XFR 0x08 134 #define SCMD_PROG_XFR 0x04 135 #define SCMD_PAD 0x01 /* if initiator */ 136 #define SCMD_PERR_STOP 0x01 /* if target */ 137 /* command codes */ 138 #define SCMD_BUS_REL 0x00 139 #define SCMD_SELECT 0x20 140 #define SCMD_RST_ATN 0x40 141 #define SCMD_SET_ATN 0x60 142 #define SCMD_XFR 0x80 143 #define SCMD_XFR_PAUSE 0xa0 144 #define SCMD_RST_ACK 0xc0 145 #define SCMD_SET_ACK 0xe0 146 147 /* SCSI_TMOD */ 148 #define TMOD_SYNC 0x80 149 150 /* SCSI_INTS */ 151 #define INTS_SEL 0x80 152 #define INTS_RESEL 0x40 153 #define INTS_DISCON 0x20 154 #define INTS_CMD_DONE 0x10 155 #define INTS_SRV_REQ 0x08 156 #define INTS_TIMEOUT 0x04 157 #define INTS_HARD_ERR 0x02 158 #define INTS_RST 0x01 159 160 /* SCSI_PSNS */ 161 #define PSNS_REQ 0x80 162 #define PSNS_ACK 0x40 163 #define PSNS_ATN 0x20 164 #define PSNS_SEL 0x10 165 #define PSNS_BSY 0x08 166 167 /* PSNS */ 168 #define REQI 0x80 169 #define ACKI 0x40 170 #define ATNI 0x20 171 #define SELI 0x10 172 #define BSYI 0x08 173 #define MSGI 0x04 174 #define CDI 0x02 175 #define IOI 0x01 176 177 /* Important! The 3 most significant bits of this register, in initiator mode, 178 * represents the "expected" SCSI bus phase and can be used to trigger phase 179 * mismatch and phase change interrupts. But more important: If there is a 180 * phase mismatch the chip will not transfer any data! This is actually a nice 181 * feature as it gives us a bit more control over what is happening when we are 182 * bursting data (in) through the FIFOs and the phase suddenly changes from 183 * DATA IN to STATUS or MESSAGE IN. The transfer will stop and wait for the 184 * proper phase to be set in this register instead of dumping the bits into the 185 * FIFOs. 186 */ 187 #if 0 188 #define REQO 0x80 189 #define ACKO 0x40 190 #define ATNO 0x20 191 #define SELO 0x10 192 #define BSYO 0x08 193 #endif 194 /* PCTL */ 195 #define MSGO 0x04 196 #define CDO 0x02 197 #define IOO 0x01 198 199 /* Information transfer phases */ 200 #define PH_DATAOUT (0) 201 #define PH_DATAIN (IOI) 202 #define PH_CMD (CDI) 203 #define PH_STAT (CDI | IOI) 204 #define PH_MSGOUT (MSGI | CDI) 205 #define PH_MSGIN (MSGI | CDI | IOI) 206 207 #define PH_MASK (MSGI | CDI | IOI) 208 209 #define PH_INVALID 0xff 210 211 /* SCSI_SSTS */ 212 #define SSTS_INITIATOR 0x80 213 #define SSTS_TARGET 0x40 214 #define SSTS_BUSY 0x20 215 #define SSTS_XFR 0x10 216 #define SSTS_ACTIVE (SSTS_INITIATOR|SSTS_XFR) 217 #define SSTS_RST 0x08 218 #define SSTS_TCZERO 0x04 219 #define SSTS_DREG_FULL 0x02 220 #define SSTS_DREG_EMPTY 0x01 221 222 /* SCSI_SERR */ 223 #define SERR_SCSI_PAR 0x80 224 #define SERR_SPC_PAR 0x40 225 #define SERR_TC_PAR 0x08 226 #define SERR_PHASE_ERR 0x04 227 #define SERR_SHORT_XFR 0x02 228 #define SERR_OFFSET 0x01 229 230 /* SCSI_PCTL */ 231 #define PCTL_BFINT_ENAB 0x80 232