1 #ifndef _COREMCTL_REG_H_ 2 #define _COREMCTL_REG_H_ 3 4 #ifndef _SYS_BITOPS_H_ 5 #include <sys/bitops.h> 6 #endif 7 8 #define PCI_CORE_MEMCTL_CHN_MAX 2 9 #define PCI_CORE_MEMCTL_CHN_DIMM_MAX 2 10 11 #define PCI_CORE_MEMCTL_VID 0x8086 12 #define PCI_E3V1_MEMCTL_DID 0x0108 13 #define PCI_E3V2_MEMCTL_DID 0x0158 14 #define PCI_E3V3_MEMCTL_DID 0x0c08 15 #define PCI_COREV3_MEMCTL_DID 0x0c00 16 17 #define PCI_CORE_MCHBAR_LO 0x48 18 #define PCI_CORE_MCHBAR_LO_EN 0x1 19 #define PCI_CORE_MCHBAR_HI 0x4c 20 21 #define PCI_E3_ERRSTS 0xc8 22 #define PCI_E3_ERRSTS_DMERR __BIT(1) 23 #define PCI_E3_ERRSTS_DSERR __BIT(0) 24 25 #define PCI_CORE_CAPID0_A 0xe4 26 #define PCI_CORE_CAPID0_A_DMFC __BITS(0, 2) /* v1 */ 27 #define PCI_CORE_CAPID0_A_ECCDIS __BIT(25) 28 29 #define PCI_CORE_CAPID0_B 0xe8 30 #define PCI_CORE_CAPID0_B_DMFC __BITS(4, 6) /* v2/v3 */ 31 32 #define PCI_CORE_CAPID0_DMFC_V1_ALL 0x0 /* v1 */ 33 #define PCI_CORE_CAPID0_DMFC_2933 0x0 /* v2/v3 */ 34 #define PCI_CORE_CAPID0_DMFC_2667 0x1 /* v2/v3 */ 35 #define PCI_CORE_CAPID0_DMFC_2400 0x2 /* v2/v3 */ 36 #define PCI_CORE_CAPID0_DMFC_2133 0x3 /* v2/v3 */ 37 #define PCI_CORE_CAPID0_DMFC_1867 0x4 /* v2/v3 */ 38 #define PCI_CORE_CAPID0_DMFC_1600 0x5 /* v2/v3 */ 39 #define PCI_CORE_CAPID0_DMFC_1333 0x6 40 #define PCI_CORE_CAPID0_DMFC_1067 0x7 41 42 #define PCI_CORE_MCHBAR_ADDRMASK __BITS64(15, 38) 43 44 #define MCH_CORE_SIZE (32 * 1024) 45 46 #define MCH_E3_ERRLOG0_C0 0x40c8 47 #define MCH_E3_ERRLOG1_C0 0x40cc 48 49 #define MCH_E3_ERRLOG0_C1 0x44c8 50 #define MCH_E3_ERRLOG1_C1 0x44cc 51 52 #define MCH_E3_ERRLOG0_CERRSTS __BIT(0) 53 #define MCH_E3_ERRLOG0_MERRSTS __BIT(1) 54 #define MCH_E3_ERRLOG0_ERRSYND __BITS(16, 23) 55 #define MCH_E3_ERRLOG0_ERRCHUNK __BITS(24, 26) 56 #define MCH_E3_ERRLOG0_ERRRANK __BITS(27, 28) 57 #define MCH_E3_ERRLOG0_ERRBANK __BITS(29, 31) 58 59 #define MCH_E3_ERRLOG1_ERRROW __BITS(0, 15) 60 #define MCH_E3_ERRLOG1_ERRCOL __BITS(16, 31) 61 62 #define MCH_CORE_DIMM_CH0 0x5004 63 #define MCH_CORE_DIMM_CH1 0x5008 64 65 #define MCH_CORE_DIMM_SIZE_UNIT 256 /* MB */ 66 #define MCH_CORE_DIMM_A_SIZE __BITS(0, 7) 67 #define MCH_CORE_DIMM_B_SIZE __BITS(8, 15) 68 #define MCH_CORE_DIMM_A_SELECT __BIT(16) 69 #define MCH_CORE_DIMM_A_DUAL_RANK __BIT(17) 70 #define MCH_CORE_DIMM_B_DUAL_RANK __BIT(18) 71 #define MCH_CORE_DIMM_A_X16 __BIT(19) 72 #define MCH_CORE_DIMM_B_X16 __BIT(20) 73 #define MCH_CORE_DIMM_RI __BIT(21) /* rank interleave */ 74 /* enchanced interleave */ 75 #define MCH_CORE_DIMM_ENHI __BIT(22) 76 #define MCH_E3_DIMM_ECC __BITS(24, 25) 77 #define MCH_E3_DIMM_ECC_NONE 0x0 78 #define MCH_E3_DIMM_ECC_IO 0x1 79 #define MCH_E3_DIMM_ECC_LOGIC 0x2 80 #define MCH_E3_DIMM_ECC_ALL 0x3 81 /* high order rank interleave */ 82 #define MCH_CORE_DIMM_HORI __BIT(26) /* v3 */ 83 /* high order rank interleave address (addr bits [20,27]) */ 84 #define MCH_CORE_DIMM_HORIADDR __BITS(27, 29) /* v3 */ 85 86 #define MCH_CORE_DDR_PTM_CTL0 0x5880 /* v3 */ 87 #define MCH_CORE_DDR_PTM_CTL0_EXTTS __BIT(4) 88 #define MCH_CORE_DDR_PTM_CTL0_CLTM __BIT(1) 89 #define MCH_CORE_DDR_PTM_CTL0_OLTM __BIT(0) 90 91 #define MCH_CORE_DIMM_TEMP_CH0 0x58b0 /* v3 */ 92 #define MCH_CORE_DIMM_TEMP_CH1 0x58b4 /* v3 */ 93 94 #define MCH_CORE_DIMM_TEMP_DIMM0 __BITS(0, 7) 95 #define MCH_CORE_DIMM_TEMP_DIMM1 __BITS(8, 15) 96 97 #endif /* !_COREMCTL_REG_H_ */ 98