Home
last modified time | relevance | path

Searched defs:MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT (Results 1 – 3 of 3) sorted by last modified time

/dragonfly/sys/dev/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_sh_mask.h9497 #define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x00000005 macro
H A Dgmc_7_1_sh_mask.h6614 #define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x5 macro
H A Dgmc_8_1_sh_mask.h7528 #define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x5 macro