1 /*========================== begin_copyright_notice ============================
2 
3 Copyright (C) 2017-2021 Intel Corporation
4 
5 SPDX-License-Identifier: MIT
6 
7 ============================= end_copyright_notice ===========================*/
8 
9 // enums for various fields in message-specific descriptors
10 typedef enum {
11     DC_OWORD_BLOCK_READ = 0,
12     DC_ALIGNED_OWORD_BLOCK_READ = 1,
13     DC_DWORD_SCATTERED_READ = 3,
14     DC_BYTE_SCATTERED_READ = 4,
15     DC_QWORD_SCATTERED_READ = 5,
16     DC_UNTYPED_ATOMIC = 6,
17     DC_MEMORY_FENCE = 7,
18     DC_OWORD_BLOCK_WRITE = 8,
19     DC_DWORD_SCATTERED_WRITE = 11,
20     DC_BYTE_SCATTERED_WRITE = 12,
21     DC_QWORD_SCATTERED_WRITE = 0xD,
22 } DATA_CACHE0_MESSAGES;
23 
24 typedef enum {
25     DC1_UNTYPED_SURFACE_READ = 0x1,
26     DC1_UNTYPED_ATOMIC = 0x2,
27     DC1_UNTYPED_HALF_INTEGER_ATOMIC = 0x3,
28     DC1_MEDIA_BLOCK_READ = 0x4,
29     DC1_TYPED_SURFACE_READ = 0x5,
30     DC1_TYPED_ATOMIC = 0x6,
31     DC1_TYPED_HALF_INTEGER_ATOMIC = 0x7,
32     DC1_UNTYPED_SURFACE_WRITE = 0x9,
33     DC1_MEDIA_BLOCK_WRITE = 0xA,
34     DC1_TYPED_HALF_COUNTER_ATOMIC = 0xC,
35     DC1_TYPED_SURFACE_WRITE = 0xD,
36     DC1_A64_SCATTERED_READ  = 0x10,
37     DC1_A64_UNTYPED_SURFACE_READ = 0x11,
38     DC1_A64_ATOMIC = 0x12,
39     DC1_A64_UNTYPED_HALF_INTEGER_ATOMIC = 0x13,
40     DC1_A64_BLOCK_READ = 0x14,
41     DC1_A64_BLOCK_WRITE = 0x15,
42     DC1_A64_UNTYPED_SURFACE_WRITE = 0x19,
43     DC1_A64_SCATTERED_WRITE = 0x1A,
44     DC1_UNTYPED_FLOAT_ATOMIC = 0x1B,
45     DC1_UNTYPED_HALF_FLOAT_ATOMIC = 0x1C,
46     DC1_A64_UNTYPED_FLOAT_ATOMIC = 0x1D,
47     DC1_A64_UNTYPED_HALF_FLOAT_ATOMIC = 0x1E
48 } DATA_CACHE1_MESSAGES;
49 
50 typedef enum
51 {
52     A64_BLOCK_MSG_OWORD_RW = 0x0,
53     A64_BLOCK_MSG_OWORD_UNALIGNED_READ = 0x1
54 } A64_BLOCK_MSG_SUBTYPE;
55 
56 typedef enum {
57     DC2_UNTYPED_SURFACE_READ        = (0x01) << 1, // MT2R_US
58     DC2_A64_SCATTERED_READ          = (0x02) << 1, // MT2R_A64_SB
59     DC2_A64_UNTYPED_SURFACE_READ    = (0x03) << 1, // MT2R_A64_US
60     DC2_BYTE_SCATTERED_READ         = (0x04) << 1, // MT2R_BS
61     DC2_UNTYPED_SURFACE_WRITE       = (0x09) << 1, // MT2W_US
62     DC2_A64_UNTYPED_SURFACE_WRITE   = (0x0A) << 1, // MT2W_A64_US
63     DC2_A64_SCATTERED_WRITE         = (0x0B) << 1, // MT2W_A64_SB
64     DC2_BYTE_SCATTERED_WRITE        = (0x0C) << 1  // MT2W_BS
65 } DATA_CACHE2_MESSAGES;
66 
67 typedef enum {
68     DC1_HWORD_BLOCK_READ              = 0x0,
69     DC1_HWORD_ALIGNED_BLOCK_READ      = 0x1,
70     DC1_HWORD_BLOCK_WRITE             = 0x8,
71     DC1_HWORD_ALIGNED_BLOCK_WRITE     = 0x9
72 } HWORD_DATA_CACHE1_MESSAGES;
73 
74 typedef enum
75 {
76     URB_WRITE_HWORD = 0,
77     URB_WRITE_OWORD = 1,
78     URB_READ_HWORD = 2,
79     URB_READ_OWORD = 3,
80     URB_ATOMIC_MOV = 4,
81     URB_ATOMIC_INC = 5,
82     URB_ATOMIC_ADD = 6,
83     URB_SIMD8_WRITE = 7,
84     URB_SIMD8_READ = 8
85 } URB_MESSAGES;
86 
87 // SIMD Mode 2 Message Descriptor Control Field
88 typedef enum {
89     MDC_SM2_SIMD8  = 0,
90     MDC_SM2_SIMD16 = 1
91 } MDC_SM2;
92 
93 // Reversed SIMD Mode 2 Message Descriptor Control Field
94 typedef enum {
95     MDC_SM2R_SIMD8  = 1,
96     MDC_SM2R_SIMD16 = 0
97 } MDC_SM2R;
98 
99 // SIMD Mode 3 Message Descriptor Control Field
100 typedef enum {
101     MDC_SM3_SIMD4x2 = 0,
102     MDC_SM3_SIMD16  = 1,
103     MDC_SM3_SIMD8   = 2
104 } MDC_SM3;
105 
106 typedef enum {
107     MDC_GW_OPEN_GATEWAY         = 0,
108     MDC_GW_CLOSE_GATEWAY        = 1,
109     MDC_GW_FORWARG_MSG          = 2,
110     MDC_GW_GET_TIMESTAMP        = 3,
111     MDC_GW_BARRIER_MSG          = 4,
112     MDC_GW_UPDATE_GATEWAY_STATE = 5
113 } MDC_GATEWAY_SUBFUNC;
114 
115 typedef enum {
116     MDC_SG3_SG4x2   = 0,
117     MDC_SG3_SG8L    = 1,
118     MDC_SG3_SG8U    = 2,
119 } MDC_SG3;
120 
121 enum SamplerSIMDMode
122 {
123     SIMD8 = 1,
124     SIMD16 = 2,
125     SIMD32 = 3
126 };
127 
128 #define A64_BLOCK_MSG_SUBTYPE_OFFSET 11
129