1 /* 2 * THIS FILE IS AUTOMATICALLY GENERATED 3 * DONT EDIT THIS FILE 4 */ 5 6 /* $OpenBSD: cn30xxuartreg.h,v 1.2 2022/12/28 01:39:21 yasuoka Exp $ */ 7 8 /* 9 * Copyright (c) 2007 Internet Initiative Japan, Inc. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Cavium Networks OCTEON CN30XX Hardware Reference Manual 36 * CN30XX-HM-1.0 37 * 16.4 UART Registers 38 */ 39 40 #ifndef _CN30XXUARTREG_H_ 41 #define _CN30XXUARTREG_H_ 42 43 /* ---- register addresses */ 44 45 #define MIO_UART0_RBR 0x0001180000000800ULL 46 #define MIO_UART0_IER 0x0001180000000808ULL 47 #define MIO_UART0_IIR 0x0001180000000810ULL 48 #define MIO_UART0_LCR 0x0001180000000818ULL 49 #define MIO_UART0_MCR 0x0001180000000820ULL 50 #define MIO_UART0_LSR 0x0001180000000828ULL 51 #define MIO_UART0_MSR 0x0001180000000830ULL 52 #define MIO_UART0_SCR 0x0001180000000838ULL 53 #define MIO_UART0_THR 0x0001180000000840ULL 54 #define MIO_UART0_FCR 0x0001180000000850ULL 55 #define MIO_UART0_DLL 0x0001180000000880ULL 56 #define MIO_UART0_DLH 0x0001180000000888ULL 57 #define MIO_UART0_FAR 0x0001180000000920ULL 58 #define MIO_UART0_TFR 0x0001180000000928ULL 59 #define MIO_UART0_RFW 0x0001180000000930ULL 60 #define MIO_UART0_USR 0x0001180000000938ULL 61 #define MIO_UART0_TFL 0x0001180000000a00ULL 62 #define MIO_UART0_RFL 0x0001180000000a08ULL 63 #define MIO_UART0_SRR 0x0001180000000a10ULL 64 #define MIO_UART0_SRTS 0x0001180000000a18ULL 65 #define MIO_UART0_SBCR 0x0001180000000a20ULL 66 #define MIO_UART0_SFE 0x0001180000000a30ULL 67 #define MIO_UART0_SRT 0x0001180000000a38ULL 68 #define MIO_UART0_STT 0x0001180000000b00ULL 69 #define MIO_UART0_HTX 0x0001180000000b08ULL 70 #define MIO_UART1_RBR 0x0001180000000c00ULL 71 #define MIO_UART1_IER 0x0001180000000c08ULL 72 #define MIO_UART1_IIR 0x0001180000000c10ULL 73 #define MIO_UART1_LCR 0x0001180000000c18ULL 74 #define MIO_UART1_MCR 0x0001180000000c20ULL 75 #define MIO_UART1_LSR 0x0001180000000c28ULL 76 #define MIO_UART1_MSR 0x0001180000000c30ULL 77 #define MIO_UART1_SCR 0x0001180000000c38ULL 78 #define MIO_UART1_THR 0x0001180000000c40ULL 79 #define MIO_UART1_FCR 0x0001180000000c50ULL 80 #define MIO_UART1_DLL 0x0001180000000c80ULL 81 #define MIO_UART1_DLH 0x0001180000000c88ULL 82 #define MIO_UART1_FAR 0x0001180000000d20ULL 83 #define MIO_UART1_TFR 0x0001180000000d28ULL 84 #define MIO_UART1_RFW 0x0001180000000d30ULL 85 #define MIO_UART1_USR 0x0001180000000d38ULL 86 #define MIO_UART1_TFL 0x0001180000000e00ULL 87 #define MIO_UART1_RFL 0x0001180000000e08ULL 88 #define MIO_UART1_SRR 0x0001180000000e10ULL 89 #define MIO_UART1_SRTS 0x0001180000000e18ULL 90 #define MIO_UART1_SBCR 0x0001180000000e20ULL 91 #define MIO_UART1_SFE 0x0001180000000e30ULL 92 #define MIO_UART1_SRT 0x0001180000000e38ULL 93 #define MIO_UART1_STT 0x0001180000000f00ULL 94 #define MIO_UART1_HTX 0x0001180000000f08ULL 95 96 /* ---- bitmask_snprintf */ 97 98 /* XXX */ 99 100 /* ---- bus_space */ 101 102 #define MIO_UART0_BASE 0x0001180000000800ULL 103 #define MIO_UART1_BASE 0x0001180000000c00ULL 104 105 #define MIO_UART_RBR_OFFSET 0x0000 106 #define MIO_UART_IER_OFFSET 0x0008 107 #define MIO_UART_IIR_OFFSET 0x0010 108 #define MIO_UART_LCR_OFFSET 0x0018 109 #define MIO_UART_MCR_OFFSET 0x0020 110 #define MIO_UART_LSR_OFFSET 0x0028 111 #define MIO_UART_MSR_OFFSET 0x0030 112 #define MIO_UART_SCR_OFFSET 0x0038 113 #define MIO_UART_THR_OFFSET 0x0040 114 #define MIO_UART_FCR_OFFSET 0x0050 115 #define MIO_UART_DLL_OFFSET 0x0080 116 #define MIO_UART_DLH_OFFSET 0x0088 117 #define MIO_UART_FAR_OFFSET 0x0120 118 #define MIO_UART_TFR_OFFSET 0x0128 119 #define MIO_UART_RFW_OFFSET 0x0130 120 #define MIO_UART_USR_OFFSET 0x0138 121 #define MIO_UART_TFL_OFFSET 0x0200 122 #define MIO_UART_RFL_OFFSET 0x0208 123 #define MIO_UART_SRR_OFFSET 0x0210 124 #define MIO_UART_SRTS_OFFSET 0x0218 125 #define MIO_UART_SBCR_OFFSET 0x0220 126 #define MIO_UART_SFE_OFFSET 0x0230 127 #define MIO_UART_SRT_OFFSET 0x0238 128 #define MIO_UART_STT_OFFSET 0x0300 129 #define MIO_UART_HTX_OFFSET 0x0308 130 131 #endif /* _CN30XXUARTREG_H_ */ 132