1 /* $OpenBSD: cpu.h,v 1.147 2024/06/09 21:15:29 jca Exp $ */
2
3 /*-
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * Copyright (C) 1989 Digital Equipment Corporation.
35 * Permission to use, copy, modify, and distribute this software and
36 * its documentation for any purpose and without fee is hereby granted,
37 * provided that the above copyright notice appears in all copies.
38 * Digital Equipment Corporation makes no representations about the
39 * suitability of this software for any purpose. It is provided "as is"
40 * without express or implied warranty.
41 *
42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94
43 */
44
45 #ifndef _MIPS64_CPU_H_
46 #define _MIPS64_CPU_H_
47
48 #ifndef _LOCORE
49
50 /*
51 * MIPS32-style segment definitions.
52 * They only cover the first 512MB of physical addresses.
53 */
54 #define CKSEG0_BASE 0xffffffff80000000UL
55 #define CKSEG1_BASE 0xffffffffa0000000UL
56 #define CKSSEG_BASE 0xffffffffc0000000UL
57 #define CKSEG3_BASE 0xffffffffe0000000UL
58 #define CKSEG_SIZE 0x0000000020000000UL
59
60 #define CKSEG0_TO_PHYS(x) ((u_long)(x) & (CKSEG_SIZE - 1))
61 #define CKSEG1_TO_PHYS(x) ((u_long)(x) & (CKSEG_SIZE - 1))
62 #define PHYS_TO_CKSEG0(x) ((u_long)(x) | CKSEG0_BASE)
63 #define PHYS_TO_CKSEG1(x) ((u_long)(x) | CKSEG1_BASE)
64
65 /*
66 * MIPS64-style segment definitions.
67 * These allow for 36 bits of addressable physical memory, thus 64GB.
68 */
69
70 /*
71 * Cache Coherency Attributes.
72 */
73 /* r8k only */
74 #define CCA_NC_COPROCESSOR 0UL /* uncached, coprocessor ordered */
75 /* common to r4, r5k, r8k and r1xk */
76 #define CCA_NC 2UL /* uncached, write-around */
77 #define CCA_NONCOHERENT 3UL /* cached, non-coherent, write-back */
78 /* r8k, r1xk only */
79 #define CCA_COHERENT_EXCL 4UL /* cached, coherent, exclusive */
80 #define CCA_COHERENT_EXCLWRITE 5UL /* cached, coherent, exclusive write */
81 /* r4k only */
82 #define CCA_COHERENT_UPDWRITE 6UL /* cached, coherent, update on write */
83 /* r1xk only */
84 #define CCA_NC_ACCELERATED 7UL /* uncached accelerated */
85
86 #ifdef TGT_COHERENT
87 #define CCA_CACHED CCA_COHERENT_EXCLWRITE
88 #else
89 #define CCA_CACHED CCA_NONCOHERENT
90 #endif
91
92 #define XKSSSEG_BASE 0x4000000000000000UL
93 #define XKPHYS_BASE 0x8000000000000000UL
94 #define XKSSEG_BASE 0xc000000000000000UL
95
96 #define XKPHYS_TO_PHYS(x) ((paddr_t)(x) & 0x0000000fffffffffUL)
97 #define PHYS_TO_XKPHYS(x,c) ((paddr_t)(x) | XKPHYS_BASE | ((c) << 59))
98 #define IS_XKPHYS(va) (((va) >> 62) == 2)
99 #define XKPHYS_TO_CCA(x) (((x) >> 59) & 0x07)
100
101 #endif /* _LOCORE */
102
103 /*
104 * Exported definitions unique to mips cpu support.
105 */
106
107 #if defined(_KERNEL) && !defined(_LOCORE)
108
109 #include <sys/clockintr.h>
110 #include <sys/device.h>
111 #include <machine/intr.h>
112 #include <sys/sched.h>
113 #include <sys/srp.h>
114
115 struct cpu_hwinfo {
116 uint32_t c0prid;
117 uint32_t c1prid;
118 uint32_t clock; /* Hz */
119 uint32_t tlbsize;
120 uint type;
121 uint32_t l2size;
122 };
123
124 /*
125 * Cache memory configuration. One struct per cache.
126 */
127 struct cache_info {
128 uint size; /* total cache size */
129 uint linesize; /* line size */
130 uint setsize; /* set size */
131 uint sets; /* number of sets */
132 };
133
134 struct cpu_info {
135 struct device *ci_dev; /* our device */
136 struct cpu_info *ci_self; /* pointer to this structure */
137 struct cpu_info *ci_next; /* next cpu */
138 struct proc *ci_curproc;
139 struct user *ci_curprocpaddr;
140 struct proc *ci_fpuproc; /* pointer to last proc to use FP */
141 uint32_t ci_delayconst;
142 struct cpu_hwinfo
143 ci_hw;
144
145 #if defined(MULTIPROCESSOR)
146 struct srp_hazard ci_srp_hazards[SRP_HAZARD_NUM];
147 #endif
148
149 /* cache information and pending flush state */
150 uint ci_cacheconfiguration;
151 uint64_t ci_cachepending_l1i;
152 struct cache_info
153 ci_l1inst,
154 ci_l1data,
155 ci_l2,
156 ci_l3;
157
158 /* function pointers for the cache handling routines */
159 void (*ci_SyncCache)(struct cpu_info *);
160 void (*ci_InvalidateICache)(struct cpu_info *, vaddr_t,
161 size_t);
162 void (*ci_InvalidateICachePage)(struct cpu_info *, vaddr_t);
163 void (*ci_SyncICache)(struct cpu_info *);
164 void (*ci_SyncDCachePage)(struct cpu_info *, vaddr_t,
165 paddr_t);
166 void (*ci_HitSyncDCachePage)(struct cpu_info *, vaddr_t,
167 paddr_t);
168 void (*ci_HitSyncDCache)(struct cpu_info *, vaddr_t, size_t);
169 void (*ci_HitInvalidateDCache)(struct cpu_info *, vaddr_t,
170 size_t);
171 void (*ci_IOSyncDCache)(struct cpu_info *, vaddr_t, size_t,
172 int);
173
174 struct schedstate_percpu
175 ci_schedstate;
176 int ci_want_resched; /* need_resched() invoked */
177 cpuid_t ci_cpuid; /* our CPU ID */
178 uint32_t ci_randseed; /* per cpu random seed */
179 volatile int ci_ipl; /* software IPL */
180 uint32_t ci_softpending; /* pending soft interrupts */
181 int ci_clock_started;
182 volatile int ci_clock_deferred; /* clock interrupt postponed */
183 struct clockqueue
184 ci_queue;
185
186 struct pmap *ci_curpmap;
187 uint ci_intrdepth; /* interrupt depth */
188 #ifdef MULTIPROCESSOR
189 u_long ci_flags; /* flags; see below */
190 #endif
191 volatile int ci_ddb;
192 #define CI_DDB_RUNNING 0
193 #define CI_DDB_SHOULDSTOP 1
194 #define CI_DDB_STOPPED 2
195 #define CI_DDB_ENTERDDB 3
196 #define CI_DDB_INDDB 4
197
198 #ifdef DIAGNOSTIC
199 int ci_mutex_level;
200 #endif
201 #ifdef GPROF
202 struct gmonparam *ci_gmon;
203 struct clockintr ci_gmonclock;
204 #endif
205 char ci_panicbuf[512];
206 };
207
208 #define CPUF_PRIMARY 0x01 /* CPU is primary CPU */
209 #define CPUF_PRESENT 0x02 /* CPU is present */
210 #define CPUF_RUNNING 0x04 /* CPU is running */
211
212 extern struct cpu_info cpu_info_primary;
213 extern struct cpu_info *cpu_info_list;
214 #define CPU_INFO_ITERATOR int
215 #define CPU_INFO_FOREACH(cii, ci) for (cii = 0, ci = cpu_info_list; \
216 ci != NULL; ci = ci->ci_next)
217
218 #define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0)
219
220 #define cpu_idle_enter() do { /* nothing */ } while (0)
221 #define cpu_idle_leave() do { /* nothing */ } while (0)
222 extern void (*cpu_idle_cycle_func)(void);
223 #define cpu_idle_cycle() (*cpu_idle_cycle_func)()
224
225 #ifdef MULTIPROCESSOR
226 #define getcurcpu() hw_getcurcpu()
227 #define setcurcpu(ci) hw_setcurcpu(ci)
228 extern struct cpu_info *get_cpu_info(int);
229 #define curcpu() getcurcpu()
230 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY)
231 #define CPU_IS_RUNNING(ci) ((ci)->ci_flags & CPUF_RUNNING)
232 #define cpu_number() (curcpu()->ci_cpuid)
233
234 void cpu_unidle(struct cpu_info *);
235 void cpu_boot_secondary_processors(void);
236 #define cpu_boot_secondary(ci) hw_cpu_boot_secondary(ci)
237 #define cpu_hatch(ci) hw_cpu_hatch(ci)
238
239 vaddr_t alloc_contiguous_pages(size_t);
240
241 #define MIPS64_IPI_NOP 0x00000001
242 #define MIPS64_IPI_RENDEZVOUS 0x00000002
243 #define MIPS64_IPI_DDB 0x00000004
244 #define MIPS64_NIPIS 3 /* must not exceed 32 */
245
246 void mips64_ipi_init(void);
247 void mips64_send_ipi(unsigned int, unsigned int);
248 void smp_rendezvous_cpus(unsigned long, void (*)(void *), void *arg);
249
250 #include <sys/mplock.h>
251 #else
252 #define MAXCPUS 1
253 #define curcpu() (&cpu_info_primary)
254 #define CPU_IS_PRIMARY(ci) 1
255 #define CPU_IS_RUNNING(ci) 1
256 #define cpu_number() 0UL
257 #define cpu_unidle(ci)
258 #define get_cpu_info(i) (&cpu_info_primary)
259 #endif
260
261 #define CPU_BUSY_CYCLE() __asm volatile ("" ::: "memory")
262
263 extern void (*md_initclock)(void);
264 extern void (*md_startclock)(struct cpu_info *);
265 extern void (*md_triggerclock)(void);
266 void cp0_calibrate(struct cpu_info *);
267
268 unsigned int cpu_rnd_messybits(void);
269
270 #include <machine/frame.h>
271
272 /*
273 * Arguments to hardclock encapsulate the previous machine state in
274 * an opaque clockframe.
275 */
276 #define clockframe trapframe /* Use normal trap frame */
277
278 #define SR_KSU_USER 0x00000010
279 #define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER)
280 #define CLKF_PC(framep) ((framep)->pc)
281 #define CLKF_INTR(framep) (curcpu()->ci_intrdepth > 1) /* XXX */
282
283 /*
284 * This is used during profiling to integrate system time.
285 */
286 #define PROC_PC(p) ((p)->p_md.md_regs->pc)
287 #define PROC_STACK(p) ((p)->p_md.md_regs->sp)
288
289 /*
290 * Preempt the current process if in interrupt from user mode,
291 * or after the current trap/syscall if in system mode.
292 */
293 void need_resched(struct cpu_info *);
294 #define clear_resched(ci) (ci)->ci_want_resched = 0
295
296 /*
297 * Give a profiling tick to the current process when the user profiling
298 * buffer pages are invalid. On MIPS designs, request an ast to send us
299 * through trap, marking the proc as needing a profiling tick.
300 */
301 #define need_proftick(p) aston(p)
302
303 /*
304 * Notify the current process (p) that it has a signal pending,
305 * process as soon as possible.
306 */
307 void signotify(struct proc *);
308
309 #define aston(p) ((p)->p_md.md_astpending = 1)
310
311 #define mips_sync() __asm__ volatile ("sync" ::: "memory")
312
313 #endif /* _KERNEL && !_LOCORE */
314
315 #ifdef _KERNEL
316 /*
317 * Values for the code field in a break instruction.
318 */
319 #define BREAK_INSTR 0x0000000d
320 #define BREAK_VAL_MASK 0x03ff0000
321 #define BREAK_VAL_SHIFT 16
322 #define BREAK_KDB_VAL 512
323 #define BREAK_SSTEP_VAL 513
324 #define BREAK_BRKPT_VAL 514
325 #define BREAK_SOVER_VAL 515
326 #define BREAK_DDB_VAL 516
327 #define BREAK_FPUEMUL_VAL 517
328 #define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT))
329 #define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT))
330 #define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT))
331 #define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT))
332 #define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT))
333 #define BREAK_FPUEMUL (BREAK_INSTR | (BREAK_FPUEMUL_VAL << BREAK_VAL_SHIFT))
334
335 #endif /* _KERNEL */
336
337 /*
338 * CTL_MACHDEP definitions.
339 */
340 #define CPU_ALLOWAPERTURE 1 /* allow mmap of /dev/xf86 */
341 /* 2 formerly: keyboard reset */
342 /* 3 formerly: CPU_LIDSUSPEND */
343 #define CPU_LIDACTION 4 /* action caused by lid close */
344 #define CPU_MAXID 5 /* number of valid machdep ids */
345
346 #define CTL_MACHDEP_NAMES { \
347 { 0, 0 }, \
348 { "allowaperture", CTLTYPE_INT }, \
349 { 0, 0 }, \
350 { 0, 0 }, \
351 { "lidaction", CTLTYPE_INT }, \
352 }
353
354 /*
355 * MIPS CPU types (cp_imp).
356 */
357 #define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */
358 #define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */
359 #define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */
360 #define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */
361 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */
362 #define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */
363 #define MIPS_CN50XX 0x06 /* Cavium OCTEON CN50xx MIPS64R2*/
364 #define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */
365 #define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
366 #define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */
367 #define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
368 #define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */
369 #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */
370 #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */
371 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
372 #define MIPS_R4600 0x20 /* PMCS R4600 Orion ISA III */
373 #define MIPS_R4700 0x21 /* PMCS R4700 Orion ISA III */
374 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */
375 #define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */
376 #define MIPS_RM7000 0x27 /* PMCS RM7000 CPU ISA IV */
377 #define MIPS_RM52X0 0x28 /* PMCS RM52X0 CPU ISA IV */
378 #define MIPS_RM9000 0x34 /* PMCS RM9000 CPU ISA IV */
379 #define MIPS_LOONGSON 0x42 /* STC LoongSon CPU ISA III */
380 #define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */
381 #define MIPS_LOONGSON2 0x63 /* STC LoongSon2/3 CPU ISA III+ */
382 #define MIPS_CN63XX 0x90 /* Cavium OCTEON II CN6[23]xx MIPS64R2 */
383 #define MIPS_CN68XX 0x91 /* Cavium OCTEON II CN68xx MIPS64R2 */
384 #define MIPS_CN66XX 0x92 /* Cavium OCTEON II CN66xx MIPS64R2 */
385 #define MIPS_CN61XX 0x93 /* Cavium OCTEON II CN6[01]xx MIPS64R2 */
386 #define MIPS_CN78XX 0x95 /* Cavium OCTEON III CN7[678]xx MIPS64R2 */
387 #define MIPS_CN71XX 0x96 /* Cavium OCTEON III CN7[01]xx MIPS64R2 */
388 #define MIPS_CN73XX 0x97 /* Cavium OCTEON III CN7[23]xx MIPS64R2 */
389
390 /*
391 * MIPS FPU types. Only soft, rest is the same as cpu type.
392 */
393 #define MIPS_SOFT 0x00 /* Software emulation ISA I */
394
395
396 #if defined(_KERNEL) && !defined(_LOCORE)
397
398 extern register_t protosr;
399 extern int cpu_has_synced_cp0_count;
400 extern int cpu_has_userlocal;
401
402 #ifdef FPUEMUL
403 #define CPU_HAS_FPU(ci) ((ci)->ci_hw.c1prid != 0)
404 #else
405 #define CPU_HAS_FPU(ci) 1
406 #endif
407
408 struct exec_package;
409 struct user;
410
411 void tlb_asid_wrap(struct cpu_info *);
412 void tlb_flush(int);
413 void tlb_flush_addr(vaddr_t);
414 void tlb_init(unsigned int);
415 void tlb_set_page_mask(uint32_t);
416 void tlb_set_pid(u_int);
417 void tlb_set_wired(uint32_t);
418 int tlb_update(vaddr_t, register_t);
419
420 void build_trampoline(vaddr_t, vaddr_t);
421 void cpu_switchto_asm(struct proc *, struct proc *);
422 int exec_md_map(struct proc *, struct exec_package *);
423 void savectx(struct user *, int);
424
425 int copyinsn(struct proc *, vaddr_t, uint32_t *);
426 void enable_fpu(struct proc *);
427 void save_fpu(void);
428 int fpe_branch_emulate(struct proc *, struct trapframe *, uint32_t,
429 vaddr_t);
430 void MipsSaveCurFPState(struct proc *);
431 void MipsSaveCurFPState16(struct proc *);
432 void MipsSwitchFPState(struct proc *, struct trapframe *);
433 void MipsSwitchFPState16(struct proc *, struct trapframe *);
434
435 void MipsFPTrap(struct trapframe *);
436 register_t MipsEmulateBranch(struct trapframe *, vaddr_t, uint32_t, uint32_t);
437
438 int classify_insn(uint32_t);
439 #define INSNCLASS_NEUTRAL 0
440 #define INSNCLASS_CALL 1
441 #define INSNCLASS_BRANCH 2
442
443 /*
444 * Low level access routines to CPU registers
445 */
446
447 void setsoftintr0(void);
448 void clearsoftintr0(void);
449 void setsoftintr1(void);
450 void clearsoftintr1(void);
451 register_t enableintr(void);
452 register_t disableintr(void);
453 register_t getsr(void);
454 register_t setsr(register_t);
455
456 uint32_t cp0_get_cause(void);
457 u_int cp0_get_count(void);
458 register_t cp0_get_config(void);
459 uint32_t cp0_get_config_1(void);
460 uint32_t cp0_get_config_2(void);
461 uint32_t cp0_get_config_3(void);
462 uint32_t cp0_get_config_4(void);
463 uint32_t cp0_get_pagegrain(void);
464 register_t cp0_get_prid(void);
465 void cp0_reset_cause(register_t);
466 void cp0_set_compare(u_int);
467 void cp0_set_config(register_t);
468 void cp0_set_pagegrain(uint32_t);
469 void cp0_set_trapbase(register_t);
470 u_int cp1_get_prid(void);
471
472 static inline uint32_t
cp0_get_hwrena(void)473 cp0_get_hwrena(void)
474 {
475 uint32_t value;
476 __asm__ volatile ("mfc0 %0, $7" : "=r" (value));
477 return value;
478 }
479
480 static inline void
cp0_set_hwrena(uint32_t value)481 cp0_set_hwrena(uint32_t value)
482 {
483 __asm__ volatile ("mtc0 %0, $7" : : "r" (value));
484 }
485
486 static inline void
cp0_set_userlocal(void * value)487 cp0_set_userlocal(void *value)
488 {
489 __asm__ volatile (
490 " .set push\n"
491 " .set mips64r2\n"
492 " dmtc0 %0, $4, 2\n"
493 " .set pop\n"
494 : : "r" (value));
495 }
496
497 static inline u_long
intr_disable(void)498 intr_disable(void)
499 {
500 return disableintr();
501 }
502
503 static inline void
intr_restore(u_long sr)504 intr_restore(u_long sr)
505 {
506 setsr(sr);
507 }
508
509 /*
510 * Cache routines (may be overridden)
511 */
512
513 #ifndef Mips_SyncCache
514 #define Mips_SyncCache(ci) \
515 ((ci)->ci_SyncCache)(ci)
516 #endif
517 #ifndef Mips_InvalidateICache
518 #define Mips_InvalidateICache(ci, va, l) \
519 ((ci)->ci_InvalidateICache)(ci, va, l)
520 #endif
521 #ifndef Mips_InvalidateICachePage
522 #define Mips_InvalidateICachePage(ci, va) \
523 ((ci)->ci_InvalidateICachePage)(ci, va)
524 #endif
525 #ifndef Mips_SyncICache
526 #define Mips_SyncICache(ci) \
527 ((ci)->ci_SyncICache)(ci)
528 #endif
529 #ifndef Mips_SyncDCachePage
530 #define Mips_SyncDCachePage(ci, va, pa) \
531 ((ci)->ci_SyncDCachePage)(ci, va, pa)
532 #endif
533 #ifndef Mips_HitSyncDCachePage
534 #define Mips_HitSyncDCachePage(ci, va, pa) \
535 ((ci)->ci_HitSyncDCachePage)(ci, va, pa)
536 #endif
537 #ifndef Mips_HitSyncDCache
538 #define Mips_HitSyncDCache(ci, va, l) \
539 ((ci)->ci_HitSyncDCache)(ci, va, l)
540 #endif
541 #ifndef Mips_HitInvalidateDCache
542 #define Mips_HitInvalidateDCache(ci, va, l) \
543 ((ci)->ci_HitInvalidateDCache)(ci, va, l)
544 #endif
545 #ifndef Mips_IOSyncDCache
546 #define Mips_IOSyncDCache(ci, va, l, h) \
547 ((ci)->ci_IOSyncDCache)(ci, va, l, h)
548 #endif
549
550 #endif /* _KERNEL && !_LOCORE */
551 #endif /* !_MIPS64_CPU_H_ */
552