1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
25
26 #include "config.h"
27 #include "system.h"
28 #include "coretypes.h"
29 #include "tm.h"
30 #include <signal.h>
31 #include "rtl.h"
32 #include "regs.h"
33 #include "hard-reg-set.h"
34 #include "real.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
38 #include "recog.h"
39 #include "toplev.h"
40 #include "output.h"
41 #include "tree.h"
42 #include "function.h"
43 #include "expr.h"
44 #include "optabs.h"
45 #include "flags.h"
46 #include "reload.h"
47 #include "tm_p.h"
48 #include "ggc.h"
49 #include "gstab.h"
50 #include "hashtab.h"
51 #include "debug.h"
52 #include "target.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
59
60 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
61 #define UNSPEC_ADDRESS_P(X) \
62 (GET_CODE (X) == UNSPEC \
63 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
64 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
65
66 /* Extract the symbol or label from UNSPEC wrapper X. */
67 #define UNSPEC_ADDRESS(X) \
68 XVECEXP (X, 0, 0)
69
70 /* Extract the symbol type from UNSPEC wrapper X. */
71 #define UNSPEC_ADDRESS_TYPE(X) \
72 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
73
74 /* The maximum distance between the top of the stack frame and the
75 value $sp has when we save & restore registers.
76
77 Use a maximum gap of 0x100 in the mips16 case. We can then use
78 unextended instructions to save and restore registers, and to
79 allocate and deallocate the top part of the frame.
80
81 The value in the !mips16 case must be a SMALL_OPERAND and must
82 preserve the maximum stack alignment. */
83 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
84
85 /* True if INSN is a mips.md pattern or asm statement. */
86 #define USEFUL_INSN_P(INSN) \
87 (INSN_P (INSN) \
88 && GET_CODE (PATTERN (INSN)) != USE \
89 && GET_CODE (PATTERN (INSN)) != CLOBBER \
90 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
91 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
92
93 /* If INSN is a delayed branch sequence, return the first instruction
94 in the sequence, otherwise return INSN itself. */
95 #define SEQ_BEGIN(INSN) \
96 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
97 ? XVECEXP (PATTERN (INSN), 0, 0) \
98 : (INSN))
99
100 /* Likewise for the last instruction in a delayed branch sequence. */
101 #define SEQ_END(INSN) \
102 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
103 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
104 : (INSN))
105
106 /* Execute the following loop body with SUBINSN set to each instruction
107 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
108 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
109 for ((SUBINSN) = SEQ_BEGIN (INSN); \
110 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
111 (SUBINSN) = NEXT_INSN (SUBINSN))
112
113 /* Classifies an address.
114
115 ADDRESS_REG
116 A natural register + offset address. The register satisfies
117 mips_valid_base_register_p and the offset is a const_arith_operand.
118
119 ADDRESS_LO_SUM
120 A LO_SUM rtx. The first operand is a valid base register and
121 the second operand is a symbolic address.
122
123 ADDRESS_CONST_INT
124 A signed 16-bit constant address.
125
126 ADDRESS_SYMBOLIC:
127 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
128 enum mips_address_type {
129 ADDRESS_REG,
130 ADDRESS_LO_SUM,
131 ADDRESS_CONST_INT,
132 ADDRESS_SYMBOLIC
133 };
134
135 /* Classifies the prototype of a builtin function. */
136 enum mips_function_type
137 {
138 MIPS_V2SF_FTYPE_V2SF,
139 MIPS_V2SF_FTYPE_V2SF_V2SF,
140 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
142 MIPS_V2SF_FTYPE_SF_SF,
143 MIPS_INT_FTYPE_V2SF_V2SF,
144 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
145 MIPS_INT_FTYPE_SF_SF,
146 MIPS_INT_FTYPE_DF_DF,
147 MIPS_SF_FTYPE_V2SF,
148 MIPS_SF_FTYPE_SF,
149 MIPS_SF_FTYPE_SF_SF,
150 MIPS_DF_FTYPE_DF,
151 MIPS_DF_FTYPE_DF_DF,
152
153 /* For MIPS DSP ASE */
154 MIPS_DI_FTYPE_DI_SI,
155 MIPS_DI_FTYPE_DI_SI_SI,
156 MIPS_DI_FTYPE_DI_V2HI_V2HI,
157 MIPS_DI_FTYPE_DI_V4QI_V4QI,
158 MIPS_SI_FTYPE_DI_SI,
159 MIPS_SI_FTYPE_PTR_SI,
160 MIPS_SI_FTYPE_SI,
161 MIPS_SI_FTYPE_SI_SI,
162 MIPS_SI_FTYPE_V2HI,
163 MIPS_SI_FTYPE_V2HI_V2HI,
164 MIPS_SI_FTYPE_V4QI,
165 MIPS_SI_FTYPE_V4QI_V4QI,
166 MIPS_SI_FTYPE_VOID,
167 MIPS_V2HI_FTYPE_SI,
168 MIPS_V2HI_FTYPE_SI_SI,
169 MIPS_V2HI_FTYPE_V2HI,
170 MIPS_V2HI_FTYPE_V2HI_SI,
171 MIPS_V2HI_FTYPE_V2HI_V2HI,
172 MIPS_V2HI_FTYPE_V4QI,
173 MIPS_V2HI_FTYPE_V4QI_V2HI,
174 MIPS_V4QI_FTYPE_SI,
175 MIPS_V4QI_FTYPE_V2HI_V2HI,
176 MIPS_V4QI_FTYPE_V4QI_SI,
177 MIPS_V4QI_FTYPE_V4QI_V4QI,
178 MIPS_VOID_FTYPE_SI_SI,
179 MIPS_VOID_FTYPE_V2HI_V2HI,
180 MIPS_VOID_FTYPE_V4QI_V4QI,
181
182 /* The last type. */
183 MIPS_MAX_FTYPE_MAX
184 };
185
186 /* Specifies how a builtin function should be converted into rtl. */
187 enum mips_builtin_type
188 {
189 /* The builtin corresponds directly to an .md pattern. The return
190 value is mapped to operand 0 and the arguments are mapped to
191 operands 1 and above. */
192 MIPS_BUILTIN_DIRECT,
193
194 /* The builtin corresponds directly to an .md pattern. There is no return
195 value and the arguments are mapped to operands 0 and above. */
196 MIPS_BUILTIN_DIRECT_NO_TARGET,
197
198 /* The builtin corresponds to a comparison instruction followed by
199 a mips_cond_move_tf_ps pattern. The first two arguments are the
200 values to compare and the second two arguments are the vector
201 operands for the movt.ps or movf.ps instruction (in assembly order). */
202 MIPS_BUILTIN_MOVF,
203 MIPS_BUILTIN_MOVT,
204
205 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
206 of this instruction is the result of the comparison, which has mode
207 CCV2 or CCV4. The function arguments are mapped to operands 1 and
208 above. The function's return value is an SImode boolean that is
209 true under the following conditions:
210
211 MIPS_BUILTIN_CMP_ANY: one of the registers is true
212 MIPS_BUILTIN_CMP_ALL: all of the registers are true
213 MIPS_BUILTIN_CMP_LOWER: the first register is true
214 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
215 MIPS_BUILTIN_CMP_ANY,
216 MIPS_BUILTIN_CMP_ALL,
217 MIPS_BUILTIN_CMP_UPPER,
218 MIPS_BUILTIN_CMP_LOWER,
219
220 /* As above, but the instruction only sets a single $fcc register. */
221 MIPS_BUILTIN_CMP_SINGLE,
222
223 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
224 MIPS_BUILTIN_BPOSGE32
225 };
226
227 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
228 #define MIPS_FP_CONDITIONS(MACRO) \
229 MACRO (f), \
230 MACRO (un), \
231 MACRO (eq), \
232 MACRO (ueq), \
233 MACRO (olt), \
234 MACRO (ult), \
235 MACRO (ole), \
236 MACRO (ule), \
237 MACRO (sf), \
238 MACRO (ngle), \
239 MACRO (seq), \
240 MACRO (ngl), \
241 MACRO (lt), \
242 MACRO (nge), \
243 MACRO (le), \
244 MACRO (ngt)
245
246 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
247 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
248 enum mips_fp_condition {
249 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
250 };
251
252 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
253 #define STRINGIFY(X) #X
254 static const char *const mips_fp_conditions[] = {
255 MIPS_FP_CONDITIONS (STRINGIFY)
256 };
257
258 /* A function to save or store a register. The first argument is the
259 register and the second is the stack slot. */
260 typedef void (*mips_save_restore_fn) (rtx, rtx);
261
262 struct mips16_constant;
263 struct mips_arg_info;
264 struct mips_address_info;
265 struct mips_integer_op;
266 struct mips_sim;
267
268 static enum mips_symbol_type mips_classify_symbol (rtx);
269 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
270 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
271 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
272 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
273 static bool mips_classify_address (struct mips_address_info *, rtx,
274 enum machine_mode, int);
275 static bool mips_cannot_force_const_mem (rtx);
276 static int mips_symbol_insns (enum mips_symbol_type);
277 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
278 static rtx mips_force_temporary (rtx, rtx);
279 static rtx mips_split_symbol (rtx, rtx);
280 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
281 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
282 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
283 static unsigned int mips_build_lower (struct mips_integer_op *,
284 unsigned HOST_WIDE_INT);
285 static unsigned int mips_build_integer (struct mips_integer_op *,
286 unsigned HOST_WIDE_INT);
287 static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
288 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
289 static int m16_check_op (rtx, int, int, int);
290 static bool mips_rtx_costs (rtx, int, int, int *);
291 static int mips_address_cost (rtx);
292 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
293 static void mips_load_call_address (rtx, rtx, int);
294 static bool mips_function_ok_for_sibcall (tree, tree);
295 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
296 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
297 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
298 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
299 tree, int, struct mips_arg_info *);
300 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
301 static void mips_set_architecture (const struct mips_cpu_info *);
302 static void mips_set_tune (const struct mips_cpu_info *);
303 static bool mips_handle_option (size_t, const char *, int);
304 static struct machine_function *mips_init_machine_status (void);
305 static void print_operand_reloc (FILE *, rtx, const char **);
306 #if TARGET_IRIX
307 static void irix_output_external_libcall (rtx);
308 #endif
309 static void mips_file_start (void);
310 static void mips_file_end (void);
311 static bool mips_rewrite_small_data_p (rtx);
312 static int mips_small_data_pattern_1 (rtx *, void *);
313 static int mips_rewrite_small_data_1 (rtx *, void *);
314 static bool mips_function_has_gp_insn (void);
315 static unsigned int mips_global_pointer (void);
316 static bool mips_save_reg_p (unsigned int);
317 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
318 mips_save_restore_fn);
319 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
320 static void mips_output_cplocal (void);
321 static void mips_emit_loadgp (void);
322 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
323 static void mips_set_frame_expr (rtx);
324 static rtx mips_frame_set (rtx, rtx);
325 static void mips_save_reg (rtx, rtx);
326 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
327 static void mips_restore_reg (rtx, rtx);
328 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
329 HOST_WIDE_INT, tree);
330 static int symbolic_expression_p (rtx);
331 static void mips_select_rtx_section (enum machine_mode, rtx,
332 unsigned HOST_WIDE_INT);
333 static void mips_function_rodata_section (tree);
334 static bool mips_in_small_data_p (tree);
335 static int mips_fpr_return_fields (tree, tree *);
336 static bool mips_return_in_msb (tree);
337 static rtx mips_return_fpr_pair (enum machine_mode mode,
338 enum machine_mode mode1, HOST_WIDE_INT,
339 enum machine_mode mode2, HOST_WIDE_INT);
340 static rtx mips16_gp_pseudo_reg (void);
341 static void mips16_fp_args (FILE *, int, int);
342 static void build_mips16_function_stub (FILE *);
343 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
344 static void dump_constants (struct mips16_constant *, rtx);
345 static int mips16_insn_length (rtx);
346 static int mips16_rewrite_pool_refs (rtx *, void *);
347 static void mips16_lay_out_constants (void);
348 static void mips_sim_reset (struct mips_sim *);
349 static void mips_sim_init (struct mips_sim *, state_t);
350 static void mips_sim_next_cycle (struct mips_sim *);
351 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
352 static int mips_sim_wait_regs_2 (rtx *, void *);
353 static void mips_sim_wait_regs_1 (rtx *, void *);
354 static void mips_sim_wait_regs (struct mips_sim *, rtx);
355 static void mips_sim_wait_units (struct mips_sim *, rtx);
356 static void mips_sim_wait_insn (struct mips_sim *, rtx);
357 static void mips_sim_record_set (rtx, rtx, void *);
358 static void mips_sim_issue_insn (struct mips_sim *, rtx);
359 static void mips_sim_issue_nop (struct mips_sim *);
360 static void mips_sim_finish_insn (struct mips_sim *, rtx);
361 static void vr4130_avoid_branch_rt_conflict (rtx);
362 static void vr4130_align_insns (void);
363 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
364 static void mips_avoid_hazards (void);
365 static void mips_reorg (void);
366 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
367 static bool mips_matching_cpu_name_p (const char *, const char *);
368 static const struct mips_cpu_info *mips_parse_cpu (const char *);
369 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
370 static bool mips_return_in_memory (tree, tree);
371 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
372 static void mips_macc_chains_record (rtx);
373 static void mips_macc_chains_reorder (rtx *, int);
374 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
375 static bool vr4130_true_reg_dependence_p (rtx);
376 static bool vr4130_swap_insns_p (rtx, rtx);
377 static void vr4130_reorder (rtx *, int);
378 static void mips_promote_ready (rtx *, int, int);
379 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
380 static int mips_variable_issue (FILE *, int, rtx, int);
381 static int mips_adjust_cost (rtx, rtx, rtx, int);
382 static int mips_issue_rate (void);
383 static int mips_multipass_dfa_lookahead (void);
384 static void mips_init_libfuncs (void);
385 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
386 tree, int *, int);
387 static tree mips_build_builtin_va_list (void);
388 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
389 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
390 tree, bool);
391 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
392 tree, bool);
393 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
394 tree, bool);
395 static bool mips_valid_pointer_mode (enum machine_mode);
396 static bool mips_vector_mode_supported_p (enum machine_mode);
397 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
398 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
399 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
400 static void mips_init_builtins (void);
401 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
402 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
403 enum insn_code, enum mips_fp_condition,
404 rtx, tree);
405 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
406 enum insn_code, enum mips_fp_condition,
407 rtx, tree);
408 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
409 static void mips_encode_section_info (tree, rtx, int);
410
411 /* Structure to be filled in by compute_frame_size with register
412 save masks, and offsets for the current function. */
413
414 struct mips_frame_info GTY(())
415 {
416 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
417 HOST_WIDE_INT var_size; /* # bytes that variables take up */
418 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
419 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
420 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
421 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
422 unsigned int mask; /* mask of saved gp registers */
423 unsigned int fmask; /* mask of saved fp registers */
424 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
425 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
426 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
427 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
428 bool initialized; /* true if frame size already calculated */
429 int num_gp; /* number of gp registers saved */
430 int num_fp; /* number of fp registers saved */
431 };
432
433 struct machine_function GTY(()) {
434 /* Pseudo-reg holding the value of $28 in a mips16 function which
435 refers to GP relative global variables. */
436 rtx mips16_gp_pseudo_rtx;
437
438 /* The number of extra stack bytes taken up by register varargs.
439 This area is allocated by the callee at the very top of the frame. */
440 int varargs_size;
441
442 /* Current frame information, calculated by compute_frame_size. */
443 struct mips_frame_info frame;
444
445 /* The register to use as the global pointer within this function. */
446 unsigned int global_pointer;
447
448 /* True if mips_adjust_insn_length should ignore an instruction's
449 hazard attribute. */
450 bool ignore_hazard_length_p;
451
452 /* True if the whole function is suitable for .set noreorder and
453 .set nomacro. */
454 bool all_noreorder_p;
455
456 /* True if the function is known to have an instruction that needs $gp. */
457 bool has_gp_insn_p;
458 };
459
460 /* Information about a single argument. */
461 struct mips_arg_info
462 {
463 /* True if the argument is passed in a floating-point register, or
464 would have been if we hadn't run out of registers. */
465 bool fpr_p;
466
467 /* The number of words passed in registers, rounded up. */
468 unsigned int reg_words;
469
470 /* For EABI, the offset of the first register from GP_ARG_FIRST or
471 FP_ARG_FIRST. For other ABIs, the offset of the first register from
472 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
473 comment for details).
474
475 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
476 on the stack. */
477 unsigned int reg_offset;
478
479 /* The number of words that must be passed on the stack, rounded up. */
480 unsigned int stack_words;
481
482 /* The offset from the start of the stack overflow area of the argument's
483 first stack word. Only meaningful when STACK_WORDS is nonzero. */
484 unsigned int stack_offset;
485 };
486
487
488 /* Information about an address described by mips_address_type.
489
490 ADDRESS_CONST_INT
491 No fields are used.
492
493 ADDRESS_REG
494 REG is the base register and OFFSET is the constant offset.
495
496 ADDRESS_LO_SUM
497 REG is the register that contains the high part of the address,
498 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
499 is the type of OFFSET's symbol.
500
501 ADDRESS_SYMBOLIC
502 SYMBOL_TYPE is the type of symbol being referenced. */
503
504 struct mips_address_info
505 {
506 enum mips_address_type type;
507 rtx reg;
508 rtx offset;
509 enum mips_symbol_type symbol_type;
510 };
511
512
513 /* One stage in a constant building sequence. These sequences have
514 the form:
515
516 A = VALUE[0]
517 A = A CODE[1] VALUE[1]
518 A = A CODE[2] VALUE[2]
519 ...
520
521 where A is an accumulator, each CODE[i] is a binary rtl operation
522 and each VALUE[i] is a constant integer. */
523 struct mips_integer_op {
524 enum rtx_code code;
525 unsigned HOST_WIDE_INT value;
526 };
527
528
529 /* The largest number of operations needed to load an integer constant.
530 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
531 When the lowest bit is clear, we can try, but reject a sequence with
532 an extra SLL at the end. */
533 #define MIPS_MAX_INTEGER_OPS 7
534
535
536 /* Global variables for machine-dependent things. */
537
538 /* Threshold for data being put into the small data/bss area, instead
539 of the normal data area. */
540 int mips_section_threshold = -1;
541
542 /* Count the number of .file directives, so that .loc is up to date. */
543 int num_source_filenames = 0;
544
545 /* Count the number of sdb related labels are generated (to find block
546 start and end boundaries). */
547 int sdb_label_count = 0;
548
549 /* Next label # for each statement for Silicon Graphics IRIS systems. */
550 int sym_lineno = 0;
551
552 /* Linked list of all externals that are to be emitted when optimizing
553 for the global pointer if they haven't been declared by the end of
554 the program with an appropriate .comm or initialization. */
555
556 struct extern_list GTY (())
557 {
558 struct extern_list *next; /* next external */
559 const char *name; /* name of the external */
560 int size; /* size in bytes */
561 };
562
563 static GTY (()) struct extern_list *extern_head = 0;
564
565 /* Name of the file containing the current function. */
566 const char *current_function_file = "";
567
568 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
569 int set_noreorder;
570 int set_noat;
571 int set_nomacro;
572 int set_volatile;
573
574 /* The next branch instruction is a branch likely, not branch normal. */
575 int mips_branch_likely;
576
577 /* The operands passed to the last cmpMM expander. */
578 rtx cmp_operands[2];
579
580 /* The target cpu for code generation. */
581 enum processor_type mips_arch;
582 const struct mips_cpu_info *mips_arch_info;
583
584 /* The target cpu for optimization and scheduling. */
585 enum processor_type mips_tune;
586 const struct mips_cpu_info *mips_tune_info;
587
588 /* Which instruction set architecture to use. */
589 int mips_isa;
590
591 /* Which ABI to use. */
592 int mips_abi = MIPS_ABI_DEFAULT;
593
594 /* Cost information to use. */
595 const struct mips_rtx_cost_data *mips_cost;
596
597 /* Whether we are generating mips16 hard float code. In mips16 mode
598 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
599 -msoft-float was not specified by the user, which means that we
600 should arrange to call mips32 hard floating point code. */
601 int mips16_hard_float;
602
603 /* The architecture selected by -mipsN. */
604 static const struct mips_cpu_info *mips_isa_info;
605
606 /* If TRUE, we split addresses into their high and low parts in the RTL. */
607 int mips_split_addresses;
608
609 /* Mode used for saving/restoring general purpose registers. */
610 static enum machine_mode gpr_mode;
611
612 /* Array giving truth value on whether or not a given hard register
613 can support a given mode. */
614 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
615
616 /* List of all MIPS punctuation characters used by print_operand. */
617 char mips_print_operand_punct[256];
618
619 /* Map GCC register number to debugger register number. */
620 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
621
622 /* A copy of the original flag_delayed_branch: see override_options. */
623 static int mips_flag_delayed_branch;
624
625 static GTY (()) int mips_output_filename_first_time = 1;
626
627 /* mips_split_p[X] is true if symbols of type X can be split by
628 mips_split_symbol(). */
629 static bool mips_split_p[NUM_SYMBOL_TYPES];
630
631 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
632 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
633 if they are matched by a special .md file pattern. */
634 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
635
636 /* Likewise for HIGHs. */
637 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
638
639 /* Map hard register number to register class */
640 const enum reg_class mips_regno_to_class[] =
641 {
642 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
643 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
644 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
645 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
646 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
647 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
648 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
649 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
650 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
651 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
652 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
653 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
654 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
655 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
656 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
657 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
658 HI_REG, LO_REG, NO_REGS, ST_REGS,
659 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
660 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
661 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
662 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
663 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
664 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
665 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
666 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
667 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
668 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
669 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
670 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
671 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
672 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
673 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
674 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
675 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
676 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
677 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
678 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
679 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
680 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
681 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
682 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
683 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
684 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
685 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
686 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
687 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
688 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
689 };
690
691 /* Map register constraint character to register class. */
692 enum reg_class mips_char_to_class[256];
693
694 /* Table of machine dependent attributes. */
695 const struct attribute_spec mips_attribute_table[] =
696 {
697 { "long_call", 0, 0, false, true, true, NULL },
698 { NULL, 0, 0, false, false, false, NULL }
699 };
700
701 /* A table describing all the processors gcc knows about. Names are
702 matched in the order listed. The first mention of an ISA level is
703 taken as the canonical name for that ISA.
704
705 To ease comparison, please keep this table in the same order as
706 gas's mips_cpu_info_table[]. */
707 const struct mips_cpu_info mips_cpu_info_table[] = {
708 /* Entries for generic ISAs */
709 { "mips1", PROCESSOR_R3000, 1 },
710 { "mips2", PROCESSOR_R6000, 2 },
711 { "mips3", PROCESSOR_R4000, 3 },
712 { "mips4", PROCESSOR_R8000, 4 },
713 { "mips32", PROCESSOR_4KC, 32 },
714 { "mips32r2", PROCESSOR_M4K, 33 },
715 { "mips64", PROCESSOR_5KC, 64 },
716
717 /* MIPS I */
718 { "r3000", PROCESSOR_R3000, 1 },
719 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
720 { "r3900", PROCESSOR_R3900, 1 },
721
722 /* MIPS II */
723 { "r6000", PROCESSOR_R6000, 2 },
724
725 /* MIPS III */
726 { "r4000", PROCESSOR_R4000, 3 },
727 { "vr4100", PROCESSOR_R4100, 3 },
728 { "vr4111", PROCESSOR_R4111, 3 },
729 { "vr4120", PROCESSOR_R4120, 3 },
730 { "vr4130", PROCESSOR_R4130, 3 },
731 { "vr4300", PROCESSOR_R4300, 3 },
732 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
733 { "r4600", PROCESSOR_R4600, 3 },
734 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
735 { "r4650", PROCESSOR_R4650, 3 },
736
737 /* MIPS IV */
738 { "r8000", PROCESSOR_R8000, 4 },
739 { "vr5000", PROCESSOR_R5000, 4 },
740 { "vr5400", PROCESSOR_R5400, 4 },
741 { "vr5500", PROCESSOR_R5500, 4 },
742 { "rm7000", PROCESSOR_R7000, 4 },
743 { "rm9000", PROCESSOR_R9000, 4 },
744
745 /* MIPS32 */
746 { "4kc", PROCESSOR_4KC, 32 },
747 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
748 { "4kp", PROCESSOR_4KP, 32 },
749
750 /* MIPS32 Release 2 */
751 { "m4k", PROCESSOR_M4K, 33 },
752 { "24k", PROCESSOR_24K, 33 },
753 { "24kc", PROCESSOR_24K, 33 }, /* 24K no FPU */
754 { "24kf", PROCESSOR_24K, 33 }, /* 24K 1:2 FPU */
755 { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
756
757 /* MIPS64 */
758 { "5kc", PROCESSOR_5KC, 64 },
759 { "5kf", PROCESSOR_5KF, 64 },
760 { "20kc", PROCESSOR_20KC, 64 },
761 { "sb1", PROCESSOR_SB1, 64 },
762 { "sr71000", PROCESSOR_SR71000, 64 },
763
764 /* End marker */
765 { 0, 0, 0 }
766 };
767
768 /* Default costs. If these are used for a processor we should look
769 up the actual costs. */
770 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
771 COSTS_N_INSNS (7), /* fp_mult_sf */ \
772 COSTS_N_INSNS (8), /* fp_mult_df */ \
773 COSTS_N_INSNS (23), /* fp_div_sf */ \
774 COSTS_N_INSNS (36), /* fp_div_df */ \
775 COSTS_N_INSNS (10), /* int_mult_si */ \
776 COSTS_N_INSNS (10), /* int_mult_di */ \
777 COSTS_N_INSNS (69), /* int_div_si */ \
778 COSTS_N_INSNS (69), /* int_div_di */ \
779 2, /* branch_cost */ \
780 4 /* memory_latency */
781
782 /* Need to replace these with the costs of calling the appropriate
783 libgcc routine. */
784 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
785 COSTS_N_INSNS (256), /* fp_mult_sf */ \
786 COSTS_N_INSNS (256), /* fp_mult_df */ \
787 COSTS_N_INSNS (256), /* fp_div_sf */ \
788 COSTS_N_INSNS (256) /* fp_div_df */
789
790 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
791 {
792 { /* R3000 */
793 COSTS_N_INSNS (2), /* fp_add */
794 COSTS_N_INSNS (4), /* fp_mult_sf */
795 COSTS_N_INSNS (5), /* fp_mult_df */
796 COSTS_N_INSNS (12), /* fp_div_sf */
797 COSTS_N_INSNS (19), /* fp_div_df */
798 COSTS_N_INSNS (12), /* int_mult_si */
799 COSTS_N_INSNS (12), /* int_mult_di */
800 COSTS_N_INSNS (35), /* int_div_si */
801 COSTS_N_INSNS (35), /* int_div_di */
802 1, /* branch_cost */
803 4 /* memory_latency */
804
805 },
806 { /* 4KC */
807 SOFT_FP_COSTS,
808 COSTS_N_INSNS (6), /* int_mult_si */
809 COSTS_N_INSNS (6), /* int_mult_di */
810 COSTS_N_INSNS (36), /* int_div_si */
811 COSTS_N_INSNS (36), /* int_div_di */
812 1, /* branch_cost */
813 4 /* memory_latency */
814 },
815 { /* 4KP */
816 SOFT_FP_COSTS,
817 COSTS_N_INSNS (36), /* int_mult_si */
818 COSTS_N_INSNS (36), /* int_mult_di */
819 COSTS_N_INSNS (37), /* int_div_si */
820 COSTS_N_INSNS (37), /* int_div_di */
821 1, /* branch_cost */
822 4 /* memory_latency */
823 },
824 { /* 5KC */
825 SOFT_FP_COSTS,
826 COSTS_N_INSNS (4), /* int_mult_si */
827 COSTS_N_INSNS (11), /* int_mult_di */
828 COSTS_N_INSNS (36), /* int_div_si */
829 COSTS_N_INSNS (68), /* int_div_di */
830 1, /* branch_cost */
831 4 /* memory_latency */
832 },
833 { /* 5KF */
834 COSTS_N_INSNS (4), /* fp_add */
835 COSTS_N_INSNS (4), /* fp_mult_sf */
836 COSTS_N_INSNS (5), /* fp_mult_df */
837 COSTS_N_INSNS (17), /* fp_div_sf */
838 COSTS_N_INSNS (32), /* fp_div_df */
839 COSTS_N_INSNS (4), /* int_mult_si */
840 COSTS_N_INSNS (11), /* int_mult_di */
841 COSTS_N_INSNS (36), /* int_div_si */
842 COSTS_N_INSNS (68), /* int_div_di */
843 1, /* branch_cost */
844 4 /* memory_latency */
845 },
846 { /* 20KC */
847 DEFAULT_COSTS
848 },
849 { /* 24k */
850 COSTS_N_INSNS (8), /* fp_add */
851 COSTS_N_INSNS (8), /* fp_mult_sf */
852 COSTS_N_INSNS (10), /* fp_mult_df */
853 COSTS_N_INSNS (34), /* fp_div_sf */
854 COSTS_N_INSNS (64), /* fp_div_df */
855 COSTS_N_INSNS (5), /* int_mult_si */
856 COSTS_N_INSNS (5), /* int_mult_di */
857 COSTS_N_INSNS (41), /* int_div_si */
858 COSTS_N_INSNS (41), /* int_div_di */
859 1, /* branch_cost */
860 4 /* memory_latency */
861 },
862 { /* 24kx */
863 COSTS_N_INSNS (4), /* fp_add */
864 COSTS_N_INSNS (4), /* fp_mult_sf */
865 COSTS_N_INSNS (5), /* fp_mult_df */
866 COSTS_N_INSNS (17), /* fp_div_sf */
867 COSTS_N_INSNS (32), /* fp_div_df */
868 COSTS_N_INSNS (5), /* int_mult_si */
869 COSTS_N_INSNS (5), /* int_mult_di */
870 COSTS_N_INSNS (41), /* int_div_si */
871 COSTS_N_INSNS (41), /* int_div_di */
872 1, /* branch_cost */
873 4 /* memory_latency */
874 },
875 { /* M4k */
876 DEFAULT_COSTS
877 },
878 { /* R3900 */
879 COSTS_N_INSNS (2), /* fp_add */
880 COSTS_N_INSNS (4), /* fp_mult_sf */
881 COSTS_N_INSNS (5), /* fp_mult_df */
882 COSTS_N_INSNS (12), /* fp_div_sf */
883 COSTS_N_INSNS (19), /* fp_div_df */
884 COSTS_N_INSNS (2), /* int_mult_si */
885 COSTS_N_INSNS (2), /* int_mult_di */
886 COSTS_N_INSNS (35), /* int_div_si */
887 COSTS_N_INSNS (35), /* int_div_di */
888 1, /* branch_cost */
889 4 /* memory_latency */
890 },
891 { /* R6000 */
892 COSTS_N_INSNS (3), /* fp_add */
893 COSTS_N_INSNS (5), /* fp_mult_sf */
894 COSTS_N_INSNS (6), /* fp_mult_df */
895 COSTS_N_INSNS (15), /* fp_div_sf */
896 COSTS_N_INSNS (16), /* fp_div_df */
897 COSTS_N_INSNS (17), /* int_mult_si */
898 COSTS_N_INSNS (17), /* int_mult_di */
899 COSTS_N_INSNS (38), /* int_div_si */
900 COSTS_N_INSNS (38), /* int_div_di */
901 2, /* branch_cost */
902 6 /* memory_latency */
903 },
904 { /* R4000 */
905 COSTS_N_INSNS (6), /* fp_add */
906 COSTS_N_INSNS (7), /* fp_mult_sf */
907 COSTS_N_INSNS (8), /* fp_mult_df */
908 COSTS_N_INSNS (23), /* fp_div_sf */
909 COSTS_N_INSNS (36), /* fp_div_df */
910 COSTS_N_INSNS (10), /* int_mult_si */
911 COSTS_N_INSNS (10), /* int_mult_di */
912 COSTS_N_INSNS (69), /* int_div_si */
913 COSTS_N_INSNS (69), /* int_div_di */
914 2, /* branch_cost */
915 6 /* memory_latency */
916 },
917 { /* R4100 */
918 DEFAULT_COSTS
919 },
920 { /* R4111 */
921 DEFAULT_COSTS
922 },
923 { /* R4120 */
924 DEFAULT_COSTS
925 },
926 { /* R4130 */
927 /* The only costs that appear to be updated here are
928 integer multiplication. */
929 SOFT_FP_COSTS,
930 COSTS_N_INSNS (4), /* int_mult_si */
931 COSTS_N_INSNS (6), /* int_mult_di */
932 COSTS_N_INSNS (69), /* int_div_si */
933 COSTS_N_INSNS (69), /* int_div_di */
934 1, /* branch_cost */
935 4 /* memory_latency */
936 },
937 { /* R4300 */
938 DEFAULT_COSTS
939 },
940 { /* R4600 */
941 DEFAULT_COSTS
942 },
943 { /* R4650 */
944 DEFAULT_COSTS
945 },
946 { /* R5000 */
947 COSTS_N_INSNS (6), /* fp_add */
948 COSTS_N_INSNS (4), /* fp_mult_sf */
949 COSTS_N_INSNS (5), /* fp_mult_df */
950 COSTS_N_INSNS (23), /* fp_div_sf */
951 COSTS_N_INSNS (36), /* fp_div_df */
952 COSTS_N_INSNS (5), /* int_mult_si */
953 COSTS_N_INSNS (5), /* int_mult_di */
954 COSTS_N_INSNS (36), /* int_div_si */
955 COSTS_N_INSNS (36), /* int_div_di */
956 1, /* branch_cost */
957 4 /* memory_latency */
958 },
959 { /* R5400 */
960 COSTS_N_INSNS (6), /* fp_add */
961 COSTS_N_INSNS (5), /* fp_mult_sf */
962 COSTS_N_INSNS (6), /* fp_mult_df */
963 COSTS_N_INSNS (30), /* fp_div_sf */
964 COSTS_N_INSNS (59), /* fp_div_df */
965 COSTS_N_INSNS (3), /* int_mult_si */
966 COSTS_N_INSNS (4), /* int_mult_di */
967 COSTS_N_INSNS (42), /* int_div_si */
968 COSTS_N_INSNS (74), /* int_div_di */
969 1, /* branch_cost */
970 4 /* memory_latency */
971 },
972 { /* R5500 */
973 COSTS_N_INSNS (6), /* fp_add */
974 COSTS_N_INSNS (5), /* fp_mult_sf */
975 COSTS_N_INSNS (6), /* fp_mult_df */
976 COSTS_N_INSNS (30), /* fp_div_sf */
977 COSTS_N_INSNS (59), /* fp_div_df */
978 COSTS_N_INSNS (5), /* int_mult_si */
979 COSTS_N_INSNS (9), /* int_mult_di */
980 COSTS_N_INSNS (42), /* int_div_si */
981 COSTS_N_INSNS (74), /* int_div_di */
982 1, /* branch_cost */
983 4 /* memory_latency */
984 },
985 { /* R7000 */
986 /* The only costs that are changed here are
987 integer multiplication. */
988 COSTS_N_INSNS (6), /* fp_add */
989 COSTS_N_INSNS (7), /* fp_mult_sf */
990 COSTS_N_INSNS (8), /* fp_mult_df */
991 COSTS_N_INSNS (23), /* fp_div_sf */
992 COSTS_N_INSNS (36), /* fp_div_df */
993 COSTS_N_INSNS (5), /* int_mult_si */
994 COSTS_N_INSNS (9), /* int_mult_di */
995 COSTS_N_INSNS (69), /* int_div_si */
996 COSTS_N_INSNS (69), /* int_div_di */
997 1, /* branch_cost */
998 4 /* memory_latency */
999 },
1000 { /* R8000 */
1001 DEFAULT_COSTS
1002 },
1003 { /* R9000 */
1004 /* The only costs that are changed here are
1005 integer multiplication. */
1006 COSTS_N_INSNS (6), /* fp_add */
1007 COSTS_N_INSNS (7), /* fp_mult_sf */
1008 COSTS_N_INSNS (8), /* fp_mult_df */
1009 COSTS_N_INSNS (23), /* fp_div_sf */
1010 COSTS_N_INSNS (36), /* fp_div_df */
1011 COSTS_N_INSNS (3), /* int_mult_si */
1012 COSTS_N_INSNS (8), /* int_mult_di */
1013 COSTS_N_INSNS (69), /* int_div_si */
1014 COSTS_N_INSNS (69), /* int_div_di */
1015 1, /* branch_cost */
1016 4 /* memory_latency */
1017 },
1018 { /* SB1 */
1019 COSTS_N_INSNS (4), /* fp_add */
1020 COSTS_N_INSNS (4), /* fp_mult_sf */
1021 COSTS_N_INSNS (4), /* fp_mult_df */
1022 COSTS_N_INSNS (24), /* fp_div_sf */
1023 COSTS_N_INSNS (32), /* fp_div_df */
1024 COSTS_N_INSNS (3), /* int_mult_si */
1025 COSTS_N_INSNS (4), /* int_mult_di */
1026 COSTS_N_INSNS (36), /* int_div_si */
1027 COSTS_N_INSNS (68), /* int_div_di */
1028 1, /* branch_cost */
1029 4 /* memory_latency */
1030 },
1031 { /* SR71000 */
1032 DEFAULT_COSTS
1033 },
1034 };
1035
1036
1037 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1038 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1039 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1040 #endif
1041
1042 /* Initialize the GCC target structure. */
1043 #undef TARGET_ASM_ALIGNED_HI_OP
1044 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1045 #undef TARGET_ASM_ALIGNED_SI_OP
1046 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1047 #undef TARGET_ASM_ALIGNED_DI_OP
1048 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1049
1050 #undef TARGET_ASM_FUNCTION_PROLOGUE
1051 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1052 #undef TARGET_ASM_FUNCTION_EPILOGUE
1053 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1054 #undef TARGET_ASM_SELECT_RTX_SECTION
1055 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1056 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1057 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1058
1059 #undef TARGET_SCHED_REORDER
1060 #define TARGET_SCHED_REORDER mips_sched_reorder
1061 #undef TARGET_SCHED_VARIABLE_ISSUE
1062 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1063 #undef TARGET_SCHED_ADJUST_COST
1064 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1065 #undef TARGET_SCHED_ISSUE_RATE
1066 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1067 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1068 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1069 mips_multipass_dfa_lookahead
1070
1071 #undef TARGET_DEFAULT_TARGET_FLAGS
1072 #define TARGET_DEFAULT_TARGET_FLAGS \
1073 (TARGET_DEFAULT \
1074 | TARGET_CPU_DEFAULT \
1075 | TARGET_ENDIAN_DEFAULT \
1076 | TARGET_FP_EXCEPTIONS_DEFAULT \
1077 | MASK_CHECK_ZERO_DIV \
1078 | MASK_FUSED_MADD)
1079 #undef TARGET_HANDLE_OPTION
1080 #define TARGET_HANDLE_OPTION mips_handle_option
1081
1082 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1083 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1084
1085 #undef TARGET_VALID_POINTER_MODE
1086 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1087 #undef TARGET_RTX_COSTS
1088 #define TARGET_RTX_COSTS mips_rtx_costs
1089 #undef TARGET_ADDRESS_COST
1090 #define TARGET_ADDRESS_COST mips_address_cost
1091
1092 #undef TARGET_IN_SMALL_DATA_P
1093 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1094
1095 #undef TARGET_MACHINE_DEPENDENT_REORG
1096 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1097
1098 #undef TARGET_ASM_FILE_START
1099 #undef TARGET_ASM_FILE_END
1100 #define TARGET_ASM_FILE_START mips_file_start
1101 #define TARGET_ASM_FILE_END mips_file_end
1102 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1103 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1104
1105 #undef TARGET_INIT_LIBFUNCS
1106 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1107
1108 #undef TARGET_BUILD_BUILTIN_VA_LIST
1109 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1110 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1111 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1112
1113 #undef TARGET_PROMOTE_FUNCTION_ARGS
1114 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1115 #undef TARGET_PROMOTE_FUNCTION_RETURN
1116 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1117 #undef TARGET_PROMOTE_PROTOTYPES
1118 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1119
1120 #undef TARGET_RETURN_IN_MEMORY
1121 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1122 #undef TARGET_RETURN_IN_MSB
1123 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1124
1125 #undef TARGET_ASM_OUTPUT_MI_THUNK
1126 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1127 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1128 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1129
1130 #undef TARGET_SETUP_INCOMING_VARARGS
1131 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1132 #undef TARGET_STRICT_ARGUMENT_NAMING
1133 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1134 #undef TARGET_MUST_PASS_IN_STACK
1135 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1136 #undef TARGET_PASS_BY_REFERENCE
1137 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1138 #undef TARGET_CALLEE_COPIES
1139 #define TARGET_CALLEE_COPIES mips_callee_copies
1140 #undef TARGET_ARG_PARTIAL_BYTES
1141 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1142
1143 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1144 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1145
1146 #undef TARGET_INIT_BUILTINS
1147 #define TARGET_INIT_BUILTINS mips_init_builtins
1148 #undef TARGET_EXPAND_BUILTIN
1149 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1150
1151 #undef TARGET_HAVE_TLS
1152 #define TARGET_HAVE_TLS HAVE_AS_TLS
1153
1154 #undef TARGET_CANNOT_FORCE_CONST_MEM
1155 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1156
1157 #undef TARGET_ENCODE_SECTION_INFO
1158 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1159
1160 #undef TARGET_ATTRIBUTE_TABLE
1161 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1162
1163 struct gcc_target targetm = TARGET_INITIALIZER;
1164
1165 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1166
1167 static enum mips_symbol_type
mips_classify_symbol(rtx x)1168 mips_classify_symbol (rtx x)
1169 {
1170 if (GET_CODE (x) == LABEL_REF)
1171 {
1172 if (TARGET_MIPS16)
1173 return SYMBOL_CONSTANT_POOL;
1174 if (TARGET_ABICALLS)
1175 return SYMBOL_GOT_LOCAL;
1176 return SYMBOL_GENERAL;
1177 }
1178
1179 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1180
1181 if (SYMBOL_REF_TLS_MODEL (x))
1182 return SYMBOL_TLS;
1183
1184 if (CONSTANT_POOL_ADDRESS_P (x))
1185 {
1186 if (TARGET_MIPS16)
1187 return SYMBOL_CONSTANT_POOL;
1188
1189 if (TARGET_ABICALLS)
1190 return SYMBOL_GOT_LOCAL;
1191
1192 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1193 return SYMBOL_SMALL_DATA;
1194
1195 return SYMBOL_GENERAL;
1196 }
1197
1198 if (SYMBOL_REF_SMALL_P (x))
1199 return SYMBOL_SMALL_DATA;
1200
1201 if (TARGET_ABICALLS)
1202 {
1203 if (SYMBOL_REF_DECL (x) == 0)
1204 return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
1205
1206 /* There are three cases to consider:
1207
1208 - o32 PIC (either with or without explicit relocs)
1209 - n32/n64 PIC without explicit relocs
1210 - n32/n64 PIC with explicit relocs
1211
1212 In the first case, both local and global accesses will use an
1213 R_MIPS_GOT16 relocation. We must correctly predict which of
1214 the two semantics (local or global) the assembler and linker
1215 will apply. The choice doesn't depend on the symbol's
1216 visibility, so we deliberately ignore decl_visibility and
1217 binds_local_p here.
1218
1219 In the second case, the assembler will not use R_MIPS_GOT16
1220 relocations, but it chooses between local and global accesses
1221 in the same way as for o32 PIC.
1222
1223 In the third case we have more freedom since both forms of
1224 access will work for any kind of symbol. However, there seems
1225 little point in doing things differently. */
1226 if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
1227 return SYMBOL_GOT_GLOBAL;
1228
1229 return SYMBOL_GOT_LOCAL;
1230 }
1231
1232 return SYMBOL_GENERAL;
1233 }
1234
1235
1236 /* Split X into a base and a constant offset, storing them in *BASE
1237 and *OFFSET respectively. */
1238
1239 static void
mips_split_const(rtx x,rtx * base,HOST_WIDE_INT * offset)1240 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
1241 {
1242 *offset = 0;
1243
1244 if (GET_CODE (x) == CONST)
1245 x = XEXP (x, 0);
1246
1247 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1248 {
1249 *offset += INTVAL (XEXP (x, 1));
1250 x = XEXP (x, 0);
1251 }
1252 *base = x;
1253 }
1254
1255
1256 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
1257 to the same object as SYMBOL. */
1258
1259 static bool
mips_offset_within_object_p(rtx symbol,HOST_WIDE_INT offset)1260 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
1261 {
1262 if (GET_CODE (symbol) != SYMBOL_REF)
1263 return false;
1264
1265 if (CONSTANT_POOL_ADDRESS_P (symbol)
1266 && offset >= 0
1267 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
1268 return true;
1269
1270 if (SYMBOL_REF_DECL (symbol) != 0
1271 && offset >= 0
1272 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
1273 return true;
1274
1275 return false;
1276 }
1277
1278
1279 /* Return true if X is a symbolic constant that can be calculated in
1280 the same way as a bare symbol. If it is, store the type of the
1281 symbol in *SYMBOL_TYPE. */
1282
1283 bool
mips_symbolic_constant_p(rtx x,enum mips_symbol_type * symbol_type)1284 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1285 {
1286 HOST_WIDE_INT offset;
1287
1288 mips_split_const (x, &x, &offset);
1289 if (UNSPEC_ADDRESS_P (x))
1290 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1291 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1292 {
1293 *symbol_type = mips_classify_symbol (x);
1294 if (*symbol_type == SYMBOL_TLS)
1295 return false;
1296 }
1297 else
1298 return false;
1299
1300 if (offset == 0)
1301 return true;
1302
1303 /* Check whether a nonzero offset is valid for the underlying
1304 relocations. */
1305 switch (*symbol_type)
1306 {
1307 case SYMBOL_GENERAL:
1308 case SYMBOL_64_HIGH:
1309 case SYMBOL_64_MID:
1310 case SYMBOL_64_LOW:
1311 /* If the target has 64-bit pointers and the object file only
1312 supports 32-bit symbols, the values of those symbols will be
1313 sign-extended. In this case we can't allow an arbitrary offset
1314 in case the 32-bit value X + OFFSET has a different sign from X. */
1315 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1316 return mips_offset_within_object_p (x, offset);
1317
1318 /* In other cases the relocations can handle any offset. */
1319 return true;
1320
1321 case SYMBOL_CONSTANT_POOL:
1322 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1323 In this case, we no longer have access to the underlying constant,
1324 but the original symbol-based access was known to be valid. */
1325 if (GET_CODE (x) == LABEL_REF)
1326 return true;
1327
1328 /* Fall through. */
1329
1330 case SYMBOL_SMALL_DATA:
1331 /* Make sure that the offset refers to something within the
1332 underlying object. This should guarantee that the final
1333 PC- or GP-relative offset is within the 16-bit limit. */
1334 return mips_offset_within_object_p (x, offset);
1335
1336 case SYMBOL_GOT_LOCAL:
1337 case SYMBOL_GOTOFF_PAGE:
1338 /* The linker should provide enough local GOT entries for a
1339 16-bit offset. Larger offsets may lead to GOT overflow. */
1340 return SMALL_OPERAND (offset);
1341
1342 case SYMBOL_GOT_GLOBAL:
1343 case SYMBOL_GOTOFF_GLOBAL:
1344 case SYMBOL_GOTOFF_CALL:
1345 case SYMBOL_GOTOFF_LOADGP:
1346 case SYMBOL_TLSGD:
1347 case SYMBOL_TLSLDM:
1348 case SYMBOL_DTPREL:
1349 case SYMBOL_TPREL:
1350 case SYMBOL_GOTTPREL:
1351 case SYMBOL_TLS:
1352 return false;
1353 }
1354 gcc_unreachable ();
1355 }
1356
1357
1358 /* Return true if X is a symbolic constant whose value is not split
1359 into separate relocations. */
1360
1361 bool
mips_atomic_symbolic_constant_p(rtx x)1362 mips_atomic_symbolic_constant_p (rtx x)
1363 {
1364 enum mips_symbol_type type;
1365 return mips_symbolic_constant_p (x, &type) && !mips_split_p[type];
1366 }
1367
1368
1369 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1370
1371 int
mips_regno_mode_ok_for_base_p(int regno,enum machine_mode mode,int strict)1372 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1373 {
1374 if (regno >= FIRST_PSEUDO_REGISTER)
1375 {
1376 if (!strict)
1377 return true;
1378 regno = reg_renumber[regno];
1379 }
1380
1381 /* These fake registers will be eliminated to either the stack or
1382 hard frame pointer, both of which are usually valid base registers.
1383 Reload deals with the cases where the eliminated form isn't valid. */
1384 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1385 return true;
1386
1387 /* In mips16 mode, the stack pointer can only address word and doubleword
1388 values, nothing smaller. There are two problems here:
1389
1390 (a) Instantiating virtual registers can introduce new uses of the
1391 stack pointer. If these virtual registers are valid addresses,
1392 the stack pointer should be too.
1393
1394 (b) Most uses of the stack pointer are not made explicit until
1395 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1396 We don't know until that stage whether we'll be eliminating to the
1397 stack pointer (which needs the restriction) or the hard frame
1398 pointer (which doesn't).
1399
1400 All in all, it seems more consistent to only enforce this restriction
1401 during and after reload. */
1402 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1403 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1404
1405 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1406 }
1407
1408
1409 /* Return true if X is a valid base register for the given mode.
1410 Allow only hard registers if STRICT. */
1411
1412 static bool
mips_valid_base_register_p(rtx x,enum machine_mode mode,int strict)1413 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1414 {
1415 if (!strict && GET_CODE (x) == SUBREG)
1416 x = SUBREG_REG (x);
1417
1418 return (REG_P (x)
1419 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1420 }
1421
1422
1423 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1424 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1425
1426 static bool
mips_symbolic_address_p(enum mips_symbol_type symbol_type,enum machine_mode mode)1427 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1428 enum machine_mode mode)
1429 {
1430 switch (symbol_type)
1431 {
1432 case SYMBOL_GENERAL:
1433 return !TARGET_MIPS16;
1434
1435 case SYMBOL_SMALL_DATA:
1436 return true;
1437
1438 case SYMBOL_CONSTANT_POOL:
1439 /* PC-relative addressing is only available for lw and ld. */
1440 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1441
1442 case SYMBOL_GOT_LOCAL:
1443 return true;
1444
1445 case SYMBOL_GOT_GLOBAL:
1446 /* The address will have to be loaded from the GOT first. */
1447 return false;
1448
1449 case SYMBOL_GOTOFF_PAGE:
1450 case SYMBOL_GOTOFF_GLOBAL:
1451 case SYMBOL_GOTOFF_CALL:
1452 case SYMBOL_GOTOFF_LOADGP:
1453 case SYMBOL_TLS:
1454 case SYMBOL_TLSGD:
1455 case SYMBOL_TLSLDM:
1456 case SYMBOL_DTPREL:
1457 case SYMBOL_GOTTPREL:
1458 case SYMBOL_TPREL:
1459 case SYMBOL_64_HIGH:
1460 case SYMBOL_64_MID:
1461 case SYMBOL_64_LOW:
1462 return true;
1463 }
1464 gcc_unreachable ();
1465 }
1466
1467
1468 /* Return true if X is a valid address for machine mode MODE. If it is,
1469 fill in INFO appropriately. STRICT is true if we should only accept
1470 hard base registers. */
1471
1472 static bool
mips_classify_address(struct mips_address_info * info,rtx x,enum machine_mode mode,int strict)1473 mips_classify_address (struct mips_address_info *info, rtx x,
1474 enum machine_mode mode, int strict)
1475 {
1476 switch (GET_CODE (x))
1477 {
1478 case REG:
1479 case SUBREG:
1480 info->type = ADDRESS_REG;
1481 info->reg = x;
1482 info->offset = const0_rtx;
1483 return mips_valid_base_register_p (info->reg, mode, strict);
1484
1485 case PLUS:
1486 info->type = ADDRESS_REG;
1487 info->reg = XEXP (x, 0);
1488 info->offset = XEXP (x, 1);
1489 return (mips_valid_base_register_p (info->reg, mode, strict)
1490 && const_arith_operand (info->offset, VOIDmode));
1491
1492 case LO_SUM:
1493 info->type = ADDRESS_LO_SUM;
1494 info->reg = XEXP (x, 0);
1495 info->offset = XEXP (x, 1);
1496 return (mips_valid_base_register_p (info->reg, mode, strict)
1497 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1498 && mips_symbolic_address_p (info->symbol_type, mode)
1499 && mips_lo_relocs[info->symbol_type] != 0);
1500
1501 case CONST_INT:
1502 /* Small-integer addresses don't occur very often, but they
1503 are legitimate if $0 is a valid base register. */
1504 info->type = ADDRESS_CONST_INT;
1505 return !TARGET_MIPS16 && SMALL_INT (x);
1506
1507 case CONST:
1508 case LABEL_REF:
1509 case SYMBOL_REF:
1510 info->type = ADDRESS_SYMBOLIC;
1511 return (mips_symbolic_constant_p (x, &info->symbol_type)
1512 && mips_symbolic_address_p (info->symbol_type, mode)
1513 && !mips_split_p[info->symbol_type]);
1514
1515 default:
1516 return false;
1517 }
1518 }
1519
1520 /* Return true if X is a thread-local symbol. */
1521
1522 static bool
mips_tls_operand_p(rtx x)1523 mips_tls_operand_p (rtx x)
1524 {
1525 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1526 }
1527
1528 /* Return true if X can not be forced into a constant pool. */
1529
1530 static int
mips_tls_symbol_ref_1(rtx * x,void * data ATTRIBUTE_UNUSED)1531 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1532 {
1533 return mips_tls_operand_p (*x);
1534 }
1535
1536 /* Return true if X can not be forced into a constant pool. */
1537
1538 static bool
mips_cannot_force_const_mem(rtx x)1539 mips_cannot_force_const_mem (rtx x)
1540 {
1541 if (! TARGET_HAVE_TLS)
1542 return false;
1543
1544 return for_each_rtx (&x, &mips_tls_symbol_ref_1, 0);
1545 }
1546
1547 /* Return the number of instructions needed to load a symbol of the
1548 given type into a register. If valid in an address, the same number
1549 of instructions are needed for loads and stores. Treat extended
1550 mips16 instructions as two instructions. */
1551
1552 static int
mips_symbol_insns(enum mips_symbol_type type)1553 mips_symbol_insns (enum mips_symbol_type type)
1554 {
1555 switch (type)
1556 {
1557 case SYMBOL_GENERAL:
1558 /* In mips16 code, general symbols must be fetched from the
1559 constant pool. */
1560 if (TARGET_MIPS16)
1561 return 0;
1562
1563 /* When using 64-bit symbols, we need 5 preparatory instructions,
1564 such as:
1565
1566 lui $at,%highest(symbol)
1567 daddiu $at,$at,%higher(symbol)
1568 dsll $at,$at,16
1569 daddiu $at,$at,%hi(symbol)
1570 dsll $at,$at,16
1571
1572 The final address is then $at + %lo(symbol). With 32-bit
1573 symbols we just need a preparatory lui. */
1574 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1575
1576 case SYMBOL_SMALL_DATA:
1577 return 1;
1578
1579 case SYMBOL_CONSTANT_POOL:
1580 /* This case is for mips16 only. Assume we'll need an
1581 extended instruction. */
1582 return 2;
1583
1584 case SYMBOL_GOT_LOCAL:
1585 case SYMBOL_GOT_GLOBAL:
1586 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1587 the local/global classification is accurate. See override_options
1588 for details.
1589
1590 The worst cases are:
1591
1592 (1) For local symbols when generating o32 or o64 code. The assembler
1593 will use:
1594
1595 lw $at,%got(symbol)
1596 nop
1597
1598 ...and the final address will be $at + %lo(symbol).
1599
1600 (2) For global symbols when -mxgot. The assembler will use:
1601
1602 lui $at,%got_hi(symbol)
1603 (d)addu $at,$at,$gp
1604
1605 ...and the final address will be $at + %got_lo(symbol). */
1606 return 3;
1607
1608 case SYMBOL_GOTOFF_PAGE:
1609 case SYMBOL_GOTOFF_GLOBAL:
1610 case SYMBOL_GOTOFF_CALL:
1611 case SYMBOL_GOTOFF_LOADGP:
1612 case SYMBOL_64_HIGH:
1613 case SYMBOL_64_MID:
1614 case SYMBOL_64_LOW:
1615 case SYMBOL_TLSGD:
1616 case SYMBOL_TLSLDM:
1617 case SYMBOL_DTPREL:
1618 case SYMBOL_GOTTPREL:
1619 case SYMBOL_TPREL:
1620 /* Check whether the offset is a 16- or 32-bit value. */
1621 return mips_split_p[type] ? 2 : 1;
1622
1623 case SYMBOL_TLS:
1624 /* We don't treat a bare TLS symbol as a constant. */
1625 return 0;
1626 }
1627 gcc_unreachable ();
1628 }
1629
1630 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1631
1632 bool
mips_stack_address_p(rtx x,enum machine_mode mode)1633 mips_stack_address_p (rtx x, enum machine_mode mode)
1634 {
1635 struct mips_address_info addr;
1636
1637 return (mips_classify_address (&addr, x, mode, false)
1638 && addr.type == ADDRESS_REG
1639 && addr.reg == stack_pointer_rtx);
1640 }
1641
1642 /* Return true if a value at OFFSET bytes from BASE can be accessed
1643 using an unextended mips16 instruction. MODE is the mode of the
1644 value.
1645
1646 Usually the offset in an unextended instruction is a 5-bit field.
1647 The offset is unsigned and shifted left once for HIs, twice
1648 for SIs, and so on. An exception is SImode accesses off the
1649 stack pointer, which have an 8-bit immediate field. */
1650
1651 static bool
mips16_unextended_reference_p(enum machine_mode mode,rtx base,rtx offset)1652 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1653 {
1654 if (TARGET_MIPS16
1655 && GET_CODE (offset) == CONST_INT
1656 && INTVAL (offset) >= 0
1657 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1658 {
1659 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1660 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1661 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1662 }
1663 return false;
1664 }
1665
1666
1667 /* Return the number of instructions needed to load or store a value
1668 of mode MODE at X. Return 0 if X isn't valid for MODE.
1669
1670 For mips16 code, count extended instructions as two instructions. */
1671
1672 int
mips_address_insns(rtx x,enum machine_mode mode)1673 mips_address_insns (rtx x, enum machine_mode mode)
1674 {
1675 struct mips_address_info addr;
1676 int factor;
1677
1678 if (mode == BLKmode)
1679 /* BLKmode is used for single unaligned loads and stores. */
1680 factor = 1;
1681 else
1682 /* Each word of a multi-word value will be accessed individually. */
1683 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1684
1685 if (mips_classify_address (&addr, x, mode, false))
1686 switch (addr.type)
1687 {
1688 case ADDRESS_REG:
1689 if (TARGET_MIPS16
1690 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1691 return factor * 2;
1692 return factor;
1693
1694 case ADDRESS_LO_SUM:
1695 return (TARGET_MIPS16 ? factor * 2 : factor);
1696
1697 case ADDRESS_CONST_INT:
1698 return factor;
1699
1700 case ADDRESS_SYMBOLIC:
1701 return factor * mips_symbol_insns (addr.symbol_type);
1702 }
1703 return 0;
1704 }
1705
1706
1707 /* Likewise for constant X. */
1708
1709 int
mips_const_insns(rtx x)1710 mips_const_insns (rtx x)
1711 {
1712 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1713 enum mips_symbol_type symbol_type;
1714 HOST_WIDE_INT offset;
1715
1716 switch (GET_CODE (x))
1717 {
1718 case HIGH:
1719 if (TARGET_MIPS16
1720 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1721 || !mips_split_p[symbol_type])
1722 return 0;
1723
1724 return 1;
1725
1726 case CONST_INT:
1727 if (TARGET_MIPS16)
1728 /* Unsigned 8-bit constants can be loaded using an unextended
1729 LI instruction. Unsigned 16-bit constants can be loaded
1730 using an extended LI. Negative constants must be loaded
1731 using LI and then negated. */
1732 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1733 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1734 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1735 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1736 : 0);
1737
1738 return mips_build_integer (codes, INTVAL (x));
1739
1740 case CONST_DOUBLE:
1741 case CONST_VECTOR:
1742 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1743
1744 case CONST:
1745 if (CONST_GP_P (x))
1746 return 1;
1747
1748 /* See if we can refer to X directly. */
1749 if (mips_symbolic_constant_p (x, &symbol_type))
1750 return mips_symbol_insns (symbol_type);
1751
1752 /* Otherwise try splitting the constant into a base and offset.
1753 16-bit offsets can be added using an extra addiu. Larger offsets
1754 must be calculated separately and then added to the base. */
1755 mips_split_const (x, &x, &offset);
1756 if (offset != 0)
1757 {
1758 int n = mips_const_insns (x);
1759 if (n != 0)
1760 {
1761 if (SMALL_OPERAND (offset))
1762 return n + 1;
1763 else
1764 return n + 1 + mips_build_integer (codes, offset);
1765 }
1766 }
1767 return 0;
1768
1769 case SYMBOL_REF:
1770 case LABEL_REF:
1771 return mips_symbol_insns (mips_classify_symbol (x));
1772
1773 default:
1774 return 0;
1775 }
1776 }
1777
1778
1779 /* Return the number of instructions needed for memory reference X.
1780 Count extended mips16 instructions as two instructions. */
1781
1782 int
mips_fetch_insns(rtx x)1783 mips_fetch_insns (rtx x)
1784 {
1785 gcc_assert (MEM_P (x));
1786 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1787 }
1788
1789
1790 /* Return the number of instructions needed for an integer division. */
1791
1792 int
mips_idiv_insns(void)1793 mips_idiv_insns (void)
1794 {
1795 int count;
1796
1797 count = 1;
1798 if (TARGET_CHECK_ZERO_DIV)
1799 {
1800 if (GENERATE_DIVIDE_TRAPS)
1801 count++;
1802 else
1803 count += 2;
1804 }
1805
1806 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1807 count++;
1808 return count;
1809 }
1810
1811 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1812 returns a nonzero value if X is a legitimate address for a memory
1813 operand of the indicated MODE. STRICT is nonzero if this function
1814 is called during reload. */
1815
1816 bool
mips_legitimate_address_p(enum machine_mode mode,rtx x,int strict)1817 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1818 {
1819 struct mips_address_info addr;
1820
1821 return mips_classify_address (&addr, x, mode, strict);
1822 }
1823
1824
1825 /* Copy VALUE to a register and return that register. If new psuedos
1826 are allowed, copy it into a new register, otherwise use DEST. */
1827
1828 static rtx
mips_force_temporary(rtx dest,rtx value)1829 mips_force_temporary (rtx dest, rtx value)
1830 {
1831 if (!no_new_pseudos)
1832 return force_reg (Pmode, value);
1833 else
1834 {
1835 emit_move_insn (copy_rtx (dest), value);
1836 return dest;
1837 }
1838 }
1839
1840
1841 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1842 and is used to load the high part into a register. */
1843
1844 static rtx
mips_split_symbol(rtx temp,rtx addr)1845 mips_split_symbol (rtx temp, rtx addr)
1846 {
1847 rtx high;
1848
1849 if (TARGET_MIPS16)
1850 high = mips16_gp_pseudo_reg ();
1851 else
1852 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1853 return gen_rtx_LO_SUM (Pmode, high, addr);
1854 }
1855
1856
1857 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1858 type SYMBOL_TYPE. */
1859
1860 rtx
mips_unspec_address(rtx address,enum mips_symbol_type symbol_type)1861 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1862 {
1863 rtx base;
1864 HOST_WIDE_INT offset;
1865
1866 mips_split_const (address, &base, &offset);
1867 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1868 UNSPEC_ADDRESS_FIRST + symbol_type);
1869 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1870 }
1871
1872
1873 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1874 high part to BASE and return the result. Just return BASE otherwise.
1875 TEMP is available as a temporary register if needed.
1876
1877 The returned expression can be used as the first operand to a LO_SUM. */
1878
1879 static rtx
mips_unspec_offset_high(rtx temp,rtx base,rtx addr,enum mips_symbol_type symbol_type)1880 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1881 enum mips_symbol_type symbol_type)
1882 {
1883 if (mips_split_p[symbol_type])
1884 {
1885 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1886 addr = mips_force_temporary (temp, addr);
1887 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1888 }
1889 return base;
1890 }
1891
1892
1893 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1894 mips_force_temporary; it is only needed when OFFSET is not a
1895 SMALL_OPERAND. */
1896
1897 static rtx
mips_add_offset(rtx temp,rtx reg,HOST_WIDE_INT offset)1898 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1899 {
1900 if (!SMALL_OPERAND (offset))
1901 {
1902 rtx high;
1903 if (TARGET_MIPS16)
1904 {
1905 /* Load the full offset into a register so that we can use
1906 an unextended instruction for the address itself. */
1907 high = GEN_INT (offset);
1908 offset = 0;
1909 }
1910 else
1911 {
1912 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1913 high = GEN_INT (CONST_HIGH_PART (offset));
1914 offset = CONST_LOW_PART (offset);
1915 }
1916 high = mips_force_temporary (temp, high);
1917 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
1918 }
1919 return plus_constant (reg, offset);
1920 }
1921
1922 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
1923 referencing, and TYPE is the symbol type to use (either global
1924 dynamic or local dynamic). V0 is an RTX for the return value
1925 location. The entire insn sequence is returned. */
1926
1927 static GTY(()) rtx mips_tls_symbol;
1928
1929 static rtx
mips_call_tls_get_addr(rtx sym,enum mips_symbol_type type,rtx v0)1930 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
1931 {
1932 rtx insn, loc, tga, a0;
1933
1934 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
1935
1936 if (!mips_tls_symbol)
1937 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
1938
1939 loc = mips_unspec_address (sym, type);
1940
1941 start_sequence ();
1942
1943 emit_insn (gen_rtx_SET (Pmode, a0,
1944 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
1945 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
1946 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
1947 CONST_OR_PURE_CALL_P (insn) = 1;
1948 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
1949 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
1950 insn = get_insns ();
1951
1952 end_sequence ();
1953
1954 return insn;
1955 }
1956
1957 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
1958 return value will be a valid address and move_operand (either a REG
1959 or a LO_SUM). */
1960
1961 static rtx
mips_legitimize_tls_address(rtx loc)1962 mips_legitimize_tls_address (rtx loc)
1963 {
1964 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
1965 enum tls_model model;
1966
1967 v0 = gen_rtx_REG (Pmode, GP_RETURN);
1968 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
1969
1970 model = SYMBOL_REF_TLS_MODEL (loc);
1971
1972 switch (model)
1973 {
1974 case TLS_MODEL_GLOBAL_DYNAMIC:
1975 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
1976 dest = gen_reg_rtx (Pmode);
1977 emit_libcall_block (insn, dest, v0, loc);
1978 break;
1979
1980 case TLS_MODEL_LOCAL_DYNAMIC:
1981 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
1982 tmp1 = gen_reg_rtx (Pmode);
1983
1984 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
1985 share the LDM result with other LD model accesses. */
1986 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1987 UNSPEC_TLS_LDM);
1988 emit_libcall_block (insn, tmp1, v0, eqv);
1989
1990 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
1991 dest = gen_rtx_LO_SUM (Pmode, tmp2,
1992 mips_unspec_address (loc, SYMBOL_DTPREL));
1993 break;
1994
1995 case TLS_MODEL_INITIAL_EXEC:
1996 tmp1 = gen_reg_rtx (Pmode);
1997 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
1998 if (Pmode == DImode)
1999 {
2000 emit_insn (gen_tls_get_tp_di (v1));
2001 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2002 }
2003 else
2004 {
2005 emit_insn (gen_tls_get_tp_si (v1));
2006 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2007 }
2008 dest = gen_reg_rtx (Pmode);
2009 emit_insn (gen_add3_insn (dest, tmp1, v1));
2010 break;
2011
2012 case TLS_MODEL_LOCAL_EXEC:
2013
2014 if (Pmode == DImode)
2015 emit_insn (gen_tls_get_tp_di (v1));
2016 else
2017 emit_insn (gen_tls_get_tp_si (v1));
2018
2019 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2020 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2021 mips_unspec_address (loc, SYMBOL_TPREL));
2022 break;
2023
2024 default:
2025 gcc_unreachable ();
2026 }
2027
2028 return dest;
2029 }
2030
2031 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2032 be legitimized in a way that the generic machinery might not expect,
2033 put the new address in *XLOC and return true. MODE is the mode of
2034 the memory being accessed. */
2035
2036 bool
mips_legitimize_address(rtx * xloc,enum machine_mode mode)2037 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2038 {
2039 enum mips_symbol_type symbol_type;
2040
2041 if (mips_tls_operand_p (*xloc))
2042 {
2043 *xloc = mips_legitimize_tls_address (*xloc);
2044 return true;
2045 }
2046
2047 /* See if the address can split into a high part and a LO_SUM. */
2048 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2049 && mips_symbolic_address_p (symbol_type, mode)
2050 && mips_split_p[symbol_type])
2051 {
2052 *xloc = mips_split_symbol (0, *xloc);
2053 return true;
2054 }
2055
2056 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2057 {
2058 /* Handle REG + CONSTANT using mips_add_offset. */
2059 rtx reg;
2060
2061 reg = XEXP (*xloc, 0);
2062 if (!mips_valid_base_register_p (reg, mode, 0))
2063 reg = copy_to_mode_reg (Pmode, reg);
2064 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2065 return true;
2066 }
2067
2068 return false;
2069 }
2070
2071
2072 /* Subroutine of mips_build_integer (with the same interface).
2073 Assume that the final action in the sequence should be a left shift. */
2074
2075 static unsigned int
mips_build_shift(struct mips_integer_op * codes,HOST_WIDE_INT value)2076 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2077 {
2078 unsigned int i, shift;
2079
2080 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2081 since signed numbers are easier to load than unsigned ones. */
2082 shift = 0;
2083 while ((value & 1) == 0)
2084 value /= 2, shift++;
2085
2086 i = mips_build_integer (codes, value);
2087 codes[i].code = ASHIFT;
2088 codes[i].value = shift;
2089 return i + 1;
2090 }
2091
2092
2093 /* As for mips_build_shift, but assume that the final action will be
2094 an IOR or PLUS operation. */
2095
2096 static unsigned int
mips_build_lower(struct mips_integer_op * codes,unsigned HOST_WIDE_INT value)2097 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2098 {
2099 unsigned HOST_WIDE_INT high;
2100 unsigned int i;
2101
2102 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2103 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2104 {
2105 /* The constant is too complex to load with a simple lui/ori pair
2106 so our goal is to clear as many trailing zeros as possible.
2107 In this case, we know bit 16 is set and that the low 16 bits
2108 form a negative number. If we subtract that number from VALUE,
2109 we will clear at least the lowest 17 bits, maybe more. */
2110 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2111 codes[i].code = PLUS;
2112 codes[i].value = CONST_LOW_PART (value);
2113 }
2114 else
2115 {
2116 i = mips_build_integer (codes, high);
2117 codes[i].code = IOR;
2118 codes[i].value = value & 0xffff;
2119 }
2120 return i + 1;
2121 }
2122
2123
2124 /* Fill CODES with a sequence of rtl operations to load VALUE.
2125 Return the number of operations needed. */
2126
2127 static unsigned int
mips_build_integer(struct mips_integer_op * codes,unsigned HOST_WIDE_INT value)2128 mips_build_integer (struct mips_integer_op *codes,
2129 unsigned HOST_WIDE_INT value)
2130 {
2131 if (SMALL_OPERAND (value)
2132 || SMALL_OPERAND_UNSIGNED (value)
2133 || LUI_OPERAND (value))
2134 {
2135 /* The value can be loaded with a single instruction. */
2136 codes[0].code = UNKNOWN;
2137 codes[0].value = value;
2138 return 1;
2139 }
2140 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2141 {
2142 /* Either the constant is a simple LUI/ORI combination or its
2143 lowest bit is set. We don't want to shift in this case. */
2144 return mips_build_lower (codes, value);
2145 }
2146 else if ((value & 0xffff) == 0)
2147 {
2148 /* The constant will need at least three actions. The lowest
2149 16 bits are clear, so the final action will be a shift. */
2150 return mips_build_shift (codes, value);
2151 }
2152 else
2153 {
2154 /* The final action could be a shift, add or inclusive OR.
2155 Rather than use a complex condition to select the best
2156 approach, try both mips_build_shift and mips_build_lower
2157 and pick the one that gives the shortest sequence.
2158 Note that this case is only used once per constant. */
2159 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2160 unsigned int cost, alt_cost;
2161
2162 cost = mips_build_shift (codes, value);
2163 alt_cost = mips_build_lower (alt_codes, value);
2164 if (alt_cost < cost)
2165 {
2166 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2167 cost = alt_cost;
2168 }
2169 return cost;
2170 }
2171 }
2172
2173
2174 /* Move VALUE into register DEST. */
2175
2176 static void
mips_move_integer(rtx dest,unsigned HOST_WIDE_INT value)2177 mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
2178 {
2179 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2180 enum machine_mode mode;
2181 unsigned int i, cost;
2182 rtx x;
2183
2184 mode = GET_MODE (dest);
2185 cost = mips_build_integer (codes, value);
2186
2187 /* Apply each binary operation to X. Invariant: X is a legitimate
2188 source operand for a SET pattern. */
2189 x = GEN_INT (codes[0].value);
2190 for (i = 1; i < cost; i++)
2191 {
2192 if (no_new_pseudos)
2193 emit_move_insn (dest, x), x = dest;
2194 else
2195 x = force_reg (mode, x);
2196 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2197 }
2198
2199 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2200 }
2201
2202
2203 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2204 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2205 move_operand. */
2206
2207 static void
mips_legitimize_const_move(enum machine_mode mode,rtx dest,rtx src)2208 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2209 {
2210 rtx base;
2211 HOST_WIDE_INT offset;
2212 enum mips_symbol_type symbol_type;
2213
2214 /* Split moves of big integers into smaller pieces. In mips16 code,
2215 it's better to force the constant into memory instead. */
2216 if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
2217 {
2218 mips_move_integer (dest, INTVAL (src));
2219 return;
2220 }
2221
2222 if (mips_tls_operand_p (src))
2223 {
2224 emit_move_insn (dest, mips_legitimize_tls_address (src));
2225 return;
2226 }
2227
2228 /* See if the symbol can be split. For mips16, this is often worse than
2229 forcing it in the constant pool since it needs the single-register form
2230 of addiu or daddiu. */
2231 if (!TARGET_MIPS16
2232 && mips_symbolic_constant_p (src, &symbol_type)
2233 && mips_split_p[symbol_type])
2234 {
2235 emit_move_insn (dest, mips_split_symbol (dest, src));
2236 return;
2237 }
2238
2239 /* If we have (const (plus symbol offset)), load the symbol first
2240 and then add in the offset. This is usually better than forcing
2241 the constant into memory, at least in non-mips16 code. */
2242 mips_split_const (src, &base, &offset);
2243 if (!TARGET_MIPS16
2244 && offset != 0
2245 && (!no_new_pseudos || SMALL_OPERAND (offset)))
2246 {
2247 base = mips_force_temporary (dest, base);
2248 emit_move_insn (dest, mips_add_offset (0, base, offset));
2249 return;
2250 }
2251
2252 src = force_const_mem (mode, src);
2253
2254 /* When using explicit relocs, constant pool references are sometimes
2255 not legitimate addresses. */
2256 if (!memory_operand (src, VOIDmode))
2257 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2258 emit_move_insn (dest, src);
2259 }
2260
2261
2262 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2263 sequence that is valid. */
2264
2265 bool
mips_legitimize_move(enum machine_mode mode,rtx dest,rtx src)2266 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2267 {
2268 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2269 {
2270 emit_move_insn (dest, force_reg (mode, src));
2271 return true;
2272 }
2273
2274 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2275 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2276 && REG_P (src) && MD_REG_P (REGNO (src))
2277 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2278 {
2279 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2280 if (GET_MODE_SIZE (mode) <= 4)
2281 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2282 gen_rtx_REG (SImode, REGNO (src)),
2283 gen_rtx_REG (SImode, other_regno)));
2284 else
2285 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2286 gen_rtx_REG (DImode, REGNO (src)),
2287 gen_rtx_REG (DImode, other_regno)));
2288 return true;
2289 }
2290
2291 /* We need to deal with constants that would be legitimate
2292 immediate_operands but not legitimate move_operands. */
2293 if (CONSTANT_P (src) && !move_operand (src, mode))
2294 {
2295 mips_legitimize_const_move (mode, dest, src);
2296 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2297 return true;
2298 }
2299 return false;
2300 }
2301
2302 /* We need a lot of little routines to check constant values on the
2303 mips16. These are used to figure out how long the instruction will
2304 be. It would be much better to do this using constraints, but
2305 there aren't nearly enough letters available. */
2306
2307 static int
m16_check_op(rtx op,int low,int high,int mask)2308 m16_check_op (rtx op, int low, int high, int mask)
2309 {
2310 return (GET_CODE (op) == CONST_INT
2311 && INTVAL (op) >= low
2312 && INTVAL (op) <= high
2313 && (INTVAL (op) & mask) == 0);
2314 }
2315
2316 int
m16_uimm3_b(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2317 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2318 {
2319 return m16_check_op (op, 0x1, 0x8, 0);
2320 }
2321
2322 int
m16_simm4_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2323 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2324 {
2325 return m16_check_op (op, - 0x8, 0x7, 0);
2326 }
2327
2328 int
m16_nsimm4_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2329 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2330 {
2331 return m16_check_op (op, - 0x7, 0x8, 0);
2332 }
2333
2334 int
m16_simm5_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2335 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2336 {
2337 return m16_check_op (op, - 0x10, 0xf, 0);
2338 }
2339
2340 int
m16_nsimm5_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2341 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2342 {
2343 return m16_check_op (op, - 0xf, 0x10, 0);
2344 }
2345
2346 int
m16_uimm5_4(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2347 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2348 {
2349 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2350 }
2351
2352 int
m16_nuimm5_4(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2353 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2354 {
2355 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2356 }
2357
2358 int
m16_simm8_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2359 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2360 {
2361 return m16_check_op (op, - 0x80, 0x7f, 0);
2362 }
2363
2364 int
m16_nsimm8_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2365 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2366 {
2367 return m16_check_op (op, - 0x7f, 0x80, 0);
2368 }
2369
2370 int
m16_uimm8_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2371 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2372 {
2373 return m16_check_op (op, 0x0, 0xff, 0);
2374 }
2375
2376 int
m16_nuimm8_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2377 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2378 {
2379 return m16_check_op (op, - 0xff, 0x0, 0);
2380 }
2381
2382 int
m16_uimm8_m1_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2383 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2384 {
2385 return m16_check_op (op, - 0x1, 0xfe, 0);
2386 }
2387
2388 int
m16_uimm8_4(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2389 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2390 {
2391 return m16_check_op (op, 0x0, 0xff << 2, 3);
2392 }
2393
2394 int
m16_nuimm8_4(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2395 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2396 {
2397 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2398 }
2399
2400 int
m16_simm8_8(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2401 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2402 {
2403 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2404 }
2405
2406 int
m16_nsimm8_8(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2407 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2408 {
2409 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2410 }
2411
2412 static bool
mips_rtx_costs(rtx x,int code,int outer_code,int * total)2413 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2414 {
2415 enum machine_mode mode = GET_MODE (x);
2416 bool float_mode_p = FLOAT_MODE_P (mode);
2417
2418 switch (code)
2419 {
2420 case CONST_INT:
2421 if (TARGET_MIPS16)
2422 {
2423 /* A number between 1 and 8 inclusive is efficient for a shift.
2424 Otherwise, we will need an extended instruction. */
2425 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2426 || (outer_code) == LSHIFTRT)
2427 {
2428 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2429 *total = 0;
2430 else
2431 *total = COSTS_N_INSNS (1);
2432 return true;
2433 }
2434
2435 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2436 if ((outer_code) == XOR
2437 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2438 {
2439 *total = 0;
2440 return true;
2441 }
2442
2443 /* We may be able to use slt or sltu for a comparison with a
2444 signed 16 bit value. (The boundary conditions aren't quite
2445 right, but this is just a heuristic anyhow.) */
2446 if (((outer_code) == LT || (outer_code) == LE
2447 || (outer_code) == GE || (outer_code) == GT
2448 || (outer_code) == LTU || (outer_code) == LEU
2449 || (outer_code) == GEU || (outer_code) == GTU)
2450 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2451 {
2452 *total = 0;
2453 return true;
2454 }
2455
2456 /* Equality comparisons with 0 are cheap. */
2457 if (((outer_code) == EQ || (outer_code) == NE)
2458 && INTVAL (x) == 0)
2459 {
2460 *total = 0;
2461 return true;
2462 }
2463
2464 /* Constants in the range 0...255 can be loaded with an unextended
2465 instruction. They are therefore as cheap as a register move.
2466
2467 Given the choice between "li R1,0...255" and "move R1,R2"
2468 (where R2 is a known constant), it is usually better to use "li",
2469 since we do not want to unnecessarily extend the lifetime
2470 of R2. */
2471 if (outer_code == SET
2472 && INTVAL (x) >= 0
2473 && INTVAL (x) < 256)
2474 {
2475 *total = 0;
2476 return true;
2477 }
2478 }
2479 else
2480 {
2481 /* These can be used anywhere. */
2482 *total = 0;
2483 return true;
2484 }
2485
2486 /* Otherwise fall through to the handling below because
2487 we'll need to construct the constant. */
2488
2489 case CONST:
2490 case SYMBOL_REF:
2491 case LABEL_REF:
2492 case CONST_DOUBLE:
2493 if (LEGITIMATE_CONSTANT_P (x))
2494 {
2495 *total = COSTS_N_INSNS (1);
2496 return true;
2497 }
2498 else
2499 {
2500 /* The value will need to be fetched from the constant pool. */
2501 *total = CONSTANT_POOL_COST;
2502 return true;
2503 }
2504
2505 case MEM:
2506 {
2507 /* If the address is legitimate, return the number of
2508 instructions it needs, otherwise use the default handling. */
2509 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2510 if (n > 0)
2511 {
2512 *total = COSTS_N_INSNS (n + 1);
2513 return true;
2514 }
2515 return false;
2516 }
2517
2518 case FFS:
2519 *total = COSTS_N_INSNS (6);
2520 return true;
2521
2522 case NOT:
2523 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2524 return true;
2525
2526 case AND:
2527 case IOR:
2528 case XOR:
2529 if (mode == DImode && !TARGET_64BIT)
2530 {
2531 *total = COSTS_N_INSNS (2);
2532 return true;
2533 }
2534 return false;
2535
2536 case ASHIFT:
2537 case ASHIFTRT:
2538 case LSHIFTRT:
2539 if (mode == DImode && !TARGET_64BIT)
2540 {
2541 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2542 ? 4 : 12);
2543 return true;
2544 }
2545 return false;
2546
2547 case ABS:
2548 if (float_mode_p)
2549 *total = COSTS_N_INSNS (1);
2550 else
2551 *total = COSTS_N_INSNS (4);
2552 return true;
2553
2554 case LO_SUM:
2555 *total = COSTS_N_INSNS (1);
2556 return true;
2557
2558 case PLUS:
2559 case MINUS:
2560 if (float_mode_p)
2561 {
2562 *total = mips_cost->fp_add;
2563 return true;
2564 }
2565
2566 else if (mode == DImode && !TARGET_64BIT)
2567 {
2568 *total = COSTS_N_INSNS (4);
2569 return true;
2570 }
2571 return false;
2572
2573 case NEG:
2574 if (mode == DImode && !TARGET_64BIT)
2575 {
2576 *total = COSTS_N_INSNS (4);
2577 return true;
2578 }
2579 return false;
2580
2581 case MULT:
2582 if (mode == SFmode)
2583 *total = mips_cost->fp_mult_sf;
2584
2585 else if (mode == DFmode)
2586 *total = mips_cost->fp_mult_df;
2587
2588 else if (mode == SImode)
2589 *total = mips_cost->int_mult_si;
2590
2591 else
2592 *total = mips_cost->int_mult_di;
2593
2594 return true;
2595
2596 case DIV:
2597 case MOD:
2598 if (float_mode_p)
2599 {
2600 if (mode == SFmode)
2601 *total = mips_cost->fp_div_sf;
2602 else
2603 *total = mips_cost->fp_div_df;
2604
2605 return true;
2606 }
2607 /* Fall through. */
2608
2609 case UDIV:
2610 case UMOD:
2611 if (mode == DImode)
2612 *total = mips_cost->int_div_di;
2613 else
2614 *total = mips_cost->int_div_si;
2615
2616 return true;
2617
2618 case SIGN_EXTEND:
2619 /* A sign extend from SImode to DImode in 64 bit mode is often
2620 zero instructions, because the result can often be used
2621 directly by another instruction; we'll call it one. */
2622 if (TARGET_64BIT && mode == DImode
2623 && GET_MODE (XEXP (x, 0)) == SImode)
2624 *total = COSTS_N_INSNS (1);
2625 else
2626 *total = COSTS_N_INSNS (2);
2627 return true;
2628
2629 case ZERO_EXTEND:
2630 if (TARGET_64BIT && mode == DImode
2631 && GET_MODE (XEXP (x, 0)) == SImode)
2632 *total = COSTS_N_INSNS (2);
2633 else
2634 *total = COSTS_N_INSNS (1);
2635 return true;
2636
2637 case FLOAT:
2638 case UNSIGNED_FLOAT:
2639 case FIX:
2640 case FLOAT_EXTEND:
2641 case FLOAT_TRUNCATE:
2642 case SQRT:
2643 *total = mips_cost->fp_add;
2644 return true;
2645
2646 default:
2647 return false;
2648 }
2649 }
2650
2651 /* Provide the costs of an addressing mode that contains ADDR.
2652 If ADDR is not a valid address, its cost is irrelevant. */
2653
2654 static int
mips_address_cost(rtx addr)2655 mips_address_cost (rtx addr)
2656 {
2657 return mips_address_insns (addr, SImode);
2658 }
2659
2660 /* Return one word of double-word value OP, taking into account the fixed
2661 endianness of certain registers. HIGH_P is true to select the high part,
2662 false to select the low part. */
2663
2664 rtx
mips_subword(rtx op,int high_p)2665 mips_subword (rtx op, int high_p)
2666 {
2667 unsigned int byte;
2668 enum machine_mode mode;
2669
2670 mode = GET_MODE (op);
2671 if (mode == VOIDmode)
2672 mode = DImode;
2673
2674 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2675 byte = UNITS_PER_WORD;
2676 else
2677 byte = 0;
2678
2679 if (REG_P (op))
2680 {
2681 if (FP_REG_P (REGNO (op)))
2682 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2683 if (ACC_HI_REG_P (REGNO (op)))
2684 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
2685 }
2686
2687 if (MEM_P (op))
2688 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2689
2690 return simplify_gen_subreg (word_mode, op, mode, byte);
2691 }
2692
2693
2694 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2695
2696 bool
mips_split_64bit_move_p(rtx dest,rtx src)2697 mips_split_64bit_move_p (rtx dest, rtx src)
2698 {
2699 if (TARGET_64BIT)
2700 return false;
2701
2702 /* FP->FP moves can be done in a single instruction. */
2703 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2704 return false;
2705
2706 /* Check for floating-point loads and stores. They can be done using
2707 ldc1 and sdc1 on MIPS II and above. */
2708 if (mips_isa > 1)
2709 {
2710 if (FP_REG_RTX_P (dest) && MEM_P (src))
2711 return false;
2712 if (FP_REG_RTX_P (src) && MEM_P (dest))
2713 return false;
2714 }
2715 return true;
2716 }
2717
2718
2719 /* Split a 64-bit move from SRC to DEST assuming that
2720 mips_split_64bit_move_p holds.
2721
2722 Moves into and out of FPRs cause some difficulty here. Such moves
2723 will always be DFmode, since paired FPRs are not allowed to store
2724 DImode values. The most natural representation would be two separate
2725 32-bit moves, such as:
2726
2727 (set (reg:SI $f0) (mem:SI ...))
2728 (set (reg:SI $f1) (mem:SI ...))
2729
2730 However, the second insn is invalid because odd-numbered FPRs are
2731 not allowed to store independent values. Use the patterns load_df_low,
2732 load_df_high and store_df_high instead. */
2733
2734 void
mips_split_64bit_move(rtx dest,rtx src)2735 mips_split_64bit_move (rtx dest, rtx src)
2736 {
2737 if (FP_REG_RTX_P (dest))
2738 {
2739 /* Loading an FPR from memory or from GPRs. */
2740 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2741 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2742 copy_rtx (dest)));
2743 }
2744 else if (FP_REG_RTX_P (src))
2745 {
2746 /* Storing an FPR into memory or GPRs. */
2747 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2748 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2749 }
2750 else
2751 {
2752 /* The operation can be split into two normal moves. Decide in
2753 which order to do them. */
2754 rtx low_dest;
2755
2756 low_dest = mips_subword (dest, 0);
2757 if (REG_P (low_dest)
2758 && reg_overlap_mentioned_p (low_dest, src))
2759 {
2760 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2761 emit_move_insn (low_dest, mips_subword (src, 0));
2762 }
2763 else
2764 {
2765 emit_move_insn (low_dest, mips_subword (src, 0));
2766 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2767 }
2768 }
2769 }
2770
2771 /* Return the appropriate instructions to move SRC into DEST. Assume
2772 that SRC is operand 1 and DEST is operand 0. */
2773
2774 const char *
mips_output_move(rtx dest,rtx src)2775 mips_output_move (rtx dest, rtx src)
2776 {
2777 enum rtx_code dest_code, src_code;
2778 bool dbl_p;
2779
2780 dest_code = GET_CODE (dest);
2781 src_code = GET_CODE (src);
2782 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2783
2784 if (dbl_p && mips_split_64bit_move_p (dest, src))
2785 return "#";
2786
2787 if ((src_code == REG && GP_REG_P (REGNO (src)))
2788 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2789 {
2790 if (dest_code == REG)
2791 {
2792 if (GP_REG_P (REGNO (dest)))
2793 return "move\t%0,%z1";
2794
2795 if (MD_REG_P (REGNO (dest)))
2796 return "mt%0\t%z1";
2797
2798 if (DSP_ACC_REG_P (REGNO (dest)))
2799 {
2800 static char retval[] = "mt__\t%z1,%q0";
2801 retval[2] = reg_names[REGNO (dest)][4];
2802 retval[3] = reg_names[REGNO (dest)][5];
2803 return retval;
2804 }
2805
2806 if (FP_REG_P (REGNO (dest)))
2807 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2808
2809 if (ALL_COP_REG_P (REGNO (dest)))
2810 {
2811 static char retval[] = "dmtc_\t%z1,%0";
2812
2813 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2814 return (dbl_p ? retval : retval + 1);
2815 }
2816 }
2817 if (dest_code == MEM)
2818 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2819 }
2820 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2821 {
2822 if (src_code == REG)
2823 {
2824 if (DSP_ACC_REG_P (REGNO (src)))
2825 {
2826 static char retval[] = "mf__\t%0,%q1";
2827 retval[2] = reg_names[REGNO (src)][4];
2828 retval[3] = reg_names[REGNO (src)][5];
2829 return retval;
2830 }
2831
2832 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2833 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2834
2835 if (FP_REG_P (REGNO (src)))
2836 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2837
2838 if (ALL_COP_REG_P (REGNO (src)))
2839 {
2840 static char retval[] = "dmfc_\t%0,%1";
2841
2842 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2843 return (dbl_p ? retval : retval + 1);
2844 }
2845 }
2846
2847 if (src_code == MEM)
2848 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2849
2850 if (src_code == CONST_INT)
2851 {
2852 /* Don't use the X format, because that will give out of
2853 range numbers for 64 bit hosts and 32 bit targets. */
2854 if (!TARGET_MIPS16)
2855 return "li\t%0,%1\t\t\t# %X1";
2856
2857 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2858 return "li\t%0,%1";
2859
2860 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2861 return "#";
2862 }
2863
2864 if (src_code == HIGH)
2865 return "lui\t%0,%h1";
2866
2867 if (CONST_GP_P (src))
2868 return "move\t%0,%1";
2869
2870 if (symbolic_operand (src, VOIDmode))
2871 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2872 }
2873 if (src_code == REG && FP_REG_P (REGNO (src)))
2874 {
2875 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2876 {
2877 if (GET_MODE (dest) == V2SFmode)
2878 return "mov.ps\t%0,%1";
2879 else
2880 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2881 }
2882
2883 if (dest_code == MEM)
2884 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2885 }
2886 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2887 {
2888 if (src_code == MEM)
2889 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2890 }
2891 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2892 {
2893 static char retval[] = "l_c_\t%0,%1";
2894
2895 retval[1] = (dbl_p ? 'd' : 'w');
2896 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2897 return retval;
2898 }
2899 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2900 {
2901 static char retval[] = "s_c_\t%1,%0";
2902
2903 retval[1] = (dbl_p ? 'd' : 'w');
2904 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2905 return retval;
2906 }
2907 gcc_unreachable ();
2908 }
2909
2910 /* Restore $gp from its save slot. Valid only when using o32 or
2911 o64 abicalls. */
2912
2913 void
mips_restore_gp(void)2914 mips_restore_gp (void)
2915 {
2916 rtx address, slot;
2917
2918 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
2919
2920 address = mips_add_offset (pic_offset_table_rtx,
2921 frame_pointer_needed
2922 ? hard_frame_pointer_rtx
2923 : stack_pointer_rtx,
2924 current_function_outgoing_args_size);
2925 slot = gen_rtx_MEM (Pmode, address);
2926
2927 emit_move_insn (pic_offset_table_rtx, slot);
2928 if (!TARGET_EXPLICIT_RELOCS)
2929 emit_insn (gen_blockage ());
2930 }
2931
2932 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2933
2934 static void
mips_emit_binary(enum rtx_code code,rtx target,rtx op0,rtx op1)2935 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2936 {
2937 emit_insn (gen_rtx_SET (VOIDmode, target,
2938 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2939 }
2940
2941 /* Return true if CMP1 is a suitable second operand for relational
2942 operator CODE. See also the *sCC patterns in mips.md. */
2943
2944 static bool
mips_relational_operand_ok_p(enum rtx_code code,rtx cmp1)2945 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
2946 {
2947 switch (code)
2948 {
2949 case GT:
2950 case GTU:
2951 return reg_or_0_operand (cmp1, VOIDmode);
2952
2953 case GE:
2954 case GEU:
2955 return !TARGET_MIPS16 && cmp1 == const1_rtx;
2956
2957 case LT:
2958 case LTU:
2959 return arith_operand (cmp1, VOIDmode);
2960
2961 case LE:
2962 return sle_operand (cmp1, VOIDmode);
2963
2964 case LEU:
2965 return sleu_operand (cmp1, VOIDmode);
2966
2967 default:
2968 gcc_unreachable ();
2969 }
2970 }
2971
2972 /* Canonicalize LE or LEU comparisons into LT comparisons when
2973 possible to avoid extra instructions or inverting the
2974 comparison. */
2975
2976 static bool
mips_canonicalize_comparison(enum rtx_code * code,rtx * cmp1,enum machine_mode mode)2977 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
2978 enum machine_mode mode)
2979 {
2980 HOST_WIDE_INT original, plus_one;
2981
2982 if (GET_CODE (*cmp1) != CONST_INT)
2983 return false;
2984
2985 original = INTVAL (*cmp1);
2986 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
2987
2988 switch (*code)
2989 {
2990 case LE:
2991 if (original < plus_one)
2992 {
2993 *code = LT;
2994 *cmp1 = force_reg (mode, GEN_INT (plus_one));
2995 return true;
2996 }
2997 break;
2998
2999 case LEU:
3000 if (plus_one != 0)
3001 {
3002 *code = LTU;
3003 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3004 return true;
3005 }
3006 break;
3007
3008 default:
3009 return false;
3010 }
3011
3012 return false;
3013
3014 }
3015
3016 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3017 result in TARGET. CMP0 and TARGET are register_operands that have
3018 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3019 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3020
3021 static void
mips_emit_int_relational(enum rtx_code code,bool * invert_ptr,rtx target,rtx cmp0,rtx cmp1)3022 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3023 rtx target, rtx cmp0, rtx cmp1)
3024 {
3025 /* First see if there is a MIPS instruction that can do this operation
3026 with CMP1 in its current form. If not, try to canonicalize the
3027 comparison to LT. If that fails, try doing the same for the
3028 inverse operation. If that also fails, force CMP1 into a register
3029 and try again. */
3030 if (mips_relational_operand_ok_p (code, cmp1))
3031 mips_emit_binary (code, target, cmp0, cmp1);
3032 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3033 mips_emit_binary (code, target, cmp0, cmp1);
3034 else
3035 {
3036 enum rtx_code inv_code = reverse_condition (code);
3037 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3038 {
3039 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3040 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3041 }
3042 else if (invert_ptr == 0)
3043 {
3044 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3045 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3046 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3047 }
3048 else
3049 {
3050 *invert_ptr = !*invert_ptr;
3051 mips_emit_binary (inv_code, target, cmp0, cmp1);
3052 }
3053 }
3054 }
3055
3056 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3057 The register will have the same mode as CMP0. */
3058
3059 static rtx
mips_zero_if_equal(rtx cmp0,rtx cmp1)3060 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3061 {
3062 if (cmp1 == const0_rtx)
3063 return cmp0;
3064
3065 if (uns_arith_operand (cmp1, VOIDmode))
3066 return expand_binop (GET_MODE (cmp0), xor_optab,
3067 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3068
3069 return expand_binop (GET_MODE (cmp0), sub_optab,
3070 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3071 }
3072
3073 /* Convert a comparison into something that can be used in a branch or
3074 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3075 being compared and *CODE is the code used to compare them.
3076
3077 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3078 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3079 otherwise any standard branch condition can be used. The standard branch
3080 conditions are:
3081
3082 - EQ/NE between two registers.
3083 - any comparison between a register and zero. */
3084
3085 static void
mips_emit_compare(enum rtx_code * code,rtx * op0,rtx * op1,bool need_eq_ne_p)3086 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3087 {
3088 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3089 {
3090 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3091 {
3092 *op0 = cmp_operands[0];
3093 *op1 = cmp_operands[1];
3094 }
3095 else if (*code == EQ || *code == NE)
3096 {
3097 if (need_eq_ne_p)
3098 {
3099 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3100 *op1 = const0_rtx;
3101 }
3102 else
3103 {
3104 *op0 = cmp_operands[0];
3105 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3106 }
3107 }
3108 else
3109 {
3110 /* The comparison needs a separate scc instruction. Store the
3111 result of the scc in *OP0 and compare it against zero. */
3112 bool invert = false;
3113 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3114 *op1 = const0_rtx;
3115 mips_emit_int_relational (*code, &invert, *op0,
3116 cmp_operands[0], cmp_operands[1]);
3117 *code = (invert ? EQ : NE);
3118 }
3119 }
3120 else
3121 {
3122 enum rtx_code cmp_code;
3123
3124 /* Floating-point tests use a separate c.cond.fmt comparison to
3125 set a condition code register. The branch or conditional move
3126 will then compare that register against zero.
3127
3128 Set CMP_CODE to the code of the comparison instruction and
3129 *CODE to the code that the branch or move should use. */
3130 switch (*code)
3131 {
3132 case NE:
3133 case LTGT:
3134 case ORDERED:
3135 cmp_code = reverse_condition_maybe_unordered (*code);
3136 *code = EQ;
3137 break;
3138
3139 default:
3140 cmp_code = *code;
3141 *code = NE;
3142 break;
3143 }
3144 *op0 = (ISA_HAS_8CC
3145 ? gen_reg_rtx (CCmode)
3146 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3147 *op1 = const0_rtx;
3148 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3149 }
3150 }
3151
3152 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3153 Store the result in TARGET and return true if successful.
3154
3155 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3156
3157 bool
mips_emit_scc(enum rtx_code code,rtx target)3158 mips_emit_scc (enum rtx_code code, rtx target)
3159 {
3160 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3161 return false;
3162
3163 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3164 if (code == EQ || code == NE)
3165 {
3166 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3167 mips_emit_binary (code, target, zie, const0_rtx);
3168 }
3169 else
3170 mips_emit_int_relational (code, 0, target,
3171 cmp_operands[0], cmp_operands[1]);
3172 return true;
3173 }
3174
3175 /* Emit the common code for doing conditional branches.
3176 operand[0] is the label to jump to.
3177 The comparison operands are saved away by cmp{si,di,sf,df}. */
3178
3179 void
gen_conditional_branch(rtx * operands,enum rtx_code code)3180 gen_conditional_branch (rtx *operands, enum rtx_code code)
3181 {
3182 rtx op0, op1, target;
3183
3184 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3185 target = gen_rtx_IF_THEN_ELSE (VOIDmode,
3186 gen_rtx_fmt_ee (code, GET_MODE (op0),
3187 op0, op1),
3188 gen_rtx_LABEL_REF (VOIDmode, operands[0]),
3189 pc_rtx);
3190 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, target));
3191 }
3192
3193 /* Emit the common code for conditional moves. OPERANDS is the array
3194 of operands passed to the conditional move define_expand. */
3195
3196 void
gen_conditional_move(rtx * operands)3197 gen_conditional_move (rtx *operands)
3198 {
3199 enum rtx_code code;
3200 rtx op0, op1;
3201
3202 code = GET_CODE (operands[1]);
3203 mips_emit_compare (&code, &op0, &op1, true);
3204 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3205 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3206 gen_rtx_fmt_ee (code,
3207 GET_MODE (op0),
3208 op0, op1),
3209 operands[2], operands[3])));
3210 }
3211
3212 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3213 the conditional_trap expander. */
3214
3215 void
mips_gen_conditional_trap(rtx * operands)3216 mips_gen_conditional_trap (rtx *operands)
3217 {
3218 rtx op0, op1;
3219 enum rtx_code cmp_code = GET_CODE (operands[0]);
3220 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3221
3222 /* MIPS conditional trap machine instructions don't have GT or LE
3223 flavors, so we must invert the comparison and convert to LT and
3224 GE, respectively. */
3225 switch (cmp_code)
3226 {
3227 case GT: cmp_code = LT; break;
3228 case LE: cmp_code = GE; break;
3229 case GTU: cmp_code = LTU; break;
3230 case LEU: cmp_code = GEU; break;
3231 default: break;
3232 }
3233 if (cmp_code == GET_CODE (operands[0]))
3234 {
3235 op0 = cmp_operands[0];
3236 op1 = cmp_operands[1];
3237 }
3238 else
3239 {
3240 op0 = cmp_operands[1];
3241 op1 = cmp_operands[0];
3242 }
3243 op0 = force_reg (mode, op0);
3244 if (!arith_operand (op1, mode))
3245 op1 = force_reg (mode, op1);
3246
3247 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3248 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3249 operands[1]));
3250 }
3251
3252 /* Load function address ADDR into register DEST. SIBCALL_P is true
3253 if the address is needed for a sibling call. */
3254
3255 static void
mips_load_call_address(rtx dest,rtx addr,int sibcall_p)3256 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3257 {
3258 /* If we're generating PIC, and this call is to a global function,
3259 try to allow its address to be resolved lazily. This isn't
3260 possible for NewABI sibcalls since the value of $gp on entry
3261 to the stub would be our caller's gp, not ours. */
3262 if (TARGET_EXPLICIT_RELOCS
3263 && !(sibcall_p && TARGET_NEWABI)
3264 && global_got_operand (addr, VOIDmode))
3265 {
3266 rtx high, lo_sum_symbol;
3267
3268 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3269 addr, SYMBOL_GOTOFF_CALL);
3270 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3271 if (Pmode == SImode)
3272 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3273 else
3274 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3275 }
3276 else
3277 emit_move_insn (dest, addr);
3278 }
3279
3280
3281 /* Expand a call or call_value instruction. RESULT is where the
3282 result will go (null for calls), ADDR is the address of the
3283 function, ARGS_SIZE is the size of the arguments and AUX is
3284 the value passed to us by mips_function_arg. SIBCALL_P is true
3285 if we are expanding a sibling call, false if we're expanding
3286 a normal call. */
3287
3288 void
mips_expand_call(rtx result,rtx addr,rtx args_size,rtx aux,int sibcall_p)3289 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3290 {
3291 rtx orig_addr, pattern, insn;
3292
3293 orig_addr = addr;
3294 if (!call_insn_operand (addr, VOIDmode))
3295 {
3296 addr = gen_reg_rtx (Pmode);
3297 mips_load_call_address (addr, orig_addr, sibcall_p);
3298 }
3299
3300 if (TARGET_MIPS16
3301 && mips16_hard_float
3302 && build_mips16_call_stub (result, addr, args_size,
3303 aux == 0 ? 0 : (int) GET_MODE (aux)))
3304 return;
3305
3306 if (result == 0)
3307 pattern = (sibcall_p
3308 ? gen_sibcall_internal (addr, args_size)
3309 : gen_call_internal (addr, args_size));
3310 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3311 {
3312 rtx reg1, reg2;
3313
3314 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3315 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3316 pattern =
3317 (sibcall_p
3318 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3319 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3320 }
3321 else
3322 pattern = (sibcall_p
3323 ? gen_sibcall_value_internal (result, addr, args_size)
3324 : gen_call_value_internal (result, addr, args_size));
3325
3326 insn = emit_call_insn (pattern);
3327
3328 /* Lazy-binding stubs require $gp to be valid on entry. */
3329 if (global_got_operand (orig_addr, VOIDmode))
3330 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3331 }
3332
3333
3334 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3335
3336 static bool
mips_function_ok_for_sibcall(tree decl ATTRIBUTE_UNUSED,tree exp ATTRIBUTE_UNUSED)3337 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3338 tree exp ATTRIBUTE_UNUSED)
3339 {
3340 return TARGET_SIBCALLS;
3341 }
3342
3343 /* Emit code to move general operand SRC into condition-code
3344 register DEST. SCRATCH is a scratch TFmode float register.
3345 The sequence is:
3346
3347 FP1 = SRC
3348 FP2 = 0.0f
3349 DEST = FP2 < FP1
3350
3351 where FP1 and FP2 are single-precision float registers
3352 taken from SCRATCH. */
3353
3354 void
mips_emit_fcc_reload(rtx dest,rtx src,rtx scratch)3355 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3356 {
3357 rtx fp1, fp2;
3358
3359 /* Change the source to SFmode. */
3360 if (MEM_P (src))
3361 src = adjust_address (src, SFmode, 0);
3362 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3363 src = gen_rtx_REG (SFmode, true_regnum (src));
3364
3365 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3366 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3367
3368 emit_move_insn (copy_rtx (fp1), src);
3369 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3370 emit_insn (gen_slt_sf (dest, fp2, fp1));
3371 }
3372
3373 /* Emit code to change the current function's return address to
3374 ADDRESS. SCRATCH is available as a scratch register, if needed.
3375 ADDRESS and SCRATCH are both word-mode GPRs. */
3376
3377 void
mips_set_return_address(rtx address,rtx scratch)3378 mips_set_return_address (rtx address, rtx scratch)
3379 {
3380 rtx slot_address;
3381
3382 compute_frame_size (get_frame_size ());
3383 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3384 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3385 cfun->machine->frame.gp_sp_offset);
3386
3387 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3388 }
3389
3390 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3391 Assume that the areas do not overlap. */
3392
3393 static void
mips_block_move_straight(rtx dest,rtx src,HOST_WIDE_INT length)3394 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3395 {
3396 HOST_WIDE_INT offset, delta;
3397 unsigned HOST_WIDE_INT bits;
3398 int i;
3399 enum machine_mode mode;
3400 rtx *regs;
3401
3402 /* Work out how many bits to move at a time. If both operands have
3403 half-word alignment, it is usually better to move in half words.
3404 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3405 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3406 Otherwise move word-sized chunks. */
3407 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3408 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3409 bits = BITS_PER_WORD / 2;
3410 else
3411 bits = BITS_PER_WORD;
3412
3413 mode = mode_for_size (bits, MODE_INT, 0);
3414 delta = bits / BITS_PER_UNIT;
3415
3416 /* Allocate a buffer for the temporary registers. */
3417 regs = alloca (sizeof (rtx) * length / delta);
3418
3419 /* Load as many BITS-sized chunks as possible. Use a normal load if
3420 the source has enough alignment, otherwise use left/right pairs. */
3421 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3422 {
3423 regs[i] = gen_reg_rtx (mode);
3424 if (MEM_ALIGN (src) >= bits)
3425 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3426 else
3427 {
3428 rtx part = adjust_address (src, BLKmode, offset);
3429 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3430 gcc_unreachable ();
3431 }
3432 }
3433
3434 /* Copy the chunks to the destination. */
3435 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3436 if (MEM_ALIGN (dest) >= bits)
3437 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3438 else
3439 {
3440 rtx part = adjust_address (dest, BLKmode, offset);
3441 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3442 gcc_unreachable ();
3443 }
3444
3445 /* Mop up any left-over bytes. */
3446 if (offset < length)
3447 {
3448 src = adjust_address (src, BLKmode, offset);
3449 dest = adjust_address (dest, BLKmode, offset);
3450 move_by_pieces (dest, src, length - offset,
3451 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3452 }
3453 }
3454
3455 #define MAX_MOVE_REGS 4
3456 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3457
3458
3459 /* Helper function for doing a loop-based block operation on memory
3460 reference MEM. Each iteration of the loop will operate on LENGTH
3461 bytes of MEM.
3462
3463 Create a new base register for use within the loop and point it to
3464 the start of MEM. Create a new memory reference that uses this
3465 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3466
3467 static void
mips_adjust_block_mem(rtx mem,HOST_WIDE_INT length,rtx * loop_reg,rtx * loop_mem)3468 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3469 rtx *loop_reg, rtx *loop_mem)
3470 {
3471 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3472
3473 /* Although the new mem does not refer to a known location,
3474 it does keep up to LENGTH bytes of alignment. */
3475 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3476 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3477 }
3478
3479
3480 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3481 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3482 memory regions do not overlap. */
3483
3484 static void
mips_block_move_loop(rtx dest,rtx src,HOST_WIDE_INT length)3485 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3486 {
3487 rtx label, src_reg, dest_reg, final_src;
3488 HOST_WIDE_INT leftover;
3489
3490 leftover = length % MAX_MOVE_BYTES;
3491 length -= leftover;
3492
3493 /* Create registers and memory references for use within the loop. */
3494 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3495 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3496
3497 /* Calculate the value that SRC_REG should have after the last iteration
3498 of the loop. */
3499 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3500 0, 0, OPTAB_WIDEN);
3501
3502 /* Emit the start of the loop. */
3503 label = gen_label_rtx ();
3504 emit_label (label);
3505
3506 /* Emit the loop body. */
3507 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3508
3509 /* Move on to the next block. */
3510 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3511 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3512
3513 /* Emit the loop condition. */
3514 if (Pmode == DImode)
3515 emit_insn (gen_cmpdi (src_reg, final_src));
3516 else
3517 emit_insn (gen_cmpsi (src_reg, final_src));
3518 emit_jump_insn (gen_bne (label));
3519
3520 /* Mop up any left-over bytes. */
3521 if (leftover)
3522 mips_block_move_straight (dest, src, leftover);
3523 }
3524
3525 /* Expand a movmemsi instruction. */
3526
3527 bool
mips_expand_block_move(rtx dest,rtx src,rtx length)3528 mips_expand_block_move (rtx dest, rtx src, rtx length)
3529 {
3530 if (GET_CODE (length) == CONST_INT)
3531 {
3532 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3533 {
3534 mips_block_move_straight (dest, src, INTVAL (length));
3535 return true;
3536 }
3537 else if (optimize)
3538 {
3539 mips_block_move_loop (dest, src, INTVAL (length));
3540 return true;
3541 }
3542 }
3543 return false;
3544 }
3545
3546 /* Argument support functions. */
3547
3548 /* Initialize CUMULATIVE_ARGS for a function. */
3549
3550 void
init_cumulative_args(CUMULATIVE_ARGS * cum,tree fntype,rtx libname ATTRIBUTE_UNUSED)3551 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3552 rtx libname ATTRIBUTE_UNUSED)
3553 {
3554 static CUMULATIVE_ARGS zero_cum;
3555 tree param, next_param;
3556
3557 *cum = zero_cum;
3558 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3559
3560 /* Determine if this function has variable arguments. This is
3561 indicated by the last argument being 'void_type_mode' if there
3562 are no variable arguments. The standard MIPS calling sequence
3563 passes all arguments in the general purpose registers in this case. */
3564
3565 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3566 param != 0; param = next_param)
3567 {
3568 next_param = TREE_CHAIN (param);
3569 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3570 cum->gp_reg_found = 1;
3571 }
3572 }
3573
3574
3575 /* Fill INFO with information about a single argument. CUM is the
3576 cumulative state for earlier arguments. MODE is the mode of this
3577 argument and TYPE is its type (if known). NAMED is true if this
3578 is a named (fixed) argument rather than a variable one. */
3579
3580 static void
mips_arg_info(const CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,int named,struct mips_arg_info * info)3581 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3582 tree type, int named, struct mips_arg_info *info)
3583 {
3584 bool doubleword_aligned_p;
3585 unsigned int num_bytes, num_words, max_regs;
3586
3587 /* Work out the size of the argument. */
3588 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3589 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3590
3591 /* Decide whether it should go in a floating-point register, assuming
3592 one is free. Later code checks for availability.
3593
3594 The checks against UNITS_PER_FPVALUE handle the soft-float and
3595 single-float cases. */
3596 switch (mips_abi)
3597 {
3598 case ABI_EABI:
3599 /* The EABI conventions have traditionally been defined in terms
3600 of TYPE_MODE, regardless of the actual type. */
3601 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3602 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3603 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3604 break;
3605
3606 case ABI_32:
3607 case ABI_O64:
3608 /* Only leading floating-point scalars are passed in
3609 floating-point registers. We also handle vector floats the same
3610 say, which is OK because they are not covered by the standard ABI. */
3611 info->fpr_p = (!cum->gp_reg_found
3612 && cum->arg_number < 2
3613 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3614 || VECTOR_FLOAT_TYPE_P (type))
3615 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3616 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3617 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3618 break;
3619
3620 case ABI_N32:
3621 case ABI_64:
3622 /* Scalar and complex floating-point types are passed in
3623 floating-point registers. */
3624 info->fpr_p = (named
3625 && (type == 0 || FLOAT_TYPE_P (type))
3626 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3627 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3628 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3629 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3630
3631 /* ??? According to the ABI documentation, the real and imaginary
3632 parts of complex floats should be passed in individual registers.
3633 The real and imaginary parts of stack arguments are supposed
3634 to be contiguous and there should be an extra word of padding
3635 at the end.
3636
3637 This has two problems. First, it makes it impossible to use a
3638 single "void *" va_list type, since register and stack arguments
3639 are passed differently. (At the time of writing, MIPSpro cannot
3640 handle complex float varargs correctly.) Second, it's unclear
3641 what should happen when there is only one register free.
3642
3643 For now, we assume that named complex floats should go into FPRs
3644 if there are two FPRs free, otherwise they should be passed in the
3645 same way as a struct containing two floats. */
3646 if (info->fpr_p
3647 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3648 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3649 {
3650 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3651 info->fpr_p = false;
3652 else
3653 num_words = 2;
3654 }
3655 break;
3656
3657 default:
3658 gcc_unreachable ();
3659 }
3660
3661 /* See whether the argument has doubleword alignment. */
3662 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3663
3664 /* Set REG_OFFSET to the register count we're interested in.
3665 The EABI allocates the floating-point registers separately,
3666 but the other ABIs allocate them like integer registers. */
3667 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3668 ? cum->num_fprs
3669 : cum->num_gprs);
3670
3671 /* Advance to an even register if the argument is doubleword-aligned. */
3672 if (doubleword_aligned_p)
3673 info->reg_offset += info->reg_offset & 1;
3674
3675 /* Work out the offset of a stack argument. */
3676 info->stack_offset = cum->stack_words;
3677 if (doubleword_aligned_p)
3678 info->stack_offset += info->stack_offset & 1;
3679
3680 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3681
3682 /* Partition the argument between registers and stack. */
3683 info->reg_words = MIN (num_words, max_regs);
3684 info->stack_words = num_words - info->reg_words;
3685 }
3686
3687
3688 /* Implement FUNCTION_ARG_ADVANCE. */
3689
3690 void
function_arg_advance(CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,int named)3691 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3692 tree type, int named)
3693 {
3694 struct mips_arg_info info;
3695
3696 mips_arg_info (cum, mode, type, named, &info);
3697
3698 if (!info.fpr_p)
3699 cum->gp_reg_found = true;
3700
3701 /* See the comment above the cumulative args structure in mips.h
3702 for an explanation of what this code does. It assumes the O32
3703 ABI, which passes at most 2 arguments in float registers. */
3704 if (cum->arg_number < 2 && info.fpr_p)
3705 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3706
3707 if (mips_abi != ABI_EABI || !info.fpr_p)
3708 cum->num_gprs = info.reg_offset + info.reg_words;
3709 else if (info.reg_words > 0)
3710 cum->num_fprs += FP_INC;
3711
3712 if (info.stack_words > 0)
3713 cum->stack_words = info.stack_offset + info.stack_words;
3714
3715 cum->arg_number++;
3716 }
3717
3718 /* Implement FUNCTION_ARG. */
3719
3720 struct rtx_def *
function_arg(const CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,int named)3721 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3722 tree type, int named)
3723 {
3724 struct mips_arg_info info;
3725
3726 /* We will be called with a mode of VOIDmode after the last argument
3727 has been seen. Whatever we return will be passed to the call
3728 insn. If we need a mips16 fp_code, return a REG with the code
3729 stored as the mode. */
3730 if (mode == VOIDmode)
3731 {
3732 if (TARGET_MIPS16 && cum->fp_code != 0)
3733 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3734
3735 else
3736 return 0;
3737 }
3738
3739 mips_arg_info (cum, mode, type, named, &info);
3740
3741 /* Return straight away if the whole argument is passed on the stack. */
3742 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3743 return 0;
3744
3745 if (type != 0
3746 && TREE_CODE (type) == RECORD_TYPE
3747 && TARGET_NEWABI
3748 && TYPE_SIZE_UNIT (type)
3749 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3750 && named)
3751 {
3752 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3753 structure contains a double in its entirety, then that 64 bit
3754 chunk is passed in a floating point register. */
3755 tree field;
3756
3757 /* First check to see if there is any such field. */
3758 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3759 if (TREE_CODE (field) == FIELD_DECL
3760 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3761 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3762 && host_integerp (bit_position (field), 0)
3763 && int_bit_position (field) % BITS_PER_WORD == 0)
3764 break;
3765
3766 if (field != 0)
3767 {
3768 /* Now handle the special case by returning a PARALLEL
3769 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3770 chunks are passed in registers. */
3771 unsigned int i;
3772 HOST_WIDE_INT bitpos;
3773 rtx ret;
3774
3775 /* assign_parms checks the mode of ENTRY_PARM, so we must
3776 use the actual mode here. */
3777 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3778
3779 bitpos = 0;
3780 field = TYPE_FIELDS (type);
3781 for (i = 0; i < info.reg_words; i++)
3782 {
3783 rtx reg;
3784
3785 for (; field; field = TREE_CHAIN (field))
3786 if (TREE_CODE (field) == FIELD_DECL
3787 && int_bit_position (field) >= bitpos)
3788 break;
3789
3790 if (field
3791 && int_bit_position (field) == bitpos
3792 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3793 && !TARGET_SOFT_FLOAT
3794 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3795 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3796 else
3797 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3798
3799 XVECEXP (ret, 0, i)
3800 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3801 GEN_INT (bitpos / BITS_PER_UNIT));
3802
3803 bitpos += BITS_PER_WORD;
3804 }
3805 return ret;
3806 }
3807 }
3808
3809 /* Handle the n32/n64 conventions for passing complex floating-point
3810 arguments in FPR pairs. The real part goes in the lower register
3811 and the imaginary part goes in the upper register. */
3812 if (TARGET_NEWABI
3813 && info.fpr_p
3814 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3815 {
3816 rtx real, imag;
3817 enum machine_mode inner;
3818 int reg;
3819
3820 inner = GET_MODE_INNER (mode);
3821 reg = FP_ARG_FIRST + info.reg_offset;
3822 real = gen_rtx_EXPR_LIST (VOIDmode,
3823 gen_rtx_REG (inner, reg),
3824 const0_rtx);
3825 imag = gen_rtx_EXPR_LIST (VOIDmode,
3826 gen_rtx_REG (inner, reg + info.reg_words / 2),
3827 GEN_INT (GET_MODE_SIZE (inner)));
3828 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3829 }
3830
3831 if (!info.fpr_p)
3832 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3833 else if (info.reg_offset == 1)
3834 /* This code handles the special o32 case in which the second word
3835 of the argument structure is passed in floating-point registers. */
3836 return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
3837 else
3838 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3839 }
3840
3841
3842 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3843
3844 static int
mips_arg_partial_bytes(CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,bool named)3845 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
3846 enum machine_mode mode, tree type, bool named)
3847 {
3848 struct mips_arg_info info;
3849
3850 mips_arg_info (cum, mode, type, named, &info);
3851 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
3852 }
3853
3854
3855 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3856 PARM_BOUNDARY bits of alignment, but will be given anything up
3857 to STACK_BOUNDARY bits if the type requires it. */
3858
3859 int
function_arg_boundary(enum machine_mode mode,tree type)3860 function_arg_boundary (enum machine_mode mode, tree type)
3861 {
3862 unsigned int alignment;
3863
3864 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3865 if (alignment < PARM_BOUNDARY)
3866 alignment = PARM_BOUNDARY;
3867 if (alignment > STACK_BOUNDARY)
3868 alignment = STACK_BOUNDARY;
3869 return alignment;
3870 }
3871
3872 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3873 upward rather than downward. In other words, return true if the
3874 first byte of the stack slot has useful data, false if the last
3875 byte does. */
3876
3877 bool
mips_pad_arg_upward(enum machine_mode mode,tree type)3878 mips_pad_arg_upward (enum machine_mode mode, tree type)
3879 {
3880 /* On little-endian targets, the first byte of every stack argument
3881 is passed in the first byte of the stack slot. */
3882 if (!BYTES_BIG_ENDIAN)
3883 return true;
3884
3885 /* Otherwise, integral types are padded downward: the last byte of a
3886 stack argument is passed in the last byte of the stack slot. */
3887 if (type != 0
3888 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3889 : GET_MODE_CLASS (mode) == MODE_INT)
3890 return false;
3891
3892 /* Big-endian o64 pads floating-point arguments downward. */
3893 if (mips_abi == ABI_O64)
3894 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3895 return false;
3896
3897 /* Other types are padded upward for o32, o64, n32 and n64. */
3898 if (mips_abi != ABI_EABI)
3899 return true;
3900
3901 /* Arguments smaller than a stack slot are padded downward. */
3902 if (mode != BLKmode)
3903 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3904 else
3905 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3906 }
3907
3908
3909 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3910 if the least significant byte of the register has useful data. Return
3911 the opposite if the most significant byte does. */
3912
3913 bool
mips_pad_reg_upward(enum machine_mode mode,tree type)3914 mips_pad_reg_upward (enum machine_mode mode, tree type)
3915 {
3916 /* No shifting is required for floating-point arguments. */
3917 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3918 return !BYTES_BIG_ENDIAN;
3919
3920 /* Otherwise, apply the same padding to register arguments as we do
3921 to stack arguments. */
3922 return mips_pad_arg_upward (mode, type);
3923 }
3924
3925 static void
mips_setup_incoming_varargs(CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,int * pretend_size ATTRIBUTE_UNUSED,int no_rtl)3926 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3927 tree type, int *pretend_size ATTRIBUTE_UNUSED,
3928 int no_rtl)
3929 {
3930 CUMULATIVE_ARGS local_cum;
3931 int gp_saved, fp_saved;
3932
3933 /* The caller has advanced CUM up to, but not beyond, the last named
3934 argument. Advance a local copy of CUM past the last "real" named
3935 argument, to find out how many registers are left over. */
3936
3937 local_cum = *cum;
3938 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
3939
3940 /* Found out how many registers we need to save. */
3941 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3942 fp_saved = (EABI_FLOAT_VARARGS_P
3943 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
3944 : 0);
3945
3946 if (!no_rtl)
3947 {
3948 if (gp_saved > 0)
3949 {
3950 rtx ptr, mem;
3951
3952 ptr = plus_constant (virtual_incoming_args_rtx,
3953 REG_PARM_STACK_SPACE (cfun->decl)
3954 - gp_saved * UNITS_PER_WORD);
3955 mem = gen_rtx_MEM (BLKmode, ptr);
3956 set_mem_alias_set (mem, get_varargs_alias_set ());
3957
3958 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3959 mem, gp_saved);
3960 }
3961 if (fp_saved > 0)
3962 {
3963 /* We can't use move_block_from_reg, because it will use
3964 the wrong mode. */
3965 enum machine_mode mode;
3966 int off, i;
3967
3968 /* Set OFF to the offset from virtual_incoming_args_rtx of
3969 the first float register. The FP save area lies below
3970 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3971 off = -gp_saved * UNITS_PER_WORD;
3972 off &= ~(UNITS_PER_FPVALUE - 1);
3973 off -= fp_saved * UNITS_PER_FPREG;
3974
3975 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
3976
3977 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
3978 {
3979 rtx ptr, mem;
3980
3981 ptr = plus_constant (virtual_incoming_args_rtx, off);
3982 mem = gen_rtx_MEM (mode, ptr);
3983 set_mem_alias_set (mem, get_varargs_alias_set ());
3984 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
3985 off += UNITS_PER_HWFPVALUE;
3986 }
3987 }
3988 }
3989 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
3990 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
3991 + fp_saved * UNITS_PER_FPREG);
3992 }
3993
3994 /* Create the va_list data type.
3995 We keep 3 pointers, and two offsets.
3996 Two pointers are to the overflow area, which starts at the CFA.
3997 One of these is constant, for addressing into the GPR save area below it.
3998 The other is advanced up the stack through the overflow region.
3999 The third pointer is to the GPR save area. Since the FPR save area
4000 is just below it, we can address FPR slots off this pointer.
4001 We also keep two one-byte offsets, which are to be subtracted from the
4002 constant pointers to yield addresses in the GPR and FPR save areas.
4003 These are downcounted as float or non-float arguments are used,
4004 and when they get to zero, the argument must be obtained from the
4005 overflow region.
4006 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4007 pointer is enough. It's started at the GPR save area, and is
4008 advanced, period.
4009 Note that the GPR save area is not constant size, due to optimization
4010 in the prologue. Hence, we can't use a design with two pointers
4011 and two offsets, although we could have designed this with two pointers
4012 and three offsets. */
4013
4014 static tree
mips_build_builtin_va_list(void)4015 mips_build_builtin_va_list (void)
4016 {
4017 if (EABI_FLOAT_VARARGS_P)
4018 {
4019 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4020 tree array, index;
4021
4022 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4023
4024 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4025 ptr_type_node);
4026 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4027 ptr_type_node);
4028 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4029 ptr_type_node);
4030 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4031 unsigned_char_type_node);
4032 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4033 unsigned_char_type_node);
4034 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4035 warn on every user file. */
4036 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4037 array = build_array_type (unsigned_char_type_node,
4038 build_index_type (index));
4039 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4040
4041 DECL_FIELD_CONTEXT (f_ovfl) = record;
4042 DECL_FIELD_CONTEXT (f_gtop) = record;
4043 DECL_FIELD_CONTEXT (f_ftop) = record;
4044 DECL_FIELD_CONTEXT (f_goff) = record;
4045 DECL_FIELD_CONTEXT (f_foff) = record;
4046 DECL_FIELD_CONTEXT (f_res) = record;
4047
4048 TYPE_FIELDS (record) = f_ovfl;
4049 TREE_CHAIN (f_ovfl) = f_gtop;
4050 TREE_CHAIN (f_gtop) = f_ftop;
4051 TREE_CHAIN (f_ftop) = f_goff;
4052 TREE_CHAIN (f_goff) = f_foff;
4053 TREE_CHAIN (f_foff) = f_res;
4054
4055 layout_type (record);
4056 return record;
4057 }
4058 else if (TARGET_IRIX && TARGET_IRIX6)
4059 /* On IRIX 6, this type is 'char *'. */
4060 return build_pointer_type (char_type_node);
4061 else
4062 /* Otherwise, we use 'void *'. */
4063 return ptr_type_node;
4064 }
4065
4066 /* Implement va_start. */
4067
4068 void
mips_va_start(tree valist,rtx nextarg)4069 mips_va_start (tree valist, rtx nextarg)
4070 {
4071 if (EABI_FLOAT_VARARGS_P)
4072 {
4073 const CUMULATIVE_ARGS *cum;
4074 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4075 tree ovfl, gtop, ftop, goff, foff;
4076 tree t;
4077 int gpr_save_area_size;
4078 int fpr_save_area_size;
4079 int fpr_offset;
4080
4081 cum = ¤t_function_args_info;
4082 gpr_save_area_size
4083 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4084 fpr_save_area_size
4085 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4086
4087 f_ovfl = TYPE_FIELDS (va_list_type_node);
4088 f_gtop = TREE_CHAIN (f_ovfl);
4089 f_ftop = TREE_CHAIN (f_gtop);
4090 f_goff = TREE_CHAIN (f_ftop);
4091 f_foff = TREE_CHAIN (f_goff);
4092
4093 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4094 NULL_TREE);
4095 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4096 NULL_TREE);
4097 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4098 NULL_TREE);
4099 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4100 NULL_TREE);
4101 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4102 NULL_TREE);
4103
4104 /* Emit code to initialize OVFL, which points to the next varargs
4105 stack argument. CUM->STACK_WORDS gives the number of stack
4106 words used by named arguments. */
4107 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4108 if (cum->stack_words > 0)
4109 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4110 build_int_cst (NULL_TREE,
4111 cum->stack_words * UNITS_PER_WORD));
4112 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4113 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4114
4115 /* Emit code to initialize GTOP, the top of the GPR save area. */
4116 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4117 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4118 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4119
4120 /* Emit code to initialize FTOP, the top of the FPR save area.
4121 This address is gpr_save_area_bytes below GTOP, rounded
4122 down to the next fp-aligned boundary. */
4123 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4124 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4125 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4126 if (fpr_offset)
4127 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
4128 build_int_cst (NULL_TREE, -fpr_offset));
4129 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4130 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4131
4132 /* Emit code to initialize GOFF, the offset from GTOP of the
4133 next GPR argument. */
4134 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4135 build_int_cst (NULL_TREE, gpr_save_area_size));
4136 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4137
4138 /* Likewise emit code to initialize FOFF, the offset from FTOP
4139 of the next FPR argument. */
4140 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4141 build_int_cst (NULL_TREE, fpr_save_area_size));
4142 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4143 }
4144 else
4145 {
4146 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4147 std_expand_builtin_va_start (valist, nextarg);
4148 }
4149 }
4150
4151 /* Implement va_arg. */
4152
4153 static tree
mips_gimplify_va_arg_expr(tree valist,tree type,tree * pre_p,tree * post_p)4154 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4155 {
4156 HOST_WIDE_INT size, rsize;
4157 tree addr;
4158 bool indirect;
4159
4160 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4161
4162 if (indirect)
4163 type = build_pointer_type (type);
4164
4165 size = int_size_in_bytes (type);
4166 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4167
4168 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4169 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4170 else
4171 {
4172 /* Not a simple merged stack. */
4173
4174 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4175 tree ovfl, top, off, align;
4176 HOST_WIDE_INT osize;
4177 tree t, u;
4178
4179 f_ovfl = TYPE_FIELDS (va_list_type_node);
4180 f_gtop = TREE_CHAIN (f_ovfl);
4181 f_ftop = TREE_CHAIN (f_gtop);
4182 f_goff = TREE_CHAIN (f_ftop);
4183 f_foff = TREE_CHAIN (f_goff);
4184
4185 /* We maintain separate pointers and offsets for floating-point
4186 and integer arguments, but we need similar code in both cases.
4187 Let:
4188
4189 TOP be the top of the register save area;
4190 OFF be the offset from TOP of the next register;
4191 ADDR_RTX be the address of the argument;
4192 RSIZE be the number of bytes used to store the argument
4193 when it's in the register save area;
4194 OSIZE be the number of bytes used to store it when it's
4195 in the stack overflow area; and
4196 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4197
4198 The code we want is:
4199
4200 1: off &= -rsize; // round down
4201 2: if (off != 0)
4202 3: {
4203 4: addr_rtx = top - off;
4204 5: off -= rsize;
4205 6: }
4206 7: else
4207 8: {
4208 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4209 10: addr_rtx = ovfl + PADDING;
4210 11: ovfl += osize;
4211 14: }
4212
4213 [1] and [9] can sometimes be optimized away. */
4214
4215 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4216 NULL_TREE);
4217
4218 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4219 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4220 {
4221 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4222 NULL_TREE);
4223 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4224 NULL_TREE);
4225
4226 /* When floating-point registers are saved to the stack,
4227 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4228 of the float's precision. */
4229 rsize = UNITS_PER_HWFPVALUE;
4230
4231 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4232 (= PARM_BOUNDARY bits). This can be different from RSIZE
4233 in two cases:
4234
4235 (1) On 32-bit targets when TYPE is a structure such as:
4236
4237 struct s { float f; };
4238
4239 Such structures are passed in paired FPRs, so RSIZE
4240 will be 8 bytes. However, the structure only takes
4241 up 4 bytes of memory, so OSIZE will only be 4.
4242
4243 (2) In combinations such as -mgp64 -msingle-float
4244 -fshort-double. Doubles passed in registers
4245 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4246 but those passed on the stack take up
4247 UNITS_PER_WORD bytes. */
4248 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4249 }
4250 else
4251 {
4252 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4253 NULL_TREE);
4254 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4255 NULL_TREE);
4256 if (rsize > UNITS_PER_WORD)
4257 {
4258 /* [1] Emit code for: off &= -rsize. */
4259 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
4260 build_int_cst (NULL_TREE, -rsize));
4261 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4262 gimplify_and_add (t, pre_p);
4263 }
4264 osize = rsize;
4265 }
4266
4267 /* [2] Emit code to branch if off == 0. */
4268 t = build (NE_EXPR, boolean_type_node, off,
4269 build_int_cst (TREE_TYPE (off), 0));
4270 addr = build (COND_EXPR, ptr_type_node, t, NULL, NULL);
4271
4272 /* [5] Emit code for: off -= rsize. We do this as a form of
4273 post-increment not available to C. Also widen for the
4274 coming pointer arithmetic. */
4275 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4276 t = build (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4277 t = fold_convert (sizetype, t);
4278 t = fold_convert (TREE_TYPE (top), t);
4279
4280 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4281 the argument has RSIZE - SIZE bytes of leading padding. */
4282 t = build (MINUS_EXPR, TREE_TYPE (top), top, t);
4283 if (BYTES_BIG_ENDIAN && rsize > size)
4284 {
4285 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
4286 rsize - size));
4287 t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
4288 }
4289 COND_EXPR_THEN (addr) = t;
4290
4291 if (osize > UNITS_PER_WORD)
4292 {
4293 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4294 u = fold_convert (TREE_TYPE (ovfl),
4295 build_int_cst (NULL_TREE, osize - 1));
4296 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4297 u = fold_convert (TREE_TYPE (ovfl),
4298 build_int_cst (NULL_TREE, -osize));
4299 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4300 align = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4301 }
4302 else
4303 align = NULL;
4304
4305 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4306 post-increment ovfl by osize. On big-endian machines,
4307 the argument has OSIZE - SIZE bytes of leading padding. */
4308 u = fold_convert (TREE_TYPE (ovfl),
4309 build_int_cst (NULL_TREE, osize));
4310 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4311 if (BYTES_BIG_ENDIAN && osize > size)
4312 {
4313 u = fold_convert (TREE_TYPE (t),
4314 build_int_cst (NULL_TREE, osize - size));
4315 t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
4316 }
4317
4318 /* String [9] and [10,11] together. */
4319 if (align)
4320 t = build (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4321 COND_EXPR_ELSE (addr) = t;
4322
4323 addr = fold_convert (build_pointer_type (type), addr);
4324 addr = build_va_arg_indirect_ref (addr);
4325 }
4326
4327 if (indirect)
4328 addr = build_va_arg_indirect_ref (addr);
4329
4330 return addr;
4331 }
4332
4333 /* Return true if it is possible to use left/right accesses for a
4334 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4335 returning true, update *OP, *LEFT and *RIGHT as follows:
4336
4337 *OP is a BLKmode reference to the whole field.
4338
4339 *LEFT is a QImode reference to the first byte if big endian or
4340 the last byte if little endian. This address can be used in the
4341 left-side instructions (lwl, swl, ldl, sdl).
4342
4343 *RIGHT is a QImode reference to the opposite end of the field and
4344 can be used in the patterning right-side instruction. */
4345
4346 static bool
mips_get_unaligned_mem(rtx * op,unsigned int width,int bitpos,rtx * left,rtx * right)4347 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4348 rtx *left, rtx *right)
4349 {
4350 rtx first, last;
4351
4352 /* Check that the operand really is a MEM. Not all the extv and
4353 extzv predicates are checked. */
4354 if (!MEM_P (*op))
4355 return false;
4356
4357 /* Check that the size is valid. */
4358 if (width != 32 && (!TARGET_64BIT || width != 64))
4359 return false;
4360
4361 /* We can only access byte-aligned values. Since we are always passed
4362 a reference to the first byte of the field, it is not necessary to
4363 do anything with BITPOS after this check. */
4364 if (bitpos % BITS_PER_UNIT != 0)
4365 return false;
4366
4367 /* Reject aligned bitfields: we want to use a normal load or store
4368 instead of a left/right pair. */
4369 if (MEM_ALIGN (*op) >= width)
4370 return false;
4371
4372 /* Adjust *OP to refer to the whole field. This also has the effect
4373 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4374 *op = adjust_address (*op, BLKmode, 0);
4375 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4376
4377 /* Get references to both ends of the field. We deliberately don't
4378 use the original QImode *OP for FIRST since the new BLKmode one
4379 might have a simpler address. */
4380 first = adjust_address (*op, QImode, 0);
4381 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4382
4383 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4384 be the upper word and RIGHT the lower word. */
4385 if (TARGET_BIG_ENDIAN)
4386 *left = first, *right = last;
4387 else
4388 *left = last, *right = first;
4389
4390 return true;
4391 }
4392
4393
4394 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4395 Return true on success. We only handle cases where zero_extract is
4396 equivalent to sign_extract. */
4397
4398 bool
mips_expand_unaligned_load(rtx dest,rtx src,unsigned int width,int bitpos)4399 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4400 {
4401 rtx left, right, temp;
4402
4403 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4404 paradoxical word_mode subreg. This is the only case in which
4405 we allow the destination to be larger than the source. */
4406 if (GET_CODE (dest) == SUBREG
4407 && GET_MODE (dest) == DImode
4408 && SUBREG_BYTE (dest) == 0
4409 && GET_MODE (SUBREG_REG (dest)) == SImode)
4410 dest = SUBREG_REG (dest);
4411
4412 /* After the above adjustment, the destination must be the same
4413 width as the source. */
4414 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4415 return false;
4416
4417 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4418 return false;
4419
4420 temp = gen_reg_rtx (GET_MODE (dest));
4421 if (GET_MODE (dest) == DImode)
4422 {
4423 emit_insn (gen_mov_ldl (temp, src, left));
4424 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4425 }
4426 else
4427 {
4428 emit_insn (gen_mov_lwl (temp, src, left));
4429 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4430 }
4431 return true;
4432 }
4433
4434
4435 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4436 true on success. */
4437
4438 bool
mips_expand_unaligned_store(rtx dest,rtx src,unsigned int width,int bitpos)4439 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4440 {
4441 rtx left, right;
4442
4443 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4444 return false;
4445
4446 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
4447
4448 if (GET_MODE (src) == DImode)
4449 {
4450 emit_insn (gen_mov_sdl (dest, src, left));
4451 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4452 }
4453 else
4454 {
4455 emit_insn (gen_mov_swl (dest, src, left));
4456 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4457 }
4458 return true;
4459 }
4460
4461 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4462 source of an "ext" instruction or the destination of an "ins"
4463 instruction. OP must be a register operand and the following
4464 conditions must hold:
4465
4466 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4467 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4468 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4469
4470 Also reject lengths equal to a word as they are better handled
4471 by the move patterns. */
4472
4473 bool
mips_use_ins_ext_p(rtx op,rtx size,rtx position)4474 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4475 {
4476 HOST_WIDE_INT len, pos;
4477
4478 if (!ISA_HAS_EXT_INS
4479 || !register_operand (op, VOIDmode)
4480 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4481 return false;
4482
4483 len = INTVAL (size);
4484 pos = INTVAL (position);
4485
4486 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4487 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4488 return false;
4489
4490 return true;
4491 }
4492
4493 /* Set up globals to generate code for the ISA or processor
4494 described by INFO. */
4495
4496 static void
mips_set_architecture(const struct mips_cpu_info * info)4497 mips_set_architecture (const struct mips_cpu_info *info)
4498 {
4499 if (info != 0)
4500 {
4501 mips_arch_info = info;
4502 mips_arch = info->cpu;
4503 mips_isa = info->isa;
4504 }
4505 }
4506
4507
4508 /* Likewise for tuning. */
4509
4510 static void
mips_set_tune(const struct mips_cpu_info * info)4511 mips_set_tune (const struct mips_cpu_info *info)
4512 {
4513 if (info != 0)
4514 {
4515 mips_tune_info = info;
4516 mips_tune = info->cpu;
4517 }
4518 }
4519
4520 /* Implement TARGET_HANDLE_OPTION. */
4521
4522 static bool
mips_handle_option(size_t code,const char * arg,int value ATTRIBUTE_UNUSED)4523 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4524 {
4525 switch (code)
4526 {
4527 case OPT_mabi_:
4528 if (strcmp (arg, "32") == 0)
4529 mips_abi = ABI_32;
4530 else if (strcmp (arg, "o64") == 0)
4531 mips_abi = ABI_O64;
4532 else if (strcmp (arg, "n32") == 0)
4533 mips_abi = ABI_N32;
4534 else if (strcmp (arg, "64") == 0)
4535 mips_abi = ABI_64;
4536 else if (strcmp (arg, "eabi") == 0)
4537 mips_abi = ABI_EABI;
4538 else
4539 return false;
4540 return true;
4541
4542 case OPT_march_:
4543 case OPT_mtune_:
4544 return mips_parse_cpu (arg) != 0;
4545
4546 case OPT_mips:
4547 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4548 return mips_isa_info != 0;
4549
4550 case OPT_mno_flush_func:
4551 mips_cache_flush_func = NULL;
4552 return true;
4553
4554 default:
4555 return true;
4556 }
4557 }
4558
4559 /* Set up the threshold for data to go into the small data area, instead
4560 of the normal data area, and detect any conflicts in the switches. */
4561
4562 void
override_options(void)4563 override_options (void)
4564 {
4565 int i, start, regno;
4566 enum machine_mode mode;
4567
4568 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4569
4570 /* The following code determines the architecture and register size.
4571 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4572 The GAS and GCC code should be kept in sync as much as possible. */
4573
4574 if (mips_arch_string != 0)
4575 mips_set_architecture (mips_parse_cpu (mips_arch_string));
4576
4577 if (mips_isa_info != 0)
4578 {
4579 if (mips_arch_info == 0)
4580 mips_set_architecture (mips_isa_info);
4581 else if (mips_arch_info->isa != mips_isa_info->isa)
4582 error ("-%s conflicts with the other architecture options, "
4583 "which specify a %s processor",
4584 mips_isa_info->name,
4585 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4586 }
4587
4588 if (mips_arch_info == 0)
4589 {
4590 #ifdef MIPS_CPU_STRING_DEFAULT
4591 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4592 #else
4593 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4594 #endif
4595 }
4596
4597 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4598 error ("-march=%s is not compatible with the selected ABI",
4599 mips_arch_info->name);
4600
4601 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4602 if (mips_tune_string != 0)
4603 mips_set_tune (mips_parse_cpu (mips_tune_string));
4604
4605 if (mips_tune_info == 0)
4606 mips_set_tune (mips_arch_info);
4607
4608 /* Set cost structure for the processor. */
4609 mips_cost = &mips_rtx_cost_data[mips_tune];
4610
4611 if ((target_flags_explicit & MASK_64BIT) != 0)
4612 {
4613 /* The user specified the size of the integer registers. Make sure
4614 it agrees with the ABI and ISA. */
4615 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4616 error ("-mgp64 used with a 32-bit processor");
4617 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4618 error ("-mgp32 used with a 64-bit ABI");
4619 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4620 error ("-mgp64 used with a 32-bit ABI");
4621 }
4622 else
4623 {
4624 /* Infer the integer register size from the ABI and processor.
4625 Restrict ourselves to 32-bit registers if that's all the
4626 processor has, or if the ABI cannot handle 64-bit registers. */
4627 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4628 target_flags &= ~MASK_64BIT;
4629 else
4630 target_flags |= MASK_64BIT;
4631 }
4632
4633 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4634 {
4635 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4636 only one right answer here. */
4637 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4638 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4639 else if (!TARGET_64BIT && TARGET_FLOAT64)
4640 error ("unsupported combination: %s", "-mgp32 -mfp64");
4641 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4642 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4643 }
4644 else
4645 {
4646 /* -msingle-float selects 32-bit float registers. Otherwise the
4647 float registers should be the same size as the integer ones. */
4648 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4649 target_flags |= MASK_FLOAT64;
4650 else
4651 target_flags &= ~MASK_FLOAT64;
4652 }
4653
4654 /* End of code shared with GAS. */
4655
4656 if ((target_flags_explicit & MASK_LONG64) == 0)
4657 {
4658 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4659 target_flags |= MASK_LONG64;
4660 else
4661 target_flags &= ~MASK_LONG64;
4662 }
4663
4664 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4665 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4666 {
4667 /* For some configurations, it is useful to have -march control
4668 the default setting of MASK_SOFT_FLOAT. */
4669 switch ((int) mips_arch)
4670 {
4671 case PROCESSOR_R4100:
4672 case PROCESSOR_R4111:
4673 case PROCESSOR_R4120:
4674 case PROCESSOR_R4130:
4675 target_flags |= MASK_SOFT_FLOAT;
4676 break;
4677
4678 default:
4679 target_flags &= ~MASK_SOFT_FLOAT;
4680 break;
4681 }
4682 }
4683
4684 if (!TARGET_OLDABI)
4685 flag_pcc_struct_return = 0;
4686
4687 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4688 {
4689 /* If neither -mbranch-likely nor -mno-branch-likely was given
4690 on the command line, set MASK_BRANCHLIKELY based on the target
4691 architecture.
4692
4693 By default, we enable use of Branch Likely instructions on
4694 all architectures which support them with the following
4695 exceptions: when creating MIPS32 or MIPS64 code, and when
4696 tuning for architectures where their use tends to hurt
4697 performance.
4698
4699 The MIPS32 and MIPS64 architecture specifications say "Software
4700 is strongly encouraged to avoid use of Branch Likely
4701 instructions, as they will be removed from a future revision
4702 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4703 issue those instructions unless instructed to do so by
4704 -mbranch-likely. */
4705 if (ISA_HAS_BRANCHLIKELY
4706 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4707 && !(TUNE_MIPS5500 || TUNE_SB1))
4708 target_flags |= MASK_BRANCHLIKELY;
4709 else
4710 target_flags &= ~MASK_BRANCHLIKELY;
4711 }
4712 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4713 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4714
4715 /* The effect of -mabicalls isn't defined for the EABI. */
4716 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4717 {
4718 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4719 target_flags &= ~MASK_ABICALLS;
4720 }
4721
4722 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4723 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4724 /* ??? -non_shared turns off pic code generation, but this is not
4725 implemented. */
4726 if (TARGET_ABICALLS)
4727 {
4728 flag_pic = 1;
4729 if (mips_section_threshold > 0)
4730 warning (0, "-G is incompatible with PIC code which is the default");
4731 }
4732
4733 /* mips_split_addresses is a half-way house between explicit
4734 relocations and the traditional assembler macros. It can
4735 split absolute 32-bit symbolic constants into a high/lo_sum
4736 pair but uses macros for other sorts of access.
4737
4738 Like explicit relocation support for REL targets, it relies
4739 on GNU extensions in the assembler and the linker.
4740
4741 Although this code should work for -O0, it has traditionally
4742 been treated as an optimization. */
4743 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4744 && optimize && !flag_pic
4745 && !ABI_HAS_64BIT_SYMBOLS)
4746 mips_split_addresses = 1;
4747 else
4748 mips_split_addresses = 0;
4749
4750 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4751 faster code, but at the expense of more nops. Enable it at -O3 and
4752 above. */
4753 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4754 target_flags |= MASK_VR4130_ALIGN;
4755
4756 /* When compiling for the mips16, we cannot use floating point. We
4757 record the original hard float value in mips16_hard_float. */
4758 if (TARGET_MIPS16)
4759 {
4760 if (TARGET_SOFT_FLOAT)
4761 mips16_hard_float = 0;
4762 else
4763 mips16_hard_float = 1;
4764 target_flags |= MASK_SOFT_FLOAT;
4765
4766 /* Don't run the scheduler before reload, since it tends to
4767 increase register pressure. */
4768 flag_schedule_insns = 0;
4769
4770 /* Don't do hot/cold partitioning. The constant layout code expects
4771 the whole function to be in a single section. */
4772 flag_reorder_blocks_and_partition = 0;
4773
4774 /* Silently disable -mexplicit-relocs since it doesn't apply
4775 to mips16 code. Even so, it would overly pedantic to warn
4776 about "-mips16 -mexplicit-relocs", especially given that
4777 we use a %gprel() operator. */
4778 target_flags &= ~MASK_EXPLICIT_RELOCS;
4779 }
4780
4781 /* When using explicit relocs, we call dbr_schedule from within
4782 mips_reorg. */
4783 if (TARGET_EXPLICIT_RELOCS)
4784 {
4785 mips_flag_delayed_branch = flag_delayed_branch;
4786 flag_delayed_branch = 0;
4787 }
4788
4789 #ifdef MIPS_TFMODE_FORMAT
4790 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4791 #endif
4792
4793 /* Make sure that the user didn't turn off paired single support when
4794 MIPS-3D support is requested. */
4795 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
4796 && !TARGET_PAIRED_SINGLE_FLOAT)
4797 error ("-mips3d requires -mpaired-single");
4798
4799 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
4800 if (TARGET_MIPS3D)
4801 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
4802
4803 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4804 and TARGET_HARD_FLOAT are both true. */
4805 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
4806 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4807
4808 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4809 enabled. */
4810 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
4811 error ("-mips3d/-mpaired-single must be used with -mips64");
4812
4813 if (TARGET_MIPS16 && TARGET_DSP)
4814 error ("-mips16 and -mdsp cannot be used together");
4815
4816 mips_print_operand_punct['?'] = 1;
4817 mips_print_operand_punct['#'] = 1;
4818 mips_print_operand_punct['/'] = 1;
4819 mips_print_operand_punct['&'] = 1;
4820 mips_print_operand_punct['!'] = 1;
4821 mips_print_operand_punct['*'] = 1;
4822 mips_print_operand_punct['@'] = 1;
4823 mips_print_operand_punct['.'] = 1;
4824 mips_print_operand_punct['('] = 1;
4825 mips_print_operand_punct[')'] = 1;
4826 mips_print_operand_punct['['] = 1;
4827 mips_print_operand_punct[']'] = 1;
4828 mips_print_operand_punct['<'] = 1;
4829 mips_print_operand_punct['>'] = 1;
4830 mips_print_operand_punct['{'] = 1;
4831 mips_print_operand_punct['}'] = 1;
4832 mips_print_operand_punct['^'] = 1;
4833 mips_print_operand_punct['$'] = 1;
4834 mips_print_operand_punct['+'] = 1;
4835 mips_print_operand_punct['~'] = 1;
4836
4837 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4838 mips_char_to_class['t'] = T_REG;
4839 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4840 mips_char_to_class['h'] = HI_REG;
4841 mips_char_to_class['l'] = LO_REG;
4842 mips_char_to_class['x'] = MD_REGS;
4843 mips_char_to_class['b'] = ALL_REGS;
4844 mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
4845 TARGET_MIPS16 ? M16_NA_REGS :
4846 GR_REGS);
4847 mips_char_to_class['e'] = LEA_REGS;
4848 mips_char_to_class['j'] = PIC_FN_ADDR_REG;
4849 mips_char_to_class['v'] = V1_REG;
4850 mips_char_to_class['y'] = GR_REGS;
4851 mips_char_to_class['z'] = ST_REGS;
4852 mips_char_to_class['B'] = COP0_REGS;
4853 mips_char_to_class['C'] = COP2_REGS;
4854 mips_char_to_class['D'] = COP3_REGS;
4855 mips_char_to_class['A'] = DSP_ACC_REGS;
4856 mips_char_to_class['a'] = ACC_REGS;
4857
4858 /* Set up array to map GCC register number to debug register number.
4859 Ignore the special purpose register numbers. */
4860
4861 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4862 mips_dbx_regno[i] = -1;
4863
4864 start = GP_DBX_FIRST - GP_REG_FIRST;
4865 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4866 mips_dbx_regno[i] = i + start;
4867
4868 start = FP_DBX_FIRST - FP_REG_FIRST;
4869 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4870 mips_dbx_regno[i] = i + start;
4871
4872 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4873 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4874
4875 /* Set up array giving whether a given register can hold a given mode. */
4876
4877 for (mode = VOIDmode;
4878 mode != MAX_MACHINE_MODE;
4879 mode = (enum machine_mode) ((int)mode + 1))
4880 {
4881 register int size = GET_MODE_SIZE (mode);
4882 register enum mode_class class = GET_MODE_CLASS (mode);
4883
4884 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4885 {
4886 register int temp;
4887
4888 if (mode == CCV2mode)
4889 temp = (ISA_HAS_8CC
4890 && ST_REG_P (regno)
4891 && (regno - ST_REG_FIRST) % 2 == 0);
4892
4893 else if (mode == CCV4mode)
4894 temp = (ISA_HAS_8CC
4895 && ST_REG_P (regno)
4896 && (regno - ST_REG_FIRST) % 4 == 0);
4897
4898 else if (mode == CCmode)
4899 {
4900 if (! ISA_HAS_8CC)
4901 temp = (regno == FPSW_REGNUM);
4902 else
4903 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4904 || FP_REG_P (regno));
4905 }
4906
4907 else if (GP_REG_P (regno))
4908 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4909
4910 else if (FP_REG_P (regno))
4911 temp = ((regno % FP_INC) == 0)
4912 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
4913 || class == MODE_VECTOR_FLOAT)
4914 && size <= UNITS_PER_FPVALUE)
4915 /* Allow integer modes that fit into a single
4916 register. We need to put integers into FPRs
4917 when using instructions like cvt and trunc.
4918 We can't allow sizes smaller than a word,
4919 the FPU has no appropriate load/store
4920 instructions for those. */
4921 || (class == MODE_INT
4922 && size >= MIN_UNITS_PER_WORD
4923 && size <= UNITS_PER_FPREG)
4924 /* Allow TFmode for CCmode reloads. */
4925 || (ISA_HAS_8CC && mode == TFmode));
4926
4927 else if (ACC_REG_P (regno))
4928 temp = (INTEGRAL_MODE_P (mode)
4929 && (size <= UNITS_PER_WORD
4930 || (ACC_HI_REG_P (regno)
4931 && size == 2 * UNITS_PER_WORD)));
4932
4933 else if (ALL_COP_REG_P (regno))
4934 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
4935 else
4936 temp = 0;
4937
4938 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4939 }
4940 }
4941
4942 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4943 initialized yet, so we can't use that here. */
4944 gpr_mode = TARGET_64BIT ? DImode : SImode;
4945
4946 /* Provide default values for align_* for 64-bit targets. */
4947 if (TARGET_64BIT && !TARGET_MIPS16)
4948 {
4949 if (align_loops == 0)
4950 align_loops = 8;
4951 if (align_jumps == 0)
4952 align_jumps = 8;
4953 if (align_functions == 0)
4954 align_functions = 8;
4955 }
4956
4957 /* Function to allocate machine-dependent function status. */
4958 init_machine_status = &mips_init_machine_status;
4959
4960 if (ABI_HAS_64BIT_SYMBOLS)
4961 {
4962 if (TARGET_EXPLICIT_RELOCS)
4963 {
4964 mips_split_p[SYMBOL_64_HIGH] = true;
4965 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
4966 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
4967
4968 mips_split_p[SYMBOL_64_MID] = true;
4969 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
4970 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
4971
4972 mips_split_p[SYMBOL_64_LOW] = true;
4973 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
4974 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
4975
4976 mips_split_p[SYMBOL_GENERAL] = true;
4977 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4978 }
4979 }
4980 else
4981 {
4982 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
4983 {
4984 mips_split_p[SYMBOL_GENERAL] = true;
4985 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
4986 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4987 }
4988 }
4989
4990 if (TARGET_MIPS16)
4991 {
4992 /* The high part is provided by a pseudo copy of $gp. */
4993 mips_split_p[SYMBOL_SMALL_DATA] = true;
4994 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
4995 }
4996
4997 if (TARGET_EXPLICIT_RELOCS)
4998 {
4999 /* Small data constants are kept whole until after reload,
5000 then lowered by mips_rewrite_small_data. */
5001 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5002
5003 mips_split_p[SYMBOL_GOT_LOCAL] = true;
5004 if (TARGET_NEWABI)
5005 {
5006 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5007 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5008 }
5009 else
5010 {
5011 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5012 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5013 }
5014
5015 if (TARGET_XGOT)
5016 {
5017 /* The HIGH and LO_SUM are matched by special .md patterns. */
5018 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5019
5020 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5021 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5022 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5023
5024 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5025 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5026 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5027 }
5028 else
5029 {
5030 if (TARGET_NEWABI)
5031 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5032 else
5033 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5034 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5035 }
5036 }
5037
5038 if (TARGET_NEWABI)
5039 {
5040 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5041 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5042 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5043 }
5044
5045 /* Thread-local relocation operators. */
5046 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5047 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5048 mips_split_p[SYMBOL_DTPREL] = 1;
5049 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5050 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5051 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5052 mips_split_p[SYMBOL_TPREL] = 1;
5053 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5054 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5055
5056 /* We don't have a thread pointer access instruction on MIPS16, or
5057 appropriate TLS relocations. */
5058 if (TARGET_MIPS16)
5059 targetm.have_tls = false;
5060
5061 /* Default to working around R4000 errata only if the processor
5062 was selected explicitly. */
5063 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5064 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5065 target_flags |= MASK_FIX_R4000;
5066
5067 /* Default to working around R4400 errata only if the processor
5068 was selected explicitly. */
5069 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5070 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5071 target_flags |= MASK_FIX_R4400;
5072 }
5073
5074 /* Implement CONDITIONAL_REGISTER_USAGE. */
5075
5076 void
mips_conditional_register_usage(void)5077 mips_conditional_register_usage (void)
5078 {
5079 if (!TARGET_DSP)
5080 {
5081 int regno;
5082
5083 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5084 fixed_regs[regno] = call_used_regs[regno] = 1;
5085 }
5086 if (!TARGET_HARD_FLOAT)
5087 {
5088 int regno;
5089
5090 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5091 fixed_regs[regno] = call_used_regs[regno] = 1;
5092 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5093 fixed_regs[regno] = call_used_regs[regno] = 1;
5094 }
5095 else if (! ISA_HAS_8CC)
5096 {
5097 int regno;
5098
5099 /* We only have a single condition code register. We
5100 implement this by hiding all the condition code registers,
5101 and generating RTL that refers directly to ST_REG_FIRST. */
5102 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5103 fixed_regs[regno] = call_used_regs[regno] = 1;
5104 }
5105 /* In mips16 mode, we permit the $t temporary registers to be used
5106 for reload. We prohibit the unused $s registers, since they
5107 are caller saved, and saving them via a mips16 register would
5108 probably waste more time than just reloading the value. */
5109 if (TARGET_MIPS16)
5110 {
5111 fixed_regs[18] = call_used_regs[18] = 1;
5112 fixed_regs[19] = call_used_regs[19] = 1;
5113 fixed_regs[20] = call_used_regs[20] = 1;
5114 fixed_regs[21] = call_used_regs[21] = 1;
5115 fixed_regs[22] = call_used_regs[22] = 1;
5116 fixed_regs[23] = call_used_regs[23] = 1;
5117 fixed_regs[26] = call_used_regs[26] = 1;
5118 fixed_regs[27] = call_used_regs[27] = 1;
5119 fixed_regs[30] = call_used_regs[30] = 1;
5120 }
5121 /* fp20-23 are now caller saved. */
5122 if (mips_abi == ABI_64)
5123 {
5124 int regno;
5125 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5126 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5127 }
5128 /* Odd registers from fp21 to fp31 are now caller saved. */
5129 if (mips_abi == ABI_N32)
5130 {
5131 int regno;
5132 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5133 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5134 }
5135 }
5136
5137 /* Allocate a chunk of memory for per-function machine-dependent data. */
5138 static struct machine_function *
mips_init_machine_status(void)5139 mips_init_machine_status (void)
5140 {
5141 return ((struct machine_function *)
5142 ggc_alloc_cleared (sizeof (struct machine_function)));
5143 }
5144
5145 /* On the mips16, we want to allocate $24 (T_REG) before other
5146 registers for instructions for which it is possible. This helps
5147 avoid shuffling registers around in order to set up for an xor,
5148 encouraging the compiler to use a cmp instead. */
5149
5150 void
mips_order_regs_for_local_alloc(void)5151 mips_order_regs_for_local_alloc (void)
5152 {
5153 register int i;
5154
5155 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5156 reg_alloc_order[i] = i;
5157
5158 if (TARGET_MIPS16)
5159 {
5160 /* It really doesn't matter where we put register 0, since it is
5161 a fixed register anyhow. */
5162 reg_alloc_order[0] = 24;
5163 reg_alloc_order[24] = 0;
5164 }
5165 }
5166
5167
5168 /* The MIPS debug format wants all automatic variables and arguments
5169 to be in terms of the virtual frame pointer (stack pointer before
5170 any adjustment in the function), while the MIPS 3.0 linker wants
5171 the frame pointer to be the stack pointer after the initial
5172 adjustment. So, we do the adjustment here. The arg pointer (which
5173 is eliminated) points to the virtual frame pointer, while the frame
5174 pointer (which may be eliminated) points to the stack pointer after
5175 the initial adjustments. */
5176
5177 HOST_WIDE_INT
mips_debugger_offset(rtx addr,HOST_WIDE_INT offset)5178 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5179 {
5180 rtx offset2 = const0_rtx;
5181 rtx reg = eliminate_constant_term (addr, &offset2);
5182
5183 if (offset == 0)
5184 offset = INTVAL (offset2);
5185
5186 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5187 || reg == hard_frame_pointer_rtx)
5188 {
5189 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5190 ? compute_frame_size (get_frame_size ())
5191 : cfun->machine->frame.total_size;
5192
5193 /* MIPS16 frame is smaller */
5194 if (frame_pointer_needed && TARGET_MIPS16)
5195 frame_size -= cfun->machine->frame.args_size;
5196
5197 offset = offset - frame_size;
5198 }
5199
5200 /* sdbout_parms does not want this to crash for unrecognized cases. */
5201 #if 0
5202 else if (reg != arg_pointer_rtx)
5203 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5204 addr);
5205 #endif
5206
5207 return offset;
5208 }
5209
5210 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5211
5212 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5213 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5214 'h' OP is HIGH, prints %hi(X),
5215 'd' output integer constant in decimal,
5216 'z' if the operand is 0, use $0 instead of normal operand.
5217 'D' print second part of double-word register or memory operand.
5218 'L' print low-order register of double-word register operand.
5219 'M' print high-order register of double-word register operand.
5220 'C' print part of opcode for a branch condition.
5221 'F' print part of opcode for a floating-point branch condition.
5222 'N' print part of opcode for a branch condition, inverted.
5223 'W' print part of opcode for a floating-point branch condition, inverted.
5224 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5225 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5226 't' like 'T', but with the EQ/NE cases reversed
5227 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5228 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5229 'R' print the reloc associated with LO_SUM
5230 'q' print DSP accumulator registers
5231
5232 The punctuation characters are:
5233
5234 '(' Turn on .set noreorder
5235 ')' Turn on .set reorder
5236 '[' Turn on .set noat
5237 ']' Turn on .set at
5238 '<' Turn on .set nomacro
5239 '>' Turn on .set macro
5240 '{' Turn on .set volatile (not GAS)
5241 '}' Turn on .set novolatile (not GAS)
5242 '&' Turn on .set noreorder if filling delay slots
5243 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5244 '!' Turn on .set nomacro if filling delay slots
5245 '#' Print nop if in a .set noreorder section.
5246 '/' Like '#', but does nothing within a delayed branch sequence
5247 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5248 '@' Print the name of the assembler temporary register (at or $1).
5249 '.' Print the name of the register with a hard-wired zero (zero or $0).
5250 '^' Print the name of the pic call-through register (t9 or $25).
5251 '$' Print the name of the stack pointer register (sp or $29).
5252 '+' Print the name of the gp register (usually gp or $28).
5253 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5254
5255 void
print_operand(FILE * file,rtx op,int letter)5256 print_operand (FILE *file, rtx op, int letter)
5257 {
5258 register enum rtx_code code;
5259
5260 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5261 {
5262 switch (letter)
5263 {
5264 case '?':
5265 if (mips_branch_likely)
5266 putc ('l', file);
5267 break;
5268
5269 case '@':
5270 fputs (reg_names [GP_REG_FIRST + 1], file);
5271 break;
5272
5273 case '^':
5274 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5275 break;
5276
5277 case '.':
5278 fputs (reg_names [GP_REG_FIRST + 0], file);
5279 break;
5280
5281 case '$':
5282 fputs (reg_names[STACK_POINTER_REGNUM], file);
5283 break;
5284
5285 case '+':
5286 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5287 break;
5288
5289 case '&':
5290 if (final_sequence != 0 && set_noreorder++ == 0)
5291 fputs (".set\tnoreorder\n\t", file);
5292 break;
5293
5294 case '*':
5295 if (final_sequence != 0)
5296 {
5297 if (set_noreorder++ == 0)
5298 fputs (".set\tnoreorder\n\t", file);
5299
5300 if (set_nomacro++ == 0)
5301 fputs (".set\tnomacro\n\t", file);
5302 }
5303 break;
5304
5305 case '!':
5306 if (final_sequence != 0 && set_nomacro++ == 0)
5307 fputs ("\n\t.set\tnomacro", file);
5308 break;
5309
5310 case '#':
5311 if (set_noreorder != 0)
5312 fputs ("\n\tnop", file);
5313 break;
5314
5315 case '/':
5316 /* Print an extra newline so that the delayed insn is separated
5317 from the following ones. This looks neater and is consistent
5318 with non-nop delayed sequences. */
5319 if (set_noreorder != 0 && final_sequence == 0)
5320 fputs ("\n\tnop\n", file);
5321 break;
5322
5323 case '(':
5324 if (set_noreorder++ == 0)
5325 fputs (".set\tnoreorder\n\t", file);
5326 break;
5327
5328 case ')':
5329 if (set_noreorder == 0)
5330 error ("internal error: %%) found without a %%( in assembler pattern");
5331
5332 else if (--set_noreorder == 0)
5333 fputs ("\n\t.set\treorder", file);
5334
5335 break;
5336
5337 case '[':
5338 if (set_noat++ == 0)
5339 fputs (".set\tnoat\n\t", file);
5340 break;
5341
5342 case ']':
5343 if (set_noat == 0)
5344 error ("internal error: %%] found without a %%[ in assembler pattern");
5345 else if (--set_noat == 0)
5346 fputs ("\n\t.set\tat", file);
5347
5348 break;
5349
5350 case '<':
5351 if (set_nomacro++ == 0)
5352 fputs (".set\tnomacro\n\t", file);
5353 break;
5354
5355 case '>':
5356 if (set_nomacro == 0)
5357 error ("internal error: %%> found without a %%< in assembler pattern");
5358 else if (--set_nomacro == 0)
5359 fputs ("\n\t.set\tmacro", file);
5360
5361 break;
5362
5363 case '{':
5364 if (set_volatile++ == 0)
5365 fputs ("#.set\tvolatile\n\t", file);
5366 break;
5367
5368 case '}':
5369 if (set_volatile == 0)
5370 error ("internal error: %%} found without a %%{ in assembler pattern");
5371 else if (--set_volatile == 0)
5372 fputs ("\n\t#.set\tnovolatile", file);
5373
5374 break;
5375
5376 case '~':
5377 {
5378 if (align_labels_log > 0)
5379 ASM_OUTPUT_ALIGN (file, align_labels_log);
5380 }
5381 break;
5382
5383 default:
5384 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5385 break;
5386 }
5387
5388 return;
5389 }
5390
5391 if (! op)
5392 {
5393 error ("PRINT_OPERAND null pointer");
5394 return;
5395 }
5396
5397 code = GET_CODE (op);
5398
5399 if (letter == 'C')
5400 switch (code)
5401 {
5402 case EQ: fputs ("eq", file); break;
5403 case NE: fputs ("ne", file); break;
5404 case GT: fputs ("gt", file); break;
5405 case GE: fputs ("ge", file); break;
5406 case LT: fputs ("lt", file); break;
5407 case LE: fputs ("le", file); break;
5408 case GTU: fputs ("gtu", file); break;
5409 case GEU: fputs ("geu", file); break;
5410 case LTU: fputs ("ltu", file); break;
5411 case LEU: fputs ("leu", file); break;
5412 default:
5413 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5414 }
5415
5416 else if (letter == 'N')
5417 switch (code)
5418 {
5419 case EQ: fputs ("ne", file); break;
5420 case NE: fputs ("eq", file); break;
5421 case GT: fputs ("le", file); break;
5422 case GE: fputs ("lt", file); break;
5423 case LT: fputs ("ge", file); break;
5424 case LE: fputs ("gt", file); break;
5425 case GTU: fputs ("leu", file); break;
5426 case GEU: fputs ("ltu", file); break;
5427 case LTU: fputs ("geu", file); break;
5428 case LEU: fputs ("gtu", file); break;
5429 default:
5430 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5431 }
5432
5433 else if (letter == 'F')
5434 switch (code)
5435 {
5436 case EQ: fputs ("c1f", file); break;
5437 case NE: fputs ("c1t", file); break;
5438 default:
5439 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5440 }
5441
5442 else if (letter == 'W')
5443 switch (code)
5444 {
5445 case EQ: fputs ("c1t", file); break;
5446 case NE: fputs ("c1f", file); break;
5447 default:
5448 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5449 }
5450
5451 else if (letter == 'h')
5452 {
5453 if (GET_CODE (op) == HIGH)
5454 op = XEXP (op, 0);
5455
5456 print_operand_reloc (file, op, mips_hi_relocs);
5457 }
5458
5459 else if (letter == 'R')
5460 print_operand_reloc (file, op, mips_lo_relocs);
5461
5462 else if (letter == 'Y')
5463 {
5464 if (GET_CODE (op) == CONST_INT
5465 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5466 < ARRAY_SIZE (mips_fp_conditions)))
5467 fputs (mips_fp_conditions[INTVAL (op)], file);
5468 else
5469 output_operand_lossage ("invalid %%Y value");
5470 }
5471
5472 else if (letter == 'Z')
5473 {
5474 if (ISA_HAS_8CC)
5475 {
5476 print_operand (file, op, 0);
5477 fputc (',', file);
5478 }
5479 }
5480
5481 else if (letter == 'q')
5482 {
5483 int regnum;
5484
5485 if (code != REG)
5486 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5487
5488 regnum = REGNO (op);
5489 if (MD_REG_P (regnum))
5490 fprintf (file, "$ac0");
5491 else if (DSP_ACC_REG_P (regnum))
5492 fprintf (file, "$ac%c", reg_names[regnum][3]);
5493 else
5494 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5495 }
5496
5497 else if (code == REG || code == SUBREG)
5498 {
5499 register int regnum;
5500
5501 if (code == REG)
5502 regnum = REGNO (op);
5503 else
5504 regnum = true_regnum (op);
5505
5506 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5507 || (letter == 'L' && WORDS_BIG_ENDIAN)
5508 || letter == 'D')
5509 regnum++;
5510
5511 fprintf (file, "%s", reg_names[regnum]);
5512 }
5513
5514 else if (code == MEM)
5515 {
5516 if (letter == 'D')
5517 output_address (plus_constant (XEXP (op, 0), 4));
5518 else
5519 output_address (XEXP (op, 0));
5520 }
5521
5522 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5523 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5524
5525 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5526 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5527
5528 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5529 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5530
5531 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5532 fputs (reg_names[GP_REG_FIRST], file);
5533
5534 else if (letter == 'd' || letter == 'x' || letter == 'X')
5535 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5536
5537 else if (letter == 'T' || letter == 't')
5538 {
5539 int truth = (code == NE) == (letter == 'T');
5540 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5541 }
5542
5543 else if (CONST_GP_P (op))
5544 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5545
5546 else
5547 output_addr_const (file, op);
5548 }
5549
5550
5551 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5552 RELOCS is the array of relocations to use. */
5553
5554 static void
print_operand_reloc(FILE * file,rtx op,const char ** relocs)5555 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5556 {
5557 enum mips_symbol_type symbol_type;
5558 const char *p;
5559 rtx base;
5560 HOST_WIDE_INT offset;
5561
5562 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5563 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5564
5565 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5566 mips_split_const (op, &base, &offset);
5567 if (UNSPEC_ADDRESS_P (base))
5568 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5569
5570 fputs (relocs[symbol_type], file);
5571 output_addr_const (file, op);
5572 for (p = relocs[symbol_type]; *p != 0; p++)
5573 if (*p == '(')
5574 fputc (')', file);
5575 }
5576
5577 /* Output address operand X to FILE. */
5578
5579 void
print_operand_address(FILE * file,rtx x)5580 print_operand_address (FILE *file, rtx x)
5581 {
5582 struct mips_address_info addr;
5583
5584 if (mips_classify_address (&addr, x, word_mode, true))
5585 switch (addr.type)
5586 {
5587 case ADDRESS_REG:
5588 print_operand (file, addr.offset, 0);
5589 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5590 return;
5591
5592 case ADDRESS_LO_SUM:
5593 print_operand (file, addr.offset, 'R');
5594 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5595 return;
5596
5597 case ADDRESS_CONST_INT:
5598 output_addr_const (file, x);
5599 fprintf (file, "(%s)", reg_names[0]);
5600 return;
5601
5602 case ADDRESS_SYMBOLIC:
5603 output_addr_const (file, x);
5604 return;
5605 }
5606 gcc_unreachable ();
5607 }
5608
5609 /* When using assembler macros, keep track of all of small-data externs
5610 so that mips_file_end can emit the appropriate declarations for them.
5611
5612 In most cases it would be safe (though pointless) to emit .externs
5613 for other symbols too. One exception is when an object is within
5614 the -G limit but declared by the user to be in a section other
5615 than .sbss or .sdata. */
5616
5617 int
mips_output_external(FILE * file ATTRIBUTE_UNUSED,tree decl,const char * name)5618 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5619 {
5620 register struct extern_list *p;
5621
5622 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5623 {
5624 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5625 p->next = extern_head;
5626 p->name = name;
5627 p->size = int_size_in_bytes (TREE_TYPE (decl));
5628 extern_head = p;
5629 }
5630
5631 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5632 {
5633 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5634 p->next = extern_head;
5635 p->name = name;
5636 p->size = -1;
5637 extern_head = p;
5638 }
5639
5640 return 0;
5641 }
5642
5643 #if TARGET_IRIX
5644 static void
irix_output_external_libcall(rtx fun)5645 irix_output_external_libcall (rtx fun)
5646 {
5647 register struct extern_list *p;
5648
5649 if (mips_abi == ABI_32)
5650 {
5651 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5652 p->next = extern_head;
5653 p->name = XSTR (fun, 0);
5654 p->size = -1;
5655 extern_head = p;
5656 }
5657 }
5658 #endif
5659
5660 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5661 put out a MIPS ECOFF file and a stab. */
5662
5663 void
mips_output_filename(FILE * stream,const char * name)5664 mips_output_filename (FILE *stream, const char *name)
5665 {
5666
5667 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5668 directives. */
5669 if (write_symbols == DWARF2_DEBUG)
5670 return;
5671 else if (mips_output_filename_first_time)
5672 {
5673 mips_output_filename_first_time = 0;
5674 num_source_filenames += 1;
5675 current_function_file = name;
5676 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5677 output_quoted_string (stream, name);
5678 putc ('\n', stream);
5679 }
5680
5681 /* If we are emitting stabs, let dbxout.c handle this (except for
5682 the mips_output_filename_first_time case). */
5683 else if (write_symbols == DBX_DEBUG)
5684 return;
5685
5686 else if (name != current_function_file
5687 && strcmp (name, current_function_file) != 0)
5688 {
5689 num_source_filenames += 1;
5690 current_function_file = name;
5691 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5692 output_quoted_string (stream, name);
5693 putc ('\n', stream);
5694 }
5695 }
5696
5697 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5698 that should be written before the opening quote, such as "\t.ascii\t"
5699 for real string data or "\t# " for a comment. */
5700
5701 void
mips_output_ascii(FILE * stream,const char * string_param,size_t len,const char * prefix)5702 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5703 const char *prefix)
5704 {
5705 size_t i;
5706 int cur_pos = 17;
5707 register const unsigned char *string =
5708 (const unsigned char *)string_param;
5709
5710 fprintf (stream, "%s\"", prefix);
5711 for (i = 0; i < len; i++)
5712 {
5713 register int c = string[i];
5714
5715 if (ISPRINT (c))
5716 {
5717 if (c == '\\' || c == '\"')
5718 {
5719 putc ('\\', stream);
5720 cur_pos++;
5721 }
5722 putc (c, stream);
5723 cur_pos++;
5724 }
5725 else
5726 {
5727 fprintf (stream, "\\%03o", c);
5728 cur_pos += 4;
5729 }
5730
5731 if (cur_pos > 72 && i+1 < len)
5732 {
5733 cur_pos = 17;
5734 fprintf (stream, "\"\n%s\"", prefix);
5735 }
5736 }
5737 fprintf (stream, "\"\n");
5738 }
5739
5740 /* Implement TARGET_ASM_FILE_START. */
5741
5742 static void
mips_file_start(void)5743 mips_file_start (void)
5744 {
5745 default_file_start ();
5746
5747 if (!TARGET_IRIX)
5748 {
5749 /* Generate a special section to describe the ABI switches used to
5750 produce the resultant binary. This used to be done by the assembler
5751 setting bits in the ELF header's flags field, but we have run out of
5752 bits. GDB needs this information in order to be able to correctly
5753 debug these binaries. See the function mips_gdbarch_init() in
5754 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5755 causes unnecessary IRIX 6 ld warnings. */
5756 const char * abi_string = NULL;
5757
5758 switch (mips_abi)
5759 {
5760 case ABI_32: abi_string = "abi32"; break;
5761 case ABI_N32: abi_string = "abiN32"; break;
5762 case ABI_64: abi_string = "abi64"; break;
5763 case ABI_O64: abi_string = "abiO64"; break;
5764 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5765 default:
5766 gcc_unreachable ();
5767 }
5768 /* Note - we use fprintf directly rather than called named_section()
5769 because in this way we can avoid creating an allocated section. We
5770 do not want this section to take up any space in the running
5771 executable. */
5772 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5773
5774 /* There is no ELF header flag to distinguish long32 forms of the
5775 EABI from long64 forms. Emit a special section to help tools
5776 such as GDB. */
5777 if (mips_abi == ABI_EABI)
5778 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5779 TARGET_LONG64 ? 64 : 32);
5780
5781 /* Restore the default section. */
5782 fprintf (asm_out_file, "\t.previous\n");
5783 }
5784
5785 /* Generate the pseudo ops that System V.4 wants. */
5786 if (TARGET_ABICALLS)
5787 /* ??? but do not want this (or want pic0) if -non-shared? */
5788 fprintf (asm_out_file, "\t.abicalls\n");
5789
5790 if (TARGET_MIPS16)
5791 fprintf (asm_out_file, "\t.set\tmips16\n");
5792
5793 if (flag_verbose_asm)
5794 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5795 ASM_COMMENT_START,
5796 mips_section_threshold, mips_arch_info->name, mips_isa);
5797 }
5798
5799 #ifdef BSS_SECTION_ASM_OP
5800 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5801 in the use of sbss. */
5802
5803 void
mips_output_aligned_bss(FILE * stream,tree decl,const char * name,unsigned HOST_WIDE_INT size,int align)5804 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5805 unsigned HOST_WIDE_INT size, int align)
5806 {
5807 extern tree last_assemble_variable_decl;
5808
5809 if (mips_in_small_data_p (decl))
5810 named_section (0, ".sbss", 0);
5811 else
5812 bss_section ();
5813 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5814 last_assemble_variable_decl = decl;
5815 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5816 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5817 }
5818 #endif
5819
5820 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5821 .externs for any small-data variables that turned out to be external. */
5822
5823 static void
mips_file_end(void)5824 mips_file_end (void)
5825 {
5826 tree name_tree;
5827 struct extern_list *p;
5828
5829 if (extern_head)
5830 {
5831 fputs ("\n", asm_out_file);
5832
5833 for (p = extern_head; p != 0; p = p->next)
5834 {
5835 name_tree = get_identifier (p->name);
5836
5837 /* Positively ensure only one .extern for any given symbol. */
5838 if (!TREE_ASM_WRITTEN (name_tree)
5839 && TREE_SYMBOL_REFERENCED (name_tree))
5840 {
5841 TREE_ASM_WRITTEN (name_tree) = 1;
5842 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5843 `.global name .text' directive for every used but
5844 undefined function. If we don't, the linker may perform
5845 an optimization (skipping over the insns that set $gp)
5846 when it is unsafe. */
5847 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5848 {
5849 fputs ("\t.globl ", asm_out_file);
5850 assemble_name (asm_out_file, p->name);
5851 fputs (" .text\n", asm_out_file);
5852 }
5853 else
5854 {
5855 fputs ("\t.extern\t", asm_out_file);
5856 assemble_name (asm_out_file, p->name);
5857 fprintf (asm_out_file, ", %d\n", p->size);
5858 }
5859 }
5860 }
5861 }
5862 }
5863
5864 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5865 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5866
5867 void
mips_output_aligned_decl_common(FILE * stream,tree decl,const char * name,unsigned HOST_WIDE_INT size,unsigned int align)5868 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5869 unsigned HOST_WIDE_INT size,
5870 unsigned int align)
5871 {
5872 /* If the target wants uninitialized const declarations in
5873 .rdata then don't put them in .comm. */
5874 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5875 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5876 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5877 {
5878 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5879 targetm.asm_out.globalize_label (stream, name);
5880
5881 readonly_data_section ();
5882 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5883 mips_declare_object (stream, name, "",
5884 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5885 size);
5886 }
5887 else
5888 mips_declare_common_object (stream, name, "\n\t.comm\t",
5889 size, align, true);
5890 }
5891
5892 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5893 NAME is the name of the object and ALIGN is the required alignment
5894 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5895 alignment argument. */
5896
5897 void
mips_declare_common_object(FILE * stream,const char * name,const char * init_string,unsigned HOST_WIDE_INT size,unsigned int align,bool takes_alignment_p)5898 mips_declare_common_object (FILE *stream, const char *name,
5899 const char *init_string,
5900 unsigned HOST_WIDE_INT size,
5901 unsigned int align, bool takes_alignment_p)
5902 {
5903 if (!takes_alignment_p)
5904 {
5905 size += (align / BITS_PER_UNIT) - 1;
5906 size -= size % (align / BITS_PER_UNIT);
5907 mips_declare_object (stream, name, init_string,
5908 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
5909 }
5910 else
5911 mips_declare_object (stream, name, init_string,
5912 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
5913 size, align / BITS_PER_UNIT);
5914 }
5915
5916 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5917 macros, mark the symbol as written so that mips_file_end won't emit an
5918 .extern for it. STREAM is the output file, NAME is the name of the
5919 symbol, INIT_STRING is the string that should be written before the
5920 symbol and FINAL_STRING is the string that should be written after it.
5921 FINAL_STRING is a printf() format that consumes the remaining arguments. */
5922
5923 void
mips_declare_object(FILE * stream,const char * name,const char * init_string,const char * final_string,...)5924 mips_declare_object (FILE *stream, const char *name, const char *init_string,
5925 const char *final_string, ...)
5926 {
5927 va_list ap;
5928
5929 fputs (init_string, stream);
5930 assemble_name (stream, name);
5931 va_start (ap, final_string);
5932 vfprintf (stream, final_string, ap);
5933 va_end (ap);
5934
5935 if (!TARGET_EXPLICIT_RELOCS)
5936 {
5937 tree name_tree = get_identifier (name);
5938 TREE_ASM_WRITTEN (name_tree) = 1;
5939 }
5940 }
5941
5942 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
5943 extern int size_directive_output;
5944
5945 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
5946 definitions except that it uses mips_declare_object() to emit the label. */
5947
5948 void
mips_declare_object_name(FILE * stream,const char * name,tree decl ATTRIBUTE_UNUSED)5949 mips_declare_object_name (FILE *stream, const char *name,
5950 tree decl ATTRIBUTE_UNUSED)
5951 {
5952 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5953 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
5954 #endif
5955
5956 size_directive_output = 0;
5957 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
5958 {
5959 HOST_WIDE_INT size;
5960
5961 size_directive_output = 1;
5962 size = int_size_in_bytes (TREE_TYPE (decl));
5963 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5964 }
5965
5966 mips_declare_object (stream, name, "", ":\n");
5967 }
5968
5969 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
5970
5971 void
mips_finish_declare_object(FILE * stream,tree decl,int top_level,int at_end)5972 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
5973 {
5974 const char *name;
5975
5976 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
5977 if (!flag_inhibit_size_directive
5978 && DECL_SIZE (decl) != 0
5979 && !at_end && top_level
5980 && DECL_INITIAL (decl) == error_mark_node
5981 && !size_directive_output)
5982 {
5983 HOST_WIDE_INT size;
5984
5985 size_directive_output = 1;
5986 size = int_size_in_bytes (TREE_TYPE (decl));
5987 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5988 }
5989 }
5990 #endif
5991
5992 /* Return true if X is a small data address that can be rewritten
5993 as a LO_SUM. */
5994
5995 static bool
mips_rewrite_small_data_p(rtx x)5996 mips_rewrite_small_data_p (rtx x)
5997 {
5998 enum mips_symbol_type symbol_type;
5999
6000 return (TARGET_EXPLICIT_RELOCS
6001 && mips_symbolic_constant_p (x, &symbol_type)
6002 && symbol_type == SYMBOL_SMALL_DATA);
6003 }
6004
6005
6006 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6007
6008 static int
mips_small_data_pattern_1(rtx * loc,void * data ATTRIBUTE_UNUSED)6009 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6010 {
6011 if (GET_CODE (*loc) == LO_SUM)
6012 return -1;
6013
6014 return mips_rewrite_small_data_p (*loc);
6015 }
6016
6017 /* Return true if OP refers to small data symbols directly, not through
6018 a LO_SUM. */
6019
6020 bool
mips_small_data_pattern_p(rtx op)6021 mips_small_data_pattern_p (rtx op)
6022 {
6023 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6024 }
6025
6026 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6027
6028 static int
mips_rewrite_small_data_1(rtx * loc,void * data ATTRIBUTE_UNUSED)6029 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6030 {
6031 if (mips_rewrite_small_data_p (*loc))
6032 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6033
6034 if (GET_CODE (*loc) == LO_SUM)
6035 return -1;
6036
6037 return 0;
6038 }
6039
6040 /* If possible, rewrite OP so that it refers to small data using
6041 explicit relocations. */
6042
6043 rtx
mips_rewrite_small_data(rtx op)6044 mips_rewrite_small_data (rtx op)
6045 {
6046 op = copy_insn (op);
6047 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6048 return op;
6049 }
6050
6051 /* Return true if the current function has an insn that implicitly
6052 refers to $gp. */
6053
6054 static bool
mips_function_has_gp_insn(void)6055 mips_function_has_gp_insn (void)
6056 {
6057 /* Don't bother rechecking if we found one last time. */
6058 if (!cfun->machine->has_gp_insn_p)
6059 {
6060 rtx insn;
6061
6062 push_topmost_sequence ();
6063 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6064 if (INSN_P (insn)
6065 && GET_CODE (PATTERN (insn)) != USE
6066 && GET_CODE (PATTERN (insn)) != CLOBBER
6067 && (get_attr_got (insn) != GOT_UNSET
6068 || small_data_pattern (PATTERN (insn), VOIDmode)))
6069 break;
6070 pop_topmost_sequence ();
6071
6072 cfun->machine->has_gp_insn_p = (insn != 0);
6073 }
6074 return cfun->machine->has_gp_insn_p;
6075 }
6076
6077
6078 /* Return the register that should be used as the global pointer
6079 within this function. Return 0 if the function doesn't need
6080 a global pointer. */
6081
6082 static unsigned int
mips_global_pointer(void)6083 mips_global_pointer (void)
6084 {
6085 unsigned int regno;
6086
6087 /* $gp is always available in non-abicalls code. */
6088 if (!TARGET_ABICALLS)
6089 return GLOBAL_POINTER_REGNUM;
6090
6091 /* We must always provide $gp when it is used implicitly. */
6092 if (!TARGET_EXPLICIT_RELOCS)
6093 return GLOBAL_POINTER_REGNUM;
6094
6095 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6096 a valid gp. */
6097 if (current_function_profile)
6098 return GLOBAL_POINTER_REGNUM;
6099
6100 /* If the function has a nonlocal goto, $gp must hold the correct
6101 global pointer for the target function. */
6102 if (current_function_has_nonlocal_goto)
6103 return GLOBAL_POINTER_REGNUM;
6104
6105 /* If the gp is never referenced, there's no need to initialize it.
6106 Note that reload can sometimes introduce constant pool references
6107 into a function that otherwise didn't need them. For example,
6108 suppose we have an instruction like:
6109
6110 (set (reg:DF R1) (float:DF (reg:SI R2)))
6111
6112 If R2 turns out to be constant such as 1, the instruction may have a
6113 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6114 using this constant if R2 doesn't get allocated to a register.
6115
6116 In cases like these, reload will have added the constant to the pool
6117 but no instruction will yet refer to it. */
6118 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6119 && !current_function_uses_const_pool
6120 && !mips_function_has_gp_insn ())
6121 return 0;
6122
6123 /* We need a global pointer, but perhaps we can use a call-clobbered
6124 register instead of $gp. */
6125 if (TARGET_NEWABI && current_function_is_leaf)
6126 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6127 if (!regs_ever_live[regno]
6128 && call_used_regs[regno]
6129 && !fixed_regs[regno]
6130 && regno != PIC_FUNCTION_ADDR_REGNUM)
6131 return regno;
6132
6133 return GLOBAL_POINTER_REGNUM;
6134 }
6135
6136
6137 /* Return true if the current function must save REGNO. */
6138
6139 static bool
mips_save_reg_p(unsigned int regno)6140 mips_save_reg_p (unsigned int regno)
6141 {
6142 /* We only need to save $gp for NewABI PIC. */
6143 if (regno == GLOBAL_POINTER_REGNUM)
6144 return (TARGET_ABICALLS && TARGET_NEWABI
6145 && cfun->machine->global_pointer == regno);
6146
6147 /* Check call-saved registers. */
6148 if (regs_ever_live[regno] && !call_used_regs[regno])
6149 return true;
6150
6151 /* We need to save the old frame pointer before setting up a new one. */
6152 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6153 return true;
6154
6155 /* We need to save the incoming return address if it is ever clobbered
6156 within the function. */
6157 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6158 return true;
6159
6160 if (TARGET_MIPS16)
6161 {
6162 tree return_type;
6163
6164 return_type = DECL_RESULT (current_function_decl);
6165
6166 /* $18 is a special case in mips16 code. It may be used to call
6167 a function which returns a floating point value, but it is
6168 marked in call_used_regs. */
6169 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6170 return true;
6171
6172 /* $31 is also a special case. It will be used to copy a return
6173 value into the floating point registers if the return value is
6174 floating point. */
6175 if (regno == GP_REG_FIRST + 31
6176 && mips16_hard_float
6177 && !aggregate_value_p (return_type, current_function_decl)
6178 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6179 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6180 return true;
6181 }
6182
6183 return false;
6184 }
6185
6186
6187 /* Return the bytes needed to compute the frame pointer from the current
6188 stack pointer. SIZE is the size (in bytes) of the local variables.
6189
6190 MIPS stack frames look like:
6191
6192 Before call After call
6193 +-----------------------+ +-----------------------+
6194 high | | | |
6195 mem. | | | |
6196 | caller's temps. | | caller's temps. |
6197 | | | |
6198 +-----------------------+ +-----------------------+
6199 | | | |
6200 | arguments on stack. | | arguments on stack. |
6201 | | | |
6202 +-----------------------+ +-----------------------+
6203 | 4 words to save | | 4 words to save |
6204 | arguments passed | | arguments passed |
6205 | in registers, even | | in registers, even |
6206 SP->| if not passed. | VFP->| if not passed. |
6207 +-----------------------+ +-----------------------+
6208 | |
6209 | fp register save |
6210 | |
6211 +-----------------------+
6212 | |
6213 | gp register save |
6214 | |
6215 +-----------------------+
6216 | |
6217 | local variables |
6218 | |
6219 +-----------------------+
6220 | |
6221 | alloca allocations |
6222 | |
6223 +-----------------------+
6224 | |
6225 | GP save for V.4 abi |
6226 | |
6227 +-----------------------+
6228 | |
6229 | arguments on stack |
6230 | |
6231 +-----------------------+
6232 | 4 words to save |
6233 | arguments passed |
6234 | in registers, even |
6235 low SP->| if not passed. |
6236 memory +-----------------------+
6237
6238 */
6239
6240 HOST_WIDE_INT
compute_frame_size(HOST_WIDE_INT size)6241 compute_frame_size (HOST_WIDE_INT size)
6242 {
6243 unsigned int regno;
6244 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6245 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6246 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6247 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6248 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6249 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6250 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6251 unsigned int mask; /* mask of saved gp registers */
6252 unsigned int fmask; /* mask of saved fp registers */
6253
6254 cfun->machine->global_pointer = mips_global_pointer ();
6255
6256 gp_reg_size = 0;
6257 fp_reg_size = 0;
6258 mask = 0;
6259 fmask = 0;
6260 var_size = MIPS_STACK_ALIGN (size);
6261 args_size = current_function_outgoing_args_size;
6262 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6263
6264 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6265 functions. If the function has local variables, we're committed
6266 to allocating it anyway. Otherwise reclaim it here. */
6267 if (var_size == 0 && current_function_is_leaf)
6268 cprestore_size = args_size = 0;
6269
6270 /* The MIPS 3.0 linker does not like functions that dynamically
6271 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6272 looks like we are trying to create a second frame pointer to the
6273 function, so allocate some stack space to make it happy. */
6274
6275 if (args_size == 0 && current_function_calls_alloca)
6276 args_size = 4 * UNITS_PER_WORD;
6277
6278 total_size = var_size + args_size + cprestore_size;
6279
6280 /* Calculate space needed for gp registers. */
6281 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6282 if (mips_save_reg_p (regno))
6283 {
6284 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6285 mask |= 1 << (regno - GP_REG_FIRST);
6286 }
6287
6288 /* We need to restore these for the handler. */
6289 if (current_function_calls_eh_return)
6290 {
6291 unsigned int i;
6292 for (i = 0; ; ++i)
6293 {
6294 regno = EH_RETURN_DATA_REGNO (i);
6295 if (regno == INVALID_REGNUM)
6296 break;
6297 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6298 mask |= 1 << (regno - GP_REG_FIRST);
6299 }
6300 }
6301
6302 /* This loop must iterate over the same space as its companion in
6303 save_restore_insns. */
6304 for (regno = (FP_REG_LAST - FP_INC + 1);
6305 regno >= FP_REG_FIRST;
6306 regno -= FP_INC)
6307 {
6308 if (mips_save_reg_p (regno))
6309 {
6310 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6311 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6312 }
6313 }
6314
6315 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6316 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6317
6318 /* Add in the space required for saving incoming register arguments. */
6319 total_size += current_function_pretend_args_size;
6320 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6321
6322 /* Save other computed information. */
6323 cfun->machine->frame.total_size = total_size;
6324 cfun->machine->frame.var_size = var_size;
6325 cfun->machine->frame.args_size = args_size;
6326 cfun->machine->frame.cprestore_size = cprestore_size;
6327 cfun->machine->frame.gp_reg_size = gp_reg_size;
6328 cfun->machine->frame.fp_reg_size = fp_reg_size;
6329 cfun->machine->frame.mask = mask;
6330 cfun->machine->frame.fmask = fmask;
6331 cfun->machine->frame.initialized = reload_completed;
6332 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6333 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6334
6335 if (mask)
6336 {
6337 HOST_WIDE_INT offset;
6338
6339 offset = (args_size + cprestore_size + var_size
6340 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6341 cfun->machine->frame.gp_sp_offset = offset;
6342 cfun->machine->frame.gp_save_offset = offset - total_size;
6343 }
6344 else
6345 {
6346 cfun->machine->frame.gp_sp_offset = 0;
6347 cfun->machine->frame.gp_save_offset = 0;
6348 }
6349
6350 if (fmask)
6351 {
6352 HOST_WIDE_INT offset;
6353
6354 offset = (args_size + cprestore_size + var_size
6355 + gp_reg_rounded + fp_reg_size
6356 - FP_INC * UNITS_PER_FPREG);
6357 cfun->machine->frame.fp_sp_offset = offset;
6358 cfun->machine->frame.fp_save_offset = offset - total_size;
6359 }
6360 else
6361 {
6362 cfun->machine->frame.fp_sp_offset = 0;
6363 cfun->machine->frame.fp_save_offset = 0;
6364 }
6365
6366 /* Ok, we're done. */
6367 return total_size;
6368 }
6369
6370 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6371 pointer or argument pointer. TO is either the stack pointer or
6372 hard frame pointer. */
6373
6374 HOST_WIDE_INT
mips_initial_elimination_offset(int from,int to)6375 mips_initial_elimination_offset (int from, int to)
6376 {
6377 HOST_WIDE_INT offset;
6378
6379 compute_frame_size (get_frame_size ());
6380
6381 /* Set OFFSET to the offset from the stack pointer. */
6382 switch (from)
6383 {
6384 case FRAME_POINTER_REGNUM:
6385 offset = 0;
6386 break;
6387
6388 case ARG_POINTER_REGNUM:
6389 offset = (cfun->machine->frame.total_size
6390 - current_function_pretend_args_size);
6391 break;
6392
6393 default:
6394 gcc_unreachable ();
6395 }
6396
6397 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6398 offset -= cfun->machine->frame.args_size;
6399
6400 return offset;
6401 }
6402
6403 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6404 back to a previous frame. */
6405 rtx
mips_return_addr(int count,rtx frame ATTRIBUTE_UNUSED)6406 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6407 {
6408 if (count != 0)
6409 return const0_rtx;
6410
6411 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6412 }
6413
6414 /* Use FN to save or restore register REGNO. MODE is the register's
6415 mode and OFFSET is the offset of its save slot from the current
6416 stack pointer. */
6417
6418 static void
mips_save_restore_reg(enum machine_mode mode,int regno,HOST_WIDE_INT offset,mips_save_restore_fn fn)6419 mips_save_restore_reg (enum machine_mode mode, int regno,
6420 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6421 {
6422 rtx mem;
6423
6424 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6425
6426 fn (gen_rtx_REG (mode, regno), mem);
6427 }
6428
6429
6430 /* Call FN for each register that is saved by the current function.
6431 SP_OFFSET is the offset of the current stack pointer from the start
6432 of the frame. */
6433
6434 static void
mips_for_each_saved_reg(HOST_WIDE_INT sp_offset,mips_save_restore_fn fn)6435 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6436 {
6437 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6438
6439 enum machine_mode fpr_mode;
6440 HOST_WIDE_INT offset;
6441 int regno;
6442
6443 /* Save registers starting from high to low. The debuggers prefer at least
6444 the return register be stored at func+4, and also it allows us not to
6445 need a nop in the epilog if at least one register is reloaded in
6446 addition to return address. */
6447 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6448 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6449 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6450 {
6451 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6452 offset -= GET_MODE_SIZE (gpr_mode);
6453 }
6454
6455 /* This loop must iterate over the same space as its companion in
6456 compute_frame_size. */
6457 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6458 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6459 for (regno = (FP_REG_LAST - FP_INC + 1);
6460 regno >= FP_REG_FIRST;
6461 regno -= FP_INC)
6462 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6463 {
6464 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6465 offset -= GET_MODE_SIZE (fpr_mode);
6466 }
6467 #undef BITSET_P
6468 }
6469
6470 /* If we're generating n32 or n64 abicalls, and the current function
6471 does not use $28 as its global pointer, emit a cplocal directive.
6472 Use pic_offset_table_rtx as the argument to the directive. */
6473
6474 static void
mips_output_cplocal(void)6475 mips_output_cplocal (void)
6476 {
6477 if (!TARGET_EXPLICIT_RELOCS
6478 && cfun->machine->global_pointer > 0
6479 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6480 output_asm_insn (".cplocal %+", 0);
6481 }
6482
6483 /* If we're generating n32 or n64 abicalls, emit instructions
6484 to set up the global pointer. */
6485
6486 static void
mips_emit_loadgp(void)6487 mips_emit_loadgp (void)
6488 {
6489 if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
6490 {
6491 rtx addr, offset, incoming_address;
6492
6493 addr = XEXP (DECL_RTL (current_function_decl), 0);
6494 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6495 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6496 emit_insn (gen_loadgp (offset, incoming_address));
6497 if (!TARGET_EXPLICIT_RELOCS)
6498 emit_insn (gen_loadgp_blockage ());
6499 }
6500 }
6501
6502 /* Set up the stack and frame (if desired) for the function. */
6503
6504 static void
mips_output_function_prologue(FILE * file,HOST_WIDE_INT size ATTRIBUTE_UNUSED)6505 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6506 {
6507 const char *fnname;
6508 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6509
6510 #ifdef SDB_DEBUGGING_INFO
6511 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6512 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6513 #endif
6514
6515 /* In mips16 mode, we may need to generate a 32 bit to handle
6516 floating point arguments. The linker will arrange for any 32 bit
6517 functions to call this stub, which will then jump to the 16 bit
6518 function proper. */
6519 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6520 && current_function_args_info.fp_code != 0)
6521 build_mips16_function_stub (file);
6522
6523 if (!FUNCTION_NAME_ALREADY_DECLARED)
6524 {
6525 /* Get the function name the same way that toplev.c does before calling
6526 assemble_start_function. This is needed so that the name used here
6527 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6528 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6529
6530 if (!flag_inhibit_size_directive)
6531 {
6532 fputs ("\t.ent\t", file);
6533 assemble_name (file, fnname);
6534 fputs ("\n", file);
6535 }
6536
6537 assemble_name (file, fnname);
6538 fputs (":\n", file);
6539 }
6540
6541 /* Stop mips_file_end from treating this function as external. */
6542 if (TARGET_IRIX && mips_abi == ABI_32)
6543 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
6544
6545 if (!flag_inhibit_size_directive)
6546 {
6547 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6548 fprintf (file,
6549 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6550 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6551 ", args= " HOST_WIDE_INT_PRINT_DEC
6552 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6553 (reg_names[(frame_pointer_needed)
6554 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6555 ((frame_pointer_needed && TARGET_MIPS16)
6556 ? tsize - cfun->machine->frame.args_size
6557 : tsize),
6558 reg_names[GP_REG_FIRST + 31],
6559 cfun->machine->frame.var_size,
6560 cfun->machine->frame.num_gp,
6561 cfun->machine->frame.num_fp,
6562 cfun->machine->frame.args_size,
6563 cfun->machine->frame.cprestore_size);
6564
6565 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6566 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6567 cfun->machine->frame.mask,
6568 cfun->machine->frame.gp_save_offset);
6569 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6570 cfun->machine->frame.fmask,
6571 cfun->machine->frame.fp_save_offset);
6572
6573 /* Require:
6574 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6575 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6576 }
6577
6578 if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
6579 {
6580 /* Handle the initialization of $gp for SVR4 PIC. */
6581 if (!cfun->machine->all_noreorder_p)
6582 output_asm_insn ("%(.cpload\t%^%)", 0);
6583 else
6584 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6585 }
6586 else if (cfun->machine->all_noreorder_p)
6587 output_asm_insn ("%(%<", 0);
6588
6589 /* Tell the assembler which register we're using as the global
6590 pointer. This is needed for thunks, since they can use either
6591 explicit relocs or assembler macros. */
6592 mips_output_cplocal ();
6593 }
6594
6595 /* Make the last instruction frame related and note that it performs
6596 the operation described by FRAME_PATTERN. */
6597
6598 static void
mips_set_frame_expr(rtx frame_pattern)6599 mips_set_frame_expr (rtx frame_pattern)
6600 {
6601 rtx insn;
6602
6603 insn = get_last_insn ();
6604 RTX_FRAME_RELATED_P (insn) = 1;
6605 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6606 frame_pattern,
6607 REG_NOTES (insn));
6608 }
6609
6610
6611 /* Return a frame-related rtx that stores REG at MEM.
6612 REG must be a single register. */
6613
6614 static rtx
mips_frame_set(rtx mem,rtx reg)6615 mips_frame_set (rtx mem, rtx reg)
6616 {
6617 rtx set;
6618
6619 /* If we're saving the return address register and the dwarf return
6620 address column differs from the hard register number, adjust the
6621 note reg to refer to the former. */
6622 if (REGNO (reg) == GP_REG_FIRST + 31
6623 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
6624 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
6625
6626 set = gen_rtx_SET (VOIDmode, mem, reg);
6627 RTX_FRAME_RELATED_P (set) = 1;
6628
6629 return set;
6630 }
6631
6632
6633 /* Save register REG to MEM. Make the instruction frame-related. */
6634
6635 static void
mips_save_reg(rtx reg,rtx mem)6636 mips_save_reg (rtx reg, rtx mem)
6637 {
6638 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6639 {
6640 rtx x1, x2;
6641
6642 if (mips_split_64bit_move_p (mem, reg))
6643 mips_split_64bit_move (mem, reg);
6644 else
6645 emit_move_insn (mem, reg);
6646
6647 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6648 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6649 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6650 }
6651 else
6652 {
6653 if (TARGET_MIPS16
6654 && REGNO (reg) != GP_REG_FIRST + 31
6655 && !M16_REG_P (REGNO (reg)))
6656 {
6657 /* Save a non-mips16 register by moving it through a temporary.
6658 We don't need to do this for $31 since there's a special
6659 instruction for it. */
6660 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6661 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6662 }
6663 else
6664 emit_move_insn (mem, reg);
6665
6666 mips_set_frame_expr (mips_frame_set (mem, reg));
6667 }
6668 }
6669
6670
6671 /* Expand the prologue into a bunch of separate insns. */
6672
6673 void
mips_expand_prologue(void)6674 mips_expand_prologue (void)
6675 {
6676 HOST_WIDE_INT size;
6677
6678 if (cfun->machine->global_pointer > 0)
6679 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6680
6681 size = compute_frame_size (get_frame_size ());
6682
6683 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6684 bytes beforehand; this is enough to cover the register save area
6685 without going out of range. */
6686 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6687 {
6688 HOST_WIDE_INT step1;
6689
6690 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6691 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6692 stack_pointer_rtx,
6693 GEN_INT (-step1)))) = 1;
6694 size -= step1;
6695 mips_for_each_saved_reg (size, mips_save_reg);
6696 }
6697
6698 /* Allocate the rest of the frame. */
6699 if (size > 0)
6700 {
6701 if (SMALL_OPERAND (-size))
6702 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6703 stack_pointer_rtx,
6704 GEN_INT (-size)))) = 1;
6705 else
6706 {
6707 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6708 if (TARGET_MIPS16)
6709 {
6710 /* There are no instructions to add or subtract registers
6711 from the stack pointer, so use the frame pointer as a
6712 temporary. We should always be using a frame pointer
6713 in this case anyway. */
6714 gcc_assert (frame_pointer_needed);
6715 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6716 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6717 hard_frame_pointer_rtx,
6718 MIPS_PROLOGUE_TEMP (Pmode)));
6719 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6720 }
6721 else
6722 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6723 stack_pointer_rtx,
6724 MIPS_PROLOGUE_TEMP (Pmode)));
6725
6726 /* Describe the combined effect of the previous instructions. */
6727 mips_set_frame_expr
6728 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6729 plus_constant (stack_pointer_rtx, -size)));
6730 }
6731 }
6732
6733 /* Set up the frame pointer, if we're using one. In mips16 code,
6734 we point the frame pointer ahead of the outgoing argument area.
6735 This should allow more variables & incoming arguments to be
6736 accessed with unextended instructions. */
6737 if (frame_pointer_needed)
6738 {
6739 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6740 {
6741 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6742 if (SMALL_OPERAND (cfun->machine->frame.args_size))
6743 RTX_FRAME_RELATED_P
6744 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6745 stack_pointer_rtx,
6746 offset))) = 1;
6747 else
6748 {
6749 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
6750 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6751 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6752 hard_frame_pointer_rtx,
6753 MIPS_PROLOGUE_TEMP (Pmode)));
6754 mips_set_frame_expr
6755 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
6756 plus_constant (stack_pointer_rtx,
6757 cfun->machine->frame.args_size)));
6758 }
6759 }
6760 else
6761 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6762 stack_pointer_rtx)) = 1;
6763 }
6764
6765 /* If generating o32/o64 abicalls, save $gp on the stack. */
6766 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6767 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6768
6769 mips_emit_loadgp ();
6770
6771 /* If we are profiling, make sure no instructions are scheduled before
6772 the call to mcount. */
6773
6774 if (current_function_profile)
6775 emit_insn (gen_blockage ());
6776 }
6777
6778 /* Do any necessary cleanup after a function to restore stack, frame,
6779 and regs. */
6780
6781 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6782
6783 static void
mips_output_function_epilogue(FILE * file ATTRIBUTE_UNUSED,HOST_WIDE_INT size ATTRIBUTE_UNUSED)6784 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6785 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6786 {
6787 /* Reinstate the normal $gp. */
6788 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6789 mips_output_cplocal ();
6790
6791 if (cfun->machine->all_noreorder_p)
6792 {
6793 /* Avoid using %>%) since it adds excess whitespace. */
6794 output_asm_insn (".set\tmacro", 0);
6795 output_asm_insn (".set\treorder", 0);
6796 set_noreorder = set_nomacro = 0;
6797 }
6798
6799 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6800 {
6801 const char *fnname;
6802
6803 /* Get the function name the same way that toplev.c does before calling
6804 assemble_start_function. This is needed so that the name used here
6805 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6806 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6807 fputs ("\t.end\t", file);
6808 assemble_name (file, fnname);
6809 fputs ("\n", file);
6810 }
6811 }
6812
6813 /* Emit instructions to restore register REG from slot MEM. */
6814
6815 static void
mips_restore_reg(rtx reg,rtx mem)6816 mips_restore_reg (rtx reg, rtx mem)
6817 {
6818 /* There's no mips16 instruction to load $31 directly. Load into
6819 $7 instead and adjust the return insn appropriately. */
6820 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6821 reg = gen_rtx_REG (GET_MODE (reg), 7);
6822
6823 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6824 {
6825 /* Can't restore directly; move through a temporary. */
6826 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6827 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6828 }
6829 else
6830 emit_move_insn (reg, mem);
6831 }
6832
6833
6834 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6835 if this epilogue precedes a sibling call, false if it is for a normal
6836 "epilogue" pattern. */
6837
6838 void
mips_expand_epilogue(int sibcall_p)6839 mips_expand_epilogue (int sibcall_p)
6840 {
6841 HOST_WIDE_INT step1, step2;
6842 rtx base, target;
6843
6844 if (!sibcall_p && mips_can_use_return_insn ())
6845 {
6846 emit_jump_insn (gen_return ());
6847 return;
6848 }
6849
6850 /* Split the frame into two. STEP1 is the amount of stack we should
6851 deallocate before restoring the registers. STEP2 is the amount we
6852 should deallocate afterwards.
6853
6854 Start off by assuming that no registers need to be restored. */
6855 step1 = cfun->machine->frame.total_size;
6856 step2 = 0;
6857
6858 /* Work out which register holds the frame address. Account for the
6859 frame pointer offset used by mips16 code. */
6860 if (!frame_pointer_needed)
6861 base = stack_pointer_rtx;
6862 else
6863 {
6864 base = hard_frame_pointer_rtx;
6865 if (TARGET_MIPS16)
6866 step1 -= cfun->machine->frame.args_size;
6867 }
6868
6869 /* If we need to restore registers, deallocate as much stack as
6870 possible in the second step without going out of range. */
6871 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6872 {
6873 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
6874 step1 -= step2;
6875 }
6876
6877 /* Set TARGET to BASE + STEP1. */
6878 target = base;
6879 if (step1 > 0)
6880 {
6881 rtx adjust;
6882
6883 /* Get an rtx for STEP1 that we can add to BASE. */
6884 adjust = GEN_INT (step1);
6885 if (!SMALL_OPERAND (step1))
6886 {
6887 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
6888 adjust = MIPS_EPILOGUE_TEMP (Pmode);
6889 }
6890
6891 /* Normal mode code can copy the result straight into $sp. */
6892 if (!TARGET_MIPS16)
6893 target = stack_pointer_rtx;
6894
6895 emit_insn (gen_add3_insn (target, base, adjust));
6896 }
6897
6898 /* Copy TARGET into the stack pointer. */
6899 if (target != stack_pointer_rtx)
6900 emit_move_insn (stack_pointer_rtx, target);
6901
6902 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6903 implicitly used by all SYMBOL_REFs. We must emit a blockage
6904 insn before restoring it. */
6905 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
6906 emit_insn (gen_blockage ());
6907
6908 /* Restore the registers. */
6909 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
6910 mips_restore_reg);
6911
6912 /* Deallocate the final bit of the frame. */
6913 if (step2 > 0)
6914 emit_insn (gen_add3_insn (stack_pointer_rtx,
6915 stack_pointer_rtx,
6916 GEN_INT (step2)));
6917
6918 /* Add in the __builtin_eh_return stack adjustment. We need to
6919 use a temporary in mips16 code. */
6920 if (current_function_calls_eh_return)
6921 {
6922 if (TARGET_MIPS16)
6923 {
6924 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
6925 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
6926 MIPS_EPILOGUE_TEMP (Pmode),
6927 EH_RETURN_STACKADJ_RTX));
6928 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
6929 }
6930 else
6931 emit_insn (gen_add3_insn (stack_pointer_rtx,
6932 stack_pointer_rtx,
6933 EH_RETURN_STACKADJ_RTX));
6934 }
6935
6936 if (!sibcall_p)
6937 {
6938 /* The mips16 loads the return address into $7, not $31. */
6939 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
6940 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6941 GP_REG_FIRST + 7)));
6942 else
6943 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6944 GP_REG_FIRST + 31)));
6945 }
6946 }
6947
6948 /* Return nonzero if this function is known to have a null epilogue.
6949 This allows the optimizer to omit jumps to jumps if no stack
6950 was created. */
6951
6952 int
mips_can_use_return_insn(void)6953 mips_can_use_return_insn (void)
6954 {
6955 tree return_type;
6956
6957 if (! reload_completed)
6958 return 0;
6959
6960 if (regs_ever_live[31] || current_function_profile)
6961 return 0;
6962
6963 return_type = DECL_RESULT (current_function_decl);
6964
6965 /* In mips16 mode, a function which returns a floating point value
6966 needs to arrange to copy the return value into the floating point
6967 registers. */
6968 if (TARGET_MIPS16
6969 && mips16_hard_float
6970 && ! aggregate_value_p (return_type, current_function_decl)
6971 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6972 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6973 return 0;
6974
6975 if (cfun->machine->frame.initialized)
6976 return cfun->machine->frame.total_size == 0;
6977
6978 return compute_frame_size (get_frame_size ()) == 0;
6979 }
6980
6981 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
6982 in order to avoid duplicating too much logic from elsewhere. */
6983
6984 static void
mips_output_mi_thunk(FILE * file,tree thunk_fndecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset,tree function)6985 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
6986 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
6987 tree function)
6988 {
6989 rtx this, temp1, temp2, insn, fnaddr;
6990
6991 /* Pretend to be a post-reload pass while generating rtl. */
6992 no_new_pseudos = 1;
6993 reload_completed = 1;
6994 reset_block_changes ();
6995
6996 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
6997 for TARGET_NEWABI since the latter is a call-saved register. */
6998 if (TARGET_ABICALLS)
6999 cfun->machine->global_pointer
7000 = REGNO (pic_offset_table_rtx)
7001 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
7002
7003 /* Set up the global pointer for n32 or n64 abicalls. */
7004 mips_emit_loadgp ();
7005
7006 /* We need two temporary registers in some cases. */
7007 temp1 = gen_rtx_REG (Pmode, 2);
7008 temp2 = gen_rtx_REG (Pmode, 3);
7009
7010 /* Find out which register contains the "this" pointer. */
7011 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7012 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7013 else
7014 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7015
7016 /* Add DELTA to THIS. */
7017 if (delta != 0)
7018 {
7019 rtx offset = GEN_INT (delta);
7020 if (!SMALL_OPERAND (delta))
7021 {
7022 emit_move_insn (temp1, offset);
7023 offset = temp1;
7024 }
7025 emit_insn (gen_add3_insn (this, this, offset));
7026 }
7027
7028 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7029 if (vcall_offset != 0)
7030 {
7031 rtx addr;
7032
7033 /* Set TEMP1 to *THIS. */
7034 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7035
7036 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7037 addr = mips_add_offset (temp2, temp1, vcall_offset);
7038
7039 /* Load the offset and add it to THIS. */
7040 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7041 emit_insn (gen_add3_insn (this, this, temp1));
7042 }
7043
7044 /* Jump to the target function. Use a sibcall if direct jumps are
7045 allowed, otherwise load the address into a register first. */
7046 fnaddr = XEXP (DECL_RTL (function), 0);
7047 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7048 {
7049 /* This is messy. gas treats "la $25,foo" as part of a call
7050 sequence and may allow a global "foo" to be lazily bound.
7051 The general move patterns therefore reject this combination.
7052
7053 In this context, lazy binding would actually be OK for o32 and o64,
7054 but it's still wrong for n32 and n64; see mips_load_call_address.
7055 We must therefore load the address via a temporary register if
7056 mips_dangerous_for_la25_p.
7057
7058 If we jump to the temporary register rather than $25, the assembler
7059 can use the move insn to fill the jump's delay slot. */
7060 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7061 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7062 mips_load_call_address (temp1, fnaddr, true);
7063
7064 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7065 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7066 emit_jump_insn (gen_indirect_jump (temp1));
7067 }
7068 else
7069 {
7070 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7071 SIBLING_CALL_P (insn) = 1;
7072 }
7073
7074 /* Run just enough of rest_of_compilation. This sequence was
7075 "borrowed" from alpha.c. */
7076 insn = get_insns ();
7077 insn_locators_initialize ();
7078 split_all_insns_noflow ();
7079 if (TARGET_MIPS16)
7080 mips16_lay_out_constants ();
7081 shorten_branches (insn);
7082 final_start_function (insn, file, 1);
7083 final (insn, file, 1);
7084 final_end_function ();
7085
7086 /* Clean up the vars set above. Note that final_end_function resets
7087 the global pointer for us. */
7088 reload_completed = 0;
7089 no_new_pseudos = 0;
7090 }
7091
7092 /* Returns nonzero if X contains a SYMBOL_REF. */
7093
7094 static int
symbolic_expression_p(rtx x)7095 symbolic_expression_p (rtx x)
7096 {
7097 if (GET_CODE (x) == SYMBOL_REF)
7098 return 1;
7099
7100 if (GET_CODE (x) == CONST)
7101 return symbolic_expression_p (XEXP (x, 0));
7102
7103 if (UNARY_P (x))
7104 return symbolic_expression_p (XEXP (x, 0));
7105
7106 if (ARITHMETIC_P (x))
7107 return (symbolic_expression_p (XEXP (x, 0))
7108 || symbolic_expression_p (XEXP (x, 1)));
7109
7110 return 0;
7111 }
7112
7113 /* Choose the section to use for the constant rtx expression X that has
7114 mode MODE. */
7115
7116 static void
mips_select_rtx_section(enum machine_mode mode,rtx x,unsigned HOST_WIDE_INT align)7117 mips_select_rtx_section (enum machine_mode mode, rtx x,
7118 unsigned HOST_WIDE_INT align)
7119 {
7120 if (TARGET_MIPS16)
7121 {
7122 /* In mips16 mode, the constant table always goes in the same section
7123 as the function, so that constants can be loaded using PC relative
7124 addressing. */
7125 function_section (current_function_decl);
7126 }
7127 else if (TARGET_EMBEDDED_DATA)
7128 {
7129 /* For embedded applications, always put constants in read-only data,
7130 in order to reduce RAM usage. */
7131 mergeable_constant_section (mode, align, 0);
7132 }
7133 else
7134 {
7135 /* For hosted applications, always put constants in small data if
7136 possible, as this gives the best performance. */
7137 /* ??? Consider using mergeable small data sections. */
7138
7139 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7140 && mips_section_threshold > 0)
7141 named_section (0, ".sdata", 0);
7142 else if (flag_pic && symbolic_expression_p (x))
7143 named_section (0, ".data.rel.ro", 3);
7144 else
7145 mergeable_constant_section (mode, align, 0);
7146 }
7147 }
7148
7149 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7150
7151 The complication here is that, with the combination TARGET_ABICALLS
7152 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
7153 therefore not be included in the read-only part of a DSO. Handle such
7154 cases by selecting a normal data section instead of a read-only one.
7155 The logic apes that in default_function_rodata_section. */
7156
7157 static void
mips_function_rodata_section(tree decl)7158 mips_function_rodata_section (tree decl)
7159 {
7160 if (!TARGET_ABICALLS || TARGET_GPWORD)
7161 default_function_rodata_section (decl);
7162 else if (decl && DECL_SECTION_NAME (decl))
7163 {
7164 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7165 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7166 {
7167 char *rname = ASTRDUP (name);
7168 rname[14] = 'd';
7169 named_section_real (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7170 }
7171 else if (flag_function_sections && flag_data_sections
7172 && strncmp (name, ".text.", 6) == 0)
7173 {
7174 char *rname = ASTRDUP (name);
7175 memcpy (rname + 1, "data", 4);
7176 named_section_flags (rname, SECTION_WRITE);
7177 }
7178 else
7179 data_section ();
7180 }
7181 else
7182 data_section ();
7183 }
7184
7185 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
7186 access DECL using %gp_rel(...)($gp). */
7187
7188 static bool
mips_in_small_data_p(tree decl)7189 mips_in_small_data_p (tree decl)
7190 {
7191 HOST_WIDE_INT size;
7192
7193 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7194 return false;
7195
7196 /* We don't yet generate small-data references for -mabicalls. See related
7197 -G handling in override_options. */
7198 if (TARGET_ABICALLS)
7199 return false;
7200
7201 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7202 {
7203 const char *name;
7204
7205 /* Reject anything that isn't in a known small-data section. */
7206 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7207 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7208 return false;
7209
7210 /* If a symbol is defined externally, the assembler will use the
7211 usual -G rules when deciding how to implement macros. */
7212 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7213 return true;
7214 }
7215 else if (TARGET_EMBEDDED_DATA)
7216 {
7217 /* Don't put constants into the small data section: we want them
7218 to be in ROM rather than RAM. */
7219 if (TREE_CODE (decl) != VAR_DECL)
7220 return false;
7221
7222 if (TREE_READONLY (decl)
7223 && !TREE_SIDE_EFFECTS (decl)
7224 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7225 return false;
7226 }
7227
7228 size = int_size_in_bytes (TREE_TYPE (decl));
7229 return (size > 0 && size <= mips_section_threshold);
7230 }
7231
7232 /* See whether VALTYPE is a record whose fields should be returned in
7233 floating-point registers. If so, return the number of fields and
7234 list them in FIELDS (which should have two elements). Return 0
7235 otherwise.
7236
7237 For n32 & n64, a structure with one or two fields is returned in
7238 floating-point registers as long as every field has a floating-point
7239 type. */
7240
7241 static int
mips_fpr_return_fields(tree valtype,tree * fields)7242 mips_fpr_return_fields (tree valtype, tree *fields)
7243 {
7244 tree field;
7245 int i;
7246
7247 if (!TARGET_NEWABI)
7248 return 0;
7249
7250 if (TREE_CODE (valtype) != RECORD_TYPE)
7251 return 0;
7252
7253 i = 0;
7254 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7255 {
7256 if (TREE_CODE (field) != FIELD_DECL)
7257 continue;
7258
7259 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7260 return 0;
7261
7262 if (i == 2)
7263 return 0;
7264
7265 fields[i++] = field;
7266 }
7267 return i;
7268 }
7269
7270
7271 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7272 a value in the most significant part of $2/$3 if:
7273
7274 - the target is big-endian;
7275
7276 - the value has a structure or union type (we generalize this to
7277 cover aggregates from other languages too); and
7278
7279 - the structure is not returned in floating-point registers. */
7280
7281 static bool
mips_return_in_msb(tree valtype)7282 mips_return_in_msb (tree valtype)
7283 {
7284 tree fields[2];
7285
7286 return (TARGET_NEWABI
7287 && TARGET_BIG_ENDIAN
7288 && AGGREGATE_TYPE_P (valtype)
7289 && mips_fpr_return_fields (valtype, fields) == 0);
7290 }
7291
7292
7293 /* Return a composite value in a pair of floating-point registers.
7294 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7295 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7296 complete value.
7297
7298 For n32 & n64, $f0 always holds the first value and $f2 the second.
7299 Otherwise the values are packed together as closely as possible. */
7300
7301 static rtx
mips_return_fpr_pair(enum machine_mode mode,enum machine_mode mode1,HOST_WIDE_INT offset1,enum machine_mode mode2,HOST_WIDE_INT offset2)7302 mips_return_fpr_pair (enum machine_mode mode,
7303 enum machine_mode mode1, HOST_WIDE_INT offset1,
7304 enum machine_mode mode2, HOST_WIDE_INT offset2)
7305 {
7306 int inc;
7307
7308 inc = (TARGET_NEWABI ? 2 : FP_INC);
7309 return gen_rtx_PARALLEL
7310 (mode,
7311 gen_rtvec (2,
7312 gen_rtx_EXPR_LIST (VOIDmode,
7313 gen_rtx_REG (mode1, FP_RETURN),
7314 GEN_INT (offset1)),
7315 gen_rtx_EXPR_LIST (VOIDmode,
7316 gen_rtx_REG (mode2, FP_RETURN + inc),
7317 GEN_INT (offset2))));
7318
7319 }
7320
7321
7322 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7323 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7324 VALTYPE is null and MODE is the mode of the return value. */
7325
7326 rtx
mips_function_value(tree valtype,tree func ATTRIBUTE_UNUSED,enum machine_mode mode)7327 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7328 enum machine_mode mode)
7329 {
7330 if (valtype)
7331 {
7332 tree fields[2];
7333 int unsignedp;
7334
7335 mode = TYPE_MODE (valtype);
7336 unsignedp = TYPE_UNSIGNED (valtype);
7337
7338 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7339 true, we must promote the mode just as PROMOTE_MODE does. */
7340 mode = promote_mode (valtype, mode, &unsignedp, 1);
7341
7342 /* Handle structures whose fields are returned in $f0/$f2. */
7343 switch (mips_fpr_return_fields (valtype, fields))
7344 {
7345 case 1:
7346 return gen_rtx_REG (mode, FP_RETURN);
7347
7348 case 2:
7349 return mips_return_fpr_pair (mode,
7350 TYPE_MODE (TREE_TYPE (fields[0])),
7351 int_byte_position (fields[0]),
7352 TYPE_MODE (TREE_TYPE (fields[1])),
7353 int_byte_position (fields[1]));
7354 }
7355
7356 /* If a value is passed in the most significant part of a register, see
7357 whether we have to round the mode up to a whole number of words. */
7358 if (mips_return_in_msb (valtype))
7359 {
7360 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7361 if (size % UNITS_PER_WORD != 0)
7362 {
7363 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7364 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7365 }
7366 }
7367
7368 /* For EABI, the class of return register depends entirely on MODE.
7369 For example, "struct { some_type x; }" and "union { some_type x; }"
7370 are returned in the same way as a bare "some_type" would be.
7371 Other ABIs only use FPRs for scalar, complex or vector types. */
7372 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
7373 return gen_rtx_REG (mode, GP_RETURN);
7374 }
7375
7376 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
7377 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
7378 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7379 return gen_rtx_REG (mode, FP_RETURN);
7380
7381 /* Handle long doubles for n32 & n64. */
7382 if (mode == TFmode)
7383 return mips_return_fpr_pair (mode,
7384 DImode, 0,
7385 DImode, GET_MODE_SIZE (mode) / 2);
7386
7387 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7388 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7389 return mips_return_fpr_pair (mode,
7390 GET_MODE_INNER (mode), 0,
7391 GET_MODE_INNER (mode),
7392 GET_MODE_SIZE (mode) / 2);
7393
7394 return gen_rtx_REG (mode, GP_RETURN);
7395 }
7396
7397 /* Return nonzero when an argument must be passed by reference. */
7398
7399 static bool
mips_pass_by_reference(CUMULATIVE_ARGS * cum ATTRIBUTE_UNUSED,enum machine_mode mode,tree type,bool named ATTRIBUTE_UNUSED)7400 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7401 enum machine_mode mode, tree type,
7402 bool named ATTRIBUTE_UNUSED)
7403 {
7404 if (mips_abi == ABI_EABI)
7405 {
7406 int size;
7407
7408 /* ??? How should SCmode be handled? */
7409 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7410 return 0;
7411
7412 size = int_size_in_bytes (type);
7413 return size == -1 || size > UNITS_PER_WORD;
7414 }
7415 else
7416 {
7417 /* If we have a variable-sized parameter, we have no choice. */
7418 return targetm.calls.must_pass_in_stack (mode, type);
7419 }
7420 }
7421
7422 static bool
mips_callee_copies(CUMULATIVE_ARGS * cum ATTRIBUTE_UNUSED,enum machine_mode mode ATTRIBUTE_UNUSED,tree type ATTRIBUTE_UNUSED,bool named)7423 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7424 enum machine_mode mode ATTRIBUTE_UNUSED,
7425 tree type ATTRIBUTE_UNUSED, bool named)
7426 {
7427 return mips_abi == ABI_EABI && named;
7428 }
7429
7430 /* Return true if registers of class CLASS cannot change from mode FROM
7431 to mode TO. */
7432
7433 bool
mips_cannot_change_mode_class(enum machine_mode from,enum machine_mode to,enum reg_class class)7434 mips_cannot_change_mode_class (enum machine_mode from,
7435 enum machine_mode to, enum reg_class class)
7436 {
7437 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
7438 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
7439 {
7440 if (TARGET_BIG_ENDIAN)
7441 {
7442 /* When a multi-word value is stored in paired floating-point
7443 registers, the first register always holds the low word.
7444 We therefore can't allow FPRs to change between single-word
7445 and multi-word modes. */
7446 if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
7447 return true;
7448 }
7449 else
7450 {
7451 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7452 in LO and HI, the high word always comes first. We therefore
7453 can't allow values stored in HI to change between single-word
7454 and multi-word modes.
7455 This rule applies to both the original HI/LO pair and the new
7456 DSP accumulators. */
7457 if (reg_classes_intersect_p (ACC_REGS, class))
7458 return true;
7459 }
7460 }
7461 /* Loading a 32-bit value into a 64-bit floating-point register
7462 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7463 We can't allow 64-bit float registers to change from SImode to
7464 to a wider mode. */
7465 if (TARGET_FLOAT64
7466 && from == SImode
7467 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
7468 && reg_classes_intersect_p (FP_REGS, class))
7469 return true;
7470 return false;
7471 }
7472
7473 /* Return true if X should not be moved directly into register $25.
7474 We need this because many versions of GAS will treat "la $25,foo" as
7475 part of a call sequence and so allow a global "foo" to be lazily bound. */
7476
7477 bool
mips_dangerous_for_la25_p(rtx x)7478 mips_dangerous_for_la25_p (rtx x)
7479 {
7480 HOST_WIDE_INT offset;
7481
7482 if (TARGET_EXPLICIT_RELOCS)
7483 return false;
7484
7485 mips_split_const (x, &x, &offset);
7486 return global_got_operand (x, VOIDmode);
7487 }
7488
7489 /* Implement PREFERRED_RELOAD_CLASS. */
7490
7491 enum reg_class
mips_preferred_reload_class(rtx x,enum reg_class class)7492 mips_preferred_reload_class (rtx x, enum reg_class class)
7493 {
7494 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7495 return LEA_REGS;
7496
7497 if (TARGET_HARD_FLOAT
7498 && FLOAT_MODE_P (GET_MODE (x))
7499 && reg_class_subset_p (FP_REGS, class))
7500 return FP_REGS;
7501
7502 if (reg_class_subset_p (GR_REGS, class))
7503 class = GR_REGS;
7504
7505 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7506 class = M16_REGS;
7507
7508 return class;
7509 }
7510
7511 /* This function returns the register class required for a secondary
7512 register when copying between one of the registers in CLASS, and X,
7513 using MODE. If IN_P is nonzero, the copy is going from X to the
7514 register, otherwise the register is the source. A return value of
7515 NO_REGS means that no secondary register is required. */
7516
7517 enum reg_class
mips_secondary_reload_class(enum reg_class class,enum machine_mode mode,rtx x,int in_p)7518 mips_secondary_reload_class (enum reg_class class,
7519 enum machine_mode mode, rtx x, int in_p)
7520 {
7521 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7522 int regno = -1;
7523 int gp_reg_p;
7524
7525 if (REG_P (x)|| GET_CODE (x) == SUBREG)
7526 regno = true_regnum (x);
7527
7528 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7529
7530 if (mips_dangerous_for_la25_p (x))
7531 {
7532 gr_regs = LEA_REGS;
7533 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7534 return gr_regs;
7535 }
7536
7537 /* Copying from HI or LO to anywhere other than a general register
7538 requires a general register.
7539 This rule applies to both the original HI/LO pair and the new
7540 DSP accumulators. */
7541 if (reg_class_subset_p (class, ACC_REGS))
7542 {
7543 if (TARGET_MIPS16 && in_p)
7544 {
7545 /* We can't really copy to HI or LO at all in mips16 mode. */
7546 return M16_REGS;
7547 }
7548 return gp_reg_p ? NO_REGS : gr_regs;
7549 }
7550 if (ACC_REG_P (regno))
7551 {
7552 if (TARGET_MIPS16 && ! in_p)
7553 {
7554 /* We can't really copy to HI or LO at all in mips16 mode. */
7555 return M16_REGS;
7556 }
7557 return class == gr_regs ? NO_REGS : gr_regs;
7558 }
7559
7560 /* We can only copy a value to a condition code register from a
7561 floating point register, and even then we require a scratch
7562 floating point register. We can only copy a value out of a
7563 condition code register into a general register. */
7564 if (class == ST_REGS)
7565 {
7566 if (in_p)
7567 return FP_REGS;
7568 return gp_reg_p ? NO_REGS : gr_regs;
7569 }
7570 if (ST_REG_P (regno))
7571 {
7572 if (! in_p)
7573 return FP_REGS;
7574 return class == gr_regs ? NO_REGS : gr_regs;
7575 }
7576
7577 if (class == FP_REGS)
7578 {
7579 if (MEM_P (x))
7580 {
7581 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7582 return NO_REGS;
7583 }
7584 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7585 {
7586 /* We can use the l.s and l.d macros to load floating-point
7587 constants. ??? For l.s, we could probably get better
7588 code by returning GR_REGS here. */
7589 return NO_REGS;
7590 }
7591 else if (gp_reg_p || x == CONST0_RTX (mode))
7592 {
7593 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7594 return NO_REGS;
7595 }
7596 else if (FP_REG_P (regno))
7597 {
7598 /* In this case we can use mov.s or mov.d. */
7599 return NO_REGS;
7600 }
7601 else
7602 {
7603 /* Otherwise, we need to reload through an integer register. */
7604 return gr_regs;
7605 }
7606 }
7607
7608 /* In mips16 mode, going between memory and anything but M16_REGS
7609 requires an M16_REG. */
7610 if (TARGET_MIPS16)
7611 {
7612 if (class != M16_REGS && class != M16_NA_REGS)
7613 {
7614 if (gp_reg_p)
7615 return NO_REGS;
7616 return M16_REGS;
7617 }
7618 if (! gp_reg_p)
7619 {
7620 if (class == M16_REGS || class == M16_NA_REGS)
7621 return NO_REGS;
7622 return M16_REGS;
7623 }
7624 }
7625
7626 return NO_REGS;
7627 }
7628
7629 /* Implement CLASS_MAX_NREGS.
7630
7631 Usually all registers are word-sized. The only supported exception
7632 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7633 registers. A word-based calculation is correct even in that case,
7634 since -msingle-float disallows multi-FPR values.
7635
7636 The FP status registers are an exception to this rule. They are always
7637 4 bytes wide as they only hold condition code modes, and CCmode is always
7638 considered to be 4 bytes wide. */
7639
7640 int
mips_class_max_nregs(enum reg_class class ATTRIBUTE_UNUSED,enum machine_mode mode)7641 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7642 enum machine_mode mode)
7643 {
7644 if (class == ST_REGS)
7645 return (GET_MODE_SIZE (mode) + 3) / 4;
7646 else
7647 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7648 }
7649
7650 static bool
mips_valid_pointer_mode(enum machine_mode mode)7651 mips_valid_pointer_mode (enum machine_mode mode)
7652 {
7653 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7654 }
7655
7656 /* Target hook for vector_mode_supported_p. */
7657
7658 static bool
mips_vector_mode_supported_p(enum machine_mode mode)7659 mips_vector_mode_supported_p (enum machine_mode mode)
7660 {
7661 switch (mode)
7662 {
7663 case V2SFmode:
7664 return TARGET_PAIRED_SINGLE_FLOAT;
7665
7666 case V2HImode:
7667 case V4QImode:
7668 return TARGET_DSP;
7669
7670 default:
7671 return false;
7672 }
7673 }
7674
7675 /* If we can access small data directly (using gp-relative relocation
7676 operators) return the small data pointer, otherwise return null.
7677
7678 For each mips16 function which refers to GP relative symbols, we
7679 use a pseudo register, initialized at the start of the function, to
7680 hold the $gp value. */
7681
7682 static rtx
mips16_gp_pseudo_reg(void)7683 mips16_gp_pseudo_reg (void)
7684 {
7685 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7686 {
7687 rtx unspec;
7688 rtx insn, scan;
7689
7690 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7691
7692 /* We want to initialize this to a value which gcc will believe
7693 is constant. */
7694 start_sequence ();
7695 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7696 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7697 gen_rtx_CONST (Pmode, unspec));
7698 insn = get_insns ();
7699 end_sequence ();
7700
7701 push_topmost_sequence ();
7702 /* We need to emit the initialization after the FUNCTION_BEG
7703 note, so that it will be integrated. */
7704 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7705 if (NOTE_P (scan)
7706 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7707 break;
7708 if (scan == NULL_RTX)
7709 scan = get_insns ();
7710 insn = emit_insn_after (insn, scan);
7711 pop_topmost_sequence ();
7712 }
7713
7714 return cfun->machine->mips16_gp_pseudo_rtx;
7715 }
7716
7717 /* Write out code to move floating point arguments in or out of
7718 general registers. Output the instructions to FILE. FP_CODE is
7719 the code describing which arguments are present (see the comment at
7720 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7721 we are copying from the floating point registers. */
7722
7723 static void
mips16_fp_args(FILE * file,int fp_code,int from_fp_p)7724 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7725 {
7726 const char *s;
7727 int gparg, fparg;
7728 unsigned int f;
7729
7730 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7731 gcc_assert (TARGET_OLDABI);
7732
7733 if (from_fp_p)
7734 s = "mfc1";
7735 else
7736 s = "mtc1";
7737 gparg = GP_ARG_FIRST;
7738 fparg = FP_ARG_FIRST;
7739 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7740 {
7741 if ((f & 3) == 1)
7742 {
7743 if ((fparg & 1) != 0)
7744 ++fparg;
7745 fprintf (file, "\t%s\t%s,%s\n", s,
7746 reg_names[gparg], reg_names[fparg]);
7747 }
7748 else if ((f & 3) == 2)
7749 {
7750 if (TARGET_64BIT)
7751 fprintf (file, "\td%s\t%s,%s\n", s,
7752 reg_names[gparg], reg_names[fparg]);
7753 else
7754 {
7755 if ((fparg & 1) != 0)
7756 ++fparg;
7757 if (TARGET_BIG_ENDIAN)
7758 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7759 reg_names[gparg], reg_names[fparg + 1], s,
7760 reg_names[gparg + 1], reg_names[fparg]);
7761 else
7762 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7763 reg_names[gparg], reg_names[fparg], s,
7764 reg_names[gparg + 1], reg_names[fparg + 1]);
7765 ++gparg;
7766 ++fparg;
7767 }
7768 }
7769 else
7770 gcc_unreachable ();
7771
7772 ++gparg;
7773 ++fparg;
7774 }
7775 }
7776
7777 /* Build a mips16 function stub. This is used for functions which
7778 take arguments in the floating point registers. It is 32 bit code
7779 that moves the floating point args into the general registers, and
7780 then jumps to the 16 bit code. */
7781
7782 static void
build_mips16_function_stub(FILE * file)7783 build_mips16_function_stub (FILE *file)
7784 {
7785 const char *fnname;
7786 char *secname, *stubname;
7787 tree stubid, stubdecl;
7788 int need_comma;
7789 unsigned int f;
7790
7791 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7792 secname = (char *) alloca (strlen (fnname) + 20);
7793 sprintf (secname, ".mips16.fn.%s", fnname);
7794 stubname = (char *) alloca (strlen (fnname) + 20);
7795 sprintf (stubname, "__fn_stub_%s", fnname);
7796 stubid = get_identifier (stubname);
7797 stubdecl = build_decl (FUNCTION_DECL, stubid,
7798 build_function_type (void_type_node, NULL_TREE));
7799 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7800
7801 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7802 need_comma = 0;
7803 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7804 {
7805 fprintf (file, "%s%s",
7806 need_comma ? ", " : "",
7807 (f & 3) == 1 ? "float" : "double");
7808 need_comma = 1;
7809 }
7810 fprintf (file, ")\n");
7811
7812 fprintf (file, "\t.set\tnomips16\n");
7813 function_section (stubdecl);
7814 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7815
7816 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7817 within a .ent, and we cannot emit another .ent. */
7818 if (!FUNCTION_NAME_ALREADY_DECLARED)
7819 {
7820 fputs ("\t.ent\t", file);
7821 assemble_name (file, stubname);
7822 fputs ("\n", file);
7823 }
7824
7825 assemble_name (file, stubname);
7826 fputs (":\n", file);
7827
7828 /* We don't want the assembler to insert any nops here. */
7829 fprintf (file, "\t.set\tnoreorder\n");
7830
7831 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7832
7833 fprintf (asm_out_file, "\t.set\tnoat\n");
7834 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7835 assemble_name (file, fnname);
7836 fprintf (file, "\n");
7837 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7838 fprintf (asm_out_file, "\t.set\tat\n");
7839
7840 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7841 with one of the mfc1 instructions, because the result is not
7842 available for one instruction, so if the very first instruction
7843 in the function refers to the register, it will see the wrong
7844 value. */
7845 fprintf (file, "\tnop\n");
7846
7847 fprintf (file, "\t.set\treorder\n");
7848
7849 if (!FUNCTION_NAME_ALREADY_DECLARED)
7850 {
7851 fputs ("\t.end\t", file);
7852 assemble_name (file, stubname);
7853 fputs ("\n", file);
7854 }
7855
7856 fprintf (file, "\t.set\tmips16\n");
7857
7858 function_section (current_function_decl);
7859 }
7860
7861 /* We keep a list of functions for which we have already built stubs
7862 in build_mips16_call_stub. */
7863
7864 struct mips16_stub
7865 {
7866 struct mips16_stub *next;
7867 char *name;
7868 int fpret;
7869 };
7870
7871 static struct mips16_stub *mips16_stubs;
7872
7873 /* Build a call stub for a mips16 call. A stub is needed if we are
7874 passing any floating point values which should go into the floating
7875 point registers. If we are, and the call turns out to be to a 32
7876 bit function, the stub will be used to move the values into the
7877 floating point registers before calling the 32 bit function. The
7878 linker will magically adjust the function call to either the 16 bit
7879 function or the 32 bit stub, depending upon where the function call
7880 is actually defined.
7881
7882 Similarly, we need a stub if the return value might come back in a
7883 floating point register.
7884
7885 RETVAL is the location of the return value, or null if this is
7886 a call rather than a call_value. FN is the address of the
7887 function and ARG_SIZE is the size of the arguments. FP_CODE
7888 is the code built by function_arg. This function returns a nonzero
7889 value if it builds the call instruction itself. */
7890
7891 int
build_mips16_call_stub(rtx retval,rtx fn,rtx arg_size,int fp_code)7892 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
7893 {
7894 int fpret;
7895 const char *fnname;
7896 char *secname, *stubname;
7897 struct mips16_stub *l;
7898 tree stubid, stubdecl;
7899 int need_comma;
7900 unsigned int f;
7901
7902 /* We don't need to do anything if we aren't in mips16 mode, or if
7903 we were invoked with the -msoft-float option. */
7904 if (! TARGET_MIPS16 || ! mips16_hard_float)
7905 return 0;
7906
7907 /* Figure out whether the value might come back in a floating point
7908 register. */
7909 fpret = (retval != 0
7910 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
7911 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
7912
7913 /* We don't need to do anything if there were no floating point
7914 arguments and the value will not be returned in a floating point
7915 register. */
7916 if (fp_code == 0 && ! fpret)
7917 return 0;
7918
7919 /* We don't need to do anything if this is a call to a special
7920 mips16 support function. */
7921 if (GET_CODE (fn) == SYMBOL_REF
7922 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
7923 return 0;
7924
7925 /* This code will only work for o32 and o64 abis. The other ABI's
7926 require more sophisticated support. */
7927 gcc_assert (TARGET_OLDABI);
7928
7929 /* We can only handle SFmode and DFmode floating point return
7930 values. */
7931 if (fpret)
7932 gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
7933
7934 /* If we're calling via a function pointer, then we must always call
7935 via a stub. There are magic stubs provided in libgcc.a for each
7936 of the required cases. Each of them expects the function address
7937 to arrive in register $2. */
7938
7939 if (GET_CODE (fn) != SYMBOL_REF)
7940 {
7941 char buf[30];
7942 tree id;
7943 rtx stub_fn, insn;
7944
7945 /* ??? If this code is modified to support other ABI's, we need
7946 to handle PARALLEL return values here. */
7947
7948 sprintf (buf, "__mips16_call_stub_%s%d",
7949 (fpret
7950 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
7951 : ""),
7952 fp_code);
7953 id = get_identifier (buf);
7954 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
7955
7956 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
7957
7958 if (retval == NULL_RTX)
7959 insn = gen_call_internal (stub_fn, arg_size);
7960 else
7961 insn = gen_call_value_internal (retval, stub_fn, arg_size);
7962 insn = emit_call_insn (insn);
7963
7964 /* Put the register usage information on the CALL. */
7965 CALL_INSN_FUNCTION_USAGE (insn) =
7966 gen_rtx_EXPR_LIST (VOIDmode,
7967 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
7968 CALL_INSN_FUNCTION_USAGE (insn));
7969
7970 /* If we are handling a floating point return value, we need to
7971 save $18 in the function prologue. Putting a note on the
7972 call will mean that regs_ever_live[$18] will be true if the
7973 call is not eliminated, and we can check that in the prologue
7974 code. */
7975 if (fpret)
7976 CALL_INSN_FUNCTION_USAGE (insn) =
7977 gen_rtx_EXPR_LIST (VOIDmode,
7978 gen_rtx_USE (VOIDmode,
7979 gen_rtx_REG (word_mode, 18)),
7980 CALL_INSN_FUNCTION_USAGE (insn));
7981
7982 /* Return 1 to tell the caller that we've generated the call
7983 insn. */
7984 return 1;
7985 }
7986
7987 /* We know the function we are going to call. If we have already
7988 built a stub, we don't need to do anything further. */
7989
7990 fnname = XSTR (fn, 0);
7991 for (l = mips16_stubs; l != NULL; l = l->next)
7992 if (strcmp (l->name, fnname) == 0)
7993 break;
7994
7995 if (l == NULL)
7996 {
7997 /* Build a special purpose stub. When the linker sees a
7998 function call in mips16 code, it will check where the target
7999 is defined. If the target is a 32 bit call, the linker will
8000 search for the section defined here. It can tell which
8001 symbol this section is associated with by looking at the
8002 relocation information (the name is unreliable, since this
8003 might be a static function). If such a section is found, the
8004 linker will redirect the call to the start of the magic
8005 section.
8006
8007 If the function does not return a floating point value, the
8008 special stub section is named
8009 .mips16.call.FNNAME
8010
8011 If the function does return a floating point value, the stub
8012 section is named
8013 .mips16.call.fp.FNNAME
8014 */
8015
8016 secname = (char *) alloca (strlen (fnname) + 40);
8017 sprintf (secname, ".mips16.call.%s%s",
8018 fpret ? "fp." : "",
8019 fnname);
8020 stubname = (char *) alloca (strlen (fnname) + 20);
8021 sprintf (stubname, "__call_stub_%s%s",
8022 fpret ? "fp_" : "",
8023 fnname);
8024 stubid = get_identifier (stubname);
8025 stubdecl = build_decl (FUNCTION_DECL, stubid,
8026 build_function_type (void_type_node, NULL_TREE));
8027 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8028
8029 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8030 (fpret
8031 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8032 : ""),
8033 fnname);
8034 need_comma = 0;
8035 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8036 {
8037 fprintf (asm_out_file, "%s%s",
8038 need_comma ? ", " : "",
8039 (f & 3) == 1 ? "float" : "double");
8040 need_comma = 1;
8041 }
8042 fprintf (asm_out_file, ")\n");
8043
8044 fprintf (asm_out_file, "\t.set\tnomips16\n");
8045 assemble_start_function (stubdecl, stubname);
8046
8047 if (!FUNCTION_NAME_ALREADY_DECLARED)
8048 {
8049 fputs ("\t.ent\t", asm_out_file);
8050 assemble_name (asm_out_file, stubname);
8051 fputs ("\n", asm_out_file);
8052
8053 assemble_name (asm_out_file, stubname);
8054 fputs (":\n", asm_out_file);
8055 }
8056
8057 /* We build the stub code by hand. That's the only way we can
8058 do it, since we can't generate 32 bit code during a 16 bit
8059 compilation. */
8060
8061 /* We don't want the assembler to insert any nops here. */
8062 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8063
8064 mips16_fp_args (asm_out_file, fp_code, 0);
8065
8066 if (! fpret)
8067 {
8068 fprintf (asm_out_file, "\t.set\tnoat\n");
8069 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8070 fnname);
8071 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8072 fprintf (asm_out_file, "\t.set\tat\n");
8073 /* Unfortunately, we can't fill the jump delay slot. We
8074 can't fill with one of the mtc1 instructions, because the
8075 result is not available for one instruction, so if the
8076 very first instruction in the function refers to the
8077 register, it will see the wrong value. */
8078 fprintf (asm_out_file, "\tnop\n");
8079 }
8080 else
8081 {
8082 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8083 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8084 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8085 /* As above, we can't fill the delay slot. */
8086 fprintf (asm_out_file, "\tnop\n");
8087 if (GET_MODE (retval) == SFmode)
8088 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8089 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8090 else
8091 {
8092 if (TARGET_BIG_ENDIAN)
8093 {
8094 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8095 reg_names[GP_REG_FIRST + 2],
8096 reg_names[FP_REG_FIRST + 1]);
8097 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8098 reg_names[GP_REG_FIRST + 3],
8099 reg_names[FP_REG_FIRST + 0]);
8100 }
8101 else
8102 {
8103 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8104 reg_names[GP_REG_FIRST + 2],
8105 reg_names[FP_REG_FIRST + 0]);
8106 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8107 reg_names[GP_REG_FIRST + 3],
8108 reg_names[FP_REG_FIRST + 1]);
8109 }
8110 }
8111 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8112 /* As above, we can't fill the delay slot. */
8113 fprintf (asm_out_file, "\tnop\n");
8114 }
8115
8116 fprintf (asm_out_file, "\t.set\treorder\n");
8117
8118 #ifdef ASM_DECLARE_FUNCTION_SIZE
8119 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8120 #endif
8121
8122 if (!FUNCTION_NAME_ALREADY_DECLARED)
8123 {
8124 fputs ("\t.end\t", asm_out_file);
8125 assemble_name (asm_out_file, stubname);
8126 fputs ("\n", asm_out_file);
8127 }
8128
8129 fprintf (asm_out_file, "\t.set\tmips16\n");
8130
8131 /* Record this stub. */
8132 l = (struct mips16_stub *) xmalloc (sizeof *l);
8133 l->name = xstrdup (fnname);
8134 l->fpret = fpret;
8135 l->next = mips16_stubs;
8136 mips16_stubs = l;
8137 }
8138
8139 /* If we expect a floating point return value, but we've built a
8140 stub which does not expect one, then we're in trouble. We can't
8141 use the existing stub, because it won't handle the floating point
8142 value. We can't build a new stub, because the linker won't know
8143 which stub to use for the various calls in this object file.
8144 Fortunately, this case is illegal, since it means that a function
8145 was declared in two different ways in a single compilation. */
8146 if (fpret && ! l->fpret)
8147 error ("cannot handle inconsistent calls to %qs", fnname);
8148
8149 /* If we are calling a stub which handles a floating point return
8150 value, we need to arrange to save $18 in the prologue. We do
8151 this by marking the function call as using the register. The
8152 prologue will later see that it is used, and emit code to save
8153 it. */
8154
8155 if (l->fpret)
8156 {
8157 rtx insn;
8158
8159 if (retval == NULL_RTX)
8160 insn = gen_call_internal (fn, arg_size);
8161 else
8162 insn = gen_call_value_internal (retval, fn, arg_size);
8163 insn = emit_call_insn (insn);
8164
8165 CALL_INSN_FUNCTION_USAGE (insn) =
8166 gen_rtx_EXPR_LIST (VOIDmode,
8167 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8168 CALL_INSN_FUNCTION_USAGE (insn));
8169
8170 /* Return 1 to tell the caller that we've generated the call
8171 insn. */
8172 return 1;
8173 }
8174
8175 /* Return 0 to let the caller generate the call insn. */
8176 return 0;
8177 }
8178
8179 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8180 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8181
8182 struct mips16_constant {
8183 struct mips16_constant *next;
8184 rtx value;
8185 rtx label;
8186 enum machine_mode mode;
8187 };
8188
8189 /* Information about an incomplete mips16 constant pool. FIRST is the
8190 first constant, HIGHEST_ADDRESS is the highest address that the first
8191 byte of the pool can have, and INSN_ADDRESS is the current instruction
8192 address. */
8193
8194 struct mips16_constant_pool {
8195 struct mips16_constant *first;
8196 int highest_address;
8197 int insn_address;
8198 };
8199
8200 /* Add constant VALUE to POOL and return its label. MODE is the
8201 value's mode (used for CONST_INTs, etc.). */
8202
8203 static rtx
add_constant(struct mips16_constant_pool * pool,rtx value,enum machine_mode mode)8204 add_constant (struct mips16_constant_pool *pool,
8205 rtx value, enum machine_mode mode)
8206 {
8207 struct mips16_constant **p, *c;
8208 bool first_of_size_p;
8209
8210 /* See whether the constant is already in the pool. If so, return the
8211 existing label, otherwise leave P pointing to the place where the
8212 constant should be added.
8213
8214 Keep the pool sorted in increasing order of mode size so that we can
8215 reduce the number of alignments needed. */
8216 first_of_size_p = true;
8217 for (p = &pool->first; *p != 0; p = &(*p)->next)
8218 {
8219 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
8220 return (*p)->label;
8221 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
8222 break;
8223 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
8224 first_of_size_p = false;
8225 }
8226
8227 /* In the worst case, the constant needed by the earliest instruction
8228 will end up at the end of the pool. The entire pool must then be
8229 accessible from that instruction.
8230
8231 When adding the first constant, set the pool's highest address to
8232 the address of the first out-of-range byte. Adjust this address
8233 downwards each time a new constant is added. */
8234 if (pool->first == 0)
8235 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8236 is the address of the instruction with the lowest two bits clear.
8237 The base PC value for ld has the lowest three bits clear. Assume
8238 the worst case here. */
8239 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8240 pool->highest_address -= GET_MODE_SIZE (mode);
8241 if (first_of_size_p)
8242 /* Take into account the worst possible padding due to alignment. */
8243 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8244
8245 /* Create a new entry. */
8246 c = (struct mips16_constant *) xmalloc (sizeof *c);
8247 c->value = value;
8248 c->mode = mode;
8249 c->label = gen_label_rtx ();
8250 c->next = *p;
8251 *p = c;
8252
8253 return c->label;
8254 }
8255
8256 /* Output constant VALUE after instruction INSN and return the last
8257 instruction emitted. MODE is the mode of the constant. */
8258
8259 static rtx
dump_constants_1(enum machine_mode mode,rtx value,rtx insn)8260 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8261 {
8262 switch (GET_MODE_CLASS (mode))
8263 {
8264 case MODE_INT:
8265 {
8266 rtx size = GEN_INT (GET_MODE_SIZE (mode));
8267 return emit_insn_after (gen_consttable_int (value, size), insn);
8268 }
8269
8270 case MODE_FLOAT:
8271 return emit_insn_after (gen_consttable_float (value), insn);
8272
8273 case MODE_VECTOR_FLOAT:
8274 case MODE_VECTOR_INT:
8275 {
8276 int i;
8277 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8278 insn = dump_constants_1 (GET_MODE_INNER (mode),
8279 CONST_VECTOR_ELT (value, i), insn);
8280 return insn;
8281 }
8282
8283 default:
8284 gcc_unreachable ();
8285 }
8286 }
8287
8288
8289 /* Dump out the constants in CONSTANTS after INSN. */
8290
8291 static void
dump_constants(struct mips16_constant * constants,rtx insn)8292 dump_constants (struct mips16_constant *constants, rtx insn)
8293 {
8294 struct mips16_constant *c, *next;
8295 int align;
8296
8297 align = 0;
8298 for (c = constants; c != NULL; c = next)
8299 {
8300 /* If necessary, increase the alignment of PC. */
8301 if (align < GET_MODE_SIZE (c->mode))
8302 {
8303 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8304 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8305 }
8306 align = GET_MODE_SIZE (c->mode);
8307
8308 insn = emit_label_after (c->label, insn);
8309 insn = dump_constants_1 (c->mode, c->value, insn);
8310
8311 next = c->next;
8312 free (c);
8313 }
8314
8315 emit_barrier_after (insn);
8316 }
8317
8318 /* Return the length of instruction INSN. */
8319
8320 static int
mips16_insn_length(rtx insn)8321 mips16_insn_length (rtx insn)
8322 {
8323 if (JUMP_P (insn))
8324 {
8325 rtx body = PATTERN (insn);
8326 if (GET_CODE (body) == ADDR_VEC)
8327 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8328 if (GET_CODE (body) == ADDR_DIFF_VEC)
8329 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8330 }
8331 return get_attr_length (insn);
8332 }
8333
8334 /* Rewrite *X so that constant pool references refer to the constant's
8335 label instead. DATA points to the constant pool structure. */
8336
8337 static int
mips16_rewrite_pool_refs(rtx * x,void * data)8338 mips16_rewrite_pool_refs (rtx *x, void *data)
8339 {
8340 struct mips16_constant_pool *pool = data;
8341 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8342 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8343 get_pool_constant (*x),
8344 get_pool_mode (*x)));
8345 return 0;
8346 }
8347
8348 /* Build MIPS16 constant pools. */
8349
8350 static void
mips16_lay_out_constants(void)8351 mips16_lay_out_constants (void)
8352 {
8353 struct mips16_constant_pool pool;
8354 rtx insn, barrier;
8355
8356 barrier = 0;
8357 memset (&pool, 0, sizeof (pool));
8358 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8359 {
8360 /* Rewrite constant pool references in INSN. */
8361 if (INSN_P (insn))
8362 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8363
8364 pool.insn_address += mips16_insn_length (insn);
8365
8366 if (pool.first != NULL)
8367 {
8368 /* If there are no natural barriers between the first user of
8369 the pool and the highest acceptable address, we'll need to
8370 create a new instruction to jump around the constant pool.
8371 In the worst case, this instruction will be 4 bytes long.
8372
8373 If it's too late to do this transformation after INSN,
8374 do it immediately before INSN. */
8375 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8376 {
8377 rtx label, jump;
8378
8379 label = gen_label_rtx ();
8380
8381 jump = emit_jump_insn_before (gen_jump (label), insn);
8382 JUMP_LABEL (jump) = label;
8383 LABEL_NUSES (label) = 1;
8384 barrier = emit_barrier_after (jump);
8385
8386 emit_label_after (label, barrier);
8387 pool.insn_address += 4;
8388 }
8389
8390 /* See whether the constant pool is now out of range of the first
8391 user. If so, output the constants after the previous barrier.
8392 Note that any instructions between BARRIER and INSN (inclusive)
8393 will use negative offsets to refer to the pool. */
8394 if (pool.insn_address > pool.highest_address)
8395 {
8396 dump_constants (pool.first, barrier);
8397 pool.first = NULL;
8398 barrier = 0;
8399 }
8400 else if (BARRIER_P (insn))
8401 barrier = insn;
8402 }
8403 }
8404 dump_constants (pool.first, get_last_insn ());
8405 }
8406
8407 /* A temporary variable used by for_each_rtx callbacks, etc. */
8408 static rtx mips_sim_insn;
8409
8410 /* A structure representing the state of the processor pipeline.
8411 Used by the mips_sim_* family of functions. */
8412 struct mips_sim {
8413 /* The maximum number of instructions that can be issued in a cycle.
8414 (Caches mips_issue_rate.) */
8415 unsigned int issue_rate;
8416
8417 /* The current simulation time. */
8418 unsigned int time;
8419
8420 /* How many more instructions can be issued in the current cycle. */
8421 unsigned int insns_left;
8422
8423 /* LAST_SET[X].INSN is the last instruction to set register X.
8424 LAST_SET[X].TIME is the time at which that instruction was issued.
8425 INSN is null if no instruction has yet set register X. */
8426 struct {
8427 rtx insn;
8428 unsigned int time;
8429 } last_set[FIRST_PSEUDO_REGISTER];
8430
8431 /* The pipeline's current DFA state. */
8432 state_t dfa_state;
8433 };
8434
8435 /* Reset STATE to the initial simulation state. */
8436
8437 static void
mips_sim_reset(struct mips_sim * state)8438 mips_sim_reset (struct mips_sim *state)
8439 {
8440 state->time = 0;
8441 state->insns_left = state->issue_rate;
8442 memset (&state->last_set, 0, sizeof (state->last_set));
8443 state_reset (state->dfa_state);
8444 }
8445
8446 /* Initialize STATE before its first use. DFA_STATE points to an
8447 allocated but uninitialized DFA state. */
8448
8449 static void
mips_sim_init(struct mips_sim * state,state_t dfa_state)8450 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8451 {
8452 state->issue_rate = mips_issue_rate ();
8453 state->dfa_state = dfa_state;
8454 mips_sim_reset (state);
8455 }
8456
8457 /* Advance STATE by one clock cycle. */
8458
8459 static void
mips_sim_next_cycle(struct mips_sim * state)8460 mips_sim_next_cycle (struct mips_sim *state)
8461 {
8462 state->time++;
8463 state->insns_left = state->issue_rate;
8464 state_transition (state->dfa_state, 0);
8465 }
8466
8467 /* Advance simulation state STATE until instruction INSN can read
8468 register REG. */
8469
8470 static void
mips_sim_wait_reg(struct mips_sim * state,rtx insn,rtx reg)8471 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8472 {
8473 unsigned int i;
8474
8475 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8476 if (state->last_set[REGNO (reg) + i].insn != 0)
8477 {
8478 unsigned int t;
8479
8480 t = state->last_set[REGNO (reg) + i].time;
8481 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8482 while (state->time < t)
8483 mips_sim_next_cycle (state);
8484 }
8485 }
8486
8487 /* A for_each_rtx callback. If *X is a register, advance simulation state
8488 DATA until mips_sim_insn can read the register's value. */
8489
8490 static int
mips_sim_wait_regs_2(rtx * x,void * data)8491 mips_sim_wait_regs_2 (rtx *x, void *data)
8492 {
8493 if (REG_P (*x))
8494 mips_sim_wait_reg (data, mips_sim_insn, *x);
8495 return 0;
8496 }
8497
8498 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8499
8500 static void
mips_sim_wait_regs_1(rtx * x,void * data)8501 mips_sim_wait_regs_1 (rtx *x, void *data)
8502 {
8503 for_each_rtx (x, mips_sim_wait_regs_2, data);
8504 }
8505
8506 /* Advance simulation state STATE until all of INSN's register
8507 dependencies are satisfied. */
8508
8509 static void
mips_sim_wait_regs(struct mips_sim * state,rtx insn)8510 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8511 {
8512 mips_sim_insn = insn;
8513 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8514 }
8515
8516 /* Advance simulation state STATE until the units required by
8517 instruction INSN are available. */
8518
8519 static void
mips_sim_wait_units(struct mips_sim * state,rtx insn)8520 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8521 {
8522 state_t tmp_state;
8523
8524 tmp_state = alloca (state_size ());
8525 while (state->insns_left == 0
8526 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8527 state_transition (tmp_state, insn) >= 0))
8528 mips_sim_next_cycle (state);
8529 }
8530
8531 /* Advance simulation state STATE until INSN is ready to issue. */
8532
8533 static void
mips_sim_wait_insn(struct mips_sim * state,rtx insn)8534 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8535 {
8536 mips_sim_wait_regs (state, insn);
8537 mips_sim_wait_units (state, insn);
8538 }
8539
8540 /* mips_sim_insn has just set X. Update the LAST_SET array
8541 in simulation state DATA. */
8542
8543 static void
mips_sim_record_set(rtx x,rtx pat ATTRIBUTE_UNUSED,void * data)8544 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8545 {
8546 struct mips_sim *state;
8547 unsigned int i;
8548
8549 state = data;
8550 if (REG_P (x))
8551 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8552 {
8553 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8554 state->last_set[REGNO (x) + i].time = state->time;
8555 }
8556 }
8557
8558 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8559 can issue immediately (i.e., that mips_sim_wait_insn has already
8560 been called). */
8561
8562 static void
mips_sim_issue_insn(struct mips_sim * state,rtx insn)8563 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8564 {
8565 state_transition (state->dfa_state, insn);
8566 state->insns_left--;
8567
8568 mips_sim_insn = insn;
8569 note_stores (PATTERN (insn), mips_sim_record_set, state);
8570 }
8571
8572 /* Simulate issuing a NOP in state STATE. */
8573
8574 static void
mips_sim_issue_nop(struct mips_sim * state)8575 mips_sim_issue_nop (struct mips_sim *state)
8576 {
8577 if (state->insns_left == 0)
8578 mips_sim_next_cycle (state);
8579 state->insns_left--;
8580 }
8581
8582 /* Update simulation state STATE so that it's ready to accept the instruction
8583 after INSN. INSN should be part of the main rtl chain, not a member of a
8584 SEQUENCE. */
8585
8586 static void
mips_sim_finish_insn(struct mips_sim * state,rtx insn)8587 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8588 {
8589 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8590 if (JUMP_P (insn))
8591 mips_sim_issue_nop (state);
8592
8593 switch (GET_CODE (SEQ_BEGIN (insn)))
8594 {
8595 case CODE_LABEL:
8596 case CALL_INSN:
8597 /* We can't predict the processor state after a call or label. */
8598 mips_sim_reset (state);
8599 break;
8600
8601 case JUMP_INSN:
8602 /* The delay slots of branch likely instructions are only executed
8603 when the branch is taken. Therefore, if the caller has simulated
8604 the delay slot instruction, STATE does not really reflect the state
8605 of the pipeline for the instruction after the delay slot. Also,
8606 branch likely instructions tend to incur a penalty when not taken,
8607 so there will probably be an extra delay between the branch and
8608 the instruction after the delay slot. */
8609 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8610 mips_sim_reset (state);
8611 break;
8612
8613 default:
8614 break;
8615 }
8616 }
8617
8618 /* The VR4130 pipeline issues aligned pairs of instructions together,
8619 but it stalls the second instruction if it depends on the first.
8620 In order to cut down the amount of logic required, this dependence
8621 check is not based on a full instruction decode. Instead, any non-SPECIAL
8622 instruction is assumed to modify the register specified by bits 20-16
8623 (which is usually the "rt" field).
8624
8625 In beq, beql, bne and bnel instructions, the rt field is actually an
8626 input, so we can end up with a false dependence between the branch
8627 and its delay slot. If this situation occurs in instruction INSN,
8628 try to avoid it by swapping rs and rt. */
8629
8630 static void
vr4130_avoid_branch_rt_conflict(rtx insn)8631 vr4130_avoid_branch_rt_conflict (rtx insn)
8632 {
8633 rtx first, second;
8634
8635 first = SEQ_BEGIN (insn);
8636 second = SEQ_END (insn);
8637 if (JUMP_P (first)
8638 && NONJUMP_INSN_P (second)
8639 && GET_CODE (PATTERN (first)) == SET
8640 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8641 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8642 {
8643 /* Check for the right kind of condition. */
8644 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8645 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8646 && REG_P (XEXP (cond, 0))
8647 && REG_P (XEXP (cond, 1))
8648 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8649 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8650 {
8651 /* SECOND mentions the rt register but not the rs register. */
8652 rtx tmp = XEXP (cond, 0);
8653 XEXP (cond, 0) = XEXP (cond, 1);
8654 XEXP (cond, 1) = tmp;
8655 }
8656 }
8657 }
8658
8659 /* Implement -mvr4130-align. Go through each basic block and simulate the
8660 processor pipeline. If we find that a pair of instructions could execute
8661 in parallel, and the first of those instruction is not 8-byte aligned,
8662 insert a nop to make it aligned. */
8663
8664 static void
vr4130_align_insns(void)8665 vr4130_align_insns (void)
8666 {
8667 struct mips_sim state;
8668 rtx insn, subinsn, last, last2, next;
8669 bool aligned_p;
8670
8671 dfa_start ();
8672
8673 /* LAST is the last instruction before INSN to have a nonzero length.
8674 LAST2 is the last such instruction before LAST. */
8675 last = 0;
8676 last2 = 0;
8677
8678 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8679 aligned_p = true;
8680
8681 mips_sim_init (&state, alloca (state_size ()));
8682 for (insn = get_insns (); insn != 0; insn = next)
8683 {
8684 unsigned int length;
8685
8686 next = NEXT_INSN (insn);
8687
8688 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8689 This isn't really related to the alignment pass, but we do it on
8690 the fly to avoid a separate instruction walk. */
8691 vr4130_avoid_branch_rt_conflict (insn);
8692
8693 if (USEFUL_INSN_P (insn))
8694 FOR_EACH_SUBINSN (subinsn, insn)
8695 {
8696 mips_sim_wait_insn (&state, subinsn);
8697
8698 /* If we want this instruction to issue in parallel with the
8699 previous one, make sure that the previous instruction is
8700 aligned. There are several reasons why this isn't worthwhile
8701 when the second instruction is a call:
8702
8703 - Calls are less likely to be performance critical,
8704 - There's a good chance that the delay slot can execute
8705 in parallel with the call.
8706 - The return address would then be unaligned.
8707
8708 In general, if we're going to insert a nop between instructions
8709 X and Y, it's better to insert it immediately after X. That
8710 way, if the nop makes Y aligned, it will also align any labels
8711 between X and Y. */
8712 if (state.insns_left != state.issue_rate
8713 && !CALL_P (subinsn))
8714 {
8715 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8716 {
8717 /* SUBINSN is the first instruction in INSN and INSN is
8718 aligned. We want to align the previous instruction
8719 instead, so insert a nop between LAST2 and LAST.
8720
8721 Note that LAST could be either a single instruction
8722 or a branch with a delay slot. In the latter case,
8723 LAST, like INSN, is already aligned, but the delay
8724 slot must have some extra delay that stops it from
8725 issuing at the same time as the branch. We therefore
8726 insert a nop before the branch in order to align its
8727 delay slot. */
8728 emit_insn_after (gen_nop (), last2);
8729 aligned_p = false;
8730 }
8731 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8732 {
8733 /* SUBINSN is the delay slot of INSN, but INSN is
8734 currently unaligned. Insert a nop between
8735 LAST and INSN to align it. */
8736 emit_insn_after (gen_nop (), last);
8737 aligned_p = true;
8738 }
8739 }
8740 mips_sim_issue_insn (&state, subinsn);
8741 }
8742 mips_sim_finish_insn (&state, insn);
8743
8744 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8745 length = get_attr_length (insn);
8746 if (length > 0)
8747 {
8748 /* If the instruction is an asm statement or multi-instruction
8749 mips.md patern, the length is only an estimate. Insert an
8750 8 byte alignment after it so that the following instructions
8751 can be handled correctly. */
8752 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
8753 && (recog_memoized (insn) < 0 || length >= 8))
8754 {
8755 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8756 next = NEXT_INSN (next);
8757 mips_sim_next_cycle (&state);
8758 aligned_p = true;
8759 }
8760 else if (length & 4)
8761 aligned_p = !aligned_p;
8762 last2 = last;
8763 last = insn;
8764 }
8765
8766 /* See whether INSN is an aligned label. */
8767 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8768 aligned_p = true;
8769 }
8770 dfa_finish ();
8771 }
8772
8773 /* Subroutine of mips_reorg. If there is a hazard between INSN
8774 and a previous instruction, avoid it by inserting nops after
8775 instruction AFTER.
8776
8777 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8778 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8779 before using the value of that register. *HILO_DELAY counts the
8780 number of instructions since the last hilo hazard (that is,
8781 the number of instructions since the last mflo or mfhi).
8782
8783 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8784 for the next instruction.
8785
8786 LO_REG is an rtx for the LO register, used in dependence checking. */
8787
8788 static void
mips_avoid_hazard(rtx after,rtx insn,int * hilo_delay,rtx * delayed_reg,rtx lo_reg)8789 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8790 rtx *delayed_reg, rtx lo_reg)
8791 {
8792 rtx pattern, set;
8793 int nops, ninsns;
8794
8795 if (!INSN_P (insn))
8796 return;
8797
8798 pattern = PATTERN (insn);
8799
8800 /* Do not put the whole function in .set noreorder if it contains
8801 an asm statement. We don't know whether there will be hazards
8802 between the asm statement and the gcc-generated code. */
8803 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8804 cfun->machine->all_noreorder_p = false;
8805
8806 /* Ignore zero-length instructions (barriers and the like). */
8807 ninsns = get_attr_length (insn) / 4;
8808 if (ninsns == 0)
8809 return;
8810
8811 /* Work out how many nops are needed. Note that we only care about
8812 registers that are explicitly mentioned in the instruction's pattern.
8813 It doesn't matter that calls use the argument registers or that they
8814 clobber hi and lo. */
8815 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8816 nops = 2 - *hilo_delay;
8817 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8818 nops = 1;
8819 else
8820 nops = 0;
8821
8822 /* Insert the nops between this instruction and the previous one.
8823 Each new nop takes us further from the last hilo hazard. */
8824 *hilo_delay += nops;
8825 while (nops-- > 0)
8826 emit_insn_after (gen_hazard_nop (), after);
8827
8828 /* Set up the state for the next instruction. */
8829 *hilo_delay += ninsns;
8830 *delayed_reg = 0;
8831 if (INSN_CODE (insn) >= 0)
8832 switch (get_attr_hazard (insn))
8833 {
8834 case HAZARD_NONE:
8835 break;
8836
8837 case HAZARD_HILO:
8838 *hilo_delay = 0;
8839 break;
8840
8841 case HAZARD_DELAY:
8842 set = single_set (insn);
8843 gcc_assert (set != 0);
8844 *delayed_reg = SET_DEST (set);
8845 break;
8846 }
8847 }
8848
8849
8850 /* Go through the instruction stream and insert nops where necessary.
8851 See if the whole function can then be put into .set noreorder &
8852 .set nomacro. */
8853
8854 static void
mips_avoid_hazards(void)8855 mips_avoid_hazards (void)
8856 {
8857 rtx insn, last_insn, lo_reg, delayed_reg;
8858 int hilo_delay, i;
8859
8860 /* Force all instructions to be split into their final form. */
8861 split_all_insns_noflow ();
8862
8863 /* Recalculate instruction lengths without taking nops into account. */
8864 cfun->machine->ignore_hazard_length_p = true;
8865 shorten_branches (get_insns ());
8866
8867 cfun->machine->all_noreorder_p = true;
8868
8869 /* Profiled functions can't be all noreorder because the profiler
8870 support uses assembler macros. */
8871 if (current_function_profile)
8872 cfun->machine->all_noreorder_p = false;
8873
8874 /* Code compiled with -mfix-vr4120 can't be all noreorder because
8875 we rely on the assembler to work around some errata. */
8876 if (TARGET_FIX_VR4120)
8877 cfun->machine->all_noreorder_p = false;
8878
8879 /* The same is true for -mfix-vr4130 if we might generate mflo or
8880 mfhi instructions. Note that we avoid using mflo and mfhi if
8881 the VR4130 macc and dmacc instructions are available instead;
8882 see the *mfhilo_{si,di}_macc patterns. */
8883 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
8884 cfun->machine->all_noreorder_p = false;
8885
8886 last_insn = 0;
8887 hilo_delay = 2;
8888 delayed_reg = 0;
8889 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8890
8891 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
8892 if (INSN_P (insn))
8893 {
8894 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8895 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8896 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
8897 &hilo_delay, &delayed_reg, lo_reg);
8898 else
8899 mips_avoid_hazard (last_insn, insn, &hilo_delay,
8900 &delayed_reg, lo_reg);
8901
8902 last_insn = insn;
8903 }
8904 }
8905
8906
8907 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8908
8909 static void
mips_reorg(void)8910 mips_reorg (void)
8911 {
8912 if (TARGET_MIPS16)
8913 mips16_lay_out_constants ();
8914 else if (TARGET_EXPLICIT_RELOCS)
8915 {
8916 if (mips_flag_delayed_branch)
8917 dbr_schedule (get_insns (), dump_file);
8918 mips_avoid_hazards ();
8919 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
8920 vr4130_align_insns ();
8921 }
8922 }
8923
8924 /* This function does three things:
8925
8926 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
8927 - Register the mips16 hardware floating point stubs.
8928 - Register the gofast functions if selected using --enable-gofast. */
8929
8930 #include "config/gofast.h"
8931
8932 static void
mips_init_libfuncs(void)8933 mips_init_libfuncs (void)
8934 {
8935 if (TARGET_FIX_VR4120)
8936 {
8937 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
8938 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
8939 }
8940
8941 if (TARGET_MIPS16 && mips16_hard_float)
8942 {
8943 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
8944 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
8945 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
8946 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
8947
8948 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
8949 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
8950 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
8951 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
8952 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
8953 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
8954
8955 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
8956 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
8957
8958 if (TARGET_DOUBLE_FLOAT)
8959 {
8960 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
8961 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
8962 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
8963 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
8964
8965 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
8966 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
8967 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
8968 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
8969 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
8970 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
8971
8972 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
8973 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
8974
8975 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
8976 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
8977 }
8978 }
8979 else
8980 gofast_maybe_init_libfuncs ();
8981 }
8982
8983 /* Return a number assessing the cost of moving a register in class
8984 FROM to class TO. The classes are expressed using the enumeration
8985 values such as `GENERAL_REGS'. A value of 2 is the default; other
8986 values are interpreted relative to that.
8987
8988 It is not required that the cost always equal 2 when FROM is the
8989 same as TO; on some machines it is expensive to move between
8990 registers if they are not general registers.
8991
8992 If reload sees an insn consisting of a single `set' between two
8993 hard registers, and if `REGISTER_MOVE_COST' applied to their
8994 classes returns a value of 2, reload does not check to ensure that
8995 the constraints of the insn are met. Setting a cost of other than
8996 2 will allow reload to verify that the constraints are met. You
8997 should do this if the `movM' pattern's constraints do not allow
8998 such copying.
8999
9000 ??? We make the cost of moving from HI/LO into general
9001 registers the same as for one of moving general registers to
9002 HI/LO for TARGET_MIPS16 in order to prevent allocating a
9003 pseudo to HI/LO. This might hurt optimizations though, it
9004 isn't clear if it is wise. And it might not work in all cases. We
9005 could solve the DImode LO reg problem by using a multiply, just
9006 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9007 problem by using divide instructions. divu puts the remainder in
9008 the HI reg, so doing a divide by -1 will move the value in the HI
9009 reg for all values except -1. We could handle that case by using a
9010 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9011 a compare/branch to test the input value to see which instruction
9012 we need to use. This gets pretty messy, but it is feasible. */
9013
9014 int
mips_register_move_cost(enum machine_mode mode ATTRIBUTE_UNUSED,enum reg_class to,enum reg_class from)9015 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
9016 enum reg_class to, enum reg_class from)
9017 {
9018 if (from == M16_REGS && GR_REG_CLASS_P (to))
9019 return 2;
9020 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
9021 return 2;
9022 else if (GR_REG_CLASS_P (from))
9023 {
9024 if (to == M16_REGS)
9025 return 2;
9026 else if (to == M16_NA_REGS)
9027 return 2;
9028 else if (GR_REG_CLASS_P (to))
9029 {
9030 if (TARGET_MIPS16)
9031 return 4;
9032 else
9033 return 2;
9034 }
9035 else if (to == FP_REGS)
9036 return 4;
9037 else if (reg_class_subset_p (to, ACC_REGS))
9038 {
9039 if (TARGET_MIPS16)
9040 return 12;
9041 else
9042 return 6;
9043 }
9044 else if (COP_REG_CLASS_P (to))
9045 {
9046 return 5;
9047 }
9048 }
9049 else if (from == FP_REGS)
9050 {
9051 if (GR_REG_CLASS_P (to))
9052 return 4;
9053 else if (to == FP_REGS)
9054 return 2;
9055 else if (to == ST_REGS)
9056 return 8;
9057 }
9058 else if (reg_class_subset_p (from, ACC_REGS))
9059 {
9060 if (GR_REG_CLASS_P (to))
9061 {
9062 if (TARGET_MIPS16)
9063 return 12;
9064 else
9065 return 6;
9066 }
9067 }
9068 else if (from == ST_REGS && GR_REG_CLASS_P (to))
9069 return 4;
9070 else if (COP_REG_CLASS_P (from))
9071 {
9072 return 5;
9073 }
9074
9075 /* Fall through.
9076 ??? What cases are these? Shouldn't we return 2 here? */
9077
9078 return 12;
9079 }
9080
9081 /* Return the length of INSN. LENGTH is the initial length computed by
9082 attributes in the machine-description file. */
9083
9084 int
mips_adjust_insn_length(rtx insn,int length)9085 mips_adjust_insn_length (rtx insn, int length)
9086 {
9087 /* A unconditional jump has an unfilled delay slot if it is not part
9088 of a sequence. A conditional jump normally has a delay slot, but
9089 does not on MIPS16. */
9090 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9091 length += 4;
9092
9093 /* See how many nops might be needed to avoid hardware hazards. */
9094 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9095 switch (get_attr_hazard (insn))
9096 {
9097 case HAZARD_NONE:
9098 break;
9099
9100 case HAZARD_DELAY:
9101 length += 4;
9102 break;
9103
9104 case HAZARD_HILO:
9105 length += 8;
9106 break;
9107 }
9108
9109 /* All MIPS16 instructions are a measly two bytes. */
9110 if (TARGET_MIPS16)
9111 length /= 2;
9112
9113 return length;
9114 }
9115
9116
9117 /* Return an asm sequence to start a noat block and load the address
9118 of a label into $1. */
9119
9120 const char *
mips_output_load_label(void)9121 mips_output_load_label (void)
9122 {
9123 if (TARGET_EXPLICIT_RELOCS)
9124 switch (mips_abi)
9125 {
9126 case ABI_N32:
9127 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9128
9129 case ABI_64:
9130 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9131
9132 default:
9133 if (ISA_HAS_LOAD_DELAY)
9134 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9135 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9136 }
9137 else
9138 {
9139 if (Pmode == DImode)
9140 return "%[dla\t%@,%0";
9141 else
9142 return "%[la\t%@,%0";
9143 }
9144 }
9145
9146
9147 /* Output assembly instructions to peform a conditional branch.
9148
9149 INSN is the branch instruction. OPERANDS[0] is the condition.
9150 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9151 of the first operand to the condition. If TWO_OPERANDS_P is
9152 nonzero the comparison takes two operands; OPERANDS[3] will be the
9153 second operand.
9154
9155 If INVERTED_P is nonzero we are to branch if the condition does
9156 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
9157
9158 LENGTH is the length (in bytes) of the sequence we are to generate.
9159 That tells us whether to generate a simple conditional branch, or a
9160 reversed conditional branch around a `jr' instruction. */
9161 const char *
mips_output_conditional_branch(rtx insn,rtx * operands,int two_operands_p,int float_p,int inverted_p,int length)9162 mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
9163 int float_p, int inverted_p, int length)
9164 {
9165 static char buffer[200];
9166 /* The kind of comparison we are doing. */
9167 enum rtx_code code = GET_CODE (operands[0]);
9168 /* Nonzero if the opcode for the comparison needs a `z' indicating
9169 that it is a comparison against zero. */
9170 int need_z_p;
9171 /* A string to use in the assembly output to represent the first
9172 operand. */
9173 const char *op1 = "%z2";
9174 /* A string to use in the assembly output to represent the second
9175 operand. Use the hard-wired zero register if there's no second
9176 operand. */
9177 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9178 /* The operand-printing string for the comparison. */
9179 const char *const comp = (float_p ? "%F0" : "%C0");
9180 /* The operand-printing string for the inverted comparison. */
9181 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
9182
9183 /* The MIPS processors (for levels of the ISA at least two), have
9184 "likely" variants of each branch instruction. These instructions
9185 annul the instruction in the delay slot if the branch is not
9186 taken. */
9187 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9188
9189 if (!two_operands_p)
9190 {
9191 /* To compute whether than A > B, for example, we normally
9192 subtract B from A and then look at the sign bit. But, if we
9193 are doing an unsigned comparison, and B is zero, we don't
9194 have to do the subtraction. Instead, we can just check to
9195 see if A is nonzero. Thus, we change the CODE here to
9196 reflect the simpler comparison operation. */
9197 switch (code)
9198 {
9199 case GTU:
9200 code = NE;
9201 break;
9202
9203 case LEU:
9204 code = EQ;
9205 break;
9206
9207 case GEU:
9208 /* A condition which will always be true. */
9209 code = EQ;
9210 op1 = "%.";
9211 break;
9212
9213 case LTU:
9214 /* A condition which will always be false. */
9215 code = NE;
9216 op1 = "%.";
9217 break;
9218
9219 default:
9220 /* Not a special case. */
9221 break;
9222 }
9223 }
9224
9225 /* Relative comparisons are always done against zero. But
9226 equality comparisons are done between two operands, and therefore
9227 do not require a `z' in the assembly language output. */
9228 need_z_p = (!float_p && code != EQ && code != NE);
9229 /* For comparisons against zero, the zero is not provided
9230 explicitly. */
9231 if (need_z_p)
9232 op2 = "";
9233
9234 /* Begin by terminating the buffer. That way we can always use
9235 strcat to add to it. */
9236 buffer[0] = '\0';
9237
9238 switch (length)
9239 {
9240 case 4:
9241 case 8:
9242 /* Just a simple conditional branch. */
9243 if (float_p)
9244 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
9245 inverted_p ? inverted_comp : comp);
9246 else
9247 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
9248 inverted_p ? inverted_comp : comp,
9249 need_z_p ? "z" : "",
9250 op1,
9251 op2);
9252 return buffer;
9253
9254 case 12:
9255 case 16:
9256 case 24:
9257 case 28:
9258 {
9259 /* Generate a reversed conditional branch around ` j'
9260 instruction:
9261
9262 .set noreorder
9263 .set nomacro
9264 bc l
9265 delay_slot or #nop
9266 j target
9267 #nop
9268 l:
9269 .set macro
9270 .set reorder
9271
9272 If the original branch was a likely branch, the delay slot
9273 must be executed only if the branch is taken, so generate:
9274
9275 .set noreorder
9276 .set nomacro
9277 bc l
9278 #nop
9279 j target
9280 delay slot or #nop
9281 l:
9282 .set macro
9283 .set reorder
9284
9285 When generating PIC, instead of:
9286
9287 j target
9288
9289 we emit:
9290
9291 .set noat
9292 la $at, target
9293 jr $at
9294 .set at
9295 */
9296
9297 rtx orig_target;
9298 rtx target = gen_label_rtx ();
9299
9300 orig_target = operands[1];
9301 operands[1] = target;
9302 /* Generate the reversed comparison. This takes four
9303 bytes. */
9304 if (float_p)
9305 sprintf (buffer, "%%*b%s\t%%Z2%%1",
9306 inverted_p ? comp : inverted_comp);
9307 else
9308 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
9309 inverted_p ? comp : inverted_comp,
9310 need_z_p ? "z" : "",
9311 op1,
9312 op2);
9313 output_asm_insn (buffer, operands);
9314
9315 if (length != 16 && length != 28 && ! mips_branch_likely)
9316 {
9317 /* Output delay slot instruction. */
9318 rtx insn = final_sequence;
9319 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9320 optimize, 1, NULL);
9321 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9322 }
9323 else
9324 output_asm_insn ("%#", 0);
9325
9326 if (length <= 16)
9327 output_asm_insn ("j\t%0", &orig_target);
9328 else
9329 {
9330 output_asm_insn (mips_output_load_label (), &orig_target);
9331 output_asm_insn ("jr\t%@%]", 0);
9332 }
9333
9334 if (length != 16 && length != 28 && mips_branch_likely)
9335 {
9336 /* Output delay slot instruction. */
9337 rtx insn = final_sequence;
9338 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9339 optimize, 1, NULL);
9340 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9341 }
9342 else
9343 output_asm_insn ("%#", 0);
9344
9345 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9346 CODE_LABEL_NUMBER (target));
9347
9348 return "";
9349 }
9350
9351 default:
9352 gcc_unreachable ();
9353 }
9354
9355 /* NOTREACHED */
9356 return 0;
9357 }
9358
9359 /* Used to output div or ddiv instruction DIVISION, which has the operands
9360 given by OPERANDS. Add in a divide-by-zero check if needed.
9361
9362 When working around R4000 and R4400 errata, we need to make sure that
9363 the division is not immediately followed by a shift[1][2]. We also
9364 need to stop the division from being put into a branch delay slot[3].
9365 The easiest way to avoid both problems is to add a nop after the
9366 division. When a divide-by-zero check is needed, this nop can be
9367 used to fill the branch delay slot.
9368
9369 [1] If a double-word or a variable shift executes immediately
9370 after starting an integer division, the shift may give an
9371 incorrect result. See quotations of errata #16 and #28 from
9372 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9373 in mips.md for details.
9374
9375 [2] A similar bug to [1] exists for all revisions of the
9376 R4000 and the R4400 when run in an MC configuration.
9377 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9378
9379 "19. In this following sequence:
9380
9381 ddiv (or ddivu or div or divu)
9382 dsll32 (or dsrl32, dsra32)
9383
9384 if an MPT stall occurs, while the divide is slipping the cpu
9385 pipeline, then the following double shift would end up with an
9386 incorrect result.
9387
9388 Workaround: The compiler needs to avoid generating any
9389 sequence with divide followed by extended double shift."
9390
9391 This erratum is also present in "MIPS R4400MC Errata, Processor
9392 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9393 & 3.0" as errata #10 and #4, respectively.
9394
9395 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9396 (also valid for MIPS R4000MC processors):
9397
9398 "52. R4000SC: This bug does not apply for the R4000PC.
9399
9400 There are two flavors of this bug:
9401
9402 1) If the instruction just after divide takes an RF exception
9403 (tlb-refill, tlb-invalid) and gets an instruction cache
9404 miss (both primary and secondary) and the line which is
9405 currently in secondary cache at this index had the first
9406 data word, where the bits 5..2 are set, then R4000 would
9407 get a wrong result for the div.
9408
9409 ##1
9410 nop
9411 div r8, r9
9412 ------------------- # end-of page. -tlb-refill
9413 nop
9414 ##2
9415 nop
9416 div r8, r9
9417 ------------------- # end-of page. -tlb-invalid
9418 nop
9419
9420 2) If the divide is in the taken branch delay slot, where the
9421 target takes RF exception and gets an I-cache miss for the
9422 exception vector or where I-cache miss occurs for the
9423 target address, under the above mentioned scenarios, the
9424 div would get wrong results.
9425
9426 ##1
9427 j r2 # to next page mapped or unmapped
9428 div r8,r9 # this bug would be there as long
9429 # as there is an ICache miss and
9430 nop # the "data pattern" is present
9431
9432 ##2
9433 beq r0, r0, NextPage # to Next page
9434 div r8,r9
9435 nop
9436
9437 This bug is present for div, divu, ddiv, and ddivu
9438 instructions.
9439
9440 Workaround: For item 1), OS could make sure that the next page
9441 after the divide instruction is also mapped. For item 2), the
9442 compiler could make sure that the divide instruction is not in
9443 the branch delay slot."
9444
9445 These processors have PRId values of 0x00004220 and 0x00004300 for
9446 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9447
9448 const char *
mips_output_division(const char * division,rtx * operands)9449 mips_output_division (const char *division, rtx *operands)
9450 {
9451 const char *s;
9452
9453 s = division;
9454 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9455 {
9456 output_asm_insn (s, operands);
9457 s = "nop";
9458 }
9459 if (TARGET_CHECK_ZERO_DIV)
9460 {
9461 if (TARGET_MIPS16)
9462 {
9463 output_asm_insn (s, operands);
9464 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9465 }
9466 else if (GENERATE_DIVIDE_TRAPS)
9467 {
9468 output_asm_insn (s, operands);
9469 s = "teq\t%2,%.,7";
9470 }
9471 else
9472 {
9473 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9474 output_asm_insn (s, operands);
9475 s = "break\t7%)\n1:";
9476 }
9477 }
9478 return s;
9479 }
9480
9481 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9482 with a final "000" replaced by "k". Ignore case.
9483
9484 Note: this function is shared between GCC and GAS. */
9485
9486 static bool
mips_strict_matching_cpu_name_p(const char * canonical,const char * given)9487 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9488 {
9489 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9490 given++, canonical++;
9491
9492 return ((*given == 0 && *canonical == 0)
9493 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9494 }
9495
9496
9497 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9498 CPU name. We've traditionally allowed a lot of variation here.
9499
9500 Note: this function is shared between GCC and GAS. */
9501
9502 static bool
mips_matching_cpu_name_p(const char * canonical,const char * given)9503 mips_matching_cpu_name_p (const char *canonical, const char *given)
9504 {
9505 /* First see if the name matches exactly, or with a final "000"
9506 turned into "k". */
9507 if (mips_strict_matching_cpu_name_p (canonical, given))
9508 return true;
9509
9510 /* If not, try comparing based on numerical designation alone.
9511 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9512 if (TOLOWER (*given) == 'r')
9513 given++;
9514 if (!ISDIGIT (*given))
9515 return false;
9516
9517 /* Skip over some well-known prefixes in the canonical name,
9518 hoping to find a number there too. */
9519 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9520 canonical += 2;
9521 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9522 canonical += 2;
9523 else if (TOLOWER (canonical[0]) == 'r')
9524 canonical += 1;
9525
9526 return mips_strict_matching_cpu_name_p (canonical, given);
9527 }
9528
9529
9530 /* Return the mips_cpu_info entry for the processor or ISA given
9531 by CPU_STRING. Return null if the string isn't recognized.
9532
9533 A similar function exists in GAS. */
9534
9535 static const struct mips_cpu_info *
mips_parse_cpu(const char * cpu_string)9536 mips_parse_cpu (const char *cpu_string)
9537 {
9538 const struct mips_cpu_info *p;
9539 const char *s;
9540
9541 /* In the past, we allowed upper-case CPU names, but it doesn't
9542 work well with the multilib machinery. */
9543 for (s = cpu_string; *s != 0; s++)
9544 if (ISUPPER (*s))
9545 {
9546 warning (0, "the cpu name must be lower case");
9547 break;
9548 }
9549
9550 /* 'from-abi' selects the most compatible architecture for the given
9551 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9552 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9553 version. Look first at the -mgp options, if given, otherwise base
9554 the choice on MASK_64BIT in TARGET_DEFAULT. */
9555 if (strcasecmp (cpu_string, "from-abi") == 0)
9556 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9557 : ABI_NEEDS_64BIT_REGS ? 3
9558 : (TARGET_64BIT ? 3 : 1));
9559
9560 /* 'default' has traditionally been a no-op. Probably not very useful. */
9561 if (strcasecmp (cpu_string, "default") == 0)
9562 return 0;
9563
9564 for (p = mips_cpu_info_table; p->name != 0; p++)
9565 if (mips_matching_cpu_name_p (p->name, cpu_string))
9566 return p;
9567
9568 return 0;
9569 }
9570
9571
9572 /* Return the processor associated with the given ISA level, or null
9573 if the ISA isn't valid. */
9574
9575 static const struct mips_cpu_info *
mips_cpu_info_from_isa(int isa)9576 mips_cpu_info_from_isa (int isa)
9577 {
9578 const struct mips_cpu_info *p;
9579
9580 for (p = mips_cpu_info_table; p->name != 0; p++)
9581 if (p->isa == isa)
9582 return p;
9583
9584 return 0;
9585 }
9586
9587 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9588 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9589 they only hold condition code modes, and CCmode is always considered to
9590 be 4 bytes wide. All other registers are word sized. */
9591
9592 unsigned int
mips_hard_regno_nregs(int regno,enum machine_mode mode)9593 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9594 {
9595 if (ST_REG_P (regno))
9596 return ((GET_MODE_SIZE (mode) + 3) / 4);
9597 else if (! FP_REG_P (regno))
9598 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9599 else
9600 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9601 }
9602
9603 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9604 all BLKmode objects are returned in memory. Under the new (N32 and
9605 64-bit MIPS ABIs) small structures are returned in a register.
9606 Objects with varying size must still be returned in memory, of
9607 course. */
9608
9609 static bool
mips_return_in_memory(tree type,tree fndecl ATTRIBUTE_UNUSED)9610 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9611 {
9612 if (TARGET_OLDABI)
9613 return (TYPE_MODE (type) == BLKmode);
9614 else
9615 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9616 || (int_size_in_bytes (type) == -1));
9617 }
9618
9619 static bool
mips_strict_argument_naming(CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)9620 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9621 {
9622 return !TARGET_OLDABI;
9623 }
9624
9625 /* Return true if INSN is a multiply-add or multiply-subtract
9626 instruction and PREV assigns to the accumulator operand. */
9627
9628 bool
mips_linked_madd_p(rtx prev,rtx insn)9629 mips_linked_madd_p (rtx prev, rtx insn)
9630 {
9631 rtx x;
9632
9633 x = single_set (insn);
9634 if (x == 0)
9635 return false;
9636
9637 x = SET_SRC (x);
9638
9639 if (GET_CODE (x) == PLUS
9640 && GET_CODE (XEXP (x, 0)) == MULT
9641 && reg_set_p (XEXP (x, 1), prev))
9642 return true;
9643
9644 if (GET_CODE (x) == MINUS
9645 && GET_CODE (XEXP (x, 1)) == MULT
9646 && reg_set_p (XEXP (x, 0), prev))
9647 return true;
9648
9649 return false;
9650 }
9651
9652 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9653 that may clobber hi or lo. */
9654
9655 static rtx mips_macc_chains_last_hilo;
9656
9657 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9658 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9659
9660 static void
mips_macc_chains_record(rtx insn)9661 mips_macc_chains_record (rtx insn)
9662 {
9663 if (get_attr_may_clobber_hilo (insn))
9664 mips_macc_chains_last_hilo = insn;
9665 }
9666
9667 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9668 has NREADY elements, looking for a multiply-add or multiply-subtract
9669 instruction that is cumulative with mips_macc_chains_last_hilo.
9670 If there is one, promote it ahead of anything else that might
9671 clobber hi or lo. */
9672
9673 static void
mips_macc_chains_reorder(rtx * ready,int nready)9674 mips_macc_chains_reorder (rtx *ready, int nready)
9675 {
9676 int i, j;
9677
9678 if (mips_macc_chains_last_hilo != 0)
9679 for (i = nready - 1; i >= 0; i--)
9680 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9681 {
9682 for (j = nready - 1; j > i; j--)
9683 if (recog_memoized (ready[j]) >= 0
9684 && get_attr_may_clobber_hilo (ready[j]))
9685 {
9686 mips_promote_ready (ready, i, j);
9687 break;
9688 }
9689 break;
9690 }
9691 }
9692
9693 /* The last instruction to be scheduled. */
9694
9695 static rtx vr4130_last_insn;
9696
9697 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9698 points to an rtx that is initially an instruction. Nullify the rtx
9699 if the instruction uses the value of register X. */
9700
9701 static void
vr4130_true_reg_dependence_p_1(rtx x,rtx pat ATTRIBUTE_UNUSED,void * data)9702 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9703 {
9704 rtx *insn_ptr = data;
9705 if (REG_P (x)
9706 && *insn_ptr != 0
9707 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9708 *insn_ptr = 0;
9709 }
9710
9711 /* Return true if there is true register dependence between vr4130_last_insn
9712 and INSN. */
9713
9714 static bool
vr4130_true_reg_dependence_p(rtx insn)9715 vr4130_true_reg_dependence_p (rtx insn)
9716 {
9717 note_stores (PATTERN (vr4130_last_insn),
9718 vr4130_true_reg_dependence_p_1, &insn);
9719 return insn == 0;
9720 }
9721
9722 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9723 the ready queue and that INSN2 is the instruction after it, return
9724 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9725 in which INSN1 and INSN2 can probably issue in parallel, but for
9726 which (INSN2, INSN1) should be less sensitive to instruction
9727 alignment than (INSN1, INSN2). See 4130.md for more details. */
9728
9729 static bool
vr4130_swap_insns_p(rtx insn1,rtx insn2)9730 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9731 {
9732 rtx dep;
9733
9734 /* Check for the following case:
9735
9736 1) there is some other instruction X with an anti dependence on INSN1;
9737 2) X has a higher priority than INSN2; and
9738 3) X is an arithmetic instruction (and thus has no unit restrictions).
9739
9740 If INSN1 is the last instruction blocking X, it would better to
9741 choose (INSN1, X) over (INSN2, INSN1). */
9742 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9743 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9744 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9745 && recog_memoized (XEXP (dep, 0)) >= 0
9746 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9747 return false;
9748
9749 if (vr4130_last_insn != 0
9750 && recog_memoized (insn1) >= 0
9751 && recog_memoized (insn2) >= 0)
9752 {
9753 /* See whether INSN1 and INSN2 use different execution units,
9754 or if they are both ALU-type instructions. If so, they can
9755 probably execute in parallel. */
9756 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9757 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9758 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9759 {
9760 /* If only one of the instructions has a dependence on
9761 vr4130_last_insn, prefer to schedule the other one first. */
9762 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9763 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9764 if (dep1 != dep2)
9765 return dep1;
9766
9767 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9768 is not an ALU-type instruction and if INSN1 uses the same
9769 execution unit. (Note that if this condition holds, we already
9770 know that INSN2 uses a different execution unit.) */
9771 if (class1 != VR4130_CLASS_ALU
9772 && recog_memoized (vr4130_last_insn) >= 0
9773 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9774 return true;
9775 }
9776 }
9777 return false;
9778 }
9779
9780 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9781 queue with at least two instructions. Swap the first two if
9782 vr4130_swap_insns_p says that it could be worthwhile. */
9783
9784 static void
vr4130_reorder(rtx * ready,int nready)9785 vr4130_reorder (rtx *ready, int nready)
9786 {
9787 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9788 mips_promote_ready (ready, nready - 2, nready - 1);
9789 }
9790
9791 /* Remove the instruction at index LOWER from ready queue READY and
9792 reinsert it in front of the instruction at index HIGHER. LOWER must
9793 be <= HIGHER. */
9794
9795 static void
mips_promote_ready(rtx * ready,int lower,int higher)9796 mips_promote_ready (rtx *ready, int lower, int higher)
9797 {
9798 rtx new_head;
9799 int i;
9800
9801 new_head = ready[lower];
9802 for (i = lower; i < higher; i++)
9803 ready[i] = ready[i + 1];
9804 ready[i] = new_head;
9805 }
9806
9807 /* Implement TARGET_SCHED_REORDER. */
9808
9809 static int
mips_sched_reorder(FILE * file ATTRIBUTE_UNUSED,int verbose ATTRIBUTE_UNUSED,rtx * ready,int * nreadyp,int cycle)9810 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9811 rtx *ready, int *nreadyp, int cycle)
9812 {
9813 if (!reload_completed && TUNE_MACC_CHAINS)
9814 {
9815 if (cycle == 0)
9816 mips_macc_chains_last_hilo = 0;
9817 if (*nreadyp > 0)
9818 mips_macc_chains_reorder (ready, *nreadyp);
9819 }
9820 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9821 {
9822 if (cycle == 0)
9823 vr4130_last_insn = 0;
9824 if (*nreadyp > 1)
9825 vr4130_reorder (ready, *nreadyp);
9826 }
9827 return mips_issue_rate ();
9828 }
9829
9830 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9831
9832 static int
mips_variable_issue(FILE * file ATTRIBUTE_UNUSED,int verbose ATTRIBUTE_UNUSED,rtx insn,int more)9833 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9834 rtx insn, int more)
9835 {
9836 switch (GET_CODE (PATTERN (insn)))
9837 {
9838 case USE:
9839 case CLOBBER:
9840 /* Don't count USEs and CLOBBERs against the issue rate. */
9841 break;
9842
9843 default:
9844 more--;
9845 if (!reload_completed && TUNE_MACC_CHAINS)
9846 mips_macc_chains_record (insn);
9847 vr4130_last_insn = insn;
9848 break;
9849 }
9850 return more;
9851 }
9852
9853 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9854 dependencies have no cost. */
9855
9856 static int
mips_adjust_cost(rtx insn ATTRIBUTE_UNUSED,rtx link,rtx dep ATTRIBUTE_UNUSED,int cost)9857 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9858 rtx dep ATTRIBUTE_UNUSED, int cost)
9859 {
9860 if (REG_NOTE_KIND (link) != 0)
9861 return 0;
9862 return cost;
9863 }
9864
9865 /* Return the number of instructions that can be issued per cycle. */
9866
9867 static int
mips_issue_rate(void)9868 mips_issue_rate (void)
9869 {
9870 switch (mips_tune)
9871 {
9872 case PROCESSOR_R4130:
9873 case PROCESSOR_R5400:
9874 case PROCESSOR_R5500:
9875 case PROCESSOR_R7000:
9876 case PROCESSOR_R9000:
9877 return 2;
9878
9879 case PROCESSOR_SB1:
9880 /* This is actually 4, but we get better performance if we claim 3.
9881 This is partly because of unwanted speculative code motion with the
9882 larger number, and partly because in most common cases we can't
9883 reach the theoretical max of 4. */
9884 return 3;
9885
9886 default:
9887 return 1;
9888 }
9889 }
9890
9891 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9892 be as wide as the scheduling freedom in the DFA. */
9893
9894 static int
mips_multipass_dfa_lookahead(void)9895 mips_multipass_dfa_lookahead (void)
9896 {
9897 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9898 if (mips_tune == PROCESSOR_SB1)
9899 return 4;
9900
9901 return 0;
9902 }
9903
9904 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9905 return the first operand of the associated "pref" or "prefx" insn. */
9906
9907 rtx
mips_prefetch_cookie(rtx write,rtx locality)9908 mips_prefetch_cookie (rtx write, rtx locality)
9909 {
9910 /* store_streamed / load_streamed. */
9911 if (INTVAL (locality) <= 0)
9912 return GEN_INT (INTVAL (write) + 4);
9913
9914 /* store / load. */
9915 if (INTVAL (locality) <= 2)
9916 return write;
9917
9918 /* store_retained / load_retained. */
9919 return GEN_INT (INTVAL (write) + 6);
9920 }
9921
9922 /* MIPS builtin function support. */
9923
9924 struct builtin_description
9925 {
9926 /* The code of the main .md file instruction. See mips_builtin_type
9927 for more information. */
9928 enum insn_code icode;
9929
9930 /* The floating-point comparison code to use with ICODE, if any. */
9931 enum mips_fp_condition cond;
9932
9933 /* The name of the builtin function. */
9934 const char *name;
9935
9936 /* Specifies how the function should be expanded. */
9937 enum mips_builtin_type builtin_type;
9938
9939 /* The function's prototype. */
9940 enum mips_function_type function_type;
9941
9942 /* The target flags required for this function. */
9943 int target_flags;
9944 };
9945
9946 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9947 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
9948 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9949 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9950 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9951
9952 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
9953 TARGET_FLAGS. */
9954 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
9955 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
9956 "__builtin_mips_" #INSN "_" #COND "_s", \
9957 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9958 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
9959 "__builtin_mips_" #INSN "_" #COND "_d", \
9960 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9961
9962 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
9963 The lower and upper forms require TARGET_FLAGS while the any and all
9964 forms require MASK_MIPS3D. */
9965 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
9966 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9967 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
9968 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9969 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9970 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
9971 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9972 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9973 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
9974 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
9975 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9976 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
9977 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
9978
9979 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
9980 require MASK_MIPS3D. */
9981 #define CMP_4S_BUILTINS(INSN, COND) \
9982 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9983 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
9984 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9985 MASK_MIPS3D }, \
9986 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9987 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
9988 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9989 MASK_MIPS3D }
9990
9991 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
9992 instruction requires TARGET_FLAGS. */
9993 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
9994 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9995 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
9996 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9997 TARGET_FLAGS }, \
9998 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9999 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10000 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10001 TARGET_FLAGS }
10002
10003 /* Define all the builtins related to c.cond.fmt condition COND. */
10004 #define CMP_BUILTINS(COND) \
10005 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10006 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10007 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10008 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10009 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10010 CMP_4S_BUILTINS (c, COND), \
10011 CMP_4S_BUILTINS (cabs, COND)
10012
10013 /* __builtin_mips_abs_ps() maps to the standard absM2 pattern. */
10014 #define CODE_FOR_mips_abs_ps CODE_FOR_absv2sf2
10015
10016 static const struct builtin_description mips_bdesc[] =
10017 {
10018 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10019 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10020 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10021 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10022 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
10023 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10024 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10025 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10026
10027 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
10028 MASK_PAIRED_SINGLE_FLOAT),
10029 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10030 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10031 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10032 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10033
10034 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10035 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10036 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10037 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10038 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10039 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10040
10041 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10042 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10043 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10044 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10045 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10046 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10047
10048 MIPS_FP_CONDITIONS (CMP_BUILTINS)
10049 };
10050
10051 /* Builtin functions for the SB-1 processor. */
10052
10053 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10054
10055 static const struct builtin_description sb1_bdesc[] =
10056 {
10057 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
10058 };
10059
10060 /* Builtin functions for DSP ASE. */
10061
10062 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10063 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10064 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10065 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10066
10067 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10068 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10069 builtin_description fields. */
10070 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10071 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10072 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10073
10074 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10075 branch instruction. TARGET_FLAGS is a builtin_description field. */
10076 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10077 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10078 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10079
10080 static const struct builtin_description dsp_bdesc[] =
10081 {
10082 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10083 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10084 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10085 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10086 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10087 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10088 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10089 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10090 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10091 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10092 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10093 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10094 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10095 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
10096 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
10097 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
10098 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10099 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10100 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10101 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10102 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10103 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10104 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10105 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10106 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10107 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10108 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10109 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10110 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10111 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10112 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10113 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10114 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10115 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10116 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10117 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10118 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10119 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10120 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10121 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10122 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10123 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10124 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10125 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10126 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10127 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10128 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10129 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10130 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10131 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10132 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10133 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10134 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10135 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10136 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10137 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10138 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10139 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10140 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10141 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10142 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10143 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10144 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10145 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10146 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10147 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10148 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10149 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10150 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10151 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10152 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10153 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10154 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10155 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10156 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10157 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10158 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10159 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10160 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10161 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10162 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10163 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10164 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10165 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10166 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10167 BPOSGE_BUILTIN (32, MASK_DSP)
10168 };
10169
10170 /* This helps provide a mapping from builtin function codes to bdesc
10171 arrays. */
10172
10173 struct bdesc_map
10174 {
10175 /* The builtin function table that this entry describes. */
10176 const struct builtin_description *bdesc;
10177
10178 /* The number of entries in the builtin function table. */
10179 unsigned int size;
10180
10181 /* The target processor that supports these builtin functions.
10182 PROCESSOR_MAX means we enable them for all processors. */
10183 enum processor_type proc;
10184 };
10185
10186 static const struct bdesc_map bdesc_arrays[] =
10187 {
10188 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
10189 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },
10190 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
10191 };
10192
10193 /* Take the head of argument list *ARGLIST and convert it into a form
10194 suitable for input operand OP of instruction ICODE. Return the value
10195 and point *ARGLIST at the next element of the list. */
10196
10197 static rtx
mips_prepare_builtin_arg(enum insn_code icode,unsigned int op,tree * arglist)10198 mips_prepare_builtin_arg (enum insn_code icode,
10199 unsigned int op, tree *arglist)
10200 {
10201 rtx value;
10202 enum machine_mode mode;
10203
10204 value = expand_expr (TREE_VALUE (*arglist), NULL_RTX, VOIDmode, 0);
10205 mode = insn_data[icode].operand[op].mode;
10206 if (!insn_data[icode].operand[op].predicate (value, mode))
10207 {
10208 value = copy_to_mode_reg (mode, value);
10209 /* Check the predicate again. */
10210 if (!insn_data[icode].operand[op].predicate (value, mode))
10211 {
10212 error ("invalid argument to builtin function");
10213 return const0_rtx;
10214 }
10215 }
10216
10217 *arglist = TREE_CHAIN (*arglist);
10218 return value;
10219 }
10220
10221 /* Return an rtx suitable for output operand OP of instruction ICODE.
10222 If TARGET is non-null, try to use it where possible. */
10223
10224 static rtx
mips_prepare_builtin_target(enum insn_code icode,unsigned int op,rtx target)10225 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10226 {
10227 enum machine_mode mode;
10228
10229 mode = insn_data[icode].operand[op].mode;
10230 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10231 target = gen_reg_rtx (mode);
10232
10233 return target;
10234 }
10235
10236 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10237
10238 rtx
mips_expand_builtin(tree exp,rtx target,rtx subtarget ATTRIBUTE_UNUSED,enum machine_mode mode ATTRIBUTE_UNUSED,int ignore ATTRIBUTE_UNUSED)10239 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10240 enum machine_mode mode ATTRIBUTE_UNUSED,
10241 int ignore ATTRIBUTE_UNUSED)
10242 {
10243 enum insn_code icode;
10244 enum mips_builtin_type type;
10245 tree fndecl, arglist;
10246 unsigned int fcode;
10247 const struct builtin_description *bdesc;
10248 const struct bdesc_map *m;
10249
10250 fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
10251 arglist = TREE_OPERAND (exp, 1);
10252 fcode = DECL_FUNCTION_CODE (fndecl);
10253
10254 bdesc = NULL;
10255 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10256 {
10257 if (fcode < m->size)
10258 {
10259 bdesc = m->bdesc;
10260 icode = bdesc[fcode].icode;
10261 type = bdesc[fcode].builtin_type;
10262 break;
10263 }
10264 fcode -= m->size;
10265 }
10266 if (bdesc == NULL)
10267 return 0;
10268
10269 switch (type)
10270 {
10271 case MIPS_BUILTIN_DIRECT:
10272 return mips_expand_builtin_direct (icode, target, arglist, true);
10273
10274 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10275 return mips_expand_builtin_direct (icode, target, arglist, false);
10276
10277 case MIPS_BUILTIN_MOVT:
10278 case MIPS_BUILTIN_MOVF:
10279 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
10280 target, arglist);
10281
10282 case MIPS_BUILTIN_CMP_ANY:
10283 case MIPS_BUILTIN_CMP_ALL:
10284 case MIPS_BUILTIN_CMP_UPPER:
10285 case MIPS_BUILTIN_CMP_LOWER:
10286 case MIPS_BUILTIN_CMP_SINGLE:
10287 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
10288 target, arglist);
10289
10290 case MIPS_BUILTIN_BPOSGE32:
10291 return mips_expand_builtin_bposge (type, target);
10292
10293 default:
10294 return 0;
10295 }
10296 }
10297
10298 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10299
10300 void
mips_init_builtins(void)10301 mips_init_builtins (void)
10302 {
10303 const struct builtin_description *d;
10304 const struct bdesc_map *m;
10305 tree types[(int) MIPS_MAX_FTYPE_MAX];
10306 tree V2SF_type_node;
10307 tree V2HI_type_node;
10308 tree V4QI_type_node;
10309 unsigned int offset;
10310
10311 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
10312 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
10313 return;
10314
10315 if (TARGET_PAIRED_SINGLE_FLOAT)
10316 {
10317 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
10318
10319 types[MIPS_V2SF_FTYPE_V2SF]
10320 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
10321
10322 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
10323 = build_function_type_list (V2SF_type_node,
10324 V2SF_type_node, V2SF_type_node, NULL_TREE);
10325
10326 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
10327 = build_function_type_list (V2SF_type_node,
10328 V2SF_type_node, V2SF_type_node,
10329 integer_type_node, NULL_TREE);
10330
10331 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
10332 = build_function_type_list (V2SF_type_node,
10333 V2SF_type_node, V2SF_type_node,
10334 V2SF_type_node, V2SF_type_node, NULL_TREE);
10335
10336 types[MIPS_V2SF_FTYPE_SF_SF]
10337 = build_function_type_list (V2SF_type_node,
10338 float_type_node, float_type_node, NULL_TREE);
10339
10340 types[MIPS_INT_FTYPE_V2SF_V2SF]
10341 = build_function_type_list (integer_type_node,
10342 V2SF_type_node, V2SF_type_node, NULL_TREE);
10343
10344 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
10345 = build_function_type_list (integer_type_node,
10346 V2SF_type_node, V2SF_type_node,
10347 V2SF_type_node, V2SF_type_node, NULL_TREE);
10348
10349 types[MIPS_INT_FTYPE_SF_SF]
10350 = build_function_type_list (integer_type_node,
10351 float_type_node, float_type_node, NULL_TREE);
10352
10353 types[MIPS_INT_FTYPE_DF_DF]
10354 = build_function_type_list (integer_type_node,
10355 double_type_node, double_type_node, NULL_TREE);
10356
10357 types[MIPS_SF_FTYPE_V2SF]
10358 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
10359
10360 types[MIPS_SF_FTYPE_SF]
10361 = build_function_type_list (float_type_node,
10362 float_type_node, NULL_TREE);
10363
10364 types[MIPS_SF_FTYPE_SF_SF]
10365 = build_function_type_list (float_type_node,
10366 float_type_node, float_type_node, NULL_TREE);
10367
10368 types[MIPS_DF_FTYPE_DF]
10369 = build_function_type_list (double_type_node,
10370 double_type_node, NULL_TREE);
10371
10372 types[MIPS_DF_FTYPE_DF_DF]
10373 = build_function_type_list (double_type_node,
10374 double_type_node, double_type_node, NULL_TREE);
10375 }
10376
10377 if (TARGET_DSP)
10378 {
10379 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
10380 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
10381
10382 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
10383 = build_function_type_list (V2HI_type_node,
10384 V2HI_type_node, V2HI_type_node,
10385 NULL_TREE);
10386
10387 types[MIPS_SI_FTYPE_SI_SI]
10388 = build_function_type_list (intSI_type_node,
10389 intSI_type_node, intSI_type_node,
10390 NULL_TREE);
10391
10392 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
10393 = build_function_type_list (V4QI_type_node,
10394 V4QI_type_node, V4QI_type_node,
10395 NULL_TREE);
10396
10397 types[MIPS_SI_FTYPE_V4QI]
10398 = build_function_type_list (intSI_type_node,
10399 V4QI_type_node,
10400 NULL_TREE);
10401
10402 types[MIPS_V2HI_FTYPE_V2HI]
10403 = build_function_type_list (V2HI_type_node,
10404 V2HI_type_node,
10405 NULL_TREE);
10406
10407 types[MIPS_SI_FTYPE_SI]
10408 = build_function_type_list (intSI_type_node,
10409 intSI_type_node,
10410 NULL_TREE);
10411
10412 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
10413 = build_function_type_list (V4QI_type_node,
10414 V2HI_type_node, V2HI_type_node,
10415 NULL_TREE);
10416
10417 types[MIPS_V2HI_FTYPE_SI_SI]
10418 = build_function_type_list (V2HI_type_node,
10419 intSI_type_node, intSI_type_node,
10420 NULL_TREE);
10421
10422 types[MIPS_SI_FTYPE_V2HI]
10423 = build_function_type_list (intSI_type_node,
10424 V2HI_type_node,
10425 NULL_TREE);
10426
10427 types[MIPS_V2HI_FTYPE_V4QI]
10428 = build_function_type_list (V2HI_type_node,
10429 V4QI_type_node,
10430 NULL_TREE);
10431
10432 types[MIPS_V4QI_FTYPE_V4QI_SI]
10433 = build_function_type_list (V4QI_type_node,
10434 V4QI_type_node, intSI_type_node,
10435 NULL_TREE);
10436
10437 types[MIPS_V2HI_FTYPE_V2HI_SI]
10438 = build_function_type_list (V2HI_type_node,
10439 V2HI_type_node, intSI_type_node,
10440 NULL_TREE);
10441
10442 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
10443 = build_function_type_list (V2HI_type_node,
10444 V4QI_type_node, V2HI_type_node,
10445 NULL_TREE);
10446
10447 types[MIPS_SI_FTYPE_V2HI_V2HI]
10448 = build_function_type_list (intSI_type_node,
10449 V2HI_type_node, V2HI_type_node,
10450 NULL_TREE);
10451
10452 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
10453 = build_function_type_list (intDI_type_node,
10454 intDI_type_node, V4QI_type_node, V4QI_type_node,
10455 NULL_TREE);
10456
10457 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
10458 = build_function_type_list (intDI_type_node,
10459 intDI_type_node, V2HI_type_node, V2HI_type_node,
10460 NULL_TREE);
10461
10462 types[MIPS_DI_FTYPE_DI_SI_SI]
10463 = build_function_type_list (intDI_type_node,
10464 intDI_type_node, intSI_type_node, intSI_type_node,
10465 NULL_TREE);
10466
10467 types[MIPS_V4QI_FTYPE_SI]
10468 = build_function_type_list (V4QI_type_node,
10469 intSI_type_node,
10470 NULL_TREE);
10471
10472 types[MIPS_V2HI_FTYPE_SI]
10473 = build_function_type_list (V2HI_type_node,
10474 intSI_type_node,
10475 NULL_TREE);
10476
10477 types[MIPS_VOID_FTYPE_V4QI_V4QI]
10478 = build_function_type_list (void_type_node,
10479 V4QI_type_node, V4QI_type_node,
10480 NULL_TREE);
10481
10482 types[MIPS_SI_FTYPE_V4QI_V4QI]
10483 = build_function_type_list (intSI_type_node,
10484 V4QI_type_node, V4QI_type_node,
10485 NULL_TREE);
10486
10487 types[MIPS_VOID_FTYPE_V2HI_V2HI]
10488 = build_function_type_list (void_type_node,
10489 V2HI_type_node, V2HI_type_node,
10490 NULL_TREE);
10491
10492 types[MIPS_SI_FTYPE_DI_SI]
10493 = build_function_type_list (intSI_type_node,
10494 intDI_type_node, intSI_type_node,
10495 NULL_TREE);
10496
10497 types[MIPS_DI_FTYPE_DI_SI]
10498 = build_function_type_list (intDI_type_node,
10499 intDI_type_node, intSI_type_node,
10500 NULL_TREE);
10501
10502 types[MIPS_VOID_FTYPE_SI_SI]
10503 = build_function_type_list (void_type_node,
10504 intSI_type_node, intSI_type_node,
10505 NULL_TREE);
10506
10507 types[MIPS_SI_FTYPE_PTR_SI]
10508 = build_function_type_list (intSI_type_node,
10509 ptr_type_node, intSI_type_node,
10510 NULL_TREE);
10511
10512 types[MIPS_SI_FTYPE_VOID]
10513 = build_function_type (intSI_type_node, void_list_node);
10514 }
10515
10516 /* Iterate through all of the bdesc arrays, initializing all of the
10517 builtin functions. */
10518
10519 offset = 0;
10520 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10521 {
10522 if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10523 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10524 if ((d->target_flags & target_flags) == d->target_flags)
10525 lang_hooks.builtin_function (d->name, types[d->function_type],
10526 d - m->bdesc + offset,
10527 BUILT_IN_MD, NULL, NULL);
10528 offset += m->size;
10529 }
10530 }
10531
10532 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10533 .md pattern and ARGLIST is the list of function arguments. TARGET,
10534 if nonnull, suggests a good place to put the result.
10535 HAS_TARGET indicates the function must return something. */
10536
10537 static rtx
mips_expand_builtin_direct(enum insn_code icode,rtx target,tree arglist,bool has_target)10538 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist,
10539 bool has_target)
10540 {
10541 rtx ops[MAX_RECOG_OPERANDS];
10542 int i = 0;
10543
10544 if (has_target)
10545 {
10546 /* We save target to ops[0]. */
10547 ops[0] = mips_prepare_builtin_target (icode, 0, target);
10548 i = 1;
10549 }
10550
10551 /* We need to test if arglist is not zero. Some instructions have extra
10552 clobber registers. */
10553 for (; i < insn_data[icode].n_operands && arglist != 0; i++)
10554 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10555
10556 switch (i)
10557 {
10558 case 2:
10559 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10560 break;
10561
10562 case 3:
10563 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10564 break;
10565
10566 case 4:
10567 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10568 break;
10569
10570 default:
10571 gcc_unreachable ();
10572 }
10573 return target;
10574 }
10575
10576 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10577 function (TYPE says which). ARGLIST is the list of arguments to the
10578 function, ICODE is the instruction that should be used to compare
10579 the first two arguments, and COND is the condition it should test.
10580 TARGET, if nonnull, suggests a good place to put the result. */
10581
10582 static rtx
mips_expand_builtin_movtf(enum mips_builtin_type type,enum insn_code icode,enum mips_fp_condition cond,rtx target,tree arglist)10583 mips_expand_builtin_movtf (enum mips_builtin_type type,
10584 enum insn_code icode, enum mips_fp_condition cond,
10585 rtx target, tree arglist)
10586 {
10587 rtx cmp_result, op0, op1;
10588
10589 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10590 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10591 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10592 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10593
10594 icode = CODE_FOR_mips_cond_move_tf_ps;
10595 target = mips_prepare_builtin_target (icode, 0, target);
10596 if (type == MIPS_BUILTIN_MOVT)
10597 {
10598 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10599 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10600 }
10601 else
10602 {
10603 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10604 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10605 }
10606 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10607 return target;
10608 }
10609
10610 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10611 of the comparison instruction and COND is the condition it should test.
10612 ARGLIST is the list of function arguments and TARGET, if nonnull,
10613 suggests a good place to put the boolean result. */
10614
10615 static rtx
mips_expand_builtin_compare(enum mips_builtin_type builtin_type,enum insn_code icode,enum mips_fp_condition cond,rtx target,tree arglist)10616 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10617 enum insn_code icode, enum mips_fp_condition cond,
10618 rtx target, tree arglist)
10619 {
10620 rtx label1, label2, if_then_else;
10621 rtx pat, cmp_result, ops[MAX_RECOG_OPERANDS];
10622 rtx target_if_equal, target_if_unequal;
10623 int cmp_value, i;
10624
10625 if (target == 0 || GET_MODE (target) != SImode)
10626 target = gen_reg_rtx (SImode);
10627
10628 /* Prepare the operands to the comparison. */
10629 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10630 for (i = 1; i < insn_data[icode].n_operands - 1; i++)
10631 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10632
10633 switch (insn_data[icode].n_operands)
10634 {
10635 case 4:
10636 pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond));
10637 break;
10638
10639 case 6:
10640 pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10641 ops[3], ops[4], GEN_INT (cond));
10642 break;
10643
10644 default:
10645 gcc_unreachable ();
10646 }
10647
10648 /* If the comparison sets more than one register, we define the result
10649 to be 0 if all registers are false and -1 if all registers are true.
10650 The value of the complete result is indeterminate otherwise. It is
10651 possible to test individual registers using SUBREGs.
10652
10653 Set up CMP_RESULT, CMP_VALUE, TARGET_IF_EQUAL and TARGET_IF_UNEQUAL so
10654 that the result should be TARGET_IF_EQUAL if (EQ CMP_RESULT CMP_VALUE)
10655 and TARGET_IF_UNEQUAL otherwise. */
10656 if (builtin_type == MIPS_BUILTIN_CMP_ALL)
10657 {
10658 cmp_value = -1;
10659 target_if_equal = const1_rtx;
10660 target_if_unequal = const0_rtx;
10661 }
10662 else
10663 {
10664 cmp_value = 0;
10665 target_if_equal = const0_rtx;
10666 target_if_unequal = const1_rtx;
10667 if (builtin_type == MIPS_BUILTIN_CMP_UPPER)
10668 cmp_result = simplify_gen_subreg (CCmode, cmp_result, CCV2mode, 4);
10669 else if (builtin_type == MIPS_BUILTIN_CMP_LOWER)
10670 cmp_result = simplify_gen_subreg (CCmode, cmp_result, CCV2mode, 0);
10671 }
10672
10673 /* First assume that CMP_RESULT == CMP_VALUE. */
10674 emit_move_insn (target, target_if_equal);
10675
10676 /* Branch to LABEL1 if CMP_RESULT != CMP_VALUE. */
10677 emit_insn (pat);
10678 label1 = gen_label_rtx ();
10679 label2 = gen_label_rtx ();
10680 if_then_else
10681 = gen_rtx_IF_THEN_ELSE (VOIDmode,
10682 gen_rtx_fmt_ee (NE, GET_MODE (cmp_result),
10683 cmp_result, GEN_INT (cmp_value)),
10684 gen_rtx_LABEL_REF (VOIDmode, label1), pc_rtx);
10685 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_then_else));
10686 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10687 gen_rtx_LABEL_REF (VOIDmode, label2)));
10688 emit_barrier ();
10689 emit_label (label1);
10690
10691 /* Fix TARGET for CMP_RESULT != CMP_VALUE. */
10692 emit_move_insn (target, target_if_unequal);
10693 emit_label (label2);
10694
10695 return target;
10696 }
10697
10698 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10699 suggests a good place to put the boolean result.
10700
10701 The sequence we want is
10702
10703 li target, 0
10704 bposge* label1
10705 j label2
10706 label1:
10707 li target, 1
10708 label2: */
10709
10710 static rtx
mips_expand_builtin_bposge(enum mips_builtin_type builtin_type,rtx target)10711 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10712 {
10713 rtx label1, label2, if_then_else;
10714 rtx cmp_result;
10715 int cmp_value;
10716
10717 if (target == 0 || GET_MODE (target) != SImode)
10718 target = gen_reg_rtx (SImode);
10719
10720 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10721
10722 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10723 cmp_value = 32;
10724 else
10725 gcc_assert (0);
10726
10727 /* Move 0 to target */
10728 emit_move_insn (target, const0_rtx);
10729
10730 /* Generate two labels */
10731 label1 = gen_label_rtx ();
10732 label2 = gen_label_rtx ();
10733
10734 /* Generate if_then_else */
10735 if_then_else
10736 = gen_rtx_IF_THEN_ELSE (VOIDmode,
10737 gen_rtx_fmt_ee (GE, CCDSPmode,
10738 cmp_result, GEN_INT (cmp_value)),
10739 gen_rtx_LABEL_REF (VOIDmode, label1), pc_rtx);
10740
10741 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_then_else));
10742 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10743 gen_rtx_LABEL_REF (VOIDmode, label2)));
10744 emit_barrier ();
10745 emit_label (label1);
10746 emit_move_insn (target, const1_rtx);
10747 emit_label (label2);
10748
10749 return target;
10750 }
10751
10752 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
10753 FIRST is true if this is the first time handling this decl. */
10754
10755 static void
mips_encode_section_info(tree decl,rtx rtl,int first)10756 mips_encode_section_info (tree decl, rtx rtl, int first)
10757 {
10758 default_encode_section_info (decl, rtl, first);
10759
10760 if (TREE_CODE (decl) == FUNCTION_DECL
10761 && lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
10762 {
10763 rtx symbol = XEXP (rtl, 0);
10764 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
10765 }
10766 }
10767
10768 #include "gt-mips.h"
10769