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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h281 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
286 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
398 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
401 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
404 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
407 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
410 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
413 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
417 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
420 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h294 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
299 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
411 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
414 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
417 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
420 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
423 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
426 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
430 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
433 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h272 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
277 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
353 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
356 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
359 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
362 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
365 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
368 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
372 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
375 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h294 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
299 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
411 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
414 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
417 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
420 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
423 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
426 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
430 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
433 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h294 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
299 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
411 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
414 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
417 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
420 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
423 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
426 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
430 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
433 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h272 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
277 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
353 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
356 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
359 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
362 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
365 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
368 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
372 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
375 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h294 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
299 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
411 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
414 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
417 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
420 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
423 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
426 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
430 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
433 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h294 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
299 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
411 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
414 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
417 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
420 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
423 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
426 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
430 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
433 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h294 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
299 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
411 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
414 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
417 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
420 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
423 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
426 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
430 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
433 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h272 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
277 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
353 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
356 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
359 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
362 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
365 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
368 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
372 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
375 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h294 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
299 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
411 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
414 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
417 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
420 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
423 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
426 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
430 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
433 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h259 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
264 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
305 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
308 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
311 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
314 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
317 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
320 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
324 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
327 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h277 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
282 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
358 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
361 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
364 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
367 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
370 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
373 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
377 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
380 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h277 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
282 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
358 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
361 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
364 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
367 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
370 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
373 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
377 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
380 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h295 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
300 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
412 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
415 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
418 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
421 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
424 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
427 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
431 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
434 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/include/llvm/CodeGen/GlobalISel/
H A DIRTranslator.h268 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateICmp()
273 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) { in translateFCmp()
349 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAdd()
352 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateSub()
355 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) { in translateAnd()
358 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) { in translateMul()
361 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) { in translateOr()
364 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) { in translateXor()
368 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateUDiv()
371 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) { in translateSDiv()
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVCallLowering.cpp24 bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, in lowerReturn()
38 MachineIRBuilder &MIRBuilder, const Function &F, in lowerFormalArguments()
47 bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, in lowerCall()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/RISCV/
H A DRISCVCallLowering.cpp24 bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, in lowerReturn()
38 MachineIRBuilder &MIRBuilder, const Function &F, in lowerFormalArguments()
47 bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, in lowerCall()
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/RISCV/
H A DRISCVCallLowering.cpp24 bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, in lowerReturn()
38 MachineIRBuilder &MIRBuilder, const Function &F, in lowerFormalArguments()
47 bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, in lowerCall()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/RISCV/
H A DRISCVCallLowering.cpp24 bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, in lowerReturn()
38 MachineIRBuilder &MIRBuilder, const Function &F, in lowerFormalArguments()
47 bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, in lowerCall()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
H A DRISCVCallLowering.cpp24 bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, in lowerReturn()
38 MachineIRBuilder &MIRBuilder, const Function &F, in lowerFormalArguments()
47 bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, in lowerCall()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/RISCV/
H A DRISCVCallLowering.cpp24 bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, in lowerReturn()
38 MachineIRBuilder &MIRBuilder, const Function &F, in lowerFormalArguments()
47 bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, in lowerCall()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp26 bool PPCCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, in lowerReturn()
39 MachineIRBuilder &MIRBuilder, const Function &F, in lowerFormalArguments()
48 bool PPCCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, in lowerCall()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVCallLowering.cpp24 bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, in lowerReturn()
37 bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, in lowerFormalArguments()
48 bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, in lowerCall()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/RISCV/
H A DRISCVCallLowering.cpp24 bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, in lowerReturn()
37 bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, in lowerFormalArguments()
48 bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, in lowerCall()

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