1 /* $OpenBSD: timekeeper.h,v 1.4 2017/11/03 06:54:06 aoyama Exp $ */ 2 /* $NetBSD: timekeeper.h,v 1.1 2000/01/05 08:48:56 nisimura Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Tohru Nishimura. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Mostek MK48T02 for LUNA-88K 35 */ 36 #define MK_CSR 0 /* control register */ 37 #define MK_SEC 1 /* seconds (0..59; BCD) */ 38 #define MK_MIN 2 /* minutes (0..59; BCD) */ 39 #define MK_HOUR 3 /* hour (0..23; BCD) */ 40 #define MK_DOW 4 /* weekday (1..7) */ 41 #define MK_DOM 5 /* day in month (1..31; BCD) */ 42 #define MK_MONTH 6 /* month (1..12; BCD) */ 43 #define MK_YEAR 7 /* year (0..99; BCD) */ 44 /* bits in cl_csr */ 45 #define MK_CSR_WRITE 0x80 /* want to write */ 46 #define MK_CSR_READ 0x40 /* want to read (freeze clock) */ 47 /* NVRAM space is mapped with 4-bytes stride */ 48 #define MK_NVRAM_SPACE (4 * (2048 - 8)) 49 50 /* 51 * Dallas Semiconductor DS1397 for LUNA-88K2 52 */ 53 #define DS_SEC 0x0 /* Time of year: seconds (0-59) */ 54 #define DS_MIN 0x2 /* Time of year: minutes (0-59) */ 55 #define DS_HOUR 0x4 /* Time of year: hour (see above) */ 56 #define DS_DOW 0x6 /* Time of year: day of week (1-7) */ 57 #define DS_DOM 0x7 /* Time of year: day of month (1-31) */ 58 #define DS_MONTH 0x8 /* Time of year: month (1-12) */ 59 #define DS_YEAR 0x9 /* Time of year: year in century (0-99) */ 60 61 #define DS_REGA 0xa /* Control register A */ 62 #define DS_REGA_RSMASK 0x0f /* Interrupt rate select mask (see below) */ 63 #define DS_REGA_DVMASK 0x70 /* Divisor select mask (see below) */ 64 #define DS_REGA_UIP 0x80 /* Update in progress; read only. */ 65 66 #define DS_REGB 0xb /* Control register B */ 67 #define DS_REGB_DSE 0x01 /* Daylight Savings Enable */ 68 #define DS_REGB_24HR 0x02 /* 24-hour mode (AM/PM mode when clear) */ 69 #define DS_REGB_BINARY 0x04 /* Binary mode (BCD mode when clear) */ 70 #define DS_REGB_SQWE 0x08 /* Square Wave Enable */ 71 #define DS_REGB_UIE 0x10 /* Update End interrupt enable */ 72 #define DS_REGB_AIE 0x20 /* Alarm interrupt enable */ 73 #define DS_REGB_PIE 0x40 /* Periodic interrupt enable */ 74 #define DS_REGB_SET 0x80 /* Allow time to be set; stops updates */ 75 76 #define DS_REGC 0xc /* Control register C */ 77 /* DS_REGC_UNUSED 0x0f UNUSED */ 78 #define DS_REGC_UF 0x10 /* Update End interrupt flag */ 79 #define DS_REGC_AF 0x20 /* Alarm interrupt flag */ 80 #define DS_REGC_PF 0x40 /* Periodic interrupt flag */ 81 #define DS_REGC_IRQF 0x80 /* Interrupt request pending flag */ 82 83 #define DS_REGD 0xd /* Control register D */ 84 /* DS_REGD_UNUSED 0x7f UNUSED */ 85 #define DS_REGD_VRT 0x80 /* Valid RAM and Time bit */ 86 87 #define DS_NREGS 0xe /* 14 registers; CMOS follows */ 88 #define DS_NTODREGS 0xa /* 10 of those regs are for TOD and alarm */ 89