1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
39 #include <linux/types.h>
40 #include <linux/bitops.h>
41 #include <linux/workqueue.h>
42 #include <linux/if_ether.h>
43 #include <linux/mutex.h>
44
45 #include <asm/atomic.h>
46
47 #include <linux/clocksource.h>
48
49 #define DEFAULT_UAR_PAGE_SHIFT 12
50
51 #define MAX_MSIX_P_PORT 17
52 #define MAX_MSIX 64
53 #define MIN_MSIX_P_PORT 5
54 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
55 (dev_cap).num_ports * MIN_MSIX_P_PORT)
56
57 #define MLX4_MAX_100M_UNITS_VAL 255 /*
58 * work around: can't set values
59 * greater then this value when
60 * using 100 Mbps units.
61 */
62 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
63 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
64 #define MLX4_RATELIMIT_DEFAULT 0x00ff
65
66 #define MLX4_ROCE_MAX_GIDS 128
67 #define MLX4_ROCE_PF_GIDS 16
68
69 #define CORE_CLOCK_MASK 0xffffffffffffULL
70
71 enum {
72 MLX4_FLAG_MSI_X = 1 << 0,
73 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
74 MLX4_FLAG_MASTER = 1 << 2,
75 MLX4_FLAG_SLAVE = 1 << 3,
76 MLX4_FLAG_SRIOV = 1 << 4,
77 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
78 MLX4_FLAG_BONDED = 1 << 7,
79 MLX4_FLAG_SECURE_HOST = 1 << 8,
80 };
81
82 enum {
83 MLX4_PORT_CAP_IS_SM = 1 << 1,
84 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
85 };
86
87 enum {
88 MLX4_MAX_PORTS = 2,
89 MLX4_MAX_PORT_PKEYS = 128,
90 MLX4_MAX_PORT_GIDS = 128
91 };
92
93 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
94 * These qkeys must not be allowed for general use. This is a 64k range,
95 * and to test for violation, we use the mask (protect against future chg).
96 */
97 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
98 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
99
100 enum {
101 MLX4_BOARD_ID_LEN = 64
102 };
103
104 enum {
105 MLX4_MAX_NUM_PF = 16,
106 MLX4_MAX_NUM_VF = 126,
107 MLX4_MAX_NUM_VF_P_PORT = 64,
108 MLX4_MFUNC_MAX = 128,
109 MLX4_MAX_EQ_NUM = 1024,
110 MLX4_MFUNC_EQ_NUM = 4,
111 MLX4_MFUNC_MAX_EQES = 8,
112 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
113 };
114
115 /* Driver supports 3 different device methods to manage traffic steering:
116 * -device managed - High level API for ib and eth flow steering. FW is
117 * managing flow steering tables.
118 * - B0 steering mode - Common low level API for ib and (if supported) eth.
119 * - A0 steering mode - Limited low level API for eth. In case of IB,
120 * B0 mode is in use.
121 */
122 enum {
123 MLX4_STEERING_MODE_A0,
124 MLX4_STEERING_MODE_B0,
125 MLX4_STEERING_MODE_DEVICE_MANAGED
126 };
127
128 enum {
129 MLX4_STEERING_DMFS_A0_DEFAULT,
130 MLX4_STEERING_DMFS_A0_DYNAMIC,
131 MLX4_STEERING_DMFS_A0_STATIC,
132 MLX4_STEERING_DMFS_A0_DISABLE,
133 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
134 };
135
mlx4_steering_mode_str(int steering_mode)136 static inline const char *mlx4_steering_mode_str(int steering_mode)
137 {
138 switch (steering_mode) {
139 case MLX4_STEERING_MODE_A0:
140 return "A0 steering";
141
142 case MLX4_STEERING_MODE_B0:
143 return "B0 steering";
144
145 case MLX4_STEERING_MODE_DEVICE_MANAGED:
146 return "Device managed flow steering";
147
148 default:
149 return "Unrecognize steering mode";
150 }
151 }
152
153 enum {
154 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
155 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
156 };
157
158 enum {
159 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
160 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
161 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
162 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
163 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
164 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
165 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
166 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
167 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
168 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
169 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
170 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
171 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
172 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
173 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
174 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
175 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
176 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
177 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
178 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
179 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
180 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
181 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
182 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
183 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
184 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52,
185 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
186 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
187 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
188 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
189 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
190 };
191
192 enum {
193 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
194 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
195 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
196 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
197 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
198 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
199 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
200 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
201 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
202 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
203 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
204 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
205 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
206 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
207 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
208 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
209 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
210 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
211 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
212 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
213 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
214 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
215 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
216 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23,
217 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24,
218 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25,
219 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26,
220 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27,
221 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28,
222 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29,
223 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30,
224 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
225 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32,
226 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33,
227 MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34,
228 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT = 1ULL << 35,
229 MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP = 1ULL << 36,
230 MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37,
231 };
232
233 enum {
234 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
235 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
236 };
237
238 enum {
239 MLX4_VF_CAP_FLAG_RESET = 1 << 0
240 };
241
242 /* bit enums for an 8-bit flags field indicating special use
243 * QPs which require special handling in qp_reserve_range.
244 * Currently, this only includes QPs used by the ETH interface,
245 * where we expect to use blueflame. These QPs must not have
246 * bits 6 and 7 set in their qp number.
247 *
248 * This enum may use only bits 0..7.
249 */
250 enum {
251 MLX4_RESERVE_A0_QP = 1 << 6,
252 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
253 };
254
255 enum {
256 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
257 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
258 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
259 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
260 };
261
262 enum {
263 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
264 };
265
266 enum {
267 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
268 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
269 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
270 };
271
272
273 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
274
275 enum {
276 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
277 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
278 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
279 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
280 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
281 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
282 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19,
283 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
284 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
285 };
286
287 enum {
288 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP,
289 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2
290 };
291
292 enum mlx4_event {
293 MLX4_EVENT_TYPE_COMP = 0x00,
294 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
295 MLX4_EVENT_TYPE_COMM_EST = 0x02,
296 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
297 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
298 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
299 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
300 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
301 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
302 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
303 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
304 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
305 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
306 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
307 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
308 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
309 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
310 MLX4_EVENT_TYPE_CMD = 0x0a,
311 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
312 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
313 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
314 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
315 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
316 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
317 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
318 MLX4_EVENT_TYPE_NONE = 0xff,
319 };
320
321 enum {
322 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
323 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
324 };
325
326 enum {
327 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
328 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
329 };
330
331 enum {
332 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
333 };
334
335 enum slave_port_state {
336 SLAVE_PORT_DOWN = 0,
337 SLAVE_PENDING_UP,
338 SLAVE_PORT_UP,
339 };
340
341 enum slave_port_gen_event {
342 SLAVE_PORT_GEN_EVENT_DOWN = 0,
343 SLAVE_PORT_GEN_EVENT_UP,
344 SLAVE_PORT_GEN_EVENT_NONE,
345 };
346
347 enum slave_port_state_event {
348 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
349 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
350 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
351 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
352 };
353
354 enum {
355 MLX4_PERM_LOCAL_READ = 1 << 10,
356 MLX4_PERM_LOCAL_WRITE = 1 << 11,
357 MLX4_PERM_REMOTE_READ = 1 << 12,
358 MLX4_PERM_REMOTE_WRITE = 1 << 13,
359 MLX4_PERM_ATOMIC = 1 << 14,
360 MLX4_PERM_BIND_MW = 1 << 15,
361 MLX4_PERM_MASK = 0xFC00
362 };
363
364 enum {
365 MLX4_OPCODE_NOP = 0x00,
366 MLX4_OPCODE_SEND_INVAL = 0x01,
367 MLX4_OPCODE_RDMA_WRITE = 0x08,
368 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
369 MLX4_OPCODE_SEND = 0x0a,
370 MLX4_OPCODE_SEND_IMM = 0x0b,
371 MLX4_OPCODE_LSO = 0x0e,
372 MLX4_OPCODE_RDMA_READ = 0x10,
373 MLX4_OPCODE_ATOMIC_CS = 0x11,
374 MLX4_OPCODE_ATOMIC_FA = 0x12,
375 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
376 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
377 MLX4_OPCODE_BIND_MW = 0x18,
378 MLX4_OPCODE_FMR = 0x19,
379 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
380 MLX4_OPCODE_CONFIG_CMD = 0x1f,
381
382 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
383 MLX4_RECV_OPCODE_SEND = 0x01,
384 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
385 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
386
387 MLX4_CQE_OPCODE_ERROR = 0x1e,
388 MLX4_CQE_OPCODE_RESIZE = 0x16,
389 };
390
391 enum {
392 MLX4_STAT_RATE_OFFSET = 5
393 };
394
395 enum mlx4_protocol {
396 MLX4_PROT_IB_IPV6 = 0,
397 MLX4_PROT_ETH,
398 MLX4_PROT_IB_IPV4,
399 MLX4_PROT_FCOE
400 };
401
402 enum {
403 MLX4_MTT_FLAG_PRESENT = 1
404 };
405
406 enum mlx4_qp_region {
407 MLX4_QP_REGION_FW = 0,
408 MLX4_QP_REGION_RSS_RAW_ETH,
409 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
410 MLX4_QP_REGION_ETH_ADDR,
411 MLX4_QP_REGION_FC_ADDR,
412 MLX4_QP_REGION_FC_EXCH,
413 MLX4_NUM_QP_REGION
414 };
415
416 enum mlx4_port_type {
417 MLX4_PORT_TYPE_NONE = 0,
418 MLX4_PORT_TYPE_IB = 1,
419 MLX4_PORT_TYPE_ETH = 2,
420 MLX4_PORT_TYPE_AUTO = 3
421 };
422
423 enum mlx4_special_vlan_idx {
424 MLX4_NO_VLAN_IDX = 0,
425 MLX4_VLAN_MISS_IDX,
426 MLX4_VLAN_REGULAR
427 };
428
429 enum mlx4_steer_type {
430 MLX4_MC_STEER = 0,
431 MLX4_UC_STEER,
432 MLX4_NUM_STEERS
433 };
434
435 enum {
436 MLX4_NUM_FEXCH = 64 * 1024,
437 };
438
439 enum {
440 MLX4_MAX_FAST_REG_PAGES = 511,
441 };
442
443 enum {
444 /*
445 * Max wqe size for rdma read is 512 bytes, so this
446 * limits our max_sge_rd as the wqe needs to fit:
447 * - ctrl segment (16 bytes)
448 * - rdma segment (16 bytes)
449 * - scatter elements (16 bytes each)
450 */
451 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16
452 };
453
454 enum {
455 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
456 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
457 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
458 MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17,
459 };
460
461 /* Port mgmt change event handling */
462 enum {
463 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
464 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
465 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
466 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
467 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
468 };
469
470 union sl2vl_tbl_to_u64 {
471 u8 sl8[8];
472 u64 sl64;
473 };
474
475 enum {
476 MLX4_DEVICE_STATE_UP = 1 << 0,
477 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
478 };
479
480 enum {
481 MLX4_INTERFACE_STATE_UP = 1 << 0,
482 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
483 };
484
485 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
486 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
487
488 enum mlx4_module_id {
489 MLX4_MODULE_ID_SFP = 0x3,
490 MLX4_MODULE_ID_QSFP = 0xC,
491 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
492 MLX4_MODULE_ID_QSFP28 = 0x11,
493 };
494
495 enum { /* rl */
496 MLX4_QP_RATE_LIMIT_NONE = 0,
497 MLX4_QP_RATE_LIMIT_KBS = 1,
498 MLX4_QP_RATE_LIMIT_MBS = 2,
499 MLX4_QP_RATE_LIMIT_GBS = 3
500 };
501
502 struct mlx4_rate_limit_caps {
503 u16 num_rates; /* Number of different rates */
504 u8 min_unit;
505 u16 min_val;
506 u8 max_unit;
507 u16 max_val;
508 };
509
mlx4_fw_ver(u64 major,u64 minor,u64 subminor)510 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
511 {
512 return (major << 32) | (minor << 16) | subminor;
513 }
514
515 struct mlx4_phys_caps {
516 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
517 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
518 u32 num_phys_eqs;
519 u32 base_sqpn;
520 u32 base_proxy_sqpn;
521 u32 base_tunnel_sqpn;
522 };
523
524 struct mlx4_caps {
525 u64 fw_ver;
526 u32 function;
527 int num_ports;
528 int vl_cap[MLX4_MAX_PORTS + 1];
529 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
530 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
531 u64 def_mac[MLX4_MAX_PORTS + 1];
532 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
533 int gid_table_len[MLX4_MAX_PORTS + 1];
534 int pkey_table_len[MLX4_MAX_PORTS + 1];
535 int trans_type[MLX4_MAX_PORTS + 1];
536 int vendor_oui[MLX4_MAX_PORTS + 1];
537 int wavelength[MLX4_MAX_PORTS + 1];
538 u64 trans_code[MLX4_MAX_PORTS + 1];
539 int local_ca_ack_delay;
540 int num_uars;
541 u32 uar_page_size;
542 int bf_reg_size;
543 int bf_regs_per_page;
544 int max_sq_sg;
545 int max_rq_sg;
546 int num_qps;
547 int max_wqes;
548 int max_sq_desc_sz;
549 int max_rq_desc_sz;
550 int max_qp_init_rdma;
551 int max_qp_dest_rdma;
552 int max_tc_eth;
553 u32 *qp0_qkey;
554 u32 *qp0_proxy;
555 u32 *qp1_proxy;
556 u32 *qp0_tunnel;
557 u32 *qp1_tunnel;
558 int num_srqs;
559 int max_srq_wqes;
560 int max_srq_sge;
561 int reserved_srqs;
562 int num_cqs;
563 int max_cqes;
564 int reserved_cqs;
565 int num_sys_eqs;
566 int num_eqs;
567 int reserved_eqs;
568 int num_comp_vectors;
569 int num_mpts;
570 int max_fmr_maps;
571 int num_mtts;
572 int fmr_reserved_mtts;
573 int reserved_mtts;
574 int reserved_mrws;
575 int reserved_uars;
576 int num_mgms;
577 int num_amgms;
578 int reserved_mcgs;
579 int num_qp_per_mgm;
580 int steering_mode;
581 int dmfs_high_steer_mode;
582 int fs_log_max_ucast_qp_range_size;
583 int num_pds;
584 int reserved_pds;
585 int max_xrcds;
586 int reserved_xrcds;
587 int mtt_entry_sz;
588 u32 max_msg_sz;
589 u32 page_size_cap;
590 u64 flags;
591 u64 flags2;
592 u32 bmme_flags;
593 u32 reserved_lkey;
594 u16 stat_rate_support;
595 u8 port_width_cap[MLX4_MAX_PORTS + 1];
596 int max_gso_sz;
597 int max_rss_tbl_sz;
598 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
599 int reserved_qps;
600 int reserved_qps_base[MLX4_NUM_QP_REGION];
601 int log_num_macs;
602 int log_num_vlans;
603 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
604 u8 supported_type[MLX4_MAX_PORTS + 1];
605 u8 suggested_type[MLX4_MAX_PORTS + 1];
606 u8 default_sense[MLX4_MAX_PORTS + 1];
607 u32 port_mask[MLX4_MAX_PORTS + 1];
608 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
609 u32 max_counters;
610 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
611 u16 sqp_demux;
612 u32 eqe_size;
613 u32 cqe_size;
614 u8 eqe_factor;
615 u32 userspace_caps; /* userspace must be aware of these */
616 u32 function_caps; /* VFs must be aware of these */
617 u16 hca_core_clock;
618 u64 phys_port_id[MLX4_MAX_PORTS + 1];
619 int tunnel_offload_mode;
620 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
621 u8 phv_bit[MLX4_MAX_PORTS + 1];
622 u8 alloc_res_qp_mask;
623 u32 dmfs_high_rate_qpn_base;
624 u32 dmfs_high_rate_qpn_range;
625 u32 vf_caps;
626 struct mlx4_rate_limit_caps rl_caps;
627 bool map_clock_to_user;
628 };
629
630 struct mlx4_buf_list {
631 void *buf;
632 dma_addr_t map;
633 };
634
635 struct mlx4_buf {
636 struct mlx4_buf_list direct;
637 struct mlx4_buf_list *page_list;
638 int nbufs;
639 int npages;
640 int page_shift;
641 };
642
643 struct mlx4_mtt {
644 u32 offset;
645 int order;
646 int page_shift;
647 };
648
649 enum {
650 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
651 };
652
653 struct mlx4_db_pgdir {
654 struct list_head list;
655 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
656 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
657 unsigned long *bits[2];
658 __be32 *db_page;
659 dma_addr_t db_dma;
660 };
661
662 struct mlx4_ib_user_db_page;
663
664 struct mlx4_db {
665 __be32 *db;
666 union {
667 struct mlx4_db_pgdir *pgdir;
668 struct mlx4_ib_user_db_page *user_page;
669 } u;
670 dma_addr_t dma;
671 int index;
672 int order;
673 };
674
675 struct mlx4_hwq_resources {
676 struct mlx4_db db;
677 struct mlx4_mtt mtt;
678 struct mlx4_buf buf;
679 };
680
681 struct mlx4_mr {
682 struct mlx4_mtt mtt;
683 u64 iova;
684 u64 size;
685 u32 key;
686 u32 pd;
687 u32 access;
688 int enabled;
689 };
690
691 enum mlx4_mw_type {
692 MLX4_MW_TYPE_1 = 1,
693 MLX4_MW_TYPE_2 = 2,
694 };
695
696 struct mlx4_mw {
697 u32 key;
698 u32 pd;
699 enum mlx4_mw_type type;
700 int enabled;
701 };
702
703 struct mlx4_fmr {
704 struct mlx4_mr mr;
705 struct mlx4_mpt_entry *mpt;
706 __be64 *mtts;
707 dma_addr_t dma_handle;
708 int max_pages;
709 int max_maps;
710 int maps;
711 u8 page_shift;
712 };
713
714 struct mlx4_uar {
715 unsigned long pfn;
716 int index;
717 struct list_head bf_list;
718 unsigned free_bf_bmap;
719 void __iomem *map;
720 void __iomem *bf_map;
721 };
722
723 struct mlx4_bf {
724 unsigned int offset;
725 int buf_size;
726 struct mlx4_uar *uar;
727 void __iomem *reg;
728 };
729
730 struct mlx4_cq {
731 void (*comp) (struct mlx4_cq *);
732 void (*event) (struct mlx4_cq *, enum mlx4_event);
733
734 struct mlx4_uar *uar;
735
736 u32 cons_index;
737
738 u16 irq;
739 __be32 *set_ci_db;
740 __be32 *arm_db;
741 int arm_sn;
742
743 int cqn;
744 unsigned vector;
745
746 atomic_t refcount;
747 struct completion free;
748 int reset_notify_added;
749 struct list_head reset_notify;
750 };
751
752 struct mlx4_qp {
753 void (*event) (struct mlx4_qp *, enum mlx4_event);
754
755 int qpn;
756
757 atomic_t refcount;
758 struct completion free;
759 };
760
761 struct mlx4_srq {
762 void (*event) (struct mlx4_srq *, enum mlx4_event);
763
764 int srqn;
765 int max;
766 int max_gs;
767 int wqe_shift;
768
769 atomic_t refcount;
770 struct completion free;
771 };
772
773 struct mlx4_av {
774 __be32 port_pd;
775 u8 reserved1;
776 u8 g_slid;
777 __be16 dlid;
778 u8 reserved2;
779 u8 gid_index;
780 u8 stat_rate;
781 u8 hop_limit;
782 __be32 sl_tclass_flowlabel;
783 u8 dgid[16];
784 };
785
786 struct mlx4_eth_av {
787 __be32 port_pd;
788 u8 reserved1;
789 u8 smac_idx;
790 u16 reserved2;
791 u8 reserved3;
792 u8 gid_index;
793 u8 stat_rate;
794 u8 hop_limit;
795 __be32 sl_tclass_flowlabel;
796 u8 dgid[16];
797 u8 s_mac[6];
798 u8 reserved4[2];
799 __be16 vlan;
800 u8 mac[ETH_ALEN];
801 };
802
803 union mlx4_ext_av {
804 struct mlx4_av ib;
805 struct mlx4_eth_av eth;
806 };
807
808 /* Counters should be saturate once they reach their maximum value */
809 #define ASSIGN_32BIT_COUNTER(counter, value) do { \
810 if ((value) > U32_MAX) \
811 counter = cpu_to_be32(U32_MAX); \
812 else \
813 counter = cpu_to_be32(value); \
814 } while (0)
815
816 struct mlx4_counter {
817 u8 reserved1[3];
818 u8 counter_mode;
819 __be32 num_ifc;
820 u32 reserved2[2];
821 __be64 rx_frames;
822 __be64 rx_bytes;
823 __be64 tx_frames;
824 __be64 tx_bytes;
825 };
826
827 struct mlx4_quotas {
828 int qp;
829 int cq;
830 int srq;
831 int mpt;
832 int mtt;
833 int counter;
834 int xrcd;
835 };
836
837 struct mlx4_vf_dev {
838 u8 min_port;
839 u8 n_ports;
840 };
841
842 enum mlx4_pci_status {
843 MLX4_PCI_STATUS_DISABLED,
844 MLX4_PCI_STATUS_ENABLED,
845 };
846
847 struct mlx4_dev_persistent {
848 struct pci_dev *pdev;
849 struct mlx4_dev *dev;
850 int nvfs[MLX4_MAX_PORTS + 1];
851 int num_vfs;
852 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
853 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
854 struct work_struct catas_work;
855 struct workqueue_struct *catas_wq;
856 struct mutex device_state_mutex; /* protect HW state */
857 u8 state;
858 struct mutex interface_state_mutex; /* protect SW state */
859 u8 interface_state;
860 struct mutex pci_status_mutex; /* sync pci state */
861 enum mlx4_pci_status pci_status;
862 };
863
864 struct mlx4_dev {
865 struct mlx4_dev_persistent *persist;
866 unsigned long flags;
867 unsigned long num_slaves;
868 struct mlx4_caps caps;
869 struct mlx4_phys_caps phys_caps;
870 struct mlx4_quotas quotas;
871 struct radix_tree_root qp_table_tree;
872 u8 rev_id;
873 u8 port_random_macs;
874 char board_id[MLX4_BOARD_ID_LEN];
875 int numa_node;
876 int oper_log_mgm_entry_size;
877 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
878 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
879 struct mlx4_vf_dev *dev_vfs;
880 u8 uar_page_shift;
881 struct sysctl_ctx_list hw_ctx;
882 char fw_str[64];
883 };
884
885 struct mlx4_clock_params {
886 u64 offset;
887 u8 bar;
888 u8 size;
889 };
890
891 struct mlx4_eqe {
892 u8 reserved1;
893 u8 type;
894 u8 reserved2;
895 u8 subtype;
896 union {
897 u32 raw[6];
898 struct {
899 __be32 cqn;
900 } __packed comp;
901 struct {
902 u16 reserved1;
903 __be16 token;
904 u32 reserved2;
905 u8 reserved3[3];
906 u8 status;
907 __be64 out_param;
908 } __packed cmd;
909 struct {
910 __be32 qpn;
911 } __packed qp;
912 struct {
913 __be32 srqn;
914 } __packed srq;
915 struct {
916 __be32 cqn;
917 u32 reserved1;
918 u8 reserved2[3];
919 u8 syndrome;
920 } __packed cq_err;
921 struct {
922 u32 reserved1[2];
923 __be32 port;
924 } __packed port_change;
925 struct {
926 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
927 u32 reserved;
928 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
929 } __packed comm_channel_arm;
930 struct {
931 u8 port;
932 u8 reserved[3];
933 __be64 mac;
934 } __packed mac_update;
935 struct {
936 __be32 slave_id;
937 } __packed flr_event;
938 struct {
939 __be16 current_temperature;
940 __be16 warning_threshold;
941 } __packed warming;
942 struct {
943 u8 reserved[3];
944 u8 port;
945 union {
946 struct {
947 __be16 mstr_sm_lid;
948 __be16 port_lid;
949 __be32 changed_attr;
950 u8 reserved[3];
951 u8 mstr_sm_sl;
952 __be64 gid_prefix;
953 } __packed port_info;
954 struct {
955 __be32 block_ptr;
956 __be32 tbl_entries_mask;
957 } __packed tbl_change_info;
958 struct {
959 u8 sl2vl_table[8];
960 } __packed sl2vl_tbl_change_info;
961 } params;
962 } __packed port_mgmt_change;
963 struct {
964 u8 reserved[3];
965 u8 port;
966 u32 reserved1[5];
967 } __packed bad_cable;
968 } event;
969 u8 slave_id;
970 u8 reserved3[2];
971 u8 owner;
972 } __packed;
973
974 struct mlx4_init_port_param {
975 int set_guid0;
976 int set_node_guid;
977 int set_si_guid;
978 u16 mtu;
979 int port_width_cap;
980 u16 vl_cap;
981 u16 max_gid;
982 u16 max_pkey;
983 u64 guid0;
984 u64 node_guid;
985 u64 si_guid;
986 };
987
988 #define MAD_IFC_DATA_SZ 192
989 /* MAD IFC Mailbox */
990 struct mlx4_mad_ifc {
991 u8 base_version;
992 u8 mgmt_class;
993 u8 class_version;
994 u8 method;
995 __be16 status;
996 __be16 class_specific;
997 __be64 tid;
998 __be16 attr_id;
999 __be16 resv;
1000 __be32 attr_mod;
1001 __be64 mkey;
1002 __be16 dr_slid;
1003 __be16 dr_dlid;
1004 u8 reserved[28];
1005 u8 data[MAD_IFC_DATA_SZ];
1006 } __packed;
1007
1008 #define mlx4_foreach_port(port, dev, type) \
1009 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
1010 if ((type) == (dev)->caps.port_mask[(port)])
1011
1012 #define mlx4_foreach_ib_transport_port(port, dev) \
1013 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
1014 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
1015 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) || \
1016 ((dev)->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2))
1017
1018 #define MLX4_INVALID_SLAVE_ID 0xFF
1019 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1)
1020
1021 void handle_port_mgmt_change_event(struct work_struct *work);
1022
mlx4_master_func_num(struct mlx4_dev * dev)1023 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
1024 {
1025 return dev->caps.function;
1026 }
1027
mlx4_is_master(struct mlx4_dev * dev)1028 static inline int mlx4_is_master(struct mlx4_dev *dev)
1029 {
1030 return dev->flags & MLX4_FLAG_MASTER;
1031 }
1032
mlx4_num_reserved_sqps(struct mlx4_dev * dev)1033 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
1034 {
1035 return dev->phys_caps.base_sqpn + 8 +
1036 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
1037 }
1038
mlx4_is_qp_reserved(struct mlx4_dev * dev,u32 qpn)1039 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
1040 {
1041 return (qpn < dev->phys_caps.base_sqpn + 8 +
1042 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
1043 qpn >= dev->phys_caps.base_sqpn) ||
1044 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
1045 }
1046
mlx4_is_guest_proxy(struct mlx4_dev * dev,int slave,u32 qpn)1047 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
1048 {
1049 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
1050
1051 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
1052 return 1;
1053
1054 return 0;
1055 }
1056
mlx4_is_mfunc(struct mlx4_dev * dev)1057 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
1058 {
1059 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
1060 }
1061
mlx4_is_slave(struct mlx4_dev * dev)1062 static inline int mlx4_is_slave(struct mlx4_dev *dev)
1063 {
1064 return dev->flags & MLX4_FLAG_SLAVE;
1065 }
1066
mlx4_is_eth(struct mlx4_dev * dev,int port)1067 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
1068 {
1069 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
1070 }
1071
1072 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1073 struct mlx4_buf *buf, gfp_t gfp);
1074 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
mlx4_buf_offset(struct mlx4_buf * buf,int offset)1075 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1076 {
1077 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
1078 return (u8 *)buf->direct.buf + offset;
1079 else
1080 return (u8 *)buf->page_list[offset >> PAGE_SHIFT].buf +
1081 (offset & (PAGE_SIZE - 1));
1082 }
1083
1084 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1085 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1086 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1087 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1088
1089 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1090 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1091 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1092 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1093
1094 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1095 struct mlx4_mtt *mtt);
1096 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1097 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1098
1099 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1100 int npages, int page_shift, struct mlx4_mr *mr);
1101 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1102 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1103 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1104 struct mlx4_mw *mw);
1105 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1106 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1107 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1108 int start_index, int npages, u64 *page_list);
1109 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1110 struct mlx4_buf *buf, gfp_t gfp);
1111
1112 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
1113 gfp_t gfp);
1114 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1115
1116 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1117 int size, int max_direct);
1118 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1119 int size);
1120
1121 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1122 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1123 unsigned vector, int collapsed, int timestamp_en);
1124 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1125 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1126 int *base, u8 flags);
1127 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1128
1129 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
1130 gfp_t gfp);
1131 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1132
1133 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1134 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1135 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1136 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1137 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1138
1139 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1140 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1141
1142 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1143 int block_mcast_loopback, enum mlx4_protocol prot);
1144 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1145 enum mlx4_protocol prot);
1146 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1147 u8 port, int block_mcast_loopback,
1148 enum mlx4_protocol protocol, u64 *reg_id);
1149 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1150 enum mlx4_protocol protocol, u64 reg_id);
1151
1152 enum {
1153 MLX4_DOMAIN_UVERBS = 0x1000,
1154 MLX4_DOMAIN_ETHTOOL = 0x2000,
1155 MLX4_DOMAIN_RFS = 0x3000,
1156 MLX4_DOMAIN_NIC = 0x5000,
1157 };
1158
1159 enum mlx4_net_trans_rule_id {
1160 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1161 MLX4_NET_TRANS_RULE_ID_IB,
1162 MLX4_NET_TRANS_RULE_ID_IPV6,
1163 MLX4_NET_TRANS_RULE_ID_IPV4,
1164 MLX4_NET_TRANS_RULE_ID_TCP,
1165 MLX4_NET_TRANS_RULE_ID_UDP,
1166 MLX4_NET_TRANS_RULE_ID_VXLAN,
1167 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1168 MLX4_NET_TRANS_RULE_DUMMY = -1, /* force enum to be signed */
1169 };
1170
1171 extern const u16 __sw_id_hw[];
1172
map_hw_to_sw_id(u16 header_id)1173 static inline int map_hw_to_sw_id(u16 header_id)
1174 {
1175
1176 int i;
1177 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1178 if (header_id == __sw_id_hw[i])
1179 return i;
1180 }
1181 return -EINVAL;
1182 }
1183
1184 enum mlx4_net_trans_promisc_mode {
1185 MLX4_FS_REGULAR = 1,
1186 MLX4_FS_ALL_DEFAULT,
1187 MLX4_FS_MC_DEFAULT,
1188 MLX4_FS_MIRROR_RX_PORT,
1189 MLX4_FS_MIRROR_SX_PORT,
1190 MLX4_FS_UC_SNIFFER,
1191 MLX4_FS_MC_SNIFFER,
1192 MLX4_FS_MODE_NUM, /* should be last */
1193 MLX4_FS_MODE_DUMMY = -1, /* force enum to be signed */
1194 };
1195
1196 struct mlx4_spec_eth {
1197 u8 dst_mac[ETH_ALEN];
1198 u8 dst_mac_msk[ETH_ALEN];
1199 u8 src_mac[ETH_ALEN];
1200 u8 src_mac_msk[ETH_ALEN];
1201 u8 ether_type_enable;
1202 __be16 ether_type;
1203 __be16 vlan_id_msk;
1204 __be16 vlan_id;
1205 };
1206
1207 struct mlx4_spec_tcp_udp {
1208 __be16 dst_port;
1209 __be16 dst_port_msk;
1210 __be16 src_port;
1211 __be16 src_port_msk;
1212 };
1213
1214 struct mlx4_spec_ipv4 {
1215 __be32 dst_ip;
1216 __be32 dst_ip_msk;
1217 __be32 src_ip;
1218 __be32 src_ip_msk;
1219 };
1220
1221 struct mlx4_spec_ib {
1222 __be32 l3_qpn;
1223 __be32 qpn_msk;
1224 u8 dst_gid[16];
1225 u8 dst_gid_msk[16];
1226 };
1227
1228 struct mlx4_spec_vxlan {
1229 __be32 vni;
1230 __be32 vni_mask;
1231
1232 };
1233
1234 struct mlx4_spec_list {
1235 struct list_head list;
1236 enum mlx4_net_trans_rule_id id;
1237 union {
1238 struct mlx4_spec_eth eth;
1239 struct mlx4_spec_ib ib;
1240 struct mlx4_spec_ipv4 ipv4;
1241 struct mlx4_spec_tcp_udp tcp_udp;
1242 struct mlx4_spec_vxlan vxlan;
1243 };
1244 };
1245
1246 enum mlx4_net_trans_hw_rule_queue {
1247 MLX4_NET_TRANS_Q_FIFO,
1248 MLX4_NET_TRANS_Q_LIFO,
1249 };
1250
1251 struct mlx4_net_trans_rule {
1252 struct list_head list;
1253 enum mlx4_net_trans_hw_rule_queue queue_mode;
1254 bool exclusive;
1255 bool allow_loopback;
1256 enum mlx4_net_trans_promisc_mode promisc_mode;
1257 u8 port;
1258 u16 priority;
1259 u32 qpn;
1260 };
1261
1262 struct mlx4_net_trans_rule_hw_ctrl {
1263 __be16 prio;
1264 u8 type;
1265 u8 flags;
1266 u8 rsvd1;
1267 u8 funcid;
1268 u8 vep;
1269 u8 port;
1270 __be32 qpn;
1271 __be32 rsvd2;
1272 };
1273
1274 struct mlx4_net_trans_rule_hw_ib {
1275 u8 size;
1276 u8 rsvd1;
1277 __be16 id;
1278 u32 rsvd2;
1279 __be32 l3_qpn;
1280 __be32 qpn_mask;
1281 u8 dst_gid[16];
1282 u8 dst_gid_msk[16];
1283 } __packed;
1284
1285 struct mlx4_net_trans_rule_hw_eth {
1286 u8 size;
1287 u8 rsvd;
1288 __be16 id;
1289 u8 rsvd1[6];
1290 u8 dst_mac[6];
1291 u16 rsvd2;
1292 u8 dst_mac_msk[6];
1293 u16 rsvd3;
1294 u8 src_mac[6];
1295 u16 rsvd4;
1296 u8 src_mac_msk[6];
1297 u8 rsvd5;
1298 u8 ether_type_enable;
1299 __be16 ether_type;
1300 __be16 vlan_tag_msk;
1301 __be16 vlan_tag;
1302 } __packed;
1303
1304 struct mlx4_net_trans_rule_hw_tcp_udp {
1305 u8 size;
1306 u8 rsvd;
1307 __be16 id;
1308 __be16 rsvd1[3];
1309 __be16 dst_port;
1310 __be16 rsvd2;
1311 __be16 dst_port_msk;
1312 __be16 rsvd3;
1313 __be16 src_port;
1314 __be16 rsvd4;
1315 __be16 src_port_msk;
1316 } __packed;
1317
1318 struct mlx4_net_trans_rule_hw_ipv4 {
1319 u8 size;
1320 u8 rsvd;
1321 __be16 id;
1322 __be32 rsvd1;
1323 __be32 dst_ip;
1324 __be32 dst_ip_msk;
1325 __be32 src_ip;
1326 __be32 src_ip_msk;
1327 } __packed;
1328
1329 struct mlx4_net_trans_rule_hw_vxlan {
1330 u8 size;
1331 u8 rsvd;
1332 __be16 id;
1333 __be32 rsvd1;
1334 __be32 vni;
1335 __be32 vni_mask;
1336 } __packed;
1337
1338 struct _rule_hw {
1339 union {
1340 struct {
1341 u8 size;
1342 u8 rsvd;
1343 __be16 id;
1344 };
1345 struct mlx4_net_trans_rule_hw_eth eth;
1346 struct mlx4_net_trans_rule_hw_ib ib;
1347 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1348 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1349 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1350 };
1351 };
1352
1353 enum {
1354 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1355 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1356 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1357 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1358 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1359 };
1360
1361 enum {
1362 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2,
1363 };
1364
1365 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1366 enum mlx4_net_trans_promisc_mode mode);
1367 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1368 enum mlx4_net_trans_promisc_mode mode);
1369 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1370 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1371 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1372 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1373 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1374
1375 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1376 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1377 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1378 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1379 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1380 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1381 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1382 u8 promisc);
1383 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
1384 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
1385 u8 ignore_fcs_value);
1386 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1387 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val);
1388 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv);
1389 int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port,
1390 bool *vlan_offload_disabled);
1391 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1392 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1393 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1394 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1395
1396 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1397 int npages, u64 iova, u32 *lkey, u32 *rkey);
1398 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1399 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1400 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1401 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1402 u32 *lkey, u32 *rkey);
1403 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1404 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1405 int mlx4_test_interrupt(struct mlx4_dev *dev, int vector);
1406 int mlx4_test_async(struct mlx4_dev *dev);
1407 int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier,
1408 const u32 offset[], u32 value[],
1409 size_t array_len, u8 port);
1410 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
1411 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
1412 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
1413 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1414
1415 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
1416 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1417
1418 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1419 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1420 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1421
1422 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1423 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1424 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
1425
1426 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
1427 int port);
1428 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
1429 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
1430 int mlx4_flow_attach(struct mlx4_dev *dev,
1431 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1432 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1433 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1434 enum mlx4_net_trans_promisc_mode flow_type);
1435 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1436 enum mlx4_net_trans_rule_id id);
1437 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1438
1439 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1440 int port, int qpn, u16 prio, u64 *reg_id);
1441
1442 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1443 int i, int val);
1444
1445 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1446
1447 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1448 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1449 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1450 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1451 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1452 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1453 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1454
1455 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1456 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1457
1458 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1459 int *slave_id);
1460 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1461 u8 *gid);
1462
1463 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1464 u32 max_range_qpn);
1465
1466 s64 mlx4_read_clock(struct mlx4_dev *dev);
1467
1468 struct mlx4_active_ports {
1469 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1470 };
1471 /* Returns a bitmap of the physical ports which are assigned to slave */
1472 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1473
1474 /* Returns the physical port that represents the virtual port of the slave, */
1475 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1476 /* mapping is returned. */
1477 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1478
1479 struct mlx4_slaves_pport {
1480 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1481 };
1482 /* Returns a bitmap of all slaves that are assigned to port. */
1483 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1484 int port);
1485
1486 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1487 /* the ports that are set in crit_ports. */
1488 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1489 struct mlx4_dev *dev,
1490 const struct mlx4_active_ports *crit_ports);
1491
1492 /* Returns the slave's virtual port that represents the physical port. */
1493 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1494
1495 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1496
1497 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1498 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1499 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port);
1500 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1501 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1502 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1503 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1504 int enable);
1505 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1506 struct mlx4_mpt_entry ***mpt_entry);
1507 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1508 struct mlx4_mpt_entry **mpt_entry);
1509 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1510 u32 pdn);
1511 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1512 struct mlx4_mpt_entry *mpt_entry,
1513 u32 access);
1514 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1515 struct mlx4_mpt_entry **mpt_entry);
1516 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1517 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1518 u64 iova, u64 size, int npages,
1519 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1520
1521 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1522 u16 offset, u16 size, u8 *data);
1523 int mlx4_max_tc(struct mlx4_dev *dev);
1524
1525 /* Returns true if running in low memory profile (kdump kernel) */
mlx4_low_memory_profile(void)1526 static inline bool mlx4_low_memory_profile(void)
1527 {
1528 return false;
1529 }
1530
1531 /* ACCESS REG commands */
1532 enum mlx4_access_reg_method {
1533 MLX4_ACCESS_REG_QUERY = 0x1,
1534 MLX4_ACCESS_REG_WRITE = 0x2,
1535 };
1536
1537 /* ACCESS PTYS Reg command */
1538 enum mlx4_ptys_proto {
1539 MLX4_PTYS_IB = 1<<0,
1540 MLX4_PTYS_EN = 1<<2,
1541 };
1542
1543 struct mlx4_ptys_reg {
1544 u8 resrvd1;
1545 u8 local_port;
1546 u8 resrvd2;
1547 u8 proto_mask;
1548 __be32 resrvd3[2];
1549 __be32 eth_proto_cap;
1550 __be16 ib_width_cap;
1551 __be16 ib_speed_cap;
1552 __be32 resrvd4;
1553 __be32 eth_proto_admin;
1554 __be16 ib_width_admin;
1555 __be16 ib_speed_admin;
1556 __be32 resrvd5;
1557 __be32 eth_proto_oper;
1558 __be16 ib_width_oper;
1559 __be16 ib_speed_oper;
1560 __be32 resrvd6;
1561 __be32 eth_proto_lp_adv;
1562 } __packed;
1563
1564 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1565 enum mlx4_access_reg_method method,
1566 struct mlx4_ptys_reg *ptys_reg);
1567
1568 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1569 struct mlx4_clock_params *params);
1570
mlx4_to_hw_uar_index(struct mlx4_dev * dev,int index)1571 static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index)
1572 {
1573 return (index << (PAGE_SHIFT - dev->uar_page_shift));
1574 }
1575
mlx4_get_num_reserved_uar(struct mlx4_dev * dev)1576 static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev)
1577 {
1578 /* The first 128 UARs are used for EQ doorbells */
1579 return (128 >> (PAGE_SHIFT - dev->uar_page_shift));
1580 }
1581 #endif /* MLX4_DEVICE_H */
1582