1 /*-
2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2022 NVIDIA corporation & affiliates.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #ifndef _MLX5_EN_H_
28 #define _MLX5_EN_H_
29
30 #include <linux/kmod.h>
31 #include <linux/page.h>
32 #include <linux/slab.h>
33 #include <linux/if_vlan.h>
34 #include <linux/if_ether.h>
35 #include <linux/vmalloc.h>
36 #include <linux/moduleparam.h>
37 #include <linux/delay.h>
38 #include <linux/etherdevice.h>
39 #include <linux/ktime.h>
40 #include <linux/net_dim.h>
41
42 #include <netinet/in_systm.h>
43 #include <netinet/in.h>
44 #include <netinet/if_ether.h>
45 #include <netinet/ip.h>
46 #include <netinet/ip6.h>
47 #include <netinet/tcp.h>
48 #include <netinet/tcp_lro.h>
49 #include <netinet/udp.h>
50 #include <net/ethernet.h>
51 #include <net/pfil.h>
52 #include <sys/buf_ring.h>
53 #include <sys/kthread.h>
54 #include <sys/counter.h>
55
56 #ifdef RSS
57 #include <net/rss_config.h>
58 #include <netinet/in_rss.h>
59 #endif
60
61 #include <machine/bus.h>
62
63 #include <dev/mlx5/driver.h>
64 #include <dev/mlx5/qp.h>
65 #include <dev/mlx5/cq.h>
66 #include <dev/mlx5/port.h>
67 #include <dev/mlx5/vport.h>
68 #include <dev/mlx5/diagnostics.h>
69
70 #include <dev/mlx5/mlx5_core/wq.h>
71 #include <dev/mlx5/mlx5_core/transobj.h>
72 #include <dev/mlx5/mlx5_core/mlx5_core.h>
73
74 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
75
76 #define MLX5E_MAX_PRIORITY 8
77
78 #define MLX5E_MAX_FEC_10X_25X 4
79 #define MLX5E_MAX_FEC_50X 4
80
81 /* IEEE 802.1Qaz standard supported values */
82 #define IEEE_8021QAZ_MAX_TCS 8
83
84 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7
85 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
86 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe
87
88 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7
89 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
90 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe
91
92 #define MLX5E_MAX_BUSDMA_RX_SEGS 15
93
94 #ifndef MLX5E_MAX_RX_BYTES
95 #define MLX5E_MAX_RX_BYTES MCLBYTES
96 #endif
97
98 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \
99 MIN(65535, 7 * MLX5E_MAX_RX_BYTES)
100
101 #define MLX5E_DIM_DEFAULT_PROFILE 3
102 #define MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO 16
103 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
104 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
105 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
106 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
107 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
108 #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7
109 #define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE
110 #define MLX5E_HW2SW_MTU(hwmtu) \
111 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
112 #define MLX5E_SW2HW_MTU(swmtu) \
113 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
114 #define MLX5E_SW2MB_MTU(swmtu) \
115 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN)
116 #define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */
117 #define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet
118 * jumbo frames */
119
120 #define MLX5E_BUDGET_MAX 8192 /* RX and TX */
121 #define MLX5E_RX_BUDGET_MAX 256
122 #define MLX5E_SQ_BF_BUDGET 16
123 #define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */
124
125 #define MLX5E_MAX_TX_NUM_TC 8 /* units */
126 #define MLX5E_MAX_TX_HEADER 192 /* bytes */
127 #define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */
128 #define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */
129 #define MLX5E_MAX_TX_MBUF_FRAGS \
130 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \
131 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \
132 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */
133 #define MLX5E_MAX_TX_INLINE \
134 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \
135 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */
136
137 #define MLX5E_100MB (100000)
138 #define MLX5E_1GB (1000000)
139
140 #define MLX5E_ZERO(ptr, field) \
141 memset(&(ptr)->field, 0, \
142 sizeof(*(ptr)) - __offsetof(__typeof(*(ptr)), field))
143
144 MALLOC_DECLARE(M_MLX5EN);
145
146 struct mlx5_core_dev;
147 struct mlx5e_cq;
148
149 typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *, struct mlx5_eqe *);
150
151 #define mlx5_en_err(_dev, format, ...) \
152 if_printf(_dev, "ERR: ""%s:%d:(pid %d): " format, \
153 __func__, __LINE__, curthread->td_proc->p_pid, \
154 ##__VA_ARGS__)
155
156 #define mlx5_en_warn(_dev, format, ...) \
157 if_printf(_dev, "WARN: ""%s:%d:(pid %d): " format, \
158 __func__, __LINE__, curthread->td_proc->p_pid, \
159 ##__VA_ARGS__)
160
161 #define mlx5_en_info(_dev, format, ...) \
162 if_printf(_dev, "INFO: ""%s:%d:(pid %d): " format, \
163 __func__, __LINE__, curthread->td_proc->p_pid, \
164 ##__VA_ARGS__)
165
166 #define MLX5E_STATS_COUNT(a, ...) a
167 #define MLX5E_STATS_VAR(a, b, c, ...) b c;
168 #define MLX5E_STATS_COUNTER(a, b, c, ...) counter_##b##_t c;
169 #define MLX5E_STATS_DESC(a, b, c, d, e, ...) d, e,
170
171 #define MLX5E_VPORT_STATS(m) \
172 /* HW counters */ \
173 m(+1, u64, rx_packets, "rx_packets", "Received packets") \
174 m(+1, u64, rx_bytes, "rx_bytes", "Received bytes") \
175 m(+1, u64, tx_packets, "tx_packets", "Transmitted packets") \
176 m(+1, u64, tx_bytes, "tx_bytes", "Transmitted bytes") \
177 m(+1, u64, rx_error_packets, "rx_error_packets", "Received error packets") \
178 m(+1, u64, rx_error_bytes, "rx_error_bytes", "Received error bytes") \
179 m(+1, u64, tx_error_packets, "tx_error_packets", "Transmitted error packets") \
180 m(+1, u64, tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \
181 m(+1, u64, rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \
182 m(+1, u64, rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \
183 m(+1, u64, tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \
184 m(+1, u64, tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \
185 m(+1, u64, rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \
186 m(+1, u64, rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \
187 m(+1, u64, tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \
188 m(+1, u64, tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \
189 m(+1, u64, rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \
190 m(+1, u64, rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \
191 m(+1, u64, tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \
192 m(+1, u64, tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \
193 m(+1, u64, rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \
194 /* SW counters */ \
195 m(+1, u64, tso_packets, "tso_packets", "Transmitted TSO packets") \
196 m(+1, u64, tso_bytes, "tso_bytes", "Transmitted TSO bytes") \
197 m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \
198 m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \
199 m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \
200 m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \
201 m(+1, u64, rx_csum_good, "rx_csum_good", "Received checksum valid packets") \
202 m(+1, u64, rx_csum_none, "rx_csum_none", "Received no checksum packets") \
203 m(+1, u64, tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \
204 m(+1, u64, tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \
205 m(+1, u64, tx_defragged, "tx_defragged", "Transmit queue defragged") \
206 m(+1, u64, rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \
207 m(+1, u64, tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets") \
208 m(+1, u64, rx_steer_missed_packets, "rx_steer_missed_packets", "RX packets dropped by steering rule(s)") \
209 m(+1, u64, rx_decrypted_ok_packets, "rx_decrypted_ok_packets", "RX packets successfully decrypted by steering rule(s)") \
210 m(+1, u64, rx_decrypted_error_packets, "rx_decrypted_error_packets", "RX packets not decrypted by steering rule(s)")
211
212 #define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT))
213
214 struct mlx5e_vport_stats {
215 struct sysctl_ctx_list ctx;
216 u64 arg [0];
217 MLX5E_VPORT_STATS(MLX5E_STATS_VAR)
218 };
219
220 #define MLX5E_PPORT_IEEE802_3_STATS(m) \
221 m(+1, u64, frames_tx, "frames_tx", "Frames transmitted") \
222 m(+1, u64, frames_rx, "frames_rx", "Frames received") \
223 m(+1, u64, check_seq_err, "check_seq_err", "Sequence errors") \
224 m(+1, u64, alignment_err, "alignment_err", "Alignment errors") \
225 m(+1, u64, octets_tx, "octets_tx", "Bytes transmitted") \
226 m(+1, u64, octets_received, "octets_received", "Bytes received") \
227 m(+1, u64, multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \
228 m(+1, u64, broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \
229 m(+1, u64, multicast_rx, "multicast_rx", "Multicast received") \
230 m(+1, u64, broadcast_rx, "broadcast_rx", "Broadcast received") \
231 m(+1, u64, in_range_len_errors, "in_range_len_errors", "In range length errors") \
232 m(+1, u64, out_of_range_len, "out_of_range_len", "Out of range length errors") \
233 m(+1, u64, too_long_errors, "too_long_errors", "Too long errors") \
234 m(+1, u64, symbol_err, "symbol_err", "Symbol errors") \
235 m(+1, u64, mac_control_tx, "mac_control_tx", "MAC control transmitted") \
236 m(+1, u64, mac_control_rx, "mac_control_rx", "MAC control received") \
237 m(+1, u64, unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \
238 m(+1, u64, pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \
239 m(+1, u64, pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted")
240
241 #define MLX5E_PPORT_RFC2819_STATS(m) \
242 m(+1, u64, drop_events, "drop_events", "Dropped events") \
243 m(+1, u64, octets, "octets", "Octets") \
244 m(+1, u64, pkts, "pkts", "Packets") \
245 m(+1, u64, broadcast_pkts, "broadcast_pkts", "Broadcast packets") \
246 m(+1, u64, multicast_pkts, "multicast_pkts", "Multicast packets") \
247 m(+1, u64, crc_align_errors, "crc_align_errors", "CRC alignment errors") \
248 m(+1, u64, undersize_pkts, "undersize_pkts", "Undersized packets") \
249 m(+1, u64, oversize_pkts, "oversize_pkts", "Oversized packets") \
250 m(+1, u64, fragments, "fragments", "Fragments") \
251 m(+1, u64, jabbers, "jabbers", "Jabbers") \
252 m(+1, u64, collisions, "collisions", "Collisions")
253
254 #define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \
255 m(+1, u64, p64octets, "p64octets", "Bytes") \
256 m(+1, u64, p65to127octets, "p65to127octets", "Bytes") \
257 m(+1, u64, p128to255octets, "p128to255octets", "Bytes") \
258 m(+1, u64, p256to511octets, "p256to511octets", "Bytes") \
259 m(+1, u64, p512to1023octets, "p512to1023octets", "Bytes") \
260 m(+1, u64, p1024to1518octets, "p1024to1518octets", "Bytes") \
261 m(+1, u64, p1519to2047octets, "p1519to2047octets", "Bytes") \
262 m(+1, u64, p2048to4095octets, "p2048to4095octets", "Bytes") \
263 m(+1, u64, p4096to8191octets, "p4096to8191octets", "Bytes") \
264 m(+1, u64, p8192to10239octets, "p8192to10239octets", "Bytes")
265
266 #define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
267 m(+1, u64, in_octets, "in_octets", "In octets") \
268 m(+1, u64, in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \
269 m(+1, u64, in_discards, "in_discards", "In discards") \
270 m(+1, u64, in_errors, "in_errors", "In errors") \
271 m(+1, u64, in_unknown_protos, "in_unknown_protos", "In unknown protocols") \
272 m(+1, u64, out_octets, "out_octets", "Out octets") \
273 m(+1, u64, out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \
274 m(+1, u64, out_discards, "out_discards", "Out discards") \
275 m(+1, u64, out_errors, "out_errors", "Out errors") \
276 m(+1, u64, in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \
277 m(+1, u64, in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \
278 m(+1, u64, out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \
279 m(+1, u64, out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets")
280
281 #define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \
282 m(+1, u64, port_transmit_wait, "port_transmit_wait", "Port transmit wait") \
283 m(+1, u64, ecn_marked, "ecn_marked", "ECN marked") \
284 m(+1, u64, no_buffer_discard_mc, "no_buffer_discard_mc", "No buffer discard mc") \
285 m(+1, u64, rx_ebp, "rx_ebp", "RX EBP") \
286 m(+1, u64, tx_ebp, "tx_ebp", "TX EBP") \
287 m(+1, u64, rx_buffer_almost_full, "rx_buffer_almost_full", "RX buffer almost full") \
288 m(+1, u64, rx_buffer_full, "rx_buffer_full", "RX buffer full") \
289 m(+1, u64, rx_icrc_encapsulated, "rx_icrc_encapsulated", "RX ICRC encapsulated") \
290 m(+1, u64, ex_reserved_0, "ex_reserved_0", "Reserved") \
291 m(+1, u64, ex_reserved_1, "ex_reserved_1", "Reserved") \
292 m(+1, u64, tx_stat_p64octets, "tx_stat_p64octets", "Bytes") \
293 m(+1, u64, tx_stat_p65to127octets, "tx_stat_p65to127octets", "Bytes") \
294 m(+1, u64, tx_stat_p128to255octets, "tx_stat_p128to255octets", "Bytes") \
295 m(+1, u64, tx_stat_p256to511octets, "tx_stat_p256to511octets", "Bytes") \
296 m(+1, u64, tx_stat_p512to1023octets, "tx_stat_p512to1023octets", "Bytes") \
297 m(+1, u64, tx_stat_p1024to1518octets, "tx_stat_p1024to1518octets", "Bytes") \
298 m(+1, u64, tx_stat_p1519to2047octets, "tx_stat_p1519to2047octets", "Bytes") \
299 m(+1, u64, tx_stat_p2048to4095octets, "tx_stat_p2048to4095octets", "Bytes") \
300 m(+1, u64, tx_stat_p4096to8191octets, "tx_stat_p4096to8191octets", "Bytes") \
301 m(+1, u64, tx_stat_p8192to10239octets, "tx_stat_p8192to10239octets", "Bytes")
302
303 #define MLX5E_PPORT_STATISTICAL_DEBUG(m) \
304 m(+1, u64, phy_time_since_last_clear, "phy_time_since_last_clear", \
305 "Time since last clear in milliseconds") \
306 m(+1, u64, phy_received_bits, "phy_received_bits", \
307 "Total amount of traffic received in bits before error correction") \
308 m(+1, u64, phy_symbol_errors, "phy_symbol_errors", \
309 "Total number of symbol errors before error correction") \
310 m(+1, u64, phy_corrected_bits, "phy_corrected_bits", \
311 "Total number of corrected bits ") \
312 m(+1, u64, phy_corrected_bits_lane0, "phy_corrected_bits_lane0", \
313 "Total number of corrected bits for lane 0") \
314 m(+1, u64, phy_corrected_bits_lane1, "phy_corrected_bits_lane1", \
315 "Total number of corrected bits for lane 1") \
316 m(+1, u64, phy_corrected_bits_lane2, "phy_corrected_bits_lane2", \
317 "Total number of corrected bits for lane 2") \
318 m(+1, u64, phy_corrected_bits_lane3, "phy_corrected_bits_lane3", \
319 "Total number of corrected bits for lane 3")
320
321 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \
322 m(+1, u64, time_since_last_clear, "time_since_last_clear", \
323 "Time since the last counters clear event (msec)") \
324 m(+1, u64, symbol_errors, "symbol_errors", "Symbol errors") \
325 m(+1, u64, sync_headers_errors, "sync_headers_errors", \
326 "Sync header error counter") \
327 m(+1, u64, bip_errors_lane0, "edpl_bip_errors_lane0", \
328 "Indicates the number of PRBS errors on lane 0") \
329 m(+1, u64, bip_errors_lane1, "edpl_bip_errors_lane1", \
330 "Indicates the number of PRBS errors on lane 1") \
331 m(+1, u64, bip_errors_lane2, "edpl_bip_errors_lane2", \
332 "Indicates the number of PRBS errors on lane 2") \
333 m(+1, u64, bip_errors_lane3, "edpl_bip_errors_lane3", \
334 "Indicates the number of PRBS errors on lane 3") \
335 m(+1, u64, fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \
336 "FEC correctable block counter lane 0") \
337 m(+1, u64, fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \
338 "FEC correctable block counter lane 1") \
339 m(+1, u64, fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \
340 "FEC correctable block counter lane 2") \
341 m(+1, u64, fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \
342 "FEC correctable block counter lane 3") \
343 m(+1, u64, rs_corrected_blocks, "rs_corrected_blocks", \
344 "FEC correcable block counter") \
345 m(+1, u64, rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \
346 "FEC uncorrecable block counter") \
347 m(+1, u64, rs_no_errors_blocks, "rs_no_errors_blocks", \
348 "The number of RS-FEC blocks received that had no errors") \
349 m(+1, u64, rs_single_error_blocks, "rs_single_error_blocks", \
350 "The number of corrected RS-FEC blocks received that had" \
351 "exactly 1 error symbol") \
352 m(+1, u64, rs_corrected_symbols_total, "rs_corrected_symbols_total", \
353 "Port FEC corrected symbol counter") \
354 m(+1, u64, rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \
355 "FEC corrected symbol counter lane 0") \
356 m(+1, u64, rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \
357 "FEC corrected symbol counter lane 1") \
358 m(+1, u64, rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \
359 "FEC corrected symbol counter lane 2") \
360 m(+1, u64, rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \
361 "FEC corrected symbol counter lane 3")
362
363 /* Per priority statistics for PFC */
364 #define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \
365 m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \
366 m(n, p, +1, u64, rx_uc_frames, "rx_uc_frames", "Received unicast frames") \
367 m(n, p, +1, u64, rx_mc_frames, "rx_mc_frames", "Received multicast frames") \
368 m(n, p, +1, u64, rx_bc_frames, "rx_bc_frames", "Received broadcast frames") \
369 m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \
370 m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \
371 m(n, p, +1, u64, tx_uc_frames, "tx_uc_frames", "Transmitted unicast frames") \
372 m(n, p, +1, u64, tx_mc_frames, "tx_mc_frames", "Transmitted multicast frames") \
373 m(n, p, +1, u64, tx_bc_frames, "tx_bc_frames", "Transmitted broadcast frames") \
374 m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \
375 m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \
376 m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \
377 "Received pause duration") \
378 m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \
379 m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \
380 "Transmitted pause duration") \
381 m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \
382 "Received pause transitions") \
383 m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \
384 m(n, p, +1, u64, device_stall_minor_watermark, \
385 "device_stall_minor_watermark", "Device stall minor watermark") \
386 m(n, p, +1, u64, device_stall_critical_watermark, \
387 "device_stall_critical_watermark", "Device stall critical watermark")
388
389 #define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \
390 m(c, t, pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d)
391
392 #define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8
393
394 #define MLX5E_PPORT_PER_PRIO_STATS(m) \
395 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \
396 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \
397 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \
398 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \
399 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \
400 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \
401 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \
402 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7)
403
404 #define MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \
405 m(+1, u64, life_time_counter_high, "life_time_counter", \
406 "Life time counter.", pcie_perf_counters) \
407 m(+1, u64, tx_overflow_buffer_pkt, "tx_overflow_buffer_pkt", \
408 "The number of packets dropped due to lack of PCIe buffers " \
409 "in receive path from NIC port toward the hosts.", \
410 pcie_perf_counters) \
411 m(+1, u64, tx_overflow_buffer_marked_pkt, \
412 "tx_overflow_buffer_marked_pkt", \
413 "The number of packets marked due to lack of PCIe buffers " \
414 "in receive path from NIC port toward the hosts.", \
415 pcie_perf_counters)
416
417 #define MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \
418 m(+1, u64, rx_errors, "rx_errors", \
419 "Number of transitions to recovery due to Framing " \
420 "errors and CRC errors.", pcie_perf_counters) \
421 m(+1, u64, tx_errors, "tx_errors", "Number of transitions " \
422 "to recovery due to EIEOS and TS errors.", pcie_perf_counters) \
423 m(+1, u64, l0_to_recovery_eieos, "l0_to_recovery_eieos", "Number of " \
424 "transitions to recovery due to getting EIEOS.", pcie_perf_counters)\
425 m(+1, u64, l0_to_recovery_ts, "l0_to_recovery_ts", "Number of " \
426 "transitions to recovery due to getting TS.", pcie_perf_counters) \
427 m(+1, u64, l0_to_recovery_framing, "l0_to_recovery_framing", "Number "\
428 "of transitions to recovery due to identifying framing " \
429 "errors at gen3/4.", pcie_perf_counters) \
430 m(+1, u64, l0_to_recovery_retrain, "l0_to_recovery_retrain", \
431 "Number of transitions to recovery due to link retrain request " \
432 "from data link.", pcie_perf_counters) \
433 m(+1, u64, crc_error_dllp, "crc_error_dllp", "Number of transitions " \
434 "to recovery due to identifying CRC DLLP errors.", \
435 pcie_perf_counters) \
436 m(+1, u64, crc_error_tlp, "crc_error_tlp", "Number of transitions to "\
437 "recovery due to identifying CRC TLP errors.", pcie_perf_counters) \
438 m(+1, u64, outbound_stalled_reads, "outbound_stalled_reads", \
439 "The percentage of time within the last second that the NIC had " \
440 "outbound non-posted read requests but could not perform the " \
441 "operation due to insufficient non-posted credits.", \
442 pcie_perf_counters) \
443 m(+1, u64, outbound_stalled_writes, "outbound_stalled_writes", \
444 "The percentage of time within the last second that the NIC had " \
445 "outbound posted writes requests but could not perform the " \
446 "operation due to insufficient posted credits.", \
447 pcie_perf_counters) \
448 m(+1, u64, outbound_stalled_reads_events, \
449 "outbound_stalled_reads_events", "The number of events where " \
450 "outbound_stalled_reads was above a threshold.", \
451 pcie_perf_counters) \
452 m(+1, u64, outbound_stalled_writes_events, \
453 "outbound_stalled_writes_events", \
454 "The number of events where outbound_stalled_writes was above " \
455 "a threshold.", pcie_perf_counters)
456
457 #define MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \
458 m(+1, u64, time_to_boot_image_start, "time_to_boot_image_start", \
459 "Time from start until FW boot image starts running in usec.", \
460 pcie_timers_states) \
461 m(+1, u64, time_to_link_image, "time_to_link_image", \
462 "Time from start until FW pci_link image starts running in usec.", \
463 pcie_timers_states) \
464 m(+1, u64, calibration_time, "calibration_time", \
465 "Time it took FW to do calibration in usec.", \
466 pcie_timers_states) \
467 m(+1, u64, time_to_first_perst, "time_to_first_perst", \
468 "Time form start until FW handle first perst. in usec.", \
469 pcie_timers_states) \
470 m(+1, u64, time_to_detect_state, "time_to_detect_state", \
471 "Time from start until first transition to LTSSM.Detect_Q in usec", \
472 pcie_timers_states) \
473 m(+1, u64, time_to_l0, "time_to_l0", \
474 "Time from start until first transition to LTSSM.L0 in usec", \
475 pcie_timers_states) \
476 m(+1, u64, time_to_crs_en, "time_to_crs_en", \
477 "Time from start until crs is enabled in usec", \
478 pcie_timers_states) \
479 m(+1, u64, time_to_plastic_image_start, "time_to_plastic_image_start",\
480 "Time form start until FW plastic image starts running in usec.", \
481 pcie_timers_states) \
482 m(+1, u64, time_to_iron_image_start, "time_to_iron_image_start", \
483 "Time form start until FW iron image starts running in usec.", \
484 pcie_timers_states) \
485 m(+1, u64, perst_handler, "perst_handler", \
486 "Number of persts arrived.", pcie_timers_states) \
487 m(+1, u64, times_in_l1, "times_in_l1", \
488 "Number of times LTSSM entered L1 flow.", pcie_timers_states) \
489 m(+1, u64, times_in_l23, "times_in_l23", \
490 "Number of times LTSSM entered L23 flow.", pcie_timers_states) \
491 m(+1, u64, dl_down, "dl_down", \
492 "Number of moves for DL_active to DL_down.", pcie_timers_states) \
493 m(+1, u64, config_cycle1usec, "config_cycle1usec", \
494 "Number of configuration requests that firmware " \
495 "handled in less than 1 usec.", pcie_timers_states) \
496 m(+1, u64, config_cycle2to7usec, "config_cycle2to7usec", \
497 "Number of configuration requests that firmware " \
498 "handled within 2 to 7 usec.", pcie_timers_states) \
499 m(+1, u64, config_cycle8to15usec, "config_cycle8to15usec", \
500 "Number of configuration requests that firmware " \
501 "handled within 8 to 15 usec.", pcie_timers_states) \
502 m(+1, u64, config_cycle16to63usec, "config_cycle16to63usec", \
503 "Number of configuration requests that firmware " \
504 "handled within 16 to 63 usec.", pcie_timers_states) \
505 m(+1, u64, config_cycle64usec, "config_cycle64usec", \
506 "Number of configuration requests that firmware " \
507 "handled took more than 64 usec.", pcie_timers_states) \
508 m(+1, u64, correctable_err_msg_sent, "correctable_err_msg_sent", \
509 "Number of correctable error messages sent.", pcie_timers_states) \
510 m(+1, u64, non_fatal_err_msg_sent, "non_fatal_err_msg_sent", \
511 "Number of non-Fatal error msg sent.", pcie_timers_states) \
512 m(+1, u64, fatal_err_msg_sent, "fatal_err_msg_sent", \
513 "Number of fatal error msg sent.", pcie_timers_states)
514
515 #define MLX5E_PCIE_LANE_COUNTERS_32(m) \
516 m(+1, u64, error_counter_lane0, "error_counter_lane0", \
517 "Error counter for PCI lane 0", pcie_lanes_counters) \
518 m(+1, u64, error_counter_lane1, "error_counter_lane1", \
519 "Error counter for PCI lane 1", pcie_lanes_counters) \
520 m(+1, u64, error_counter_lane2, "error_counter_lane2", \
521 "Error counter for PCI lane 2", pcie_lanes_counters) \
522 m(+1, u64, error_counter_lane3, "error_counter_lane3", \
523 "Error counter for PCI lane 3", pcie_lanes_counters) \
524 m(+1, u64, error_counter_lane4, "error_counter_lane4", \
525 "Error counter for PCI lane 4", pcie_lanes_counters) \
526 m(+1, u64, error_counter_lane5, "error_counter_lane5", \
527 "Error counter for PCI lane 5", pcie_lanes_counters) \
528 m(+1, u64, error_counter_lane6, "error_counter_lane6", \
529 "Error counter for PCI lane 6", pcie_lanes_counters) \
530 m(+1, u64, error_counter_lane7, "error_counter_lane7", \
531 "Error counter for PCI lane 7", pcie_lanes_counters) \
532 m(+1, u64, error_counter_lane8, "error_counter_lane8", \
533 "Error counter for PCI lane 8", pcie_lanes_counters) \
534 m(+1, u64, error_counter_lane9, "error_counter_lane9", \
535 "Error counter for PCI lane 9", pcie_lanes_counters) \
536 m(+1, u64, error_counter_lane10, "error_counter_lane10", \
537 "Error counter for PCI lane 10", pcie_lanes_counters) \
538 m(+1, u64, error_counter_lane11, "error_counter_lane11", \
539 "Error counter for PCI lane 11", pcie_lanes_counters) \
540 m(+1, u64, error_counter_lane12, "error_counter_lane12", \
541 "Error counter for PCI lane 12", pcie_lanes_counters) \
542 m(+1, u64, error_counter_lane13, "error_counter_lane13", \
543 "Error counter for PCI lane 13", pcie_lanes_counters) \
544 m(+1, u64, error_counter_lane14, "error_counter_lane14", \
545 "Error counter for PCI lane 14", pcie_lanes_counters) \
546 m(+1, u64, error_counter_lane15, "error_counter_lane15", \
547 "Error counter for PCI lane 15", pcie_lanes_counters)
548
549 /*
550 * Make sure to update mlx5e_update_pport_counters()
551 * when adding a new MLX5E_PPORT_STATS block
552 */
553 #define MLX5E_PPORT_STATS(m) \
554 MLX5E_PPORT_PER_PRIO_STATS(m) \
555 MLX5E_PPORT_IEEE802_3_STATS(m) \
556 MLX5E_PPORT_RFC2819_STATS(m)
557
558 #define MLX5E_PORT_STATS_DEBUG(m) \
559 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \
560 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
561 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \
562 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \
563 MLX5E_PPORT_STATISTICAL_DEBUG(m) \
564 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \
565 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \
566 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \
567 MLX5E_PCIE_LANE_COUNTERS_32(m)
568
569 #define MLX5E_PPORT_IEEE802_3_STATS_NUM \
570 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT))
571 #define MLX5E_PPORT_RFC2819_STATS_NUM \
572 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT))
573 #define MLX5E_PPORT_STATS_NUM \
574 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT))
575
576 #define MLX5E_PPORT_PER_PRIO_STATS_NUM \
577 (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT))
578 #define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \
579 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT))
580 #define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \
581 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT))
582 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \
583 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT))
584 #define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM \
585 (0 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(MLX5E_STATS_COUNT))
586 #define MLX5E_PPORT_STATISTICAL_DEBUG_NUM \
587 (0 MLX5E_PPORT_STATISTICAL_DEBUG(MLX5E_STATS_COUNT))
588 #define MLX5E_PORT_STATS_DEBUG_NUM \
589 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT))
590
591 struct mlx5e_pport_stats {
592 struct sysctl_ctx_list ctx;
593 u64 arg [0];
594 MLX5E_PPORT_STATS(MLX5E_STATS_VAR)
595 };
596
597 struct mlx5e_port_stats_debug {
598 struct sysctl_ctx_list ctx;
599 u64 arg [0];
600 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR)
601 };
602
603 #define MLX5E_RQ_STATS(m) \
604 m(+1, u64, packets, "packets", "Received packets") \
605 m(+1, u64, bytes, "bytes", "Received bytes") \
606 m(+1, u64, csum_none, "csum_none", "Received packets") \
607 m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \
608 m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \
609 m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \
610 m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \
611 m(+1, u64, wqe_err, "wqe_err", "Received packets") \
612 m(+1, u64, decrypted_ok_packets, "decrypted_ok_packets", "Received packets successfully decrypted by steering rule(s)") \
613 m(+1, u64, decrypted_error_packets, "decrypted_error_packets", "Received packets not decrypted by steering rule(s)")
614
615 #define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT))
616
617 struct mlx5e_rq_stats {
618 struct sysctl_ctx_list ctx;
619 u64 arg [0];
620 MLX5E_RQ_STATS(MLX5E_STATS_VAR)
621 };
622
623 #define MLX5E_SQ_STATS(m) \
624 m(+1, u64, packets, "packets", "Transmitted packets") \
625 m(+1, u64, bytes, "bytes", "Transmitted bytes") \
626 m(+1, u64, tso_packets, "tso_packets", "Transmitted packets") \
627 m(+1, u64, tso_bytes, "tso_bytes", "Transmitted bytes") \
628 m(+1, u64, csum_offload_none, "csum_offload_none", "Transmitted packets") \
629 m(+1, u64, defragged, "defragged", "Transmitted packets") \
630 m(+1, u64, dropped, "dropped", "Transmitted packets") \
631 m(+1, u64, enobuf, "enobuf", "Transmitted packets") \
632 m(+1, u64, cqe_err, "cqe_err", "Transmit CQE errors") \
633 m(+1, u64, nop, "nop", "Transmitted packets")
634
635 #define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT))
636
637 struct mlx5e_sq_stats {
638 struct sysctl_ctx_list ctx;
639 u64 arg [0];
640 MLX5E_SQ_STATS(MLX5E_STATS_VAR)
641 };
642
643 struct mlx5e_stats {
644 struct mlx5e_vport_stats vport;
645 struct mlx5e_pport_stats pport;
646 struct mlx5e_port_stats_debug port_stats_debug;
647 };
648
649 struct mlx5e_rq_param {
650 u32 rqc [MLX5_ST_SZ_DW(rqc)];
651 struct mlx5_wq_param wq;
652 };
653
654 struct mlx5e_sq_param {
655 u32 sqc [MLX5_ST_SZ_DW(sqc)];
656 struct mlx5_wq_param wq;
657 };
658
659 struct mlx5e_cq_param {
660 u32 cqc [MLX5_ST_SZ_DW(cqc)];
661 struct mlx5_wq_param wq;
662 };
663
664 struct mlx5e_params {
665 u8 log_sq_size;
666 u8 log_rq_size;
667 u16 num_channels;
668 u8 default_vlan_prio;
669 u8 num_tc;
670 u8 rx_cq_moderation_mode;
671 u8 tx_cq_moderation_mode;
672 u16 rx_cq_moderation_usec;
673 u16 rx_cq_moderation_pkts;
674 u16 tx_cq_moderation_usec;
675 u16 tx_cq_moderation_pkts;
676 bool hw_lro_en;
677 bool cqe_zipping_en;
678 u32 lro_wqe_sz;
679 u16 rx_hash_log_tbl_sz;
680 u32 tx_pauseframe_control __aligned(4);
681 u32 rx_pauseframe_control __aligned(4);
682 u16 tx_max_inline;
683 u8 tx_min_inline_mode;
684 u8 tx_priority_flow_control;
685 u8 rx_priority_flow_control;
686 u8 channels_rsss;
687 };
688
689 #define MLX5E_PARAMS(m) \
690 m(+1, u64, tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \
691 m(+1, u64, rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \
692 m(+1, u64, tx_queue_size, "tx_queue_size", "Default send queue size") \
693 m(+1, u64, rx_queue_size, "rx_queue_size", "Default receive queue size") \
694 m(+1, u64, channels, "channels", "Default number of channels") \
695 m(+1, u64, channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \
696 m(+1, u64, coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \
697 m(+1, u64, coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \
698 m(+1, u64, rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \
699 m(+1, u64, rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \
700 m(+1, u64, rx_coalesce_mode, "rx_coalesce_mode", "0: EQE fixed mode 1: CQE fixed mode 2: EQE auto mode 3: CQE auto mode") \
701 m(+1, u64, tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \
702 m(+1, u64, tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \
703 m(+1, u64, tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \
704 m(+1, u64, tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \
705 m(+1, u64, tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \
706 m(+1, u64, hw_lro, "hw_lro", "set to enable hw_lro") \
707 m(+1, u64, cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \
708 m(+1, u64, modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \
709 m(+1, u64, modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \
710 m(+1, u64, diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \
711 m(+1, u64, diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \
712 m(+1, u64, hw_mtu, "hw_mtu", "Current hardware MTU value") \
713 m(+1, u64, mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \
714 m(+1, u64, uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") \
715 m(+1, s64, irq_cpu_base, "irq_cpu_base", "-1: Don't bind IRQ 0..NCPU-1: select this base CPU when binding IRQs") \
716 m(+1, s64, irq_cpu_stride, "irq_cpu_stride", "0..NCPU-1: Distance between IRQ vectors when binding them")
717
718 #define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT))
719
720 struct mlx5e_params_ethtool {
721 u64 arg [0];
722 MLX5E_PARAMS(MLX5E_STATS_VAR)
723 u64 max_bw_value[IEEE_8021QAZ_MAX_TCS];
724 u8 max_bw_share[IEEE_8021QAZ_MAX_TCS];
725 u8 prio_tc[MLX5E_MAX_PRIORITY];
726 u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP];
727 u8 trust_state;
728 u8 fec_mask_10x_25x[MLX5E_MAX_FEC_10X_25X];
729 u16 fec_mask_50x[MLX5E_MAX_FEC_50X];
730 u8 fec_avail_10x_25x[MLX5E_MAX_FEC_10X_25X];
731 u16 fec_avail_50x[MLX5E_MAX_FEC_50X];
732 u32 fec_mode_active;
733 u32 hw_mtu_msb;
734 s32 hw_val_temp[MLX5_MAX_TEMPERATURE];
735 u32 hw_num_temp;
736 };
737
738 struct mlx5e_cq {
739 /* data path - accessed per cqe */
740 struct mlx5_cqwq wq;
741
742 /* data path - accessed per HW polling */
743 struct mlx5_core_cq mcq;
744
745 /* control */
746 struct mlx5e_priv *priv;
747 struct mlx5_wq_ctrl wq_ctrl;
748 } __aligned(MLX5E_CACHELINE_SIZE);
749
750 struct mlx5e_rq_mbuf {
751 bus_dmamap_t dma_map;
752 caddr_t data;
753 struct mbuf *mbuf;
754 };
755
756 struct mlx5e_rq {
757 /* persistent fields */
758 struct mtx mtx;
759 struct mlx5e_rq_stats stats;
760 struct callout watchdog;
761
762 /* data path */
763 #define mlx5e_rq_zero_start wq
764 struct mlx5_wq_ll wq;
765 bus_dma_tag_t dma_tag;
766 u32 wqe_sz;
767 u32 nsegs;
768 struct mlx5e_rq_mbuf *mbuf;
769 if_t ifp;
770 struct mlx5e_cq cq;
771 struct lro_ctrl lro;
772 volatile int enabled;
773 int ix;
774
775 /* Dynamic Interrupt Moderation */
776 struct net_dim dim;
777
778 /* control */
779 struct mlx5_wq_ctrl wq_ctrl;
780 u32 rqn;
781 struct mlx5e_channel *channel;
782 } __aligned(MLX5E_CACHELINE_SIZE);
783
784 typedef void (mlx5e_iq_callback_t)(void *arg);
785
786 struct mlx5e_iq_data {
787 bus_dmamap_t dma_map;
788 mlx5e_iq_callback_t *callback;
789 void *arg;
790 volatile s32 *p_refcount; /* in use refcount, if any */
791 u32 num_wqebbs;
792 u32 dma_sync;
793 };
794
795 struct mlx5e_iq {
796 /* persistant fields */
797 struct mtx lock;
798 struct mtx comp_lock;
799 int db_inhibit;
800
801 /* data path */
802 #define mlx5e_iq_zero_start dma_tag
803 bus_dma_tag_t dma_tag;
804
805 u16 cc; /* consumer counter */
806 u16 pc __aligned(MLX5E_CACHELINE_SIZE);
807 u16 running;
808
809 union {
810 u32 d32[2];
811 u64 d64;
812 } doorbell;
813
814 struct mlx5e_cq cq;
815
816 /* pointers to per request info: write@xmit, read@completion */
817 struct mlx5e_iq_data *data;
818
819 /* read only */
820 struct mlx5_wq_cyc wq;
821 void __iomem *uar_map;
822 u32 sqn;
823 u32 mkey_be;
824
825 /* control path */
826 struct mlx5_wq_ctrl wq_ctrl;
827 struct mlx5e_priv *priv;
828 };
829
830 struct mlx5e_sq_mbuf {
831 bus_dmamap_t dma_map;
832 struct mbuf *mbuf;
833 struct m_snd_tag *mst; /* if set, unref this send tag on completion */
834 u32 num_bytes;
835 u32 num_wqebbs;
836 };
837
838 enum {
839 MLX5E_SQ_READY,
840 MLX5E_SQ_FULL
841 };
842
843 struct mlx5e_sq {
844 /* persistent fields */
845 struct mtx lock;
846 struct mtx comp_lock;
847 struct mlx5e_sq_stats stats;
848 struct callout cev_callout;
849 int db_inhibit;
850
851 /* data path */
852 #define mlx5e_sq_zero_start dma_tag
853 bus_dma_tag_t dma_tag;
854
855 /* dirtied @completion */
856 u16 cc;
857
858 /* dirtied @xmit */
859 u16 pc __aligned(MLX5E_CACHELINE_SIZE);
860 u16 cev_counter; /* completion event counter */
861 u16 cev_factor; /* completion event factor */
862 u16 cev_next_state; /* next completion event state */
863 #define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */
864 #define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */
865 #define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */
866 u16 running; /* set if SQ is running */
867 union {
868 u32 d32[2];
869 u64 d64;
870 } doorbell;
871
872 struct mlx5e_cq cq;
873
874 /* pointers to per packet info: write@xmit, read@completion */
875 struct mlx5e_sq_mbuf *mbuf;
876
877 /* read only */
878 struct mlx5_wq_cyc wq;
879 void __iomem *uar_map;
880 struct ifnet *ifp;
881 u32 sqn;
882 u32 mkey_be;
883 u16 max_inline;
884 u8 min_inline_mode;
885 u8 min_insert_caps;
886 u32 queue_handle; /* SQ remap support */
887 #define MLX5E_INSERT_VLAN 1
888 #define MLX5E_INSERT_NON_VLAN 2
889
890 /* control path */
891 struct mlx5_wq_ctrl wq_ctrl;
892 struct mlx5e_priv *priv;
893 int tc;
894 } __aligned(MLX5E_CACHELINE_SIZE);
895
896 static inline bool
mlx5e_sq_has_room_for(struct mlx5e_sq * sq,u16 n)897 mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
898 {
899 u16 cc = sq->cc;
900 u16 pc = sq->pc;
901
902 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc);
903 }
904
905 static inline u32
mlx5e_sq_queue_level(struct mlx5e_sq * sq)906 mlx5e_sq_queue_level(struct mlx5e_sq *sq)
907 {
908 u16 cc;
909 u16 pc;
910
911 if (sq == NULL)
912 return (0);
913
914 cc = sq->cc;
915 pc = sq->pc;
916
917 return (((sq->wq.sz_m1 & (pc - cc)) *
918 IF_SND_QUEUE_LEVEL_MAX) / sq->wq.sz_m1);
919 }
920
921 struct mlx5e_channel {
922 struct mlx5e_rq rq;
923 struct m_snd_tag tag;
924 struct mlx5_sq_bfreg bfreg;
925 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC];
926 struct mlx5e_iq iq;
927 struct mlx5e_priv *priv;
928 struct completion completion;
929 int ix;
930 u32 rqtn;
931 } __aligned(MLX5E_CACHELINE_SIZE);
932
933 enum mlx5e_traffic_types {
934 MLX5E_TT_IPV4_TCP,
935 MLX5E_TT_IPV6_TCP,
936 MLX5E_TT_IPV4_UDP,
937 MLX5E_TT_IPV6_UDP,
938 MLX5E_TT_IPV4_IPSEC_AH,
939 MLX5E_TT_IPV6_IPSEC_AH,
940 MLX5E_TT_IPV4_IPSEC_ESP,
941 MLX5E_TT_IPV6_IPSEC_ESP,
942 MLX5E_TT_IPV4,
943 MLX5E_TT_IPV6,
944 MLX5E_TT_ANY,
945 MLX5E_NUM_TT,
946 };
947
948 enum {
949 MLX5E_RQT_SPREADING = 0,
950 MLX5E_RQT_DEFAULT_RQ = 1,
951 MLX5E_NUM_RQT = 2,
952 };
953
954 struct mlx5_flow_rule;
955
956 struct mlx5e_eth_addr_info {
957 u8 addr [ETH_ALEN + 2];
958 /* flow table rule per traffic type */
959 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
960 };
961
962 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
963
964 struct mlx5e_eth_addr_hash_node;
965
966 struct mlx5e_eth_addr_hash_head {
967 struct mlx5e_eth_addr_hash_node *lh_first;
968 };
969
970 struct mlx5e_eth_addr_db {
971 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE];
972 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE];
973 struct mlx5e_eth_addr_info broadcast;
974 struct mlx5e_eth_addr_info allmulti;
975 struct mlx5e_eth_addr_info promisc;
976 bool broadcast_enabled;
977 bool allmulti_enabled;
978 bool promisc_enabled;
979 };
980
981 enum {
982 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
983 MLX5E_STATE_OPENED,
984 MLX5E_STATE_FLOW_RULES_READY,
985 };
986
987 enum {
988 MLX5_BW_NO_LIMIT = 0,
989 MLX5_100_MBPS_UNIT = 3,
990 MLX5_GBPS_UNIT = 4,
991 };
992
993 struct mlx5e_vlan_db {
994 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
995 struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID];
996 struct mlx5_flow_rule *untagged_ft_rule;
997 struct mlx5_flow_rule *any_cvlan_ft_rule;
998 struct mlx5_flow_rule *any_svlan_ft_rule;
999 bool filter_disabled;
1000 };
1001
1002 struct mlx5e_vxlan_db_el {
1003 u_int refcount;
1004 u_int proto;
1005 u_int port;
1006 bool installed;
1007 struct mlx5_flow_rule *vxlan_ft_rule;
1008 TAILQ_ENTRY(mlx5e_vxlan_db_el) link;
1009 };
1010
1011 struct mlx5e_vxlan_db {
1012 TAILQ_HEAD(, mlx5e_vxlan_db_el) head;
1013 };
1014
1015 struct mlx5e_flow_table {
1016 int num_groups;
1017 struct mlx5_flow_table *t;
1018 struct mlx5_flow_group **g;
1019 };
1020
1021 enum accel_fs_tcp_type {
1022 MLX5E_ACCEL_FS_IPV4_TCP,
1023 MLX5E_ACCEL_FS_IPV6_TCP,
1024 MLX5E_ACCEL_FS_TCP_NUM_TYPES,
1025 };
1026
1027 struct mlx5e_accel_fs_tcp {
1028 struct mlx5_flow_namespace *ns;
1029 struct mlx5e_flow_table tables[MLX5E_ACCEL_FS_TCP_NUM_TYPES];
1030 struct mlx5_flow_rule *default_rules[MLX5E_ACCEL_FS_TCP_NUM_TYPES];
1031 };
1032
1033 struct mlx5e_flow_tables {
1034 struct mlx5_flow_namespace *ns;
1035 struct mlx5e_flow_table vlan;
1036 struct mlx5e_flow_table vxlan;
1037 struct mlx5_flow_rule *vxlan_catchall_ft_rule;
1038 struct mlx5e_flow_table main;
1039 struct mlx5e_flow_table main_vxlan;
1040 struct mlx5_flow_rule *main_vxlan_rule[MLX5E_NUM_TT];
1041 struct mlx5e_flow_table inner_rss;
1042 struct mlx5e_accel_fs_tcp accel_tcp;
1043 };
1044
1045 struct mlx5e_xmit_args {
1046 struct m_snd_tag *mst;
1047 u32 tisn;
1048 u16 ihs;
1049 };
1050
1051 #include <dev/mlx5/mlx5_en/en_rl.h>
1052 #include <dev/mlx5/mlx5_en/en_hw_tls.h>
1053 #include <dev/mlx5/mlx5_en/en_hw_tls_rx.h>
1054
1055 #define MLX5E_TSTMP_PREC 10
1056
1057 struct mlx5e_clbr_point {
1058 uint64_t base_curr;
1059 uint64_t base_prev;
1060 uint64_t clbr_hw_prev;
1061 uint64_t clbr_hw_curr;
1062 u_int clbr_gen;
1063 };
1064
1065 struct mlx5e_dcbx {
1066 u32 cable_len;
1067 u32 xoff;
1068 };
1069
1070 struct mlx5e_priv {
1071 struct mlx5_core_dev *mdev; /* must be first */
1072
1073 /* priv data path fields - start */
1074 int order_base_2_num_channels;
1075 int queue_mapping_channel_mask;
1076 int num_tc;
1077 int default_vlan_prio;
1078 /* priv data path fields - end */
1079
1080 unsigned long state;
1081 int gone;
1082 #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock)
1083 #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock)
1084 #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock)
1085 #define PRIV_ASSERT_LOCKED(priv) sx_assert(&(priv)->state_lock, SA_XLOCKED)
1086 struct sx state_lock; /* Protects Interface state */
1087 struct mlx5e_rq drop_rq;
1088 u32 pdn;
1089 u32 tdn;
1090 struct mlx5_core_mkey mr;
1091
1092 u32 tisn[MLX5E_MAX_TX_NUM_TC];
1093 u32 rqtn;
1094 u32 tirn[MLX5E_NUM_TT];
1095 u32 tirn_inner_vxlan[MLX5E_NUM_TT];
1096
1097 struct mlx5e_flow_tables fts;
1098 struct mlx5e_eth_addr_db eth_addr;
1099 struct mlx5e_vlan_db vlan;
1100 struct mlx5e_vxlan_db vxlan;
1101
1102 struct mlx5e_params params;
1103 struct mlx5e_params_ethtool params_ethtool;
1104 union mlx5_core_pci_diagnostics params_pci;
1105 union mlx5_core_general_diagnostics params_general;
1106 struct mtx async_events_mtx; /* sync hw events */
1107 struct work_struct update_stats_work;
1108 struct work_struct update_carrier_work;
1109 struct work_struct set_rx_mode_work;
1110 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock)
1111
1112 if_t ifp;
1113 struct sysctl_ctx_list sysctl_ctx;
1114 struct sysctl_oid *sysctl_ifnet;
1115 struct sysctl_oid *sysctl_hw;
1116 int sysctl_debug;
1117 struct mlx5e_stats stats;
1118 int counter_set_id;
1119
1120 struct workqueue_struct *wq;
1121
1122 eventhandler_tag vlan_detach;
1123 eventhandler_tag vlan_attach;
1124 struct ifmedia media;
1125 int media_status_last;
1126 int media_active_last;
1127 eventhandler_tag vxlan_start;
1128 eventhandler_tag vxlan_stop;
1129
1130 struct callout watchdog;
1131
1132 struct mlx5e_rl_priv_data rl;
1133
1134 struct mlx5e_tls tls;
1135 struct mlx5e_tls_rx tls_rx;
1136
1137 struct callout tstmp_clbr;
1138 int clbr_done;
1139 int clbr_curr;
1140 struct mlx5e_clbr_point clbr_points[2];
1141 u_int clbr_gen;
1142 uint64_t cclk;
1143
1144 struct mlx5e_dcbx dcbx;
1145 bool sw_is_port_buf_owner;
1146
1147 struct pfil_head *pfil;
1148 struct mlx5e_channel channel[];
1149 };
1150
1151 #define MLX5E_NET_IP_ALIGN 2
1152
1153 struct mlx5e_tx_wqe {
1154 struct mlx5_wqe_ctrl_seg ctrl;
1155 struct mlx5_wqe_eth_seg eth;
1156 };
1157
1158 struct mlx5e_tx_umr_wqe {
1159 struct mlx5_wqe_ctrl_seg ctrl;
1160 struct mlx5_wqe_umr_ctrl_seg umr;
1161 uint8_t mkc[64];
1162 };
1163
1164 struct mlx5e_tx_psv_wqe {
1165 struct mlx5_wqe_ctrl_seg ctrl;
1166 struct mlx5_seg_set_psv psv;
1167 };
1168
1169 struct mlx5e_tx_qos_remap_wqe {
1170 struct mlx5_wqe_ctrl_seg ctrl;
1171 struct mlx5_wqe_qos_remap_seg qos_remap;
1172 };
1173
1174 struct mlx5e_rx_wqe {
1175 struct mlx5_wqe_srq_next_seg next;
1176 struct mlx5_wqe_data_seg data[];
1177 };
1178
1179 /* the size of the structure above must be power of two */
1180 CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe)));
1181
1182 struct mlx5e_eeprom {
1183 int lock_bit;
1184 int i2c_addr;
1185 int page_num;
1186 int device_addr;
1187 int module_num;
1188 int len;
1189 int type;
1190 int page_valid;
1191 u32 *data;
1192 };
1193
1194 #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL)
1195
1196 bool mlx5e_do_send_cqe(struct mlx5e_sq *);
1197 int mlx5e_get_full_header_size(const struct mbuf *, const struct tcphdr **);
1198 int mlx5e_xmit(if_t, struct mbuf *);
1199
1200 int mlx5e_open_locked(if_t);
1201 int mlx5e_close_locked(if_t);
1202
1203 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event);
1204 void mlx5e_dump_err_cqe(struct mlx5e_cq *, u32, const struct mlx5_err_cqe *);
1205
1206 mlx5e_cq_comp_t mlx5e_rx_cq_comp;
1207 mlx5e_cq_comp_t mlx5e_tx_cq_comp;
1208 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
1209
1210 void mlx5e_dim_work(struct work_struct *);
1211 void mlx5e_dim_build_cq_param(struct mlx5e_priv *, struct mlx5e_cq_param *);
1212
1213 int mlx5e_open_flow_tables(struct mlx5e_priv *priv);
1214 void mlx5e_close_flow_tables(struct mlx5e_priv *priv);
1215 int mlx5e_open_flow_rules(struct mlx5e_priv *priv);
1216 void mlx5e_close_flow_rules(struct mlx5e_priv *priv);
1217 void mlx5e_set_rx_mode_work(struct work_struct *work);
1218
1219 void mlx5e_vlan_rx_add_vid(void *, if_t, u16);
1220 void mlx5e_vlan_rx_kill_vid(void *, if_t, u16);
1221 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
1222 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
1223
1224 void mlx5e_vxlan_start(void *arg, if_t ifp, sa_family_t family,
1225 u_int port);
1226 void mlx5e_vxlan_stop(void *arg, if_t ifp, sa_family_t family,
1227 u_int port);
1228 int mlx5e_add_all_vxlan_rules(struct mlx5e_priv *priv);
1229 void mlx5e_del_all_vxlan_rules(struct mlx5e_priv *priv);
1230
1231 static inline void
mlx5e_tx_notify_hw(struct mlx5e_sq * sq,bool force)1232 mlx5e_tx_notify_hw(struct mlx5e_sq *sq, bool force)
1233 {
1234 if (unlikely((force == false && sq->db_inhibit != 0) || sq->doorbell.d64 == 0)) {
1235 /* skip writing the doorbell record */
1236 return;
1237 }
1238
1239 /* ensure wqe is visible to device before updating doorbell record */
1240 wmb();
1241
1242 *sq->wq.db = cpu_to_be32(sq->pc);
1243
1244 /*
1245 * Ensure the doorbell record is visible to device before ringing
1246 * the doorbell:
1247 */
1248 wmb();
1249
1250 mlx5_write64(sq->doorbell.d32, sq->uar_map,
1251 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock));
1252
1253 sq->doorbell.d64 = 0;
1254 }
1255
1256 static inline void
mlx5e_cq_arm(struct mlx5e_cq * cq,spinlock_t * dblock)1257 mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock)
1258 {
1259 struct mlx5_core_cq *mcq;
1260
1261 mcq = &cq->mcq;
1262 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc);
1263 }
1264
1265 #define mlx5e_dbg(_IGN, _priv, ...) mlx5_core_dbg((_priv)->mdev, __VA_ARGS__)
1266
1267 extern const struct ethtool_ops mlx5e_ethtool_ops;
1268 void mlx5e_create_ethtool(struct mlx5e_priv *);
1269 void mlx5e_create_stats(struct sysctl_ctx_list *,
1270 struct sysctl_oid_list *, const char *,
1271 const char **, unsigned, u64 *);
1272 void mlx5e_create_counter_stats(struct sysctl_ctx_list *,
1273 struct sysctl_oid_list *, const char *,
1274 const char **, unsigned, counter_u64_t *);
1275 void mlx5e_send_nop(struct mlx5e_sq *, u32);
1276 int mlx5e_sq_dump_xmit(struct mlx5e_sq *, struct mlx5e_xmit_args *, struct mbuf **);
1277 int mlx5e_sq_xmit(struct mlx5e_sq *, struct mbuf **);
1278 void mlx5e_sq_cev_timeout(void *);
1279 int mlx5e_refresh_channel_params(struct mlx5e_priv *);
1280 int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *,
1281 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix);
1282 void mlx5e_close_cq(struct mlx5e_cq *);
1283 void mlx5e_free_sq_db(struct mlx5e_sq *);
1284 int mlx5e_alloc_sq_db(struct mlx5e_sq *);
1285 int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *,
1286 const struct mlx5_sq_bfreg *, int tis_num);
1287 int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state);
1288 void mlx5e_disable_sq(struct mlx5e_sq *);
1289 void mlx5e_drain_sq(struct mlx5e_sq *);
1290 void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value);
1291 void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value);
1292 void mlx5e_resume_sq(struct mlx5e_sq *sq);
1293 void mlx5e_update_sq_inline(struct mlx5e_sq *sq);
1294 void mlx5e_refresh_sq_inline(struct mlx5e_priv *priv);
1295 int mlx5e_update_buf_lossy(struct mlx5e_priv *priv);
1296 int mlx5e_fec_update(struct mlx5e_priv *priv);
1297 int mlx5e_hw_temperature_update(struct mlx5e_priv *priv);
1298
1299 /* Internal Queue, IQ, API functions */
1300 void mlx5e_iq_send_nop(struct mlx5e_iq *, u32);
1301 int mlx5e_iq_open(struct mlx5e_channel *, struct mlx5e_sq_param *, struct mlx5e_cq_param *, struct mlx5e_iq *);
1302 void mlx5e_iq_close(struct mlx5e_iq *);
1303 void mlx5e_iq_static_init(struct mlx5e_iq *);
1304 void mlx5e_iq_static_destroy(struct mlx5e_iq *);
1305 void mlx5e_iq_notify_hw(struct mlx5e_iq *);
1306 int mlx5e_iq_get_producer_index(struct mlx5e_iq *);
1307 void mlx5e_iq_load_memory_single(struct mlx5e_iq *, u16, void *, size_t, u64 *, u32);
1308
1309 #endif /* _MLX5_EN_H_ */
1310