1 /* 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved. 5 * Support: <fbsd-storage-driver.pdl@broadcom.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation and/or other 15 * materials provided with the distribution. 16 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors 17 * may be used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 * 32 * The views and conclusions contained in the software and documentation are 33 * those of the authors and should not be interpreted as representing 34 * official policies,either expressed or implied, of the FreeBSD Project. 35 * 36 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 37 * 38 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD 39 * 40 * 41 * Version History 42 * --------------- 43 * 44 * Date Version Description 45 * -------- ----------- ------------------------------------------------------ 46 * 11-30-18 03.00.00.08 Corresponds to Fusion-MPT MPI 3.0 Specification Rev H. 47 * 02-08-19 03.00.00.09 Corresponds to Fusion-MPT MPI 3.0 Specification Rev I. 48 * 05-03-19 03.00.00.10 Corresponds to Fusion-MPT MPI 3.0 Specification Rev J. 49 * 08-30-19 03.00.00.12 Corresponds to Fusion-MPT MPI 3.0 Specification Rev L. 50 * 11-01-19 03.00.00.13 Corresponds to Fusion-MPT MPI 3.0 Specification Rev M. 51 * 12-16-19 03.00.00.14 Corresponds to Fusion-MPT MPI 3.0 Specification Rev N. 52 * 02-28-20 03.00.00.15 Corresponds to Fusion-MPT MPI 3.0 Specification Rev O. 53 * 05-01-20 03.00.00.16 Corresponds to Fusion-MPT MPI 3.0 Specification Rev P. 54 * 06-26-20 03.00.00.17 Corresponds to Fusion-MPT MPI 3.0 Specification Rev Q. 55 * 08-28-20 03.00.00.18 Corresponds to Fusion-MPT MPI 3.0 Specification Rev R. 56 * 10-30-20 03.00.00.19 Corresponds to Fusion-MPT MPI 3.0 Specification Rev S. 57 * 12-18-20 03.00.00.20 Corresponds to Fusion-MPT MPI 3.0 Specification Rev T. 58 * 02-09-21 03.00.20.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev T - Interim Release 1. 59 * 02-26-21 03.00.21.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U. 60 * 04-16-21 03.00.21.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U - Interim Release 1. 61 * 04-28-21 03.00.21.02 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U - Interim Release 2. 62 * 05-28-21 03.00.22.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev V. 63 * 07-23-21 03.00.22.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev V - Interim Release 1. 64 * 09-03-21 03.00.23.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 23. 65 * 10-23-21 03.00.23.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 23 - Interim Release 1. 66 * 12-03-21 03.00.24.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 24. 67 * 02-25-22 03.00.25.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 25. 68 * 06-03-22 03.00.26.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 26. 69 * 08-09-22 03.00.26.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 26 - Interim Release 1. 70 * 09-02-22 03.00.27.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 27. 71 * 10-20-22 03.00.27.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 27 - Interim Release 1. 72 * 12-02-22 03.00.28.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 28. 73 * 02-24-23 03.00.29.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 29. 74 * 05-19-23 03.00.30.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 30. 75 * 08-18-23 03.00.30.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 30 - Interim Release 1. 76 * 11-17-23 03.00.31.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 31 77 * 02-16-24 03.00.32.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 32 78 */ 79 #ifndef MPI30_TRANSPORT_H 80 #define MPI30_TRANSPORT_H 1 81 82 /***************************************************************************** 83 * Common version structure/union used in * 84 * messages and configuration pages * 85 ****************************************************************************/ 86 87 typedef struct _MPI3_VERSION_STRUCT 88 { 89 U8 Dev; /* 0x00 */ 90 U8 Unit; /* 0x01 */ 91 U8 Minor; /* 0x02 */ 92 U8 Major; /* 0x03 */ 93 } MPI3_VERSION_STRUCT, MPI3_POINTER PTR_MPI3_VERSION_STRUCT, 94 Mpi3VersionStruct_t, MPI3_POINTER pMpi3VersionStruct_t; 95 96 typedef union _MPI3_VERSION_UNION 97 { 98 MPI3_VERSION_STRUCT Struct; 99 U32 Word; 100 } MPI3_VERSION_UNION, MPI3_POINTER PTR_MPI3_VERSION_UNION, 101 Mpi3VersionUnion_t, MPI3_POINTER pMpi3VersionUnion_t; 102 103 /****** Version constants for this revision ****/ 104 #define MPI3_VERSION_MAJOR (3) 105 #define MPI3_VERSION_MINOR (0) 106 #define MPI3_VERSION_UNIT (32) 107 #define MPI3_VERSION_DEV (0) 108 109 /****** DevHandle definitions *****/ 110 #define MPI3_DEVHANDLE_INVALID (0xFFFF) 111 112 /***************************************************************************** 113 * System Interface Register Definitions * 114 ****************************************************************************/ 115 typedef struct _MPI3_SYSIF_OPER_QUEUE_INDEXES 116 { 117 U16 ProducerIndex; /* 0x00 */ 118 U16 Reserved02; /* 0x02 */ 119 U16 ConsumerIndex; /* 0x04 */ 120 U16 Reserved06; /* 0x06 */ 121 } MPI3_SYSIF_OPER_QUEUE_INDEXES, MPI3_POINTER PTR_MPI3_SYSIF_OPER_QUEUE_INDEXES; 122 123 typedef volatile struct _MPI3_SYSIF_REGISTERS 124 { 125 U64 IOCInformation; /* 0x00 */ 126 MPI3_VERSION_UNION Version; /* 0x08 */ 127 U32 Reserved0C[2]; /* 0x0C */ 128 U32 IOCConfiguration; /* 0x14 */ 129 U32 Reserved18; /* 0x18 */ 130 U32 IOCStatus; /* 0x1C */ 131 U32 Reserved20; /* 0x20 */ 132 U32 AdminQueueNumEntries; /* 0x24 */ 133 U64 AdminRequestQueueAddress; /* 0x28 */ 134 U64 AdminReplyQueueAddress; /* 0x30 */ 135 U32 Reserved38[2]; /* 0x38 */ 136 U32 CoalesceControl; /* 0x40 */ 137 U32 Reserved44[1007]; /* 0x44 */ 138 U16 AdminRequestQueuePI; /* 0x1000 */ 139 U16 Reserved1002; /* 0x1002 */ 140 U16 AdminReplyQueueCI; /* 0x1004 */ 141 U16 Reserved1006; /* 0x1006 */ 142 MPI3_SYSIF_OPER_QUEUE_INDEXES OperQueueIndexes[383]; /* 0x1008 */ 143 U32 Reserved1C00; /* 0x1C00 */ 144 U32 WriteSequence; /* 0x1C04 */ 145 U32 HostDiagnostic; /* 0x1C08 */ 146 U32 Reserved1C0C; /* 0x1C0C */ 147 U32 Fault; /* 0x1C10 */ 148 U32 FaultInfo[3]; /* 0x1C14 */ 149 U32 Reserved1C20[4]; /* 0x1C20 */ 150 U64 HCBAddress; /* 0x1C30 */ 151 U32 HCBSize; /* 0x1C38 */ 152 U32 Reserved1C3C; /* 0x1C3C */ 153 U32 ReplyFreeHostIndex; /* 0x1C40 */ 154 U32 SenseBufferFreeHostIndex; /* 0x1C44 */ 155 U32 Reserved1C48[2]; /* 0x1C48 */ 156 U64 DiagRWData; /* 0x1C50 */ 157 U64 DiagRWAddress; /* 0x1C58 */ 158 U16 DiagRWControl; /* 0x1C60 */ 159 U16 DiagRWStatus; /* 0x1C62 */ 160 U32 Reserved1C64[35]; /* 0x1C64 */ 161 U32 Scratchpad[4]; /* 0x1CF0 */ 162 U32 Reserved1D00[192]; /* 0x1D00 */ 163 U32 DeviceAssignedRegisters[2048]; /* 0x2000 */ 164 } MPI3_SYSIF_REGS, MPI3_POINTER PTR_MPI3_SYSIF_REGS, 165 Mpi3SysIfRegs_t, MPI3_POINTER pMpi3SysIfRegs_t; 166 167 /**** Defines for the IOCInformation register ****/ 168 #define MPI3_SYSIF_IOC_INFO_LOW_OFFSET (0x00000000) 169 #define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004) 170 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xFF000000) 171 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT (24) 172 #define MPI3_SYSIF_IOC_INFO_LOW_HCB_DISABLED (0x00000001) 173 174 /**** Defines for the IOCConfiguration register ****/ 175 #define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014) 176 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ (0x00F00000) 177 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT (20) 178 #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ (0x000F0000) 179 #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT (16) 180 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_MASK (0x0000C000) 181 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NO (0x00000000) 182 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL (0x00004000) 183 #define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ (0x00002000) 184 #define MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE (0x00000010) 185 #define MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC (0x00000001) 186 187 /**** Defines for the IOCStatus register ****/ 188 #define MPI3_SYSIF_IOC_STATUS_OFFSET (0x0000001C) 189 #define MPI3_SYSIF_IOC_STATUS_RESET_HISTORY (0x00000010) 190 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK (0x0000000C) 191 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_SHIFT (0x00000002) 192 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_NONE (0x00000000) 193 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS (0x00000004) 194 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE (0x00000008) 195 #define MPI3_SYSIF_IOC_STATUS_FAULT (0x00000002) 196 #define MPI3_SYSIF_IOC_STATUS_READY (0x00000001) 197 198 /**** Defines for the AdminQueueNumEntries register ****/ 199 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_OFFSET (0x00000024) 200 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_MASK (0x0FFF) 201 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_OFFSET (0x00000026) 202 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_MASK (0x0FFF0000) 203 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_SHIFT (16) 204 205 /**** Defines for the AdminRequestQueueAddress register ****/ 206 #define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_LOW_OFFSET (0x00000028) 207 #define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_HIGH_OFFSET (0x0000002C) 208 209 /**** Defines for the AdminReplyQueueAddress register ****/ 210 #define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_LOW_OFFSET (0x00000030) 211 #define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_HIGH_OFFSET (0x00000034) 212 213 /**** Defines for the CoalesceControl register ****/ 214 #define MPI3_SYSIF_COALESCE_CONTROL_OFFSET (0x00000040) 215 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_MASK (0xC0000000) 216 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_NO_CHANGE (0x00000000) 217 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_DISABLE (0x40000000) 218 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_ENABLE (0xC0000000) 219 #define MPI3_SYSIF_COALESCE_CONTROL_VALID (0x20000000) 220 #define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_MASK (0x01FF0000) 221 #define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_SHIFT (16) 222 #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_MASK (0x0000FF00) 223 #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_SHIFT (8) 224 #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_MASK (0x000000FF) 225 #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_SHIFT (0) 226 227 /**** Defines for the AdminRequestQueuePI register ****/ 228 #define MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET (0x00001000) 229 230 /**** Defines for the AdminReplyQueueCI register ****/ 231 #define MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET (0x00001004) 232 233 /**** Defines for the OperationalRequestQueuePI register */ 234 #define MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET (0x00001008) 235 #define MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(N) (MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET + (((N)-1)*8)) /* N = 1, 2, 3, ..., 255 */ 236 237 /**** Defines for the OperationalReplyQueueCI register */ 238 #define MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET (0x0000100C) 239 #define MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(N) (MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET + (((N)-1)*8)) /* N = 1, 2, 3, ..., 255 */ 240 241 /**** Defines for the WriteSequence register *****/ 242 #define MPI3_SYSIF_WRITE_SEQUENCE_OFFSET (0x00001C04) 243 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_MASK (0x0000000F) 244 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH (0x0) 245 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST (0xF) 246 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND (0x4) 247 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD (0xB) 248 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH (0x2) 249 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH (0x7) 250 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH (0xD) 251 252 /**** Defines for the HostDiagnostic register *****/ 253 #define MPI3_SYSIF_HOST_DIAG_OFFSET (0x00001C08) 254 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_MASK (0x00000700) 255 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_NO_RESET (0x00000000) 256 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET (0x00000100) 257 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_HOST_CONTROL_BOOT_RESET (0x00000200) 258 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_COMPLETE_RESET (0x00000300) 259 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT (0x00000700) 260 #define MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS (0x00000080) 261 #define MPI3_SYSIF_HOST_DIAG_SECURE_BOOT (0x00000040) 262 #define MPI3_SYSIF_HOST_DIAG_CLEAR_INVALID_FW_IMAGE (0x00000020) 263 #define MPI3_SYSIF_HOST_DIAG_INVALID_FW_IMAGE (0x00000010) 264 #define MPI3_SYSIF_HOST_DIAG_HCBENABLE (0x00000008) 265 #define MPI3_SYSIF_HOST_DIAG_HCBMODE (0x00000004) 266 #define MPI3_SYSIF_HOST_DIAG_DIAG_RW_ENABLE (0x00000002) 267 #define MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE (0x00000001) 268 269 /**** Defines for the Fault register ****/ 270 #define MPI3_SYSIF_FAULT_OFFSET (0x00001C10) 271 #define MPI3_SYSIF_FAULT_CODE_MASK (0x0000FFFF) 272 #define MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET (0x0000F000) 273 #define MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET (0x0000F001) 274 #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS (0x0000F002) 275 #define MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED (0x0000F003) 276 #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_NEEDED (0x0000F004) 277 #define MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED (0x0000F005) 278 #define MPI3_SYSIF_FAULT_CODE_TEMP_THRESHOLD_EXCEEDED (0x0000F006) 279 280 /**** Defines for FaultCodeAdditionalInfo registers ****/ 281 #define MPI3_SYSIF_FAULT_INFO0_OFFSET (0x00001C14) 282 #define MPI3_SYSIF_FAULT_INFO1_OFFSET (0x00001C18) 283 #define MPI3_SYSIF_FAULT_INFO2_OFFSET (0x00001C1C) 284 285 /**** Defines for HCBAddress register ****/ 286 #define MPI3_SYSIF_HCB_ADDRESS_LOW_OFFSET (0x00001C30) 287 #define MPI3_SYSIF_HCB_ADDRESS_HIGH_OFFSET (0x00001C34) 288 289 /**** Defines for HCBSize register ****/ 290 #define MPI3_SYSIF_HCB_SIZE_OFFSET (0x00001C38) 291 #define MPI3_SYSIF_HCB_SIZE_SIZE_MASK (0xFFFFF000) 292 #define MPI3_SYSIF_HCB_SIZE_SIZE_SHIFT (12) 293 #define MPI3_SYSIF_HCB_SIZE_HCDW_ENABLE (0x00000001) 294 295 /**** Defines for ReplyFreeHostIndex register ****/ 296 #define MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET (0x00001C40) 297 298 /**** Defines for SenseBufferFreeHostIndex register ****/ 299 #define MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET (0x00001C44) 300 301 /**** Defines for DiagRWData register ****/ 302 #define MPI3_SYSIF_DIAG_RW_DATA_LOW_OFFSET (0x00001C50) 303 #define MPI3_SYSIF_DIAG_RW_DATA_HIGH_OFFSET (0x00001C54) 304 305 /**** Defines for DiagRWAddress ****/ 306 #define MPI3_SYSIF_DIAG_RW_ADDRESS_LOW_OFFSET (0x00001C58) 307 #define MPI3_SYSIF_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00001C5C) 308 309 /**** Defines for DiagRWControl register ****/ 310 #define MPI3_SYSIF_DIAG_RW_CONTROL_OFFSET (0x00001C60) 311 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_MASK (0x00000030) 312 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_1BYTE (0x00000000) 313 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_2BYTES (0x00000010) 314 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_4BYTES (0x00000020) 315 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_8BYTES (0x00000030) 316 #define MPI3_SYSIF_DIAG_RW_CONTROL_RESET (0x00000004) 317 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_MASK (0x00000002) 318 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_READ (0x00000000) 319 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_WRITE (0x00000002) 320 #define MPI3_SYSIF_DIAG_RW_CONTROL_START (0x00000001) 321 322 /**** Defines for DiagRWStatus register ****/ 323 #define MPI3_SYSIF_DIAG_RW_STATUS_OFFSET (0x00001C62) 324 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_MASK (0x0000000E) 325 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SUCCESS (0x00000000) 326 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_INV_ADDR (0x00000002) 327 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_ACC_ERR (0x00000004) 328 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_PAR_ERR (0x00000006) 329 #define MPI3_SYSIF_DIAG_RW_STATUS_BUSY (0x00000001) 330 331 /**** Defines for Scratchpad registers ****/ 332 #define MPI3_SYSIF_SCRATCHPAD0_OFFSET (0x00001CF0) 333 #define MPI3_SYSIF_SCRATCHPAD1_OFFSET (0x00001CF4) 334 #define MPI3_SYSIF_SCRATCHPAD2_OFFSET (0x00001CF8) 335 #define MPI3_SYSIF_SCRATCHPAD3_OFFSET (0x00001CFC) 336 337 /**** Defines for Device Assigned registers ****/ 338 #define MPI3_SYSIF_DEVICE_ASSIGNED_REGS_OFFSET (0x00002000) 339 340 /**** Default Defines for Diag Save Timeout ****/ 341 #define MPI3_SYSIF_DIAG_SAVE_TIMEOUT (60) /* seconds */ 342 343 /***************************************************************************** 344 * Reply Descriptors * 345 ****************************************************************************/ 346 347 /***************************************************************************** 348 * Default Reply Descriptor * 349 ****************************************************************************/ 350 typedef struct _MPI3_DEFAULT_REPLY_DESCRIPTOR 351 { 352 U32 DescriptorTypeDependent1[2]; /* 0x00 */ 353 U16 RequestQueueCI; /* 0x08 */ 354 U16 RequestQueueID; /* 0x0A */ 355 U16 DescriptorTypeDependent2; /* 0x0C */ 356 U16 ReplyFlags; /* 0x0E */ 357 } MPI3_DEFAULT_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_DEFAULT_REPLY_DESCRIPTOR, 358 Mpi3DefaultReplyDescriptor_t, MPI3_POINTER pMpi3DefaultReplyDescriptor_t; 359 360 /**** Defines for the ReplyFlags field ****/ 361 #define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK (0x0001) 362 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK (0xF000) 363 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY (0x0000) 364 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS (0x1000) 365 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_TARGET_COMMAND_BUFFER (0x2000) 366 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS (0x3000) 367 368 /**** Defines for the RequestQueueID field ****/ 369 #define MPI3_REPLY_DESCRIPT_REQUEST_QUEUE_ID_INVALID (0xFFFF) 370 371 /***************************************************************************** 372 * Address Reply Descriptor * 373 ****************************************************************************/ 374 typedef struct _MPI3_ADDRESS_REPLY_DESCRIPTOR 375 { 376 U64 ReplyFrameAddress; /* 0x00 */ 377 U16 RequestQueueCI; /* 0x08 */ 378 U16 RequestQueueID; /* 0x0A */ 379 U16 Reserved0C; /* 0x0C */ 380 U16 ReplyFlags; /* 0x0E */ 381 } MPI3_ADDRESS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_ADDRESS_REPLY_DESCRIPTOR, 382 Mpi3AddressReplyDescriptor_t, MPI3_POINTER pMpi3AddressReplyDescriptor_t; 383 384 /***************************************************************************** 385 * Success Reply Descriptor * 386 ****************************************************************************/ 387 typedef struct _MPI3_SUCCESS_REPLY_DESCRIPTOR 388 { 389 U32 Reserved00[2]; /* 0x00 */ 390 U16 RequestQueueCI; /* 0x08 */ 391 U16 RequestQueueID; /* 0x0A */ 392 U16 HostTag; /* 0x0C */ 393 U16 ReplyFlags; /* 0x0E */ 394 } MPI3_SUCCESS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_SUCCESS_REPLY_DESCRIPTOR, 395 Mpi3SuccessReplyDescriptor_t, MPI3_POINTER pMpi3SuccessReplyDescriptor_t; 396 397 /***************************************************************************** 398 * Target Command Buffer Reply Descriptor * 399 ****************************************************************************/ 400 typedef struct _MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 401 { 402 U32 Reserved00; /* 0x00 */ 403 U16 InitiatorDevHandle; /* 0x04 */ 404 U8 PhyNum; /* 0x06 */ 405 U8 Reserved07; /* 0x07 */ 406 U16 RequestQueueCI; /* 0x08 */ 407 U16 RequestQueueID; /* 0x0A */ 408 U16 IOIndex; /* 0x0C */ 409 U16 ReplyFlags; /* 0x0E */ 410 } MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 411 Mpi3TargetCommandBufferReplyDescriptor_t, MPI3_POINTER pMpi3TargetCommandBufferReplyDescriptor_t; 412 413 /**** See Default Reply Descriptor Defines above for definitions in the ReplyFlags field ****/ 414 415 /***************************************************************************** 416 * Status Reply Descriptor * 417 ****************************************************************************/ 418 typedef struct _MPI3_STATUS_REPLY_DESCRIPTOR 419 { 420 U16 IOCStatus; /* 0x00 */ 421 U16 Reserved02; /* 0x02 */ 422 U32 IOCLogInfo; /* 0x04 */ 423 U16 RequestQueueCI; /* 0x08 */ 424 U16 RequestQueueID; /* 0x0A */ 425 U16 HostTag; /* 0x0C */ 426 U16 ReplyFlags; /* 0x0E */ 427 } MPI3_STATUS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_STATUS_REPLY_DESCRIPTOR, 428 Mpi3StatusReplyDescriptor_t, MPI3_POINTER pMpi3StatusReplyDescriptor_t; 429 430 /**** Use MPI3_IOCSTATUS_ defines for the IOCStatus field ****/ 431 432 /**** Use MPI3_IOCLOGINFO_ defines for the IOCLogInfo field ****/ 433 434 /***************************************************************************** 435 * Union of Reply Descriptors * 436 ****************************************************************************/ 437 typedef union _MPI3_REPLY_DESCRIPTORS_UNION 438 { 439 MPI3_DEFAULT_REPLY_DESCRIPTOR Default; 440 MPI3_ADDRESS_REPLY_DESCRIPTOR AddressReply; 441 MPI3_SUCCESS_REPLY_DESCRIPTOR Success; 442 MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 443 MPI3_STATUS_REPLY_DESCRIPTOR Status; 444 U32 Words[4]; 445 } MPI3_REPLY_DESCRIPTORS_UNION, MPI3_POINTER PTR_MPI3_REPLY_DESCRIPTORS_UNION, 446 Mpi3ReplyDescriptorsUnion_t, MPI3_POINTER pMpi3ReplyDescriptorsUnion_t; 447 448 449 /***************************************************************************** 450 * Scatter Gather Elements * 451 ****************************************************************************/ 452 453 /***************************************************************************** 454 * Common structure for Simple, Chain, and Last Chain * 455 * scatter gather elements * 456 ****************************************************************************/ 457 typedef struct _MPI3_SGE_COMMON 458 { 459 U64 Address; /* 0x00 */ 460 U32 Length; /* 0x08 */ 461 U8 Reserved0C[3]; /* 0x0C */ 462 U8 Flags; /* 0x0F */ 463 } MPI3_SGE_SIMPLE, MPI3_POINTER PTR_MPI3_SGE_SIMPLE, 464 Mpi3SGESimple_t, MPI3_POINTER pMpi3SGESimple_t, 465 MPI3_SGE_CHAIN, MPI3_POINTER PTR_MPI3_SGE_CHAIN, 466 Mpi3SGEChain_t, MPI3_POINTER pMpi3SGEChain_t, 467 MPI3_SGE_LAST_CHAIN, MPI3_POINTER PTR_MPI3_SGE_LAST_CHAIN, 468 Mpi3SGELastChain_t, MPI3_POINTER pMpi3SGELastChain_t; 469 470 /***************************************************************************** 471 * Bit Bucket scatter gather element * 472 ****************************************************************************/ 473 typedef struct _MPI3_SGE_BIT_BUCKET 474 { 475 U64 Reserved00; /* 0x00 */ 476 U32 Length; /* 0x08 */ 477 U8 Reserved0C[3]; /* 0x0C */ 478 U8 Flags; /* 0x0F */ 479 } MPI3_SGE_BIT_BUCKET, MPI3_POINTER PTR_MPI3_SGE_BIT_BUCKET, 480 Mpi3SGEBitBucket_t, MPI3_POINTER pMpi3SGEBitBucket_t; 481 482 /***************************************************************************** 483 * Extended EEDP scatter gather element * 484 ****************************************************************************/ 485 typedef struct _MPI3_SGE_EXTENDED_EEDP 486 { 487 U8 UserDataSize; /* 0x00 */ 488 U8 Reserved01; /* 0x01 */ 489 U16 EEDPFlags; /* 0x02 */ 490 U32 SecondaryReferenceTag; /* 0x04 */ 491 U16 SecondaryApplicationTag; /* 0x08 */ 492 U16 ApplicationTagTranslationMask; /* 0x0A */ 493 U16 Reserved0C; /* 0x0C */ 494 U8 ExtendedOperation; /* 0x0E */ 495 U8 Flags; /* 0x0F */ 496 } MPI3_SGE_EXTENDED_EEDP, MPI3_POINTER PTR_MPI3_SGE_EXTENDED_EEDP, 497 Mpi3SGEExtendedEEDP_t, MPI3_POINTER pMpi3SGEExtendedEEDP_t; 498 499 /***************************************************************************** 500 * Union of scatter gather elements * 501 ****************************************************************************/ 502 typedef union _MPI3_SGE_UNION 503 { 504 MPI3_SGE_SIMPLE Simple; 505 MPI3_SGE_CHAIN Chain; 506 MPI3_SGE_LAST_CHAIN LastChain; 507 MPI3_SGE_BIT_BUCKET BitBucket; 508 MPI3_SGE_EXTENDED_EEDP Eedp; 509 U32 Words[4]; 510 } MPI3_SGE_UNION, MPI3_POINTER PTR_MPI3_SGE_UNION, 511 Mpi3SGEUnion_t, MPI3_POINTER pMpi3SGEUnion_t; 512 513 /**** Definitions for the Flags field ****/ 514 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_MASK (0xF0) 515 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE (0x00) 516 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_BIT_BUCKET (0x10) 517 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_CHAIN (0x20) 518 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_LAST_CHAIN (0x30) 519 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_EXTENDED (0xF0) 520 #define MPI3_SGE_FLAGS_END_OF_LIST (0x08) 521 #define MPI3_SGE_FLAGS_END_OF_BUFFER (0x04) 522 #define MPI3_SGE_FLAGS_DLAS_MASK (0x03) 523 #define MPI3_SGE_FLAGS_DLAS_SYSTEM (0x00) 524 #define MPI3_SGE_FLAGS_DLAS_IOC_UDP (0x01) 525 #define MPI3_SGE_FLAGS_DLAS_IOC_CTL (0x02) 526 527 /**** Definitions for the ExtendedOperation field of Extended element ****/ 528 #define MPI3_SGE_EXT_OPER_EEDP (0x00) 529 530 /**** Definitions for the EEDPFlags field of Extended EEDP element ****/ 531 #define MPI3_EEDPFLAGS_INCR_PRI_REF_TAG (0x8000) 532 #define MPI3_EEDPFLAGS_INCR_SEC_REF_TAG (0x4000) 533 #define MPI3_EEDPFLAGS_INCR_PRI_APP_TAG (0x2000) 534 #define MPI3_EEDPFLAGS_INCR_SEC_APP_TAG (0x1000) 535 #define MPI3_EEDPFLAGS_ESC_PASSTHROUGH (0x0800) 536 #define MPI3_EEDPFLAGS_CHK_REF_TAG (0x0400) 537 #define MPI3_EEDPFLAGS_CHK_APP_TAG (0x0200) 538 #define MPI3_EEDPFLAGS_CHK_GUARD (0x0100) 539 #define MPI3_EEDPFLAGS_ESC_MODE_MASK (0x00C0) 540 #define MPI3_EEDPFLAGS_ESC_MODE_DO_NOT_DISABLE (0x0040) 541 #define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_DISABLE (0x0080) 542 #define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_REFTAG_DISABLE (0x00C0) 543 #define MPI3_EEDPFLAGS_HOST_GUARD_MASK (0x0030) 544 #define MPI3_EEDPFLAGS_HOST_GUARD_T10_CRC (0x0000) 545 #define MPI3_EEDPFLAGS_HOST_GUARD_IP_CHKSUM (0x0010) 546 #define MPI3_EEDPFLAGS_HOST_GUARD_OEM_SPECIFIC (0x0020) 547 #define MPI3_EEDPFLAGS_PT_REF_TAG (0x0008) 548 #define MPI3_EEDPFLAGS_EEDP_OP_MASK (0x0007) 549 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK (0x0001) 550 #define MPI3_EEDPFLAGS_EEDP_OP_STRIP (0x0002) 551 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE (0x0003) 552 #define MPI3_EEDPFLAGS_EEDP_OP_INSERT (0x0004) 553 #define MPI3_EEDPFLAGS_EEDP_OP_REPLACE (0x0006) 554 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REGEN (0x0007) 555 556 /**** Definitions for the UserDataSize field of Extended EEDP element ****/ 557 #define MPI3_EEDP_UDS_512 (0x01) 558 #define MPI3_EEDP_UDS_520 (0x02) 559 #define MPI3_EEDP_UDS_4080 (0x03) 560 #define MPI3_EEDP_UDS_4088 (0x04) 561 #define MPI3_EEDP_UDS_4096 (0x05) 562 #define MPI3_EEDP_UDS_4104 (0x06) 563 #define MPI3_EEDP_UDS_4160 (0x07) 564 565 /***************************************************************************** 566 * Standard Message Structures * 567 ****************************************************************************/ 568 569 /***************************************************************************** 570 * Request Message Header for all request messages * 571 ****************************************************************************/ 572 typedef struct _MPI3_REQUEST_HEADER 573 { 574 U16 HostTag; /* 0x00 */ 575 U8 IOCUseOnly02; /* 0x02 */ 576 U8 Function; /* 0x03 */ 577 U16 IOCUseOnly04; /* 0x04 */ 578 U8 IOCUseOnly06; /* 0x06 */ 579 U8 MsgFlags; /* 0x07 */ 580 U16 ChangeCount; /* 0x08 */ 581 U16 FunctionDependent; /* 0x0A */ 582 } MPI3_REQUEST_HEADER, MPI3_POINTER PTR_MPI3_REQUEST_HEADER, 583 Mpi3RequestHeader_t, MPI3_POINTER pMpi3RequestHeader_t; 584 585 /***************************************************************************** 586 * Default Reply * 587 ****************************************************************************/ 588 typedef struct _MPI3_DEFAULT_REPLY 589 { 590 U16 HostTag; /* 0x00 */ 591 U8 IOCUseOnly02; /* 0x02 */ 592 U8 Function; /* 0x03 */ 593 U16 IOCUseOnly04; /* 0x04 */ 594 U8 IOCUseOnly06; /* 0x06 */ 595 U8 MsgFlags; /* 0x07 */ 596 U16 IOCUseOnly08; /* 0x08 */ 597 U16 IOCStatus; /* 0x0A */ 598 U32 IOCLogInfo; /* 0x0C */ 599 } MPI3_DEFAULT_REPLY, MPI3_POINTER PTR_MPI3_DEFAULT_REPLY, 600 Mpi3DefaultReply_t, MPI3_POINTER pMpi3DefaultReply_t; 601 602 /**** Defines for the HostTag field ****/ 603 #define MPI3_HOST_TAG_INVALID (0xFFFF) 604 605 /**** Defines for message Function ****/ 606 /* I/O Controller functions */ 607 #define MPI3_FUNCTION_IOC_FACTS (0x01) /* IOC Facts */ 608 #define MPI3_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 609 #define MPI3_FUNCTION_PORT_ENABLE (0x03) /* Port Enable */ 610 #define MPI3_FUNCTION_EVENT_NOTIFICATION (0x04) /* Event Notification */ 611 #define MPI3_FUNCTION_EVENT_ACK (0x05) /* Event Acknowledge */ 612 #define MPI3_FUNCTION_CI_DOWNLOAD (0x06) /* Component Image Download */ 613 #define MPI3_FUNCTION_CI_UPLOAD (0x07) /* Component Image Upload */ 614 #define MPI3_FUNCTION_IO_UNIT_CONTROL (0x08) /* IO Unit Control */ 615 #define MPI3_FUNCTION_PERSISTENT_EVENT_LOG (0x09) /* Persistent Event Log */ 616 #define MPI3_FUNCTION_MGMT_PASSTHROUGH (0x0A) /* Management Passthrough */ 617 #define MPI3_FUNCTION_CONFIG (0x10) /* Configuration */ 618 619 /* SCSI Initiator I/O functions */ 620 #define MPI3_FUNCTION_SCSI_IO (0x20) /* SCSI IO */ 621 #define MPI3_FUNCTION_SCSI_TASK_MGMT (0x21) /* SCSI Task Management */ 622 #define MPI3_FUNCTION_SMP_PASSTHROUGH (0x22) /* SMP Passthrough */ 623 #define MPI3_FUNCTION_NVME_ENCAPSULATED (0x24) /* NVMe Encapsulated */ 624 625 /* SCSI Target I/O functions */ 626 #define MPI3_FUNCTION_TARGET_ASSIST (0x30) /* Target Assist */ 627 #define MPI3_FUNCTION_TARGET_STATUS_SEND (0x31) /* Target Status Send */ 628 #define MPI3_FUNCTION_TARGET_MODE_ABORT (0x32) /* Target Mode Abort */ 629 #define MPI3_FUNCTION_TARGET_CMD_BUF_POST_BASE (0x33) /* Target Command Buffer Post Base */ 630 #define MPI3_FUNCTION_TARGET_CMD_BUF_POST_LIST (0x34) /* Target Command Buffer Post List */ 631 632 /* Queue Management functions */ 633 #define MPI3_FUNCTION_CREATE_REQUEST_QUEUE (0x70) /* Create an operational request queue */ 634 #define MPI3_FUNCTION_DELETE_REQUEST_QUEUE (0x71) /* Delete an operational request queue */ 635 #define MPI3_FUNCTION_CREATE_REPLY_QUEUE (0x72) /* Create an operational reply queue */ 636 #define MPI3_FUNCTION_DELETE_REPLY_QUEUE (0x73) /* Delete an operational reply queue */ 637 638 /* Diagnostic Tools */ 639 #define MPI3_FUNCTION_TOOLBOX (0x80) /* Toolbox */ 640 #define MPI3_FUNCTION_DIAG_BUFFER_POST (0x81) /* Post a Diagnostic Buffer to the I/O Unit */ 641 #define MPI3_FUNCTION_DIAG_BUFFER_MANAGE (0x82) /* Manage a Diagnostic Buffer */ 642 #define MPI3_FUNCTION_DIAG_BUFFER_UPLOAD (0x83) /* Upload a Diagnostic Buffer */ 643 644 /* Miscellaneous functions */ 645 #define MPI3_FUNCTION_MIN_IOC_USE_ONLY (0xC0) /* Beginning of IOC Use Only range of function codes */ 646 #define MPI3_FUNCTION_MAX_IOC_USE_ONLY (0xEF) /* End of IOC Use Only range of function codes */ 647 #define MPI3_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* Beginning of the product-specific range of function codes */ 648 #define MPI3_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* End of the product-specific range of function codes */ 649 650 /**** Defines for IOCStatus ****/ 651 #define MPI3_IOCSTATUS_LOG_INFO_AVAILABLE (0x8000) 652 #define MPI3_IOCSTATUS_STATUS_MASK (0x7FFF) 653 654 /* Common IOCStatus values for all replies */ 655 #define MPI3_IOCSTATUS_SUCCESS (0x0000) 656 #define MPI3_IOCSTATUS_INVALID_FUNCTION (0x0001) 657 #define MPI3_IOCSTATUS_BUSY (0x0002) 658 #define MPI3_IOCSTATUS_INVALID_SGL (0x0003) 659 #define MPI3_IOCSTATUS_INTERNAL_ERROR (0x0004) 660 #define MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 661 #define MPI3_IOCSTATUS_INVALID_FIELD (0x0007) 662 #define MPI3_IOCSTATUS_INVALID_STATE (0x0008) 663 #define MPI3_IOCSTATUS_INSUFFICIENT_POWER (0x000A) 664 #define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT (0x000B) 665 #define MPI3_IOCSTATUS_ALLOWED_CMD_BLOCK (0x000C) 666 #define MPI3_IOCSTATUS_SUPERVISOR_ONLY (0x000D) 667 #define MPI3_IOCSTATUS_FAILURE (0x001F) 668 669 /* Config IOCStatus values */ 670 #define MPI3_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 671 #define MPI3_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 672 #define MPI3_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 673 #define MPI3_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 674 #define MPI3_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 675 #define MPI3_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 676 677 /* SCSI IO IOCStatus values */ 678 #define MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 679 #define MPI3_IOCSTATUS_SCSI_TM_NOT_SUPPORTED (0x0041) 680 #define MPI3_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 681 #define MPI3_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 682 #define MPI3_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 683 #define MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 684 #define MPI3_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 685 #define MPI3_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 686 #define MPI3_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 687 #define MPI3_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 688 #define MPI3_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 689 #define MPI3_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 690 #define MPI3_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 691 692 /* SCSI Initiator and SCSI Target end-to-end data protection values */ 693 #define MPI3_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 694 #define MPI3_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 695 #define MPI3_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 696 697 /* SCSI Target IOCStatus values */ 698 #define MPI3_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 699 #define MPI3_IOCSTATUS_TARGET_ABORTED (0x0063) 700 #define MPI3_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 701 #define MPI3_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 702 #define MPI3_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 703 #define MPI3_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 704 #define MPI3_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 705 #define MPI3_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 706 #define MPI3_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 707 #define MPI3_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 708 709 /* Serial Attached SCSI IOCStatus values */ 710 #define MPI3_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 711 #define MPI3_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 712 713 /* Diagnostic Buffer Post/Release IOCStatus values */ 714 #define MPI3_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 715 716 /* Component Image Upload/Download */ 717 #define MPI3_IOCSTATUS_CI_UNSUPPORTED (0x00B0) 718 #define MPI3_IOCSTATUS_CI_UPDATE_SEQUENCE (0x00B1) 719 #define MPI3_IOCSTATUS_CI_VALIDATION_FAILED (0x00B2) 720 #define MPI3_IOCSTATUS_CI_KEY_UPDATE_PENDING (0x00B3) 721 #define MPI3_IOCSTATUS_CI_KEY_UPDATE_NOT_POSSIBLE (0x00B4) 722 723 /* Security values */ 724 #define MPI3_IOCSTATUS_SECURITY_KEY_REQUIRED (0x00C0) 725 #define MPI3_IOCSTATUS_SECURITY_VIOLATION (0x00C1) 726 727 /* Request and Reply Queues related IOCStatus values */ 728 #define MPI3_IOCSTATUS_INVALID_QUEUE_ID (0x0F00) 729 #define MPI3_IOCSTATUS_INVALID_QUEUE_SIZE (0x0F01) 730 #define MPI3_IOCSTATUS_INVALID_MSIX_VECTOR (0x0F02) 731 #define MPI3_IOCSTATUS_INVALID_REPLY_QUEUE_ID (0x0F03) 732 #define MPI3_IOCSTATUS_INVALID_QUEUE_DELETION (0x0F04) 733 734 /**** Defines for IOCLogInfo ****/ 735 #define MPI3_IOCLOGINFO_TYPE_MASK (0xF0000000) 736 #define MPI3_IOCLOGINFO_TYPE_SHIFT (28) 737 #define MPI3_IOCLOGINFO_TYPE_NONE (0x0) 738 #define MPI3_IOCLOGINFO_TYPE_SAS (0x3) 739 #define MPI3_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 740 741 #endif /* MPI30_TRANSPORT_H */ 742 743 744