1 /* 2 * This file is auto-generated by running 'make ../riscv-isa-sim/riscv/encoding.h' in 3 * https://github.com/riscv/riscv-opcodes (a4069bc) 4 */ 5 6 /* See LICENSE for license details. */ 7 8 #ifndef RISCV_CSR_ENCODING_H 9 #define RISCV_CSR_ENCODING_H 10 11 #define MSTATUS_UIE 0x00000001 12 #define MSTATUS_SIE 0x00000002 13 #define MSTATUS_HIE 0x00000004 14 #define MSTATUS_MIE 0x00000008 15 #define MSTATUS_UPIE 0x00000010 16 #define MSTATUS_SPIE 0x00000020 17 #define MSTATUS_UBE 0x00000040 18 #define MSTATUS_MPIE 0x00000080 19 #define MSTATUS_SPP 0x00000100 20 #define MSTATUS_VS 0x00000600 21 #define MSTATUS_MPP 0x00001800 22 #define MSTATUS_FS 0x00006000 23 #define MSTATUS_XS 0x00018000 24 #define MSTATUS_MPRV 0x00020000 25 #define MSTATUS_SUM 0x00040000 26 #define MSTATUS_MXR 0x00080000 27 #define MSTATUS_TVM 0x00100000 28 #define MSTATUS_TW 0x00200000 29 #define MSTATUS_TSR 0x00400000 30 #define MSTATUS32_SD 0x80000000 31 #define MSTATUS_UXL 0x0000000300000000 32 #define MSTATUS_SXL 0x0000000C00000000 33 #define MSTATUS_SBE 0x0000001000000000 34 #define MSTATUS_MBE 0x0000002000000000 35 #define MSTATUS_GVA 0x0000004000000000 36 #define MSTATUS_MPV 0x0000008000000000 37 #define MSTATUS64_SD 0x8000000000000000 38 39 #define MSTATUSH_SBE 0x00000010 40 #define MSTATUSH_MBE 0x00000020 41 #define MSTATUSH_GVA 0x00000040 42 #define MSTATUSH_MPV 0x00000080 43 44 #define SSTATUS_UIE 0x00000001 45 #define SSTATUS_SIE 0x00000002 46 #define SSTATUS_UPIE 0x00000010 47 #define SSTATUS_SPIE 0x00000020 48 #define SSTATUS_UBE 0x00000040 49 #define SSTATUS_SPP 0x00000100 50 #define SSTATUS_VS 0x00000600 51 #define SSTATUS_FS 0x00006000 52 #define SSTATUS_XS 0x00018000 53 #define SSTATUS_SUM 0x00040000 54 #define SSTATUS_MXR 0x00080000 55 #define SSTATUS32_SD 0x80000000 56 #define SSTATUS_UXL 0x0000000300000000 57 #define SSTATUS64_SD 0x8000000000000000 58 59 #define HSTATUS_VSXL 0x300000000 60 #define HSTATUS_VTSR 0x00400000 61 #define HSTATUS_VTW 0x00200000 62 #define HSTATUS_VTVM 0x00100000 63 #define HSTATUS_VGEIN 0x0003f000 64 #define HSTATUS_HU 0x00000200 65 #define HSTATUS_SPVP 0x00000100 66 #define HSTATUS_SPV 0x00000080 67 #define HSTATUS_GVA 0x00000040 68 #define HSTATUS_VSBE 0x00000020 69 70 #define USTATUS_UIE 0x00000001 71 #define USTATUS_UPIE 0x00000010 72 73 #define DCSR_XDEBUGVER (3U<<30) 74 #define DCSR_NDRESET (1<<29) 75 #define DCSR_FULLRESET (1<<28) 76 #define DCSR_EBREAKM (1<<15) 77 #define DCSR_EBREAKH (1<<14) 78 #define DCSR_EBREAKS (1<<13) 79 #define DCSR_EBREAKU (1<<12) 80 #define DCSR_STOPCYCLE (1<<10) 81 #define DCSR_STOPTIME (1<<9) 82 #define DCSR_CAUSE (7<<6) 83 #define DCSR_DEBUGINT (1<<5) 84 #define DCSR_HALT (1<<3) 85 #define DCSR_STEP (1<<2) 86 #define DCSR_PRV (3<<0) 87 88 #define DCSR_CAUSE_NONE 0 89 #define DCSR_CAUSE_SWBP 1 90 #define DCSR_CAUSE_HWBP 2 91 #define DCSR_CAUSE_DEBUGINT 3 92 #define DCSR_CAUSE_STEP 4 93 #define DCSR_CAUSE_HALT 5 94 #define DCSR_CAUSE_GROUP 6 95 96 #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) 97 #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) 98 #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) 99 100 #define MCONTROL_SELECT (1<<19) 101 #define MCONTROL_TIMING (1<<18) 102 #define MCONTROL_ACTION (0x3f<<12) 103 #define MCONTROL_CHAIN (1<<11) 104 #define MCONTROL_MATCH (0xf<<7) 105 #define MCONTROL_M (1<<6) 106 #define MCONTROL_H (1<<5) 107 #define MCONTROL_S (1<<4) 108 #define MCONTROL_U (1<<3) 109 #define MCONTROL_EXECUTE (1<<2) 110 #define MCONTROL_STORE (1<<1) 111 #define MCONTROL_LOAD (1<<0) 112 113 #define MCONTROL_TYPE_NONE 0 114 #define MCONTROL_TYPE_MATCH 2 115 116 #define MCONTROL_ACTION_DEBUG_EXCEPTION 0 117 #define MCONTROL_ACTION_DEBUG_MODE 1 118 #define MCONTROL_ACTION_TRACE_START 2 119 #define MCONTROL_ACTION_TRACE_STOP 3 120 #define MCONTROL_ACTION_TRACE_EMIT 4 121 122 #define MCONTROL_MATCH_EQUAL 0 123 #define MCONTROL_MATCH_NAPOT 1 124 #define MCONTROL_MATCH_GE 2 125 #define MCONTROL_MATCH_LT 3 126 #define MCONTROL_MATCH_MASK_LOW 4 127 #define MCONTROL_MATCH_MASK_HIGH 5 128 129 #define MIP_USIP (1 << IRQ_U_SOFT) 130 #define MIP_SSIP (1 << IRQ_S_SOFT) 131 #define MIP_VSSIP (1 << IRQ_VS_SOFT) 132 #define MIP_MSIP (1 << IRQ_M_SOFT) 133 #define MIP_UTIP (1 << IRQ_U_TIMER) 134 #define MIP_STIP (1 << IRQ_S_TIMER) 135 #define MIP_VSTIP (1 << IRQ_VS_TIMER) 136 #define MIP_MTIP (1 << IRQ_M_TIMER) 137 #define MIP_UEIP (1 << IRQ_U_EXT) 138 #define MIP_SEIP (1 << IRQ_S_EXT) 139 #define MIP_VSEIP (1 << IRQ_VS_EXT) 140 #define MIP_MEIP (1 << IRQ_M_EXT) 141 #define MIP_SGEIP (1 << IRQ_S_GEXT) 142 143 #define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP) 144 #define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) 145 #define MIP_HS_MASK (MIP_VS_MASK | MIP_SGEIP) 146 147 #define MIDELEG_FORCED_MASK MIP_HS_MASK 148 149 #define SIP_SSIP MIP_SSIP 150 #define SIP_STIP MIP_STIP 151 152 #define PRV_U 0 153 #define PRV_S 1 154 #define PRV_M 3 155 156 #define PRV_HS (PRV_S + 1) 157 158 #define SATP32_MODE 0x80000000 159 #define SATP32_ASID 0x7FC00000 160 #define SATP32_PPN 0x003FFFFF 161 #define SATP64_MODE 0xF000000000000000 162 #define SATP64_ASID 0x0FFFF00000000000 163 #define SATP64_PPN 0x00000FFFFFFFFFFF 164 165 #define SATP_MODE_OFF 0 166 #define SATP_MODE_SV32 1 167 #define SATP_MODE_SV39 8 168 #define SATP_MODE_SV48 9 169 #define SATP_MODE_SV57 10 170 #define SATP_MODE_SV64 11 171 172 #define HGATP32_MODE 0x80000000 173 #define HGATP32_VMID 0x1FC00000 174 #define HGATP32_PPN 0x003FFFFF 175 176 #define HGATP64_MODE 0xF000000000000000 177 #define HGATP64_VMID 0x03FFF00000000000 178 #define HGATP64_PPN 0x00000FFFFFFFFFFF 179 180 #define HGATP_MODE_OFF 0 181 #define HGATP_MODE_SV32X4 1 182 #define HGATP_MODE_SV39X4 8 183 #define HGATP_MODE_SV48X4 9 184 185 #define PMP_R 0x01 186 #define PMP_W 0x02 187 #define PMP_X 0x04 188 #define PMP_A 0x18 189 #define PMP_L 0x80 190 #define PMP_SHIFT 2 191 192 #define PMP_TOR 0x08 193 #define PMP_NA4 0x10 194 #define PMP_NAPOT 0x18 195 196 #define IRQ_U_SOFT 0 197 #define IRQ_S_SOFT 1 198 #define IRQ_VS_SOFT 2 199 #define IRQ_M_SOFT 3 200 #define IRQ_U_TIMER 4 201 #define IRQ_S_TIMER 5 202 #define IRQ_VS_TIMER 6 203 #define IRQ_M_TIMER 7 204 #define IRQ_U_EXT 8 205 #define IRQ_S_EXT 9 206 #define IRQ_VS_EXT 10 207 #define IRQ_M_EXT 11 208 #define IRQ_S_GEXT 12 209 #define IRQ_COP 12 210 #define IRQ_HOST 13 211 212 /* page table entry (PTE) fields */ 213 #define PTE_V 0x001 /* Valid */ 214 #define PTE_R 0x002 /* Read */ 215 #define PTE_W 0x004 /* Write */ 216 #define PTE_X 0x008 /* Execute */ 217 #define PTE_U 0x010 /* User */ 218 #define PTE_G 0x020 /* Global */ 219 #define PTE_A 0x040 /* Accessed */ 220 #define PTE_D 0x080 /* Dirty */ 221 #define PTE_SOFT 0x300 /* Reserved for Software */ 222 #define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ 223 #define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ 224 #define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ 225 #define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ 226 227 #define PTE_PPN_SHIFT 10 228 229 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) 230 231 #ifdef __riscv 232 233 #if __riscv_xlen == 64 234 # define MSTATUS_SD MSTATUS64_SD 235 # define SSTATUS_SD SSTATUS64_SD 236 # define RISCV_PGLEVEL_BITS 9 237 # define SATP_MODE SATP64_MODE 238 #else 239 # define MSTATUS_SD MSTATUS32_SD 240 # define SSTATUS_SD SSTATUS32_SD 241 # define RISCV_PGLEVEL_BITS 10 242 # define SATP_MODE SATP32_MODE 243 #endif 244 #define RISCV_PGSHIFT 12 245 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) 246 247 #ifndef __ASSEMBLER__ 248 249 #ifdef __GNUC__ 250 251 #define read_csr(reg) ({ unsigned long __tmp; \ 252 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 253 __tmp; }) 254 255 #define write_csr(reg, val) ({ \ 256 asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) 257 258 #define swap_csr(reg, val) ({ unsigned long __tmp; \ 259 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ 260 __tmp; }) 261 262 #define set_csr(reg, bit) ({ unsigned long __tmp; \ 263 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ 264 __tmp; }) 265 266 #define clear_csr(reg, bit) ({ unsigned long __tmp; \ 267 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ 268 __tmp; }) 269 270 #define rdtime() read_csr(time) 271 #define rdcycle() read_csr(cycle) 272 #define rdinstret() read_csr(instret) 273 274 #endif 275 276 #endif 277 278 #endif 279 280 #endif 281 /* Automatically generated by parse_opcodes. */ 282 #ifndef RISCV_ENCODING_H 283 #define RISCV_ENCODING_H 284 #define MATCH_SLLI_RV32 0x1013 285 #define MASK_SLLI_RV32 0xfe00707f 286 #define MATCH_SRLI_RV32 0x5013 287 #define MASK_SRLI_RV32 0xfe00707f 288 #define MATCH_SRAI_RV32 0x40005013 289 #define MASK_SRAI_RV32 0xfe00707f 290 #define MATCH_FRFLAGS 0x102073 291 #define MASK_FRFLAGS 0xfffff07f 292 #define MATCH_FSFLAGS 0x101073 293 #define MASK_FSFLAGS 0xfff0707f 294 #define MATCH_FSFLAGSI 0x105073 295 #define MASK_FSFLAGSI 0xfff0707f 296 #define MATCH_FRRM 0x202073 297 #define MASK_FRRM 0xfffff07f 298 #define MATCH_FSRM 0x201073 299 #define MASK_FSRM 0xfff0707f 300 #define MATCH_FSRMI 0x205073 301 #define MASK_FSRMI 0xfff0707f 302 #define MATCH_FSCSR 0x301073 303 #define MASK_FSCSR 0xfff0707f 304 #define MATCH_FRCSR 0x302073 305 #define MASK_FRCSR 0xfffff07f 306 #define MATCH_RDCYCLE 0xc0002073 307 #define MASK_RDCYCLE 0xfffff07f 308 #define MATCH_RDTIME 0xc0102073 309 #define MASK_RDTIME 0xfffff07f 310 #define MATCH_RDINSTRET 0xc0202073 311 #define MASK_RDINSTRET 0xfffff07f 312 #define MATCH_RDCYCLEH 0xc8002073 313 #define MASK_RDCYCLEH 0xfffff07f 314 #define MATCH_RDTIMEH 0xc8102073 315 #define MASK_RDTIMEH 0xfffff07f 316 #define MATCH_RDINSTRETH 0xc8202073 317 #define MASK_RDINSTRETH 0xfffff07f 318 #define MATCH_SCALL 0x73 319 #define MASK_SCALL 0xffffffff 320 #define MATCH_SBREAK 0x100073 321 #define MASK_SBREAK 0xffffffff 322 #define MATCH_FMV_X_S 0xe0000053 323 #define MASK_FMV_X_S 0xfff0707f 324 #define MATCH_FMV_S_X 0xf0000053 325 #define MASK_FMV_S_X 0xfff0707f 326 #define MATCH_FENCE_TSO 0x8330000f 327 #define MASK_FENCE_TSO 0xfff0707f 328 #define MATCH_PAUSE 0x100000f 329 #define MASK_PAUSE 0xffffffff 330 #define MATCH_BEQ 0x63 331 #define MASK_BEQ 0x707f 332 #define MATCH_BNE 0x1063 333 #define MASK_BNE 0x707f 334 #define MATCH_BLT 0x4063 335 #define MASK_BLT 0x707f 336 #define MATCH_BGE 0x5063 337 #define MASK_BGE 0x707f 338 #define MATCH_BLTU 0x6063 339 #define MASK_BLTU 0x707f 340 #define MATCH_BGEU 0x7063 341 #define MASK_BGEU 0x707f 342 #define MATCH_JALR 0x67 343 #define MASK_JALR 0x707f 344 #define MATCH_JAL 0x6f 345 #define MASK_JAL 0x7f 346 #define MATCH_LUI 0x37 347 #define MASK_LUI 0x7f 348 #define MATCH_AUIPC 0x17 349 #define MASK_AUIPC 0x7f 350 #define MATCH_ADDI 0x13 351 #define MASK_ADDI 0x707f 352 #define MATCH_SLTI 0x2013 353 #define MASK_SLTI 0x707f 354 #define MATCH_SLTIU 0x3013 355 #define MASK_SLTIU 0x707f 356 #define MATCH_XORI 0x4013 357 #define MASK_XORI 0x707f 358 #define MATCH_ORI 0x6013 359 #define MASK_ORI 0x707f 360 #define MATCH_ANDI 0x7013 361 #define MASK_ANDI 0x707f 362 #define MATCH_ADD 0x33 363 #define MASK_ADD 0xfe00707f 364 #define MATCH_SUB 0x40000033 365 #define MASK_SUB 0xfe00707f 366 #define MATCH_SLL 0x1033 367 #define MASK_SLL 0xfe00707f 368 #define MATCH_SLT 0x2033 369 #define MASK_SLT 0xfe00707f 370 #define MATCH_SLTU 0x3033 371 #define MASK_SLTU 0xfe00707f 372 #define MATCH_XOR 0x4033 373 #define MASK_XOR 0xfe00707f 374 #define MATCH_SRL 0x5033 375 #define MASK_SRL 0xfe00707f 376 #define MATCH_SRA 0x40005033 377 #define MASK_SRA 0xfe00707f 378 #define MATCH_OR 0x6033 379 #define MASK_OR 0xfe00707f 380 #define MATCH_AND 0x7033 381 #define MASK_AND 0xfe00707f 382 #define MATCH_LB 0x3 383 #define MASK_LB 0x707f 384 #define MATCH_LH 0x1003 385 #define MASK_LH 0x707f 386 #define MATCH_LW 0x2003 387 #define MASK_LW 0x707f 388 #define MATCH_LBU 0x4003 389 #define MASK_LBU 0x707f 390 #define MATCH_LHU 0x5003 391 #define MASK_LHU 0x707f 392 #define MATCH_SB 0x23 393 #define MASK_SB 0x707f 394 #define MATCH_SH 0x1023 395 #define MASK_SH 0x707f 396 #define MATCH_SW 0x2023 397 #define MASK_SW 0x707f 398 #define MATCH_FENCE 0xf 399 #define MASK_FENCE 0x707f 400 #define MATCH_FENCE_I 0x100f 401 #define MASK_FENCE_I 0x707f 402 #define MATCH_ADDIW 0x1b 403 #define MASK_ADDIW 0x707f 404 #define MATCH_SLLIW 0x101b 405 #define MASK_SLLIW 0xfe00707f 406 #define MATCH_SRLIW 0x501b 407 #define MASK_SRLIW 0xfe00707f 408 #define MATCH_SRAIW 0x4000501b 409 #define MASK_SRAIW 0xfe00707f 410 #define MATCH_ADDW 0x3b 411 #define MASK_ADDW 0xfe00707f 412 #define MATCH_SUBW 0x4000003b 413 #define MASK_SUBW 0xfe00707f 414 #define MATCH_SLLW 0x103b 415 #define MASK_SLLW 0xfe00707f 416 #define MATCH_SRLW 0x503b 417 #define MASK_SRLW 0xfe00707f 418 #define MATCH_SRAW 0x4000503b 419 #define MASK_SRAW 0xfe00707f 420 #define MATCH_LD 0x3003 421 #define MASK_LD 0x707f 422 #define MATCH_LWU 0x6003 423 #define MASK_LWU 0x707f 424 #define MATCH_SD 0x3023 425 #define MASK_SD 0x707f 426 #define MATCH_SLLI 0x1013 427 #define MASK_SLLI 0xfc00707f 428 #define MATCH_SRLI 0x5013 429 #define MASK_SRLI 0xfc00707f 430 #define MATCH_SRAI 0x40005013 431 #define MASK_SRAI 0xfc00707f 432 #define MATCH_MUL 0x2000033 433 #define MASK_MUL 0xfe00707f 434 #define MATCH_MULH 0x2001033 435 #define MASK_MULH 0xfe00707f 436 #define MATCH_MULHSU 0x2002033 437 #define MASK_MULHSU 0xfe00707f 438 #define MATCH_MULHU 0x2003033 439 #define MASK_MULHU 0xfe00707f 440 #define MATCH_DIV 0x2004033 441 #define MASK_DIV 0xfe00707f 442 #define MATCH_DIVU 0x2005033 443 #define MASK_DIVU 0xfe00707f 444 #define MATCH_REM 0x2006033 445 #define MASK_REM 0xfe00707f 446 #define MATCH_REMU 0x2007033 447 #define MASK_REMU 0xfe00707f 448 #define MATCH_MULW 0x200003b 449 #define MASK_MULW 0xfe00707f 450 #define MATCH_DIVW 0x200403b 451 #define MASK_DIVW 0xfe00707f 452 #define MATCH_DIVUW 0x200503b 453 #define MASK_DIVUW 0xfe00707f 454 #define MATCH_REMW 0x200603b 455 #define MASK_REMW 0xfe00707f 456 #define MATCH_REMUW 0x200703b 457 #define MASK_REMUW 0xfe00707f 458 #define MATCH_AMOADD_W 0x202f 459 #define MASK_AMOADD_W 0xf800707f 460 #define MATCH_AMOXOR_W 0x2000202f 461 #define MASK_AMOXOR_W 0xf800707f 462 #define MATCH_AMOOR_W 0x4000202f 463 #define MASK_AMOOR_W 0xf800707f 464 #define MATCH_AMOAND_W 0x6000202f 465 #define MASK_AMOAND_W 0xf800707f 466 #define MATCH_AMOMIN_W 0x8000202f 467 #define MASK_AMOMIN_W 0xf800707f 468 #define MATCH_AMOMAX_W 0xa000202f 469 #define MASK_AMOMAX_W 0xf800707f 470 #define MATCH_AMOMINU_W 0xc000202f 471 #define MASK_AMOMINU_W 0xf800707f 472 #define MATCH_AMOMAXU_W 0xe000202f 473 #define MASK_AMOMAXU_W 0xf800707f 474 #define MATCH_AMOSWAP_W 0x800202f 475 #define MASK_AMOSWAP_W 0xf800707f 476 #define MATCH_LR_W 0x1000202f 477 #define MASK_LR_W 0xf9f0707f 478 #define MATCH_SC_W 0x1800202f 479 #define MASK_SC_W 0xf800707f 480 #define MATCH_AMOADD_D 0x302f 481 #define MASK_AMOADD_D 0xf800707f 482 #define MATCH_AMOXOR_D 0x2000302f 483 #define MASK_AMOXOR_D 0xf800707f 484 #define MATCH_AMOOR_D 0x4000302f 485 #define MASK_AMOOR_D 0xf800707f 486 #define MATCH_AMOAND_D 0x6000302f 487 #define MASK_AMOAND_D 0xf800707f 488 #define MATCH_AMOMIN_D 0x8000302f 489 #define MASK_AMOMIN_D 0xf800707f 490 #define MATCH_AMOMAX_D 0xa000302f 491 #define MASK_AMOMAX_D 0xf800707f 492 #define MATCH_AMOMINU_D 0xc000302f 493 #define MASK_AMOMINU_D 0xf800707f 494 #define MATCH_AMOMAXU_D 0xe000302f 495 #define MASK_AMOMAXU_D 0xf800707f 496 #define MATCH_AMOSWAP_D 0x800302f 497 #define MASK_AMOSWAP_D 0xf800707f 498 #define MATCH_LR_D 0x1000302f 499 #define MASK_LR_D 0xf9f0707f 500 #define MATCH_SC_D 0x1800302f 501 #define MASK_SC_D 0xf800707f 502 #define MATCH_HFENCE_VVMA 0x22000073 503 #define MASK_HFENCE_VVMA 0xfe007fff 504 #define MATCH_HFENCE_GVMA 0x62000073 505 #define MASK_HFENCE_GVMA 0xfe007fff 506 #define MATCH_HLV_B 0x60004073 507 #define MASK_HLV_B 0xfff0707f 508 #define MATCH_HLV_BU 0x60104073 509 #define MASK_HLV_BU 0xfff0707f 510 #define MATCH_HLV_H 0x64004073 511 #define MASK_HLV_H 0xfff0707f 512 #define MATCH_HLV_HU 0x64104073 513 #define MASK_HLV_HU 0xfff0707f 514 #define MATCH_HLVX_HU 0x64304073 515 #define MASK_HLVX_HU 0xfff0707f 516 #define MATCH_HLV_W 0x68004073 517 #define MASK_HLV_W 0xfff0707f 518 #define MATCH_HLVX_WU 0x68304073 519 #define MASK_HLVX_WU 0xfff0707f 520 #define MATCH_HSV_B 0x62004073 521 #define MASK_HSV_B 0xfe007fff 522 #define MATCH_HSV_H 0x66004073 523 #define MASK_HSV_H 0xfe007fff 524 #define MATCH_HSV_W 0x6a004073 525 #define MASK_HSV_W 0xfe007fff 526 #define MATCH_HLV_WU 0x68104073 527 #define MASK_HLV_WU 0xfff0707f 528 #define MATCH_HLV_D 0x6c004073 529 #define MASK_HLV_D 0xfff0707f 530 #define MATCH_HSV_D 0x6e004073 531 #define MASK_HSV_D 0xfe007fff 532 #define MATCH_FADD_S 0x53 533 #define MASK_FADD_S 0xfe00007f 534 #define MATCH_FSUB_S 0x8000053 535 #define MASK_FSUB_S 0xfe00007f 536 #define MATCH_FMUL_S 0x10000053 537 #define MASK_FMUL_S 0xfe00007f 538 #define MATCH_FDIV_S 0x18000053 539 #define MASK_FDIV_S 0xfe00007f 540 #define MATCH_FSGNJ_S 0x20000053 541 #define MASK_FSGNJ_S 0xfe00707f 542 #define MATCH_FSGNJN_S 0x20001053 543 #define MASK_FSGNJN_S 0xfe00707f 544 #define MATCH_FSGNJX_S 0x20002053 545 #define MASK_FSGNJX_S 0xfe00707f 546 #define MATCH_FMIN_S 0x28000053 547 #define MASK_FMIN_S 0xfe00707f 548 #define MATCH_FMAX_S 0x28001053 549 #define MASK_FMAX_S 0xfe00707f 550 #define MATCH_FSQRT_S 0x58000053 551 #define MASK_FSQRT_S 0xfff0007f 552 #define MATCH_FLE_S 0xa0000053 553 #define MASK_FLE_S 0xfe00707f 554 #define MATCH_FLT_S 0xa0001053 555 #define MASK_FLT_S 0xfe00707f 556 #define MATCH_FEQ_S 0xa0002053 557 #define MASK_FEQ_S 0xfe00707f 558 #define MATCH_FCVT_W_S 0xc0000053 559 #define MASK_FCVT_W_S 0xfff0007f 560 #define MATCH_FCVT_WU_S 0xc0100053 561 #define MASK_FCVT_WU_S 0xfff0007f 562 #define MATCH_FMV_X_W 0xe0000053 563 #define MASK_FMV_X_W 0xfff0707f 564 #define MATCH_FCLASS_S 0xe0001053 565 #define MASK_FCLASS_S 0xfff0707f 566 #define MATCH_FCVT_S_W 0xd0000053 567 #define MASK_FCVT_S_W 0xfff0007f 568 #define MATCH_FCVT_S_WU 0xd0100053 569 #define MASK_FCVT_S_WU 0xfff0007f 570 #define MATCH_FMV_W_X 0xf0000053 571 #define MASK_FMV_W_X 0xfff0707f 572 #define MATCH_FLW 0x2007 573 #define MASK_FLW 0x707f 574 #define MATCH_FSW 0x2027 575 #define MASK_FSW 0x707f 576 #define MATCH_FMADD_S 0x43 577 #define MASK_FMADD_S 0x600007f 578 #define MATCH_FMSUB_S 0x47 579 #define MASK_FMSUB_S 0x600007f 580 #define MATCH_FNMSUB_S 0x4b 581 #define MASK_FNMSUB_S 0x600007f 582 #define MATCH_FNMADD_S 0x4f 583 #define MASK_FNMADD_S 0x600007f 584 #define MATCH_FCVT_L_S 0xc0200053 585 #define MASK_FCVT_L_S 0xfff0007f 586 #define MATCH_FCVT_LU_S 0xc0300053 587 #define MASK_FCVT_LU_S 0xfff0007f 588 #define MATCH_FCVT_S_L 0xd0200053 589 #define MASK_FCVT_S_L 0xfff0007f 590 #define MATCH_FCVT_S_LU 0xd0300053 591 #define MASK_FCVT_S_LU 0xfff0007f 592 #define MATCH_FADD_D 0x2000053 593 #define MASK_FADD_D 0xfe00007f 594 #define MATCH_FSUB_D 0xa000053 595 #define MASK_FSUB_D 0xfe00007f 596 #define MATCH_FMUL_D 0x12000053 597 #define MASK_FMUL_D 0xfe00007f 598 #define MATCH_FDIV_D 0x1a000053 599 #define MASK_FDIV_D 0xfe00007f 600 #define MATCH_FSGNJ_D 0x22000053 601 #define MASK_FSGNJ_D 0xfe00707f 602 #define MATCH_FSGNJN_D 0x22001053 603 #define MASK_FSGNJN_D 0xfe00707f 604 #define MATCH_FSGNJX_D 0x22002053 605 #define MASK_FSGNJX_D 0xfe00707f 606 #define MATCH_FMIN_D 0x2a000053 607 #define MASK_FMIN_D 0xfe00707f 608 #define MATCH_FMAX_D 0x2a001053 609 #define MASK_FMAX_D 0xfe00707f 610 #define MATCH_FCVT_S_D 0x40100053 611 #define MASK_FCVT_S_D 0xfff0007f 612 #define MATCH_FCVT_D_S 0x42000053 613 #define MASK_FCVT_D_S 0xfff0007f 614 #define MATCH_FSQRT_D 0x5a000053 615 #define MASK_FSQRT_D 0xfff0007f 616 #define MATCH_FLE_D 0xa2000053 617 #define MASK_FLE_D 0xfe00707f 618 #define MATCH_FLT_D 0xa2001053 619 #define MASK_FLT_D 0xfe00707f 620 #define MATCH_FEQ_D 0xa2002053 621 #define MASK_FEQ_D 0xfe00707f 622 #define MATCH_FCVT_W_D 0xc2000053 623 #define MASK_FCVT_W_D 0xfff0007f 624 #define MATCH_FCVT_WU_D 0xc2100053 625 #define MASK_FCVT_WU_D 0xfff0007f 626 #define MATCH_FCLASS_D 0xe2001053 627 #define MASK_FCLASS_D 0xfff0707f 628 #define MATCH_FCVT_D_W 0xd2000053 629 #define MASK_FCVT_D_W 0xfff0007f 630 #define MATCH_FCVT_D_WU 0xd2100053 631 #define MASK_FCVT_D_WU 0xfff0007f 632 #define MATCH_FLD 0x3007 633 #define MASK_FLD 0x707f 634 #define MATCH_FSD 0x3027 635 #define MASK_FSD 0x707f 636 #define MATCH_FMADD_D 0x2000043 637 #define MASK_FMADD_D 0x600007f 638 #define MATCH_FMSUB_D 0x2000047 639 #define MASK_FMSUB_D 0x600007f 640 #define MATCH_FNMSUB_D 0x200004b 641 #define MASK_FNMSUB_D 0x600007f 642 #define MATCH_FNMADD_D 0x200004f 643 #define MASK_FNMADD_D 0x600007f 644 #define MATCH_FCVT_L_D 0xc2200053 645 #define MASK_FCVT_L_D 0xfff0007f 646 #define MATCH_FCVT_LU_D 0xc2300053 647 #define MASK_FCVT_LU_D 0xfff0007f 648 #define MATCH_FMV_X_D 0xe2000053 649 #define MASK_FMV_X_D 0xfff0707f 650 #define MATCH_FCVT_D_L 0xd2200053 651 #define MASK_FCVT_D_L 0xfff0007f 652 #define MATCH_FCVT_D_LU 0xd2300053 653 #define MASK_FCVT_D_LU 0xfff0007f 654 #define MATCH_FMV_D_X 0xf2000053 655 #define MASK_FMV_D_X 0xfff0707f 656 #define MATCH_FADD_Q 0x6000053 657 #define MASK_FADD_Q 0xfe00007f 658 #define MATCH_FSUB_Q 0xe000053 659 #define MASK_FSUB_Q 0xfe00007f 660 #define MATCH_FMUL_Q 0x16000053 661 #define MASK_FMUL_Q 0xfe00007f 662 #define MATCH_FDIV_Q 0x1e000053 663 #define MASK_FDIV_Q 0xfe00007f 664 #define MATCH_FSGNJ_Q 0x26000053 665 #define MASK_FSGNJ_Q 0xfe00707f 666 #define MATCH_FSGNJN_Q 0x26001053 667 #define MASK_FSGNJN_Q 0xfe00707f 668 #define MATCH_FSGNJX_Q 0x26002053 669 #define MASK_FSGNJX_Q 0xfe00707f 670 #define MATCH_FMIN_Q 0x2e000053 671 #define MASK_FMIN_Q 0xfe00707f 672 #define MATCH_FMAX_Q 0x2e001053 673 #define MASK_FMAX_Q 0xfe00707f 674 #define MATCH_FCVT_S_Q 0x40300053 675 #define MASK_FCVT_S_Q 0xfff0007f 676 #define MATCH_FCVT_Q_S 0x46000053 677 #define MASK_FCVT_Q_S 0xfff0007f 678 #define MATCH_FCVT_D_Q 0x42300053 679 #define MASK_FCVT_D_Q 0xfff0007f 680 #define MATCH_FCVT_Q_D 0x46100053 681 #define MASK_FCVT_Q_D 0xfff0007f 682 #define MATCH_FSQRT_Q 0x5e000053 683 #define MASK_FSQRT_Q 0xfff0007f 684 #define MATCH_FLE_Q 0xa6000053 685 #define MASK_FLE_Q 0xfe00707f 686 #define MATCH_FLT_Q 0xa6001053 687 #define MASK_FLT_Q 0xfe00707f 688 #define MATCH_FEQ_Q 0xa6002053 689 #define MASK_FEQ_Q 0xfe00707f 690 #define MATCH_FCVT_W_Q 0xc6000053 691 #define MASK_FCVT_W_Q 0xfff0007f 692 #define MATCH_FCVT_WU_Q 0xc6100053 693 #define MASK_FCVT_WU_Q 0xfff0007f 694 #define MATCH_FCLASS_Q 0xe6001053 695 #define MASK_FCLASS_Q 0xfff0707f 696 #define MATCH_FCVT_Q_W 0xd6000053 697 #define MASK_FCVT_Q_W 0xfff0007f 698 #define MATCH_FCVT_Q_WU 0xd6100053 699 #define MASK_FCVT_Q_WU 0xfff0007f 700 #define MATCH_FLQ 0x4007 701 #define MASK_FLQ 0x707f 702 #define MATCH_FSQ 0x4027 703 #define MASK_FSQ 0x707f 704 #define MATCH_FMADD_Q 0x6000043 705 #define MASK_FMADD_Q 0x600007f 706 #define MATCH_FMSUB_Q 0x6000047 707 #define MASK_FMSUB_Q 0x600007f 708 #define MATCH_FNMSUB_Q 0x600004b 709 #define MASK_FNMSUB_Q 0x600007f 710 #define MATCH_FNMADD_Q 0x600004f 711 #define MASK_FNMADD_Q 0x600007f 712 #define MATCH_FCVT_L_Q 0xc6200053 713 #define MASK_FCVT_L_Q 0xfff0007f 714 #define MATCH_FCVT_LU_Q 0xc6300053 715 #define MASK_FCVT_LU_Q 0xfff0007f 716 #define MATCH_FCVT_Q_L 0xd6200053 717 #define MASK_FCVT_Q_L 0xfff0007f 718 #define MATCH_FCVT_Q_LU 0xd6300053 719 #define MASK_FCVT_Q_LU 0xfff0007f 720 #define MATCH_ANDN 0x40007033 721 #define MASK_ANDN 0xfe00707f 722 #define MATCH_ORN 0x40006033 723 #define MASK_ORN 0xfe00707f 724 #define MATCH_XNOR 0x40004033 725 #define MASK_XNOR 0xfe00707f 726 #define MATCH_SLO 0x20001033 727 #define MASK_SLO 0xfe00707f 728 #define MATCH_SRO 0x20005033 729 #define MASK_SRO 0xfe00707f 730 #define MATCH_ROL 0x60001033 731 #define MASK_ROL 0xfe00707f 732 #define MATCH_ROR 0x60005033 733 #define MASK_ROR 0xfe00707f 734 #define MATCH_BCLR 0x48001033 735 #define MASK_BCLR 0xfe00707f 736 #define MATCH_BSET 0x28001033 737 #define MASK_BSET 0xfe00707f 738 #define MATCH_BINV 0x68001033 739 #define MASK_BINV 0xfe00707f 740 #define MATCH_BEXT 0x48005033 741 #define MASK_BEXT 0xfe00707f 742 #define MATCH_GORC 0x28005033 743 #define MASK_GORC 0xfe00707f 744 #define MATCH_GREV 0x68005033 745 #define MASK_GREV 0xfe00707f 746 #define MATCH_SLOI 0x20001013 747 #define MASK_SLOI 0xfc00707f 748 #define MATCH_SROI 0x20005013 749 #define MASK_SROI 0xfc00707f 750 #define MATCH_RORI 0x60005013 751 #define MASK_RORI 0xfc00707f 752 #define MATCH_BCLRI 0x48001013 753 #define MASK_BCLRI 0xfc00707f 754 #define MATCH_BSETI 0x28001013 755 #define MASK_BSETI 0xfc00707f 756 #define MATCH_BINVI 0x68001013 757 #define MASK_BINVI 0xfc00707f 758 #define MATCH_BEXTI 0x48005013 759 #define MASK_BEXTI 0xfc00707f 760 #define MATCH_GORCI 0x28005013 761 #define MASK_GORCI 0xfc00707f 762 #define MATCH_GREVI 0x68005013 763 #define MASK_GREVI 0xfc00707f 764 #define MATCH_CMIX 0x6001033 765 #define MASK_CMIX 0x600707f 766 #define MATCH_CMOV 0x6005033 767 #define MASK_CMOV 0x600707f 768 #define MATCH_FSL 0x4001033 769 #define MASK_FSL 0x600707f 770 #define MATCH_FSR 0x4005033 771 #define MASK_FSR 0x600707f 772 #define MATCH_FSRI 0x4005013 773 #define MASK_FSRI 0x400707f 774 #define MATCH_CLZ 0x60001013 775 #define MASK_CLZ 0xfff0707f 776 #define MATCH_CTZ 0x60101013 777 #define MASK_CTZ 0xfff0707f 778 #define MATCH_CPOP 0x60201013 779 #define MASK_CPOP 0xfff0707f 780 #define MATCH_SEXT_B 0x60401013 781 #define MASK_SEXT_B 0xfff0707f 782 #define MATCH_SEXT_H 0x60501013 783 #define MASK_SEXT_H 0xfff0707f 784 #define MATCH_CRC32_B 0x61001013 785 #define MASK_CRC32_B 0xfff0707f 786 #define MATCH_CRC32_H 0x61101013 787 #define MASK_CRC32_H 0xfff0707f 788 #define MATCH_CRC32_W 0x61201013 789 #define MASK_CRC32_W 0xfff0707f 790 #define MATCH_CRC32C_B 0x61801013 791 #define MASK_CRC32C_B 0xfff0707f 792 #define MATCH_CRC32C_H 0x61901013 793 #define MASK_CRC32C_H 0xfff0707f 794 #define MATCH_CRC32C_W 0x61a01013 795 #define MASK_CRC32C_W 0xfff0707f 796 #define MATCH_SH1ADD 0x20002033 797 #define MASK_SH1ADD 0xfe00707f 798 #define MATCH_SH2ADD 0x20004033 799 #define MASK_SH2ADD 0xfe00707f 800 #define MATCH_SH3ADD 0x20006033 801 #define MASK_SH3ADD 0xfe00707f 802 #define MATCH_CLMUL 0xa001033 803 #define MASK_CLMUL 0xfe00707f 804 #define MATCH_CLMULR 0xa002033 805 #define MASK_CLMULR 0xfe00707f 806 #define MATCH_CLMULH 0xa003033 807 #define MASK_CLMULH 0xfe00707f 808 #define MATCH_MIN 0xa004033 809 #define MASK_MIN 0xfe00707f 810 #define MATCH_MINU 0xa005033 811 #define MASK_MINU 0xfe00707f 812 #define MATCH_MAX 0xa006033 813 #define MASK_MAX 0xfe00707f 814 #define MATCH_MAXU 0xa007033 815 #define MASK_MAXU 0xfe00707f 816 #define MATCH_SHFL 0x8001033 817 #define MASK_SHFL 0xfe00707f 818 #define MATCH_UNSHFL 0x8005033 819 #define MASK_UNSHFL 0xfe00707f 820 #define MATCH_BCOMPRESS 0x8006033 821 #define MASK_BCOMPRESS 0xfe00707f 822 #define MATCH_BDECOMPRESS 0x48006033 823 #define MASK_BDECOMPRESS 0xfe00707f 824 #define MATCH_PACK 0x8004033 825 #define MASK_PACK 0xfe00707f 826 #define MATCH_PACKU 0x48004033 827 #define MASK_PACKU 0xfe00707f 828 #define MATCH_PACKH 0x8007033 829 #define MASK_PACKH 0xfe00707f 830 #define MATCH_BFP 0x48007033 831 #define MASK_BFP 0xfe00707f 832 #define MATCH_SHFLI 0x8001013 833 #define MASK_SHFLI 0xfe00707f 834 #define MATCH_UNSHFLI 0x8005013 835 #define MASK_UNSHFLI 0xfe00707f 836 #define MATCH_XPERM_N 0x28002033 837 #define MASK_XPERM_N 0xfe00707f 838 #define MATCH_XPERM_B 0x28004033 839 #define MASK_XPERM_B 0xfe00707f 840 #define MATCH_XPERM_H 0x28006033 841 #define MASK_XPERM_H 0xfe00707f 842 #define MATCH_BMATFLIP 0x60301013 843 #define MASK_BMATFLIP 0xfff0707f 844 #define MATCH_CRC32_D 0x61301013 845 #define MASK_CRC32_D 0xfff0707f 846 #define MATCH_CRC32C_D 0x61b01013 847 #define MASK_CRC32C_D 0xfff0707f 848 #define MATCH_BMATOR 0x8003033 849 #define MASK_BMATOR 0xfe00707f 850 #define MATCH_BMATXOR 0x48003033 851 #define MASK_BMATXOR 0xfe00707f 852 #define MATCH_SLLI_UW 0x800101b 853 #define MASK_SLLI_UW 0xfc00707f 854 #define MATCH_ADD_UW 0x800003b 855 #define MASK_ADD_UW 0xfe00707f 856 #define MATCH_SLOW 0x2000103b 857 #define MASK_SLOW 0xfe00707f 858 #define MATCH_SROW 0x2000503b 859 #define MASK_SROW 0xfe00707f 860 #define MATCH_ROLW 0x6000103b 861 #define MASK_ROLW 0xfe00707f 862 #define MATCH_RORW 0x6000503b 863 #define MASK_RORW 0xfe00707f 864 #define MATCH_SBCLRW 0x4800103b 865 #define MASK_SBCLRW 0xfe00707f 866 #define MATCH_SBSETW 0x2800103b 867 #define MASK_SBSETW 0xfe00707f 868 #define MATCH_SBINVW 0x6800103b 869 #define MASK_SBINVW 0xfe00707f 870 #define MATCH_SBEXTW 0x4800503b 871 #define MASK_SBEXTW 0xfe00707f 872 #define MATCH_GORCW 0x2800503b 873 #define MASK_GORCW 0xfe00707f 874 #define MATCH_GREVW 0x6800503b 875 #define MASK_GREVW 0xfe00707f 876 #define MATCH_SLOIW 0x2000101b 877 #define MASK_SLOIW 0xfe00707f 878 #define MATCH_SROIW 0x2000501b 879 #define MASK_SROIW 0xfe00707f 880 #define MATCH_RORIW 0x6000501b 881 #define MASK_RORIW 0xfe00707f 882 #define MATCH_SBCLRIW 0x4800101b 883 #define MASK_SBCLRIW 0xfe00707f 884 #define MATCH_SBSETIW 0x2800101b 885 #define MASK_SBSETIW 0xfe00707f 886 #define MATCH_SBINVIW 0x6800101b 887 #define MASK_SBINVIW 0xfe00707f 888 #define MATCH_GORCIW 0x2800501b 889 #define MASK_GORCIW 0xfe00707f 890 #define MATCH_GREVIW 0x6800501b 891 #define MASK_GREVIW 0xfe00707f 892 #define MATCH_FSLW 0x400103b 893 #define MASK_FSLW 0x600707f 894 #define MATCH_FSRW 0x400503b 895 #define MASK_FSRW 0x600707f 896 #define MATCH_FSRIW 0x400501b 897 #define MASK_FSRIW 0x600707f 898 #define MATCH_CLZW 0x6000101b 899 #define MASK_CLZW 0xfff0707f 900 #define MATCH_CTZW 0x6010101b 901 #define MASK_CTZW 0xfff0707f 902 #define MATCH_CPOPW 0x6020101b 903 #define MASK_CPOPW 0xfff0707f 904 #define MATCH_SH1ADD_UW 0x2000203b 905 #define MASK_SH1ADD_UW 0xfe00707f 906 #define MATCH_SH2ADD_UW 0x2000403b 907 #define MASK_SH2ADD_UW 0xfe00707f 908 #define MATCH_SH3ADD_UW 0x2000603b 909 #define MASK_SH3ADD_UW 0xfe00707f 910 #define MATCH_SHFLW 0x800103b 911 #define MASK_SHFLW 0xfe00707f 912 #define MATCH_UNSHFLW 0x800503b 913 #define MASK_UNSHFLW 0xfe00707f 914 #define MATCH_BCOMPRESSW 0x800603b 915 #define MASK_BCOMPRESSW 0xfe00707f 916 #define MATCH_BDECOMPRESSW 0x4800603b 917 #define MASK_BDECOMPRESSW 0xfe00707f 918 #define MATCH_PACKW 0x800403b 919 #define MASK_PACKW 0xfe00707f 920 #define MATCH_PACKUW 0x4800403b 921 #define MASK_PACKUW 0xfe00707f 922 #define MATCH_BFPW 0x4800703b 923 #define MASK_BFPW 0xfe00707f 924 #define MATCH_XPERM_W 0x28000033 925 #define MASK_XPERM_W 0xfe00707f 926 #define MATCH_ECALL 0x73 927 #define MASK_ECALL 0xffffffff 928 #define MATCH_EBREAK 0x100073 929 #define MASK_EBREAK 0xffffffff 930 #define MATCH_URET 0x200073 931 #define MASK_URET 0xffffffff 932 #define MATCH_SRET 0x10200073 933 #define MASK_SRET 0xffffffff 934 #define MATCH_MRET 0x30200073 935 #define MASK_MRET 0xffffffff 936 #define MATCH_DRET 0x7b200073 937 #define MASK_DRET 0xffffffff 938 #define MATCH_SFENCE_VMA 0x12000073 939 #define MASK_SFENCE_VMA 0xfe007fff 940 #define MATCH_WFI 0x10500073 941 #define MASK_WFI 0xffffffff 942 #define MATCH_CSRRW 0x1073 943 #define MASK_CSRRW 0x707f 944 #define MATCH_CSRRS 0x2073 945 #define MASK_CSRRS 0x707f 946 #define MATCH_CSRRC 0x3073 947 #define MASK_CSRRC 0x707f 948 #define MATCH_CSRRWI 0x5073 949 #define MASK_CSRRWI 0x707f 950 #define MATCH_CSRRSI 0x6073 951 #define MASK_CSRRSI 0x707f 952 #define MATCH_CSRRCI 0x7073 953 #define MASK_CSRRCI 0x707f 954 #define MATCH_SINVAL_VMA 0x16000073 955 #define MASK_SINVAL_VMA 0xfe007fff 956 #define MATCH_SFENCE_W_INVAL 0x18000073 957 #define MASK_SFENCE_W_INVAL 0xfff07fff 958 #define MATCH_SFENCE_INVAL_IR 0x18100073 959 #define MASK_SFENCE_INVAL_IR 0xfff07fff 960 #define MATCH_HINVAL_VVMA 0x36000073 961 #define MASK_HINVAL_VVMA 0xfe007fff 962 #define MATCH_HINVAL_GVMA 0x76000073 963 #define MASK_HINVAL_GVMA 0xfe007fff 964 #define MATCH_FADD_H 0x4000053 965 #define MASK_FADD_H 0xfe00007f 966 #define MATCH_FSUB_H 0xc000053 967 #define MASK_FSUB_H 0xfe00007f 968 #define MATCH_FMUL_H 0x14000053 969 #define MASK_FMUL_H 0xfe00007f 970 #define MATCH_FDIV_H 0x1c000053 971 #define MASK_FDIV_H 0xfe00007f 972 #define MATCH_FSGNJ_H 0x24000053 973 #define MASK_FSGNJ_H 0xfe00707f 974 #define MATCH_FSGNJN_H 0x24001053 975 #define MASK_FSGNJN_H 0xfe00707f 976 #define MATCH_FSGNJX_H 0x24002053 977 #define MASK_FSGNJX_H 0xfe00707f 978 #define MATCH_FMIN_H 0x2c000053 979 #define MASK_FMIN_H 0xfe00707f 980 #define MATCH_FMAX_H 0x2c001053 981 #define MASK_FMAX_H 0xfe00707f 982 #define MATCH_FCVT_H_S 0x44000053 983 #define MASK_FCVT_H_S 0xfff0007f 984 #define MATCH_FCVT_S_H 0x40200053 985 #define MASK_FCVT_S_H 0xfff0007f 986 #define MATCH_FSQRT_H 0x5c000053 987 #define MASK_FSQRT_H 0xfff0007f 988 #define MATCH_FLE_H 0xa4000053 989 #define MASK_FLE_H 0xfe00707f 990 #define MATCH_FLT_H 0xa4001053 991 #define MASK_FLT_H 0xfe00707f 992 #define MATCH_FEQ_H 0xa4002053 993 #define MASK_FEQ_H 0xfe00707f 994 #define MATCH_FCVT_W_H 0xc4000053 995 #define MASK_FCVT_W_H 0xfff0007f 996 #define MATCH_FCVT_WU_H 0xc4100053 997 #define MASK_FCVT_WU_H 0xfff0007f 998 #define MATCH_FMV_X_H 0xe4000053 999 #define MASK_FMV_X_H 0xfff0707f 1000 #define MATCH_FCLASS_H 0xe4001053 1001 #define MASK_FCLASS_H 0xfff0707f 1002 #define MATCH_FCVT_H_W 0xd4000053 1003 #define MASK_FCVT_H_W 0xfff0007f 1004 #define MATCH_FCVT_H_WU 0xd4100053 1005 #define MASK_FCVT_H_WU 0xfff0007f 1006 #define MATCH_FMV_H_X 0xf4000053 1007 #define MASK_FMV_H_X 0xfff0707f 1008 #define MATCH_FLH 0x1007 1009 #define MASK_FLH 0x707f 1010 #define MATCH_FSH 0x1027 1011 #define MASK_FSH 0x707f 1012 #define MATCH_FMADD_H 0x4000043 1013 #define MASK_FMADD_H 0x600007f 1014 #define MATCH_FMSUB_H 0x4000047 1015 #define MASK_FMSUB_H 0x600007f 1016 #define MATCH_FNMSUB_H 0x400004b 1017 #define MASK_FNMSUB_H 0x600007f 1018 #define MATCH_FNMADD_H 0x400004f 1019 #define MASK_FNMADD_H 0x600007f 1020 #define MATCH_FCVT_H_D 0x44100053 1021 #define MASK_FCVT_H_D 0xfff0007f 1022 #define MATCH_FCVT_D_H 0x42200053 1023 #define MASK_FCVT_D_H 0xfff0007f 1024 #define MATCH_FCVT_H_Q 0x44300053 1025 #define MASK_FCVT_H_Q 0xfff0007f 1026 #define MATCH_FCVT_Q_H 0x46200053 1027 #define MASK_FCVT_Q_H 0xfff0007f 1028 #define MATCH_FCVT_L_H 0xc4200053 1029 #define MASK_FCVT_L_H 0xfff0007f 1030 #define MATCH_FCVT_LU_H 0xc4300053 1031 #define MASK_FCVT_LU_H 0xfff0007f 1032 #define MATCH_FCVT_H_L 0xd4200053 1033 #define MASK_FCVT_H_L 0xfff0007f 1034 #define MATCH_FCVT_H_LU 0xd4300053 1035 #define MASK_FCVT_H_LU 0xfff0007f 1036 #define MATCH_SM4ED 0x30000033 1037 #define MASK_SM4ED 0x3e00707f 1038 #define MATCH_SM4KS 0x34000033 1039 #define MASK_SM4KS 0x3e00707f 1040 #define MATCH_SM3P0 0x10801013 1041 #define MASK_SM3P0 0xfff0707f 1042 #define MATCH_SM3P1 0x10901013 1043 #define MASK_SM3P1 0xfff0707f 1044 #define MATCH_SHA256SUM0 0x10001013 1045 #define MASK_SHA256SUM0 0xfff0707f 1046 #define MATCH_SHA256SUM1 0x10101013 1047 #define MASK_SHA256SUM1 0xfff0707f 1048 #define MATCH_SHA256SIG0 0x10201013 1049 #define MASK_SHA256SIG0 0xfff0707f 1050 #define MATCH_SHA256SIG1 0x10301013 1051 #define MASK_SHA256SIG1 0xfff0707f 1052 #define MATCH_AES32ESMI 0x26000033 1053 #define MASK_AES32ESMI 0x3e00707f 1054 #define MATCH_AES32ESI 0x22000033 1055 #define MASK_AES32ESI 0x3e00707f 1056 #define MATCH_AES32DSMI 0x2e000033 1057 #define MASK_AES32DSMI 0x3e00707f 1058 #define MATCH_AES32DSI 0x2a000033 1059 #define MASK_AES32DSI 0x3e00707f 1060 #define MATCH_SHA512SUM0R 0x50000033 1061 #define MASK_SHA512SUM0R 0xfe00707f 1062 #define MATCH_SHA512SUM1R 0x52000033 1063 #define MASK_SHA512SUM1R 0xfe00707f 1064 #define MATCH_SHA512SIG0L 0x54000033 1065 #define MASK_SHA512SIG0L 0xfe00707f 1066 #define MATCH_SHA512SIG0H 0x5c000033 1067 #define MASK_SHA512SIG0H 0xfe00707f 1068 #define MATCH_SHA512SIG1L 0x56000033 1069 #define MASK_SHA512SIG1L 0xfe00707f 1070 #define MATCH_SHA512SIG1H 0x5e000033 1071 #define MASK_SHA512SIG1H 0xfe00707f 1072 #define MATCH_AES64KS1I 0x31001013 1073 #define MASK_AES64KS1I 0xff00707f 1074 #define MATCH_AES64IM 0x30001013 1075 #define MASK_AES64IM 0xfff0707f 1076 #define MATCH_AES64KS2 0x7e000033 1077 #define MASK_AES64KS2 0xfe00707f 1078 #define MATCH_AES64ESM 0x36000033 1079 #define MASK_AES64ESM 0xfe00707f 1080 #define MATCH_AES64ES 0x32000033 1081 #define MASK_AES64ES 0xfe00707f 1082 #define MATCH_AES64DSM 0x3e000033 1083 #define MASK_AES64DSM 0xfe00707f 1084 #define MATCH_AES64DS 0x3a000033 1085 #define MASK_AES64DS 0xfe00707f 1086 #define MATCH_SHA512SUM0 0x10401013 1087 #define MASK_SHA512SUM0 0xfff0707f 1088 #define MATCH_SHA512SUM1 0x10501013 1089 #define MASK_SHA512SUM1 0xfff0707f 1090 #define MATCH_SHA512SIG0 0x10601013 1091 #define MASK_SHA512SIG0 0xfff0707f 1092 #define MATCH_SHA512SIG1 0x10701013 1093 #define MASK_SHA512SIG1 0xfff0707f 1094 #define MATCH_C_NOP 0x1 1095 #define MASK_C_NOP 0xffff 1096 #define MATCH_C_ADDI16SP 0x6101 1097 #define MASK_C_ADDI16SP 0xef83 1098 #define MATCH_C_JR 0x8002 1099 #define MASK_C_JR 0xf07f 1100 #define MATCH_C_JALR 0x9002 1101 #define MASK_C_JALR 0xf07f 1102 #define MATCH_C_EBREAK 0x9002 1103 #define MASK_C_EBREAK 0xffff 1104 #define MATCH_C_ADDI4SPN 0x0 1105 #define MASK_C_ADDI4SPN 0xe003 1106 #define MATCH_C_FLD 0x2000 1107 #define MASK_C_FLD 0xe003 1108 #define MATCH_C_LW 0x4000 1109 #define MASK_C_LW 0xe003 1110 #define MATCH_C_FLW 0x6000 1111 #define MASK_C_FLW 0xe003 1112 #define MATCH_C_FSD 0xa000 1113 #define MASK_C_FSD 0xe003 1114 #define MATCH_C_SW 0xc000 1115 #define MASK_C_SW 0xe003 1116 #define MATCH_C_FSW 0xe000 1117 #define MASK_C_FSW 0xe003 1118 #define MATCH_C_ADDI 0x1 1119 #define MASK_C_ADDI 0xe003 1120 #define MATCH_C_JAL 0x2001 1121 #define MASK_C_JAL 0xe003 1122 #define MATCH_C_LI 0x4001 1123 #define MASK_C_LI 0xe003 1124 #define MATCH_C_LUI 0x6001 1125 #define MASK_C_LUI 0xe003 1126 #define MATCH_C_SRLI 0x8001 1127 #define MASK_C_SRLI 0xec03 1128 #define MATCH_C_SRAI 0x8401 1129 #define MASK_C_SRAI 0xec03 1130 #define MATCH_C_ANDI 0x8801 1131 #define MASK_C_ANDI 0xec03 1132 #define MATCH_C_SUB 0x8c01 1133 #define MASK_C_SUB 0xfc63 1134 #define MATCH_C_XOR 0x8c21 1135 #define MASK_C_XOR 0xfc63 1136 #define MATCH_C_OR 0x8c41 1137 #define MASK_C_OR 0xfc63 1138 #define MATCH_C_AND 0x8c61 1139 #define MASK_C_AND 0xfc63 1140 #define MATCH_C_J 0xa001 1141 #define MASK_C_J 0xe003 1142 #define MATCH_C_BEQZ 0xc001 1143 #define MASK_C_BEQZ 0xe003 1144 #define MATCH_C_BNEZ 0xe001 1145 #define MASK_C_BNEZ 0xe003 1146 #define MATCH_C_SLLI 0x2 1147 #define MASK_C_SLLI 0xe003 1148 #define MATCH_C_FLDSP 0x2002 1149 #define MASK_C_FLDSP 0xe003 1150 #define MATCH_C_LWSP 0x4002 1151 #define MASK_C_LWSP 0xe003 1152 #define MATCH_C_FLWSP 0x6002 1153 #define MASK_C_FLWSP 0xe003 1154 #define MATCH_C_MV 0x8002 1155 #define MASK_C_MV 0xf003 1156 #define MATCH_C_ADD 0x9002 1157 #define MASK_C_ADD 0xf003 1158 #define MATCH_C_FSDSP 0xa002 1159 #define MASK_C_FSDSP 0xe003 1160 #define MATCH_C_SWSP 0xc002 1161 #define MASK_C_SWSP 0xe003 1162 #define MATCH_C_FSWSP 0xe002 1163 #define MASK_C_FSWSP 0xe003 1164 #define MATCH_C_SRLI_RV32 0x8001 1165 #define MASK_C_SRLI_RV32 0xfc03 1166 #define MATCH_C_SRAI_RV32 0x8401 1167 #define MASK_C_SRAI_RV32 0xfc03 1168 #define MATCH_C_SLLI_RV32 0x2 1169 #define MASK_C_SLLI_RV32 0xf003 1170 #define MATCH_C_LD 0x6000 1171 #define MASK_C_LD 0xe003 1172 #define MATCH_C_SD 0xe000 1173 #define MASK_C_SD 0xe003 1174 #define MATCH_C_SUBW 0x9c01 1175 #define MASK_C_SUBW 0xfc63 1176 #define MATCH_C_ADDW 0x9c21 1177 #define MASK_C_ADDW 0xfc63 1178 #define MATCH_C_ADDIW 0x2001 1179 #define MASK_C_ADDIW 0xe003 1180 #define MATCH_C_LDSP 0x6002 1181 #define MASK_C_LDSP 0xe003 1182 #define MATCH_C_SDSP 0xe002 1183 #define MASK_C_SDSP 0xe003 1184 #define MATCH_CUSTOM0 0xb 1185 #define MASK_CUSTOM0 0x707f 1186 #define MATCH_CUSTOM0_RS1 0x200b 1187 #define MASK_CUSTOM0_RS1 0x707f 1188 #define MATCH_CUSTOM0_RS1_RS2 0x300b 1189 #define MASK_CUSTOM0_RS1_RS2 0x707f 1190 #define MATCH_CUSTOM0_RD 0x400b 1191 #define MASK_CUSTOM0_RD 0x707f 1192 #define MATCH_CUSTOM0_RD_RS1 0x600b 1193 #define MASK_CUSTOM0_RD_RS1 0x707f 1194 #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b 1195 #define MASK_CUSTOM0_RD_RS1_RS2 0x707f 1196 #define MATCH_CUSTOM1 0x2b 1197 #define MASK_CUSTOM1 0x707f 1198 #define MATCH_CUSTOM1_RS1 0x202b 1199 #define MASK_CUSTOM1_RS1 0x707f 1200 #define MATCH_CUSTOM1_RS1_RS2 0x302b 1201 #define MASK_CUSTOM1_RS1_RS2 0x707f 1202 #define MATCH_CUSTOM1_RD 0x402b 1203 #define MASK_CUSTOM1_RD 0x707f 1204 #define MATCH_CUSTOM1_RD_RS1 0x602b 1205 #define MASK_CUSTOM1_RD_RS1 0x707f 1206 #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b 1207 #define MASK_CUSTOM1_RD_RS1_RS2 0x707f 1208 #define MATCH_CUSTOM2 0x5b 1209 #define MASK_CUSTOM2 0x707f 1210 #define MATCH_CUSTOM2_RS1 0x205b 1211 #define MASK_CUSTOM2_RS1 0x707f 1212 #define MATCH_CUSTOM2_RS1_RS2 0x305b 1213 #define MASK_CUSTOM2_RS1_RS2 0x707f 1214 #define MATCH_CUSTOM2_RD 0x405b 1215 #define MASK_CUSTOM2_RD 0x707f 1216 #define MATCH_CUSTOM2_RD_RS1 0x605b 1217 #define MASK_CUSTOM2_RD_RS1 0x707f 1218 #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b 1219 #define MASK_CUSTOM2_RD_RS1_RS2 0x707f 1220 #define MATCH_CUSTOM3 0x7b 1221 #define MASK_CUSTOM3 0x707f 1222 #define MATCH_CUSTOM3_RS1 0x207b 1223 #define MASK_CUSTOM3_RS1 0x707f 1224 #define MATCH_CUSTOM3_RS1_RS2 0x307b 1225 #define MASK_CUSTOM3_RS1_RS2 0x707f 1226 #define MATCH_CUSTOM3_RD 0x407b 1227 #define MASK_CUSTOM3_RD 0x707f 1228 #define MATCH_CUSTOM3_RD_RS1 0x607b 1229 #define MASK_CUSTOM3_RD_RS1 0x707f 1230 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b 1231 #define MASK_CUSTOM3_RD_RS1_RS2 0x707f 1232 #define MATCH_VSETIVLI 0xc0007057 1233 #define MASK_VSETIVLI 0xc000707f 1234 #define MATCH_VSETVLI 0x7057 1235 #define MASK_VSETVLI 0x8000707f 1236 #define MATCH_VSETVL 0x80007057 1237 #define MASK_VSETVL 0xfe00707f 1238 #define MATCH_VLM_V 0x2b00007 1239 #define MASK_VLM_V 0xfff0707f 1240 #define MATCH_VSM_V 0x2b00027 1241 #define MASK_VSM_V 0xfff0707f 1242 #define MATCH_VLE8_V 0x7 1243 #define MASK_VLE8_V 0x1df0707f 1244 #define MATCH_VLE16_V 0x5007 1245 #define MASK_VLE16_V 0x1df0707f 1246 #define MATCH_VLE32_V 0x6007 1247 #define MASK_VLE32_V 0x1df0707f 1248 #define MATCH_VLE64_V 0x7007 1249 #define MASK_VLE64_V 0x1df0707f 1250 #define MATCH_VLE128_V 0x10000007 1251 #define MASK_VLE128_V 0x1df0707f 1252 #define MATCH_VLE256_V 0x10005007 1253 #define MASK_VLE256_V 0x1df0707f 1254 #define MATCH_VLE512_V 0x10006007 1255 #define MASK_VLE512_V 0x1df0707f 1256 #define MATCH_VLE1024_V 0x10007007 1257 #define MASK_VLE1024_V 0x1df0707f 1258 #define MATCH_VSE8_V 0x27 1259 #define MASK_VSE8_V 0x1df0707f 1260 #define MATCH_VSE16_V 0x5027 1261 #define MASK_VSE16_V 0x1df0707f 1262 #define MATCH_VSE32_V 0x6027 1263 #define MASK_VSE32_V 0x1df0707f 1264 #define MATCH_VSE64_V 0x7027 1265 #define MASK_VSE64_V 0x1df0707f 1266 #define MATCH_VSE128_V 0x10000027 1267 #define MASK_VSE128_V 0x1df0707f 1268 #define MATCH_VSE256_V 0x10005027 1269 #define MASK_VSE256_V 0x1df0707f 1270 #define MATCH_VSE512_V 0x10006027 1271 #define MASK_VSE512_V 0x1df0707f 1272 #define MATCH_VSE1024_V 0x10007027 1273 #define MASK_VSE1024_V 0x1df0707f 1274 #define MATCH_VLUXEI8_V 0x4000007 1275 #define MASK_VLUXEI8_V 0x1c00707f 1276 #define MATCH_VLUXEI16_V 0x4005007 1277 #define MASK_VLUXEI16_V 0x1c00707f 1278 #define MATCH_VLUXEI32_V 0x4006007 1279 #define MASK_VLUXEI32_V 0x1c00707f 1280 #define MATCH_VLUXEI64_V 0x4007007 1281 #define MASK_VLUXEI64_V 0x1c00707f 1282 #define MATCH_VLUXEI128_V 0x14000007 1283 #define MASK_VLUXEI128_V 0x1c00707f 1284 #define MATCH_VLUXEI256_V 0x14005007 1285 #define MASK_VLUXEI256_V 0x1c00707f 1286 #define MATCH_VLUXEI512_V 0x14006007 1287 #define MASK_VLUXEI512_V 0x1c00707f 1288 #define MATCH_VLUXEI1024_V 0x14007007 1289 #define MASK_VLUXEI1024_V 0x1c00707f 1290 #define MATCH_VSUXEI8_V 0x4000027 1291 #define MASK_VSUXEI8_V 0x1c00707f 1292 #define MATCH_VSUXEI16_V 0x4005027 1293 #define MASK_VSUXEI16_V 0x1c00707f 1294 #define MATCH_VSUXEI32_V 0x4006027 1295 #define MASK_VSUXEI32_V 0x1c00707f 1296 #define MATCH_VSUXEI64_V 0x4007027 1297 #define MASK_VSUXEI64_V 0x1c00707f 1298 #define MATCH_VSUXEI128_V 0x14000027 1299 #define MASK_VSUXEI128_V 0x1c00707f 1300 #define MATCH_VSUXEI256_V 0x14005027 1301 #define MASK_VSUXEI256_V 0x1c00707f 1302 #define MATCH_VSUXEI512_V 0x14006027 1303 #define MASK_VSUXEI512_V 0x1c00707f 1304 #define MATCH_VSUXEI1024_V 0x14007027 1305 #define MASK_VSUXEI1024_V 0x1c00707f 1306 #define MATCH_VLSE8_V 0x8000007 1307 #define MASK_VLSE8_V 0x1c00707f 1308 #define MATCH_VLSE16_V 0x8005007 1309 #define MASK_VLSE16_V 0x1c00707f 1310 #define MATCH_VLSE32_V 0x8006007 1311 #define MASK_VLSE32_V 0x1c00707f 1312 #define MATCH_VLSE64_V 0x8007007 1313 #define MASK_VLSE64_V 0x1c00707f 1314 #define MATCH_VLSE128_V 0x18000007 1315 #define MASK_VLSE128_V 0x1c00707f 1316 #define MATCH_VLSE256_V 0x18005007 1317 #define MASK_VLSE256_V 0x1c00707f 1318 #define MATCH_VLSE512_V 0x18006007 1319 #define MASK_VLSE512_V 0x1c00707f 1320 #define MATCH_VLSE1024_V 0x18007007 1321 #define MASK_VLSE1024_V 0x1c00707f 1322 #define MATCH_VSSE8_V 0x8000027 1323 #define MASK_VSSE8_V 0x1c00707f 1324 #define MATCH_VSSE16_V 0x8005027 1325 #define MASK_VSSE16_V 0x1c00707f 1326 #define MATCH_VSSE32_V 0x8006027 1327 #define MASK_VSSE32_V 0x1c00707f 1328 #define MATCH_VSSE64_V 0x8007027 1329 #define MASK_VSSE64_V 0x1c00707f 1330 #define MATCH_VSSE128_V 0x18000027 1331 #define MASK_VSSE128_V 0x1c00707f 1332 #define MATCH_VSSE256_V 0x18005027 1333 #define MASK_VSSE256_V 0x1c00707f 1334 #define MATCH_VSSE512_V 0x18006027 1335 #define MASK_VSSE512_V 0x1c00707f 1336 #define MATCH_VSSE1024_V 0x18007027 1337 #define MASK_VSSE1024_V 0x1c00707f 1338 #define MATCH_VLOXEI8_V 0xc000007 1339 #define MASK_VLOXEI8_V 0x1c00707f 1340 #define MATCH_VLOXEI16_V 0xc005007 1341 #define MASK_VLOXEI16_V 0x1c00707f 1342 #define MATCH_VLOXEI32_V 0xc006007 1343 #define MASK_VLOXEI32_V 0x1c00707f 1344 #define MATCH_VLOXEI64_V 0xc007007 1345 #define MASK_VLOXEI64_V 0x1c00707f 1346 #define MATCH_VLOXEI128_V 0x1c000007 1347 #define MASK_VLOXEI128_V 0x1c00707f 1348 #define MATCH_VLOXEI256_V 0x1c005007 1349 #define MASK_VLOXEI256_V 0x1c00707f 1350 #define MATCH_VLOXEI512_V 0x1c006007 1351 #define MASK_VLOXEI512_V 0x1c00707f 1352 #define MATCH_VLOXEI1024_V 0x1c007007 1353 #define MASK_VLOXEI1024_V 0x1c00707f 1354 #define MATCH_VSOXEI8_V 0xc000027 1355 #define MASK_VSOXEI8_V 0x1c00707f 1356 #define MATCH_VSOXEI16_V 0xc005027 1357 #define MASK_VSOXEI16_V 0x1c00707f 1358 #define MATCH_VSOXEI32_V 0xc006027 1359 #define MASK_VSOXEI32_V 0x1c00707f 1360 #define MATCH_VSOXEI64_V 0xc007027 1361 #define MASK_VSOXEI64_V 0x1c00707f 1362 #define MATCH_VSOXEI128_V 0x1c000027 1363 #define MASK_VSOXEI128_V 0x1c00707f 1364 #define MATCH_VSOXEI256_V 0x1c005027 1365 #define MASK_VSOXEI256_V 0x1c00707f 1366 #define MATCH_VSOXEI512_V 0x1c006027 1367 #define MASK_VSOXEI512_V 0x1c00707f 1368 #define MATCH_VSOXEI1024_V 0x1c007027 1369 #define MASK_VSOXEI1024_V 0x1c00707f 1370 #define MATCH_VLE8FF_V 0x1000007 1371 #define MASK_VLE8FF_V 0x1df0707f 1372 #define MATCH_VLE16FF_V 0x1005007 1373 #define MASK_VLE16FF_V 0x1df0707f 1374 #define MATCH_VLE32FF_V 0x1006007 1375 #define MASK_VLE32FF_V 0x1df0707f 1376 #define MATCH_VLE64FF_V 0x1007007 1377 #define MASK_VLE64FF_V 0x1df0707f 1378 #define MATCH_VLE128FF_V 0x11000007 1379 #define MASK_VLE128FF_V 0x1df0707f 1380 #define MATCH_VLE256FF_V 0x11005007 1381 #define MASK_VLE256FF_V 0x1df0707f 1382 #define MATCH_VLE512FF_V 0x11006007 1383 #define MASK_VLE512FF_V 0x1df0707f 1384 #define MATCH_VLE1024FF_V 0x11007007 1385 #define MASK_VLE1024FF_V 0x1df0707f 1386 #define MATCH_VL1RE8_V 0x2800007 1387 #define MASK_VL1RE8_V 0xfff0707f 1388 #define MATCH_VL1RE16_V 0x2805007 1389 #define MASK_VL1RE16_V 0xfff0707f 1390 #define MATCH_VL1RE32_V 0x2806007 1391 #define MASK_VL1RE32_V 0xfff0707f 1392 #define MATCH_VL1RE64_V 0x2807007 1393 #define MASK_VL1RE64_V 0xfff0707f 1394 #define MATCH_VL2RE8_V 0x22800007 1395 #define MASK_VL2RE8_V 0xfff0707f 1396 #define MATCH_VL2RE16_V 0x22805007 1397 #define MASK_VL2RE16_V 0xfff0707f 1398 #define MATCH_VL2RE32_V 0x22806007 1399 #define MASK_VL2RE32_V 0xfff0707f 1400 #define MATCH_VL2RE64_V 0x22807007 1401 #define MASK_VL2RE64_V 0xfff0707f 1402 #define MATCH_VL4RE8_V 0x62800007 1403 #define MASK_VL4RE8_V 0xfff0707f 1404 #define MATCH_VL4RE16_V 0x62805007 1405 #define MASK_VL4RE16_V 0xfff0707f 1406 #define MATCH_VL4RE32_V 0x62806007 1407 #define MASK_VL4RE32_V 0xfff0707f 1408 #define MATCH_VL4RE64_V 0x62807007 1409 #define MASK_VL4RE64_V 0xfff0707f 1410 #define MATCH_VL8RE8_V 0xe2800007 1411 #define MASK_VL8RE8_V 0xfff0707f 1412 #define MATCH_VL8RE16_V 0xe2805007 1413 #define MASK_VL8RE16_V 0xfff0707f 1414 #define MATCH_VL8RE32_V 0xe2806007 1415 #define MASK_VL8RE32_V 0xfff0707f 1416 #define MATCH_VL8RE64_V 0xe2807007 1417 #define MASK_VL8RE64_V 0xfff0707f 1418 #define MATCH_VS1R_V 0x2800027 1419 #define MASK_VS1R_V 0xfff0707f 1420 #define MATCH_VS2R_V 0x22800027 1421 #define MASK_VS2R_V 0xfff0707f 1422 #define MATCH_VS4R_V 0x62800027 1423 #define MASK_VS4R_V 0xfff0707f 1424 #define MATCH_VS8R_V 0xe2800027 1425 #define MASK_VS8R_V 0xfff0707f 1426 #define MATCH_VFADD_VF 0x5057 1427 #define MASK_VFADD_VF 0xfc00707f 1428 #define MATCH_VFSUB_VF 0x8005057 1429 #define MASK_VFSUB_VF 0xfc00707f 1430 #define MATCH_VFMIN_VF 0x10005057 1431 #define MASK_VFMIN_VF 0xfc00707f 1432 #define MATCH_VFMAX_VF 0x18005057 1433 #define MASK_VFMAX_VF 0xfc00707f 1434 #define MATCH_VFSGNJ_VF 0x20005057 1435 #define MASK_VFSGNJ_VF 0xfc00707f 1436 #define MATCH_VFSGNJN_VF 0x24005057 1437 #define MASK_VFSGNJN_VF 0xfc00707f 1438 #define MATCH_VFSGNJX_VF 0x28005057 1439 #define MASK_VFSGNJX_VF 0xfc00707f 1440 #define MATCH_VFSLIDE1UP_VF 0x38005057 1441 #define MASK_VFSLIDE1UP_VF 0xfc00707f 1442 #define MATCH_VFSLIDE1DOWN_VF 0x3c005057 1443 #define MASK_VFSLIDE1DOWN_VF 0xfc00707f 1444 #define MATCH_VFMV_S_F 0x42005057 1445 #define MASK_VFMV_S_F 0xfff0707f 1446 #define MATCH_VFMERGE_VFM 0x5c005057 1447 #define MASK_VFMERGE_VFM 0xfe00707f 1448 #define MATCH_VFMV_V_F 0x5e005057 1449 #define MASK_VFMV_V_F 0xfff0707f 1450 #define MATCH_VMFEQ_VF 0x60005057 1451 #define MASK_VMFEQ_VF 0xfc00707f 1452 #define MATCH_VMFLE_VF 0x64005057 1453 #define MASK_VMFLE_VF 0xfc00707f 1454 #define MATCH_VMFLT_VF 0x6c005057 1455 #define MASK_VMFLT_VF 0xfc00707f 1456 #define MATCH_VMFNE_VF 0x70005057 1457 #define MASK_VMFNE_VF 0xfc00707f 1458 #define MATCH_VMFGT_VF 0x74005057 1459 #define MASK_VMFGT_VF 0xfc00707f 1460 #define MATCH_VMFGE_VF 0x7c005057 1461 #define MASK_VMFGE_VF 0xfc00707f 1462 #define MATCH_VFDIV_VF 0x80005057 1463 #define MASK_VFDIV_VF 0xfc00707f 1464 #define MATCH_VFRDIV_VF 0x84005057 1465 #define MASK_VFRDIV_VF 0xfc00707f 1466 #define MATCH_VFMUL_VF 0x90005057 1467 #define MASK_VFMUL_VF 0xfc00707f 1468 #define MATCH_VFRSUB_VF 0x9c005057 1469 #define MASK_VFRSUB_VF 0xfc00707f 1470 #define MATCH_VFMADD_VF 0xa0005057 1471 #define MASK_VFMADD_VF 0xfc00707f 1472 #define MATCH_VFNMADD_VF 0xa4005057 1473 #define MASK_VFNMADD_VF 0xfc00707f 1474 #define MATCH_VFMSUB_VF 0xa8005057 1475 #define MASK_VFMSUB_VF 0xfc00707f 1476 #define MATCH_VFNMSUB_VF 0xac005057 1477 #define MASK_VFNMSUB_VF 0xfc00707f 1478 #define MATCH_VFMACC_VF 0xb0005057 1479 #define MASK_VFMACC_VF 0xfc00707f 1480 #define MATCH_VFNMACC_VF 0xb4005057 1481 #define MASK_VFNMACC_VF 0xfc00707f 1482 #define MATCH_VFMSAC_VF 0xb8005057 1483 #define MASK_VFMSAC_VF 0xfc00707f 1484 #define MATCH_VFNMSAC_VF 0xbc005057 1485 #define MASK_VFNMSAC_VF 0xfc00707f 1486 #define MATCH_VFWADD_VF 0xc0005057 1487 #define MASK_VFWADD_VF 0xfc00707f 1488 #define MATCH_VFWSUB_VF 0xc8005057 1489 #define MASK_VFWSUB_VF 0xfc00707f 1490 #define MATCH_VFWADD_WF 0xd0005057 1491 #define MASK_VFWADD_WF 0xfc00707f 1492 #define MATCH_VFWSUB_WF 0xd8005057 1493 #define MASK_VFWSUB_WF 0xfc00707f 1494 #define MATCH_VFWMUL_VF 0xe0005057 1495 #define MASK_VFWMUL_VF 0xfc00707f 1496 #define MATCH_VFWMACC_VF 0xf0005057 1497 #define MASK_VFWMACC_VF 0xfc00707f 1498 #define MATCH_VFWNMACC_VF 0xf4005057 1499 #define MASK_VFWNMACC_VF 0xfc00707f 1500 #define MATCH_VFWMSAC_VF 0xf8005057 1501 #define MASK_VFWMSAC_VF 0xfc00707f 1502 #define MATCH_VFWNMSAC_VF 0xfc005057 1503 #define MASK_VFWNMSAC_VF 0xfc00707f 1504 #define MATCH_VFADD_VV 0x1057 1505 #define MASK_VFADD_VV 0xfc00707f 1506 #define MATCH_VFREDUSUM_VS 0x4001057 1507 #define MASK_VFREDUSUM_VS 0xfc00707f 1508 #define MATCH_VFSUB_VV 0x8001057 1509 #define MASK_VFSUB_VV 0xfc00707f 1510 #define MATCH_VFREDOSUM_VS 0xc001057 1511 #define MASK_VFREDOSUM_VS 0xfc00707f 1512 #define MATCH_VFMIN_VV 0x10001057 1513 #define MASK_VFMIN_VV 0xfc00707f 1514 #define MATCH_VFREDMIN_VS 0x14001057 1515 #define MASK_VFREDMIN_VS 0xfc00707f 1516 #define MATCH_VFMAX_VV 0x18001057 1517 #define MASK_VFMAX_VV 0xfc00707f 1518 #define MATCH_VFREDMAX_VS 0x1c001057 1519 #define MASK_VFREDMAX_VS 0xfc00707f 1520 #define MATCH_VFSGNJ_VV 0x20001057 1521 #define MASK_VFSGNJ_VV 0xfc00707f 1522 #define MATCH_VFSGNJN_VV 0x24001057 1523 #define MASK_VFSGNJN_VV 0xfc00707f 1524 #define MATCH_VFSGNJX_VV 0x28001057 1525 #define MASK_VFSGNJX_VV 0xfc00707f 1526 #define MATCH_VFMV_F_S 0x42001057 1527 #define MASK_VFMV_F_S 0xfe0ff07f 1528 #define MATCH_VMFEQ_VV 0x60001057 1529 #define MASK_VMFEQ_VV 0xfc00707f 1530 #define MATCH_VMFLE_VV 0x64001057 1531 #define MASK_VMFLE_VV 0xfc00707f 1532 #define MATCH_VMFLT_VV 0x6c001057 1533 #define MASK_VMFLT_VV 0xfc00707f 1534 #define MATCH_VMFNE_VV 0x70001057 1535 #define MASK_VMFNE_VV 0xfc00707f 1536 #define MATCH_VFDIV_VV 0x80001057 1537 #define MASK_VFDIV_VV 0xfc00707f 1538 #define MATCH_VFMUL_VV 0x90001057 1539 #define MASK_VFMUL_VV 0xfc00707f 1540 #define MATCH_VFMADD_VV 0xa0001057 1541 #define MASK_VFMADD_VV 0xfc00707f 1542 #define MATCH_VFNMADD_VV 0xa4001057 1543 #define MASK_VFNMADD_VV 0xfc00707f 1544 #define MATCH_VFMSUB_VV 0xa8001057 1545 #define MASK_VFMSUB_VV 0xfc00707f 1546 #define MATCH_VFNMSUB_VV 0xac001057 1547 #define MASK_VFNMSUB_VV 0xfc00707f 1548 #define MATCH_VFMACC_VV 0xb0001057 1549 #define MASK_VFMACC_VV 0xfc00707f 1550 #define MATCH_VFNMACC_VV 0xb4001057 1551 #define MASK_VFNMACC_VV 0xfc00707f 1552 #define MATCH_VFMSAC_VV 0xb8001057 1553 #define MASK_VFMSAC_VV 0xfc00707f 1554 #define MATCH_VFNMSAC_VV 0xbc001057 1555 #define MASK_VFNMSAC_VV 0xfc00707f 1556 #define MATCH_VFCVT_XU_F_V 0x48001057 1557 #define MASK_VFCVT_XU_F_V 0xfc0ff07f 1558 #define MATCH_VFCVT_X_F_V 0x48009057 1559 #define MASK_VFCVT_X_F_V 0xfc0ff07f 1560 #define MATCH_VFCVT_F_XU_V 0x48011057 1561 #define MASK_VFCVT_F_XU_V 0xfc0ff07f 1562 #define MATCH_VFCVT_F_X_V 0x48019057 1563 #define MASK_VFCVT_F_X_V 0xfc0ff07f 1564 #define MATCH_VFCVT_RTZ_XU_F_V 0x48031057 1565 #define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f 1566 #define MATCH_VFCVT_RTZ_X_F_V 0x48039057 1567 #define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f 1568 #define MATCH_VFWCVT_XU_F_V 0x48041057 1569 #define MASK_VFWCVT_XU_F_V 0xfc0ff07f 1570 #define MATCH_VFWCVT_X_F_V 0x48049057 1571 #define MASK_VFWCVT_X_F_V 0xfc0ff07f 1572 #define MATCH_VFWCVT_F_XU_V 0x48051057 1573 #define MASK_VFWCVT_F_XU_V 0xfc0ff07f 1574 #define MATCH_VFWCVT_F_X_V 0x48059057 1575 #define MASK_VFWCVT_F_X_V 0xfc0ff07f 1576 #define MATCH_VFWCVT_F_F_V 0x48061057 1577 #define MASK_VFWCVT_F_F_V 0xfc0ff07f 1578 #define MATCH_VFWCVT_RTZ_XU_F_V 0x48071057 1579 #define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f 1580 #define MATCH_VFWCVT_RTZ_X_F_V 0x48079057 1581 #define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f 1582 #define MATCH_VFNCVT_XU_F_W 0x48081057 1583 #define MASK_VFNCVT_XU_F_W 0xfc0ff07f 1584 #define MATCH_VFNCVT_X_F_W 0x48089057 1585 #define MASK_VFNCVT_X_F_W 0xfc0ff07f 1586 #define MATCH_VFNCVT_F_XU_W 0x48091057 1587 #define MASK_VFNCVT_F_XU_W 0xfc0ff07f 1588 #define MATCH_VFNCVT_F_X_W 0x48099057 1589 #define MASK_VFNCVT_F_X_W 0xfc0ff07f 1590 #define MATCH_VFNCVT_F_F_W 0x480a1057 1591 #define MASK_VFNCVT_F_F_W 0xfc0ff07f 1592 #define MATCH_VFNCVT_ROD_F_F_W 0x480a9057 1593 #define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f 1594 #define MATCH_VFNCVT_RTZ_XU_F_W 0x480b1057 1595 #define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f 1596 #define MATCH_VFNCVT_RTZ_X_F_W 0x480b9057 1597 #define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f 1598 #define MATCH_VFSQRT_V 0x4c001057 1599 #define MASK_VFSQRT_V 0xfc0ff07f 1600 #define MATCH_VFRSQRT7_V 0x4c021057 1601 #define MASK_VFRSQRT7_V 0xfc0ff07f 1602 #define MATCH_VFREC7_V 0x4c029057 1603 #define MASK_VFREC7_V 0xfc0ff07f 1604 #define MATCH_VFCLASS_V 0x4c081057 1605 #define MASK_VFCLASS_V 0xfc0ff07f 1606 #define MATCH_VFWADD_VV 0xc0001057 1607 #define MASK_VFWADD_VV 0xfc00707f 1608 #define MATCH_VFWREDUSUM_VS 0xc4001057 1609 #define MASK_VFWREDUSUM_VS 0xfc00707f 1610 #define MATCH_VFWSUB_VV 0xc8001057 1611 #define MASK_VFWSUB_VV 0xfc00707f 1612 #define MATCH_VFWREDOSUM_VS 0xcc001057 1613 #define MASK_VFWREDOSUM_VS 0xfc00707f 1614 #define MATCH_VFWADD_WV 0xd0001057 1615 #define MASK_VFWADD_WV 0xfc00707f 1616 #define MATCH_VFWSUB_WV 0xd8001057 1617 #define MASK_VFWSUB_WV 0xfc00707f 1618 #define MATCH_VFWMUL_VV 0xe0001057 1619 #define MASK_VFWMUL_VV 0xfc00707f 1620 #define MATCH_VFWMACC_VV 0xf0001057 1621 #define MASK_VFWMACC_VV 0xfc00707f 1622 #define MATCH_VFWNMACC_VV 0xf4001057 1623 #define MASK_VFWNMACC_VV 0xfc00707f 1624 #define MATCH_VFWMSAC_VV 0xf8001057 1625 #define MASK_VFWMSAC_VV 0xfc00707f 1626 #define MATCH_VFWNMSAC_VV 0xfc001057 1627 #define MASK_VFWNMSAC_VV 0xfc00707f 1628 #define MATCH_VADD_VX 0x4057 1629 #define MASK_VADD_VX 0xfc00707f 1630 #define MATCH_VSUB_VX 0x8004057 1631 #define MASK_VSUB_VX 0xfc00707f 1632 #define MATCH_VRSUB_VX 0xc004057 1633 #define MASK_VRSUB_VX 0xfc00707f 1634 #define MATCH_VMINU_VX 0x10004057 1635 #define MASK_VMINU_VX 0xfc00707f 1636 #define MATCH_VMIN_VX 0x14004057 1637 #define MASK_VMIN_VX 0xfc00707f 1638 #define MATCH_VMAXU_VX 0x18004057 1639 #define MASK_VMAXU_VX 0xfc00707f 1640 #define MATCH_VMAX_VX 0x1c004057 1641 #define MASK_VMAX_VX 0xfc00707f 1642 #define MATCH_VAND_VX 0x24004057 1643 #define MASK_VAND_VX 0xfc00707f 1644 #define MATCH_VOR_VX 0x28004057 1645 #define MASK_VOR_VX 0xfc00707f 1646 #define MATCH_VXOR_VX 0x2c004057 1647 #define MASK_VXOR_VX 0xfc00707f 1648 #define MATCH_VRGATHER_VX 0x30004057 1649 #define MASK_VRGATHER_VX 0xfc00707f 1650 #define MATCH_VSLIDEUP_VX 0x38004057 1651 #define MASK_VSLIDEUP_VX 0xfc00707f 1652 #define MATCH_VSLIDEDOWN_VX 0x3c004057 1653 #define MASK_VSLIDEDOWN_VX 0xfc00707f 1654 #define MATCH_VADC_VXM 0x40004057 1655 #define MASK_VADC_VXM 0xfe00707f 1656 #define MATCH_VMADC_VXM 0x44004057 1657 #define MASK_VMADC_VXM 0xfe00707f 1658 #define MATCH_VMADC_VX 0x46004057 1659 #define MASK_VMADC_VX 0xfe00707f 1660 #define MATCH_VSBC_VXM 0x48004057 1661 #define MASK_VSBC_VXM 0xfe00707f 1662 #define MATCH_VMSBC_VXM 0x4c004057 1663 #define MASK_VMSBC_VXM 0xfe00707f 1664 #define MATCH_VMSBC_VX 0x4e004057 1665 #define MASK_VMSBC_VX 0xfe00707f 1666 #define MATCH_VMERGE_VXM 0x5c004057 1667 #define MASK_VMERGE_VXM 0xfe00707f 1668 #define MATCH_VMV_V_X 0x5e004057 1669 #define MASK_VMV_V_X 0xfff0707f 1670 #define MATCH_VMSEQ_VX 0x60004057 1671 #define MASK_VMSEQ_VX 0xfc00707f 1672 #define MATCH_VMSNE_VX 0x64004057 1673 #define MASK_VMSNE_VX 0xfc00707f 1674 #define MATCH_VMSLTU_VX 0x68004057 1675 #define MASK_VMSLTU_VX 0xfc00707f 1676 #define MATCH_VMSLT_VX 0x6c004057 1677 #define MASK_VMSLT_VX 0xfc00707f 1678 #define MATCH_VMSLEU_VX 0x70004057 1679 #define MASK_VMSLEU_VX 0xfc00707f 1680 #define MATCH_VMSLE_VX 0x74004057 1681 #define MASK_VMSLE_VX 0xfc00707f 1682 #define MATCH_VMSGTU_VX 0x78004057 1683 #define MASK_VMSGTU_VX 0xfc00707f 1684 #define MATCH_VMSGT_VX 0x7c004057 1685 #define MASK_VMSGT_VX 0xfc00707f 1686 #define MATCH_VSADDU_VX 0x80004057 1687 #define MASK_VSADDU_VX 0xfc00707f 1688 #define MATCH_VSADD_VX 0x84004057 1689 #define MASK_VSADD_VX 0xfc00707f 1690 #define MATCH_VSSUBU_VX 0x88004057 1691 #define MASK_VSSUBU_VX 0xfc00707f 1692 #define MATCH_VSSUB_VX 0x8c004057 1693 #define MASK_VSSUB_VX 0xfc00707f 1694 #define MATCH_VSLL_VX 0x94004057 1695 #define MASK_VSLL_VX 0xfc00707f 1696 #define MATCH_VSMUL_VX 0x9c004057 1697 #define MASK_VSMUL_VX 0xfc00707f 1698 #define MATCH_VSRL_VX 0xa0004057 1699 #define MASK_VSRL_VX 0xfc00707f 1700 #define MATCH_VSRA_VX 0xa4004057 1701 #define MASK_VSRA_VX 0xfc00707f 1702 #define MATCH_VSSRL_VX 0xa8004057 1703 #define MASK_VSSRL_VX 0xfc00707f 1704 #define MATCH_VSSRA_VX 0xac004057 1705 #define MASK_VSSRA_VX 0xfc00707f 1706 #define MATCH_VNSRL_WX 0xb0004057 1707 #define MASK_VNSRL_WX 0xfc00707f 1708 #define MATCH_VNSRA_WX 0xb4004057 1709 #define MASK_VNSRA_WX 0xfc00707f 1710 #define MATCH_VNCLIPU_WX 0xb8004057 1711 #define MASK_VNCLIPU_WX 0xfc00707f 1712 #define MATCH_VNCLIP_WX 0xbc004057 1713 #define MASK_VNCLIP_WX 0xfc00707f 1714 #define MATCH_VADD_VV 0x57 1715 #define MASK_VADD_VV 0xfc00707f 1716 #define MATCH_VSUB_VV 0x8000057 1717 #define MASK_VSUB_VV 0xfc00707f 1718 #define MATCH_VMINU_VV 0x10000057 1719 #define MASK_VMINU_VV 0xfc00707f 1720 #define MATCH_VMIN_VV 0x14000057 1721 #define MASK_VMIN_VV 0xfc00707f 1722 #define MATCH_VMAXU_VV 0x18000057 1723 #define MASK_VMAXU_VV 0xfc00707f 1724 #define MATCH_VMAX_VV 0x1c000057 1725 #define MASK_VMAX_VV 0xfc00707f 1726 #define MATCH_VAND_VV 0x24000057 1727 #define MASK_VAND_VV 0xfc00707f 1728 #define MATCH_VOR_VV 0x28000057 1729 #define MASK_VOR_VV 0xfc00707f 1730 #define MATCH_VXOR_VV 0x2c000057 1731 #define MASK_VXOR_VV 0xfc00707f 1732 #define MATCH_VRGATHER_VV 0x30000057 1733 #define MASK_VRGATHER_VV 0xfc00707f 1734 #define MATCH_VRGATHEREI16_VV 0x38000057 1735 #define MASK_VRGATHEREI16_VV 0xfc00707f 1736 #define MATCH_VADC_VVM 0x40000057 1737 #define MASK_VADC_VVM 0xfe00707f 1738 #define MATCH_VMADC_VVM 0x44000057 1739 #define MASK_VMADC_VVM 0xfe00707f 1740 #define MATCH_VMADC_VV 0x46000057 1741 #define MASK_VMADC_VV 0xfe00707f 1742 #define MATCH_VSBC_VVM 0x48000057 1743 #define MASK_VSBC_VVM 0xfe00707f 1744 #define MATCH_VMSBC_VVM 0x4c000057 1745 #define MASK_VMSBC_VVM 0xfe00707f 1746 #define MATCH_VMSBC_VV 0x4e000057 1747 #define MASK_VMSBC_VV 0xfe00707f 1748 #define MATCH_VMERGE_VVM 0x5c000057 1749 #define MASK_VMERGE_VVM 0xfe00707f 1750 #define MATCH_VMV_V_V 0x5e000057 1751 #define MASK_VMV_V_V 0xfff0707f 1752 #define MATCH_VMSEQ_VV 0x60000057 1753 #define MASK_VMSEQ_VV 0xfc00707f 1754 #define MATCH_VMSNE_VV 0x64000057 1755 #define MASK_VMSNE_VV 0xfc00707f 1756 #define MATCH_VMSLTU_VV 0x68000057 1757 #define MASK_VMSLTU_VV 0xfc00707f 1758 #define MATCH_VMSLT_VV 0x6c000057 1759 #define MASK_VMSLT_VV 0xfc00707f 1760 #define MATCH_VMSLEU_VV 0x70000057 1761 #define MASK_VMSLEU_VV 0xfc00707f 1762 #define MATCH_VMSLE_VV 0x74000057 1763 #define MASK_VMSLE_VV 0xfc00707f 1764 #define MATCH_VSADDU_VV 0x80000057 1765 #define MASK_VSADDU_VV 0xfc00707f 1766 #define MATCH_VSADD_VV 0x84000057 1767 #define MASK_VSADD_VV 0xfc00707f 1768 #define MATCH_VSSUBU_VV 0x88000057 1769 #define MASK_VSSUBU_VV 0xfc00707f 1770 #define MATCH_VSSUB_VV 0x8c000057 1771 #define MASK_VSSUB_VV 0xfc00707f 1772 #define MATCH_VSLL_VV 0x94000057 1773 #define MASK_VSLL_VV 0xfc00707f 1774 #define MATCH_VSMUL_VV 0x9c000057 1775 #define MASK_VSMUL_VV 0xfc00707f 1776 #define MATCH_VSRL_VV 0xa0000057 1777 #define MASK_VSRL_VV 0xfc00707f 1778 #define MATCH_VSRA_VV 0xa4000057 1779 #define MASK_VSRA_VV 0xfc00707f 1780 #define MATCH_VSSRL_VV 0xa8000057 1781 #define MASK_VSSRL_VV 0xfc00707f 1782 #define MATCH_VSSRA_VV 0xac000057 1783 #define MASK_VSSRA_VV 0xfc00707f 1784 #define MATCH_VNSRL_WV 0xb0000057 1785 #define MASK_VNSRL_WV 0xfc00707f 1786 #define MATCH_VNSRA_WV 0xb4000057 1787 #define MASK_VNSRA_WV 0xfc00707f 1788 #define MATCH_VNCLIPU_WV 0xb8000057 1789 #define MASK_VNCLIPU_WV 0xfc00707f 1790 #define MATCH_VNCLIP_WV 0xbc000057 1791 #define MASK_VNCLIP_WV 0xfc00707f 1792 #define MATCH_VWREDSUMU_VS 0xc0000057 1793 #define MASK_VWREDSUMU_VS 0xfc00707f 1794 #define MATCH_VWREDSUM_VS 0xc4000057 1795 #define MASK_VWREDSUM_VS 0xfc00707f 1796 #define MATCH_VADD_VI 0x3057 1797 #define MASK_VADD_VI 0xfc00707f 1798 #define MATCH_VRSUB_VI 0xc003057 1799 #define MASK_VRSUB_VI 0xfc00707f 1800 #define MATCH_VAND_VI 0x24003057 1801 #define MASK_VAND_VI 0xfc00707f 1802 #define MATCH_VOR_VI 0x28003057 1803 #define MASK_VOR_VI 0xfc00707f 1804 #define MATCH_VXOR_VI 0x2c003057 1805 #define MASK_VXOR_VI 0xfc00707f 1806 #define MATCH_VRGATHER_VI 0x30003057 1807 #define MASK_VRGATHER_VI 0xfc00707f 1808 #define MATCH_VSLIDEUP_VI 0x38003057 1809 #define MASK_VSLIDEUP_VI 0xfc00707f 1810 #define MATCH_VSLIDEDOWN_VI 0x3c003057 1811 #define MASK_VSLIDEDOWN_VI 0xfc00707f 1812 #define MATCH_VADC_VIM 0x40003057 1813 #define MASK_VADC_VIM 0xfe00707f 1814 #define MATCH_VMADC_VIM 0x44003057 1815 #define MASK_VMADC_VIM 0xfe00707f 1816 #define MATCH_VMADC_VI 0x46003057 1817 #define MASK_VMADC_VI 0xfe00707f 1818 #define MATCH_VMERGE_VIM 0x5c003057 1819 #define MASK_VMERGE_VIM 0xfe00707f 1820 #define MATCH_VMV_V_I 0x5e003057 1821 #define MASK_VMV_V_I 0xfff0707f 1822 #define MATCH_VMSEQ_VI 0x60003057 1823 #define MASK_VMSEQ_VI 0xfc00707f 1824 #define MATCH_VMSNE_VI 0x64003057 1825 #define MASK_VMSNE_VI 0xfc00707f 1826 #define MATCH_VMSLEU_VI 0x70003057 1827 #define MASK_VMSLEU_VI 0xfc00707f 1828 #define MATCH_VMSLE_VI 0x74003057 1829 #define MASK_VMSLE_VI 0xfc00707f 1830 #define MATCH_VMSGTU_VI 0x78003057 1831 #define MASK_VMSGTU_VI 0xfc00707f 1832 #define MATCH_VMSGT_VI 0x7c003057 1833 #define MASK_VMSGT_VI 0xfc00707f 1834 #define MATCH_VSADDU_VI 0x80003057 1835 #define MASK_VSADDU_VI 0xfc00707f 1836 #define MATCH_VSADD_VI 0x84003057 1837 #define MASK_VSADD_VI 0xfc00707f 1838 #define MATCH_VSLL_VI 0x94003057 1839 #define MASK_VSLL_VI 0xfc00707f 1840 #define MATCH_VMV1R_V 0x9e003057 1841 #define MASK_VMV1R_V 0xfe0ff07f 1842 #define MATCH_VMV2R_V 0x9e00b057 1843 #define MASK_VMV2R_V 0xfe0ff07f 1844 #define MATCH_VMV4R_V 0x9e01b057 1845 #define MASK_VMV4R_V 0xfe0ff07f 1846 #define MATCH_VMV8R_V 0x9e03b057 1847 #define MASK_VMV8R_V 0xfe0ff07f 1848 #define MATCH_VSRL_VI 0xa0003057 1849 #define MASK_VSRL_VI 0xfc00707f 1850 #define MATCH_VSRA_VI 0xa4003057 1851 #define MASK_VSRA_VI 0xfc00707f 1852 #define MATCH_VSSRL_VI 0xa8003057 1853 #define MASK_VSSRL_VI 0xfc00707f 1854 #define MATCH_VSSRA_VI 0xac003057 1855 #define MASK_VSSRA_VI 0xfc00707f 1856 #define MATCH_VNSRL_WI 0xb0003057 1857 #define MASK_VNSRL_WI 0xfc00707f 1858 #define MATCH_VNSRA_WI 0xb4003057 1859 #define MASK_VNSRA_WI 0xfc00707f 1860 #define MATCH_VNCLIPU_WI 0xb8003057 1861 #define MASK_VNCLIPU_WI 0xfc00707f 1862 #define MATCH_VNCLIP_WI 0xbc003057 1863 #define MASK_VNCLIP_WI 0xfc00707f 1864 #define MATCH_VREDSUM_VS 0x2057 1865 #define MASK_VREDSUM_VS 0xfc00707f 1866 #define MATCH_VREDAND_VS 0x4002057 1867 #define MASK_VREDAND_VS 0xfc00707f 1868 #define MATCH_VREDOR_VS 0x8002057 1869 #define MASK_VREDOR_VS 0xfc00707f 1870 #define MATCH_VREDXOR_VS 0xc002057 1871 #define MASK_VREDXOR_VS 0xfc00707f 1872 #define MATCH_VREDMINU_VS 0x10002057 1873 #define MASK_VREDMINU_VS 0xfc00707f 1874 #define MATCH_VREDMIN_VS 0x14002057 1875 #define MASK_VREDMIN_VS 0xfc00707f 1876 #define MATCH_VREDMAXU_VS 0x18002057 1877 #define MASK_VREDMAXU_VS 0xfc00707f 1878 #define MATCH_VREDMAX_VS 0x1c002057 1879 #define MASK_VREDMAX_VS 0xfc00707f 1880 #define MATCH_VAADDU_VV 0x20002057 1881 #define MASK_VAADDU_VV 0xfc00707f 1882 #define MATCH_VAADD_VV 0x24002057 1883 #define MASK_VAADD_VV 0xfc00707f 1884 #define MATCH_VASUBU_VV 0x28002057 1885 #define MASK_VASUBU_VV 0xfc00707f 1886 #define MATCH_VASUB_VV 0x2c002057 1887 #define MASK_VASUB_VV 0xfc00707f 1888 #define MATCH_VMV_X_S 0x42002057 1889 #define MASK_VMV_X_S 0xfe0ff07f 1890 #define MATCH_VZEXT_VF8 0x48012057 1891 #define MASK_VZEXT_VF8 0xfc0ff07f 1892 #define MATCH_VSEXT_VF8 0x4801a057 1893 #define MASK_VSEXT_VF8 0xfc0ff07f 1894 #define MATCH_VZEXT_VF4 0x48022057 1895 #define MASK_VZEXT_VF4 0xfc0ff07f 1896 #define MATCH_VSEXT_VF4 0x4802a057 1897 #define MASK_VSEXT_VF4 0xfc0ff07f 1898 #define MATCH_VZEXT_VF2 0x48032057 1899 #define MASK_VZEXT_VF2 0xfc0ff07f 1900 #define MATCH_VSEXT_VF2 0x4803a057 1901 #define MASK_VSEXT_VF2 0xfc0ff07f 1902 #define MATCH_VCOMPRESS_VM 0x5e002057 1903 #define MASK_VCOMPRESS_VM 0xfe00707f 1904 #define MATCH_VMANDNOT_MM 0x60002057 1905 #define MASK_VMANDNOT_MM 0xfc00707f 1906 #define MATCH_VMAND_MM 0x64002057 1907 #define MASK_VMAND_MM 0xfc00707f 1908 #define MATCH_VMOR_MM 0x68002057 1909 #define MASK_VMOR_MM 0xfc00707f 1910 #define MATCH_VMXOR_MM 0x6c002057 1911 #define MASK_VMXOR_MM 0xfc00707f 1912 #define MATCH_VMORNOT_MM 0x70002057 1913 #define MASK_VMORNOT_MM 0xfc00707f 1914 #define MATCH_VMNAND_MM 0x74002057 1915 #define MASK_VMNAND_MM 0xfc00707f 1916 #define MATCH_VMNOR_MM 0x78002057 1917 #define MASK_VMNOR_MM 0xfc00707f 1918 #define MATCH_VMXNOR_MM 0x7c002057 1919 #define MASK_VMXNOR_MM 0xfc00707f 1920 #define MATCH_VMSBF_M 0x5000a057 1921 #define MASK_VMSBF_M 0xfc0ff07f 1922 #define MATCH_VMSOF_M 0x50012057 1923 #define MASK_VMSOF_M 0xfc0ff07f 1924 #define MATCH_VMSIF_M 0x5001a057 1925 #define MASK_VMSIF_M 0xfc0ff07f 1926 #define MATCH_VIOTA_M 0x50082057 1927 #define MASK_VIOTA_M 0xfc0ff07f 1928 #define MATCH_VID_V 0x5008a057 1929 #define MASK_VID_V 0xfdfff07f 1930 #define MATCH_VCPOP_M 0x40082057 1931 #define MASK_VCPOP_M 0xfc0ff07f 1932 #define MATCH_VFIRST_M 0x4008a057 1933 #define MASK_VFIRST_M 0xfc0ff07f 1934 #define MATCH_VDIVU_VV 0x80002057 1935 #define MASK_VDIVU_VV 0xfc00707f 1936 #define MATCH_VDIV_VV 0x84002057 1937 #define MASK_VDIV_VV 0xfc00707f 1938 #define MATCH_VREMU_VV 0x88002057 1939 #define MASK_VREMU_VV 0xfc00707f 1940 #define MATCH_VREM_VV 0x8c002057 1941 #define MASK_VREM_VV 0xfc00707f 1942 #define MATCH_VMULHU_VV 0x90002057 1943 #define MASK_VMULHU_VV 0xfc00707f 1944 #define MATCH_VMUL_VV 0x94002057 1945 #define MASK_VMUL_VV 0xfc00707f 1946 #define MATCH_VMULHSU_VV 0x98002057 1947 #define MASK_VMULHSU_VV 0xfc00707f 1948 #define MATCH_VMULH_VV 0x9c002057 1949 #define MASK_VMULH_VV 0xfc00707f 1950 #define MATCH_VMADD_VV 0xa4002057 1951 #define MASK_VMADD_VV 0xfc00707f 1952 #define MATCH_VNMSUB_VV 0xac002057 1953 #define MASK_VNMSUB_VV 0xfc00707f 1954 #define MATCH_VMACC_VV 0xb4002057 1955 #define MASK_VMACC_VV 0xfc00707f 1956 #define MATCH_VNMSAC_VV 0xbc002057 1957 #define MASK_VNMSAC_VV 0xfc00707f 1958 #define MATCH_VWADDU_VV 0xc0002057 1959 #define MASK_VWADDU_VV 0xfc00707f 1960 #define MATCH_VWADD_VV 0xc4002057 1961 #define MASK_VWADD_VV 0xfc00707f 1962 #define MATCH_VWSUBU_VV 0xc8002057 1963 #define MASK_VWSUBU_VV 0xfc00707f 1964 #define MATCH_VWSUB_VV 0xcc002057 1965 #define MASK_VWSUB_VV 0xfc00707f 1966 #define MATCH_VWADDU_WV 0xd0002057 1967 #define MASK_VWADDU_WV 0xfc00707f 1968 #define MATCH_VWADD_WV 0xd4002057 1969 #define MASK_VWADD_WV 0xfc00707f 1970 #define MATCH_VWSUBU_WV 0xd8002057 1971 #define MASK_VWSUBU_WV 0xfc00707f 1972 #define MATCH_VWSUB_WV 0xdc002057 1973 #define MASK_VWSUB_WV 0xfc00707f 1974 #define MATCH_VWMULU_VV 0xe0002057 1975 #define MASK_VWMULU_VV 0xfc00707f 1976 #define MATCH_VWMULSU_VV 0xe8002057 1977 #define MASK_VWMULSU_VV 0xfc00707f 1978 #define MATCH_VWMUL_VV 0xec002057 1979 #define MASK_VWMUL_VV 0xfc00707f 1980 #define MATCH_VWMACCU_VV 0xf0002057 1981 #define MASK_VWMACCU_VV 0xfc00707f 1982 #define MATCH_VWMACC_VV 0xf4002057 1983 #define MASK_VWMACC_VV 0xfc00707f 1984 #define MATCH_VWMACCSU_VV 0xfc002057 1985 #define MASK_VWMACCSU_VV 0xfc00707f 1986 #define MATCH_VAADDU_VX 0x20006057 1987 #define MASK_VAADDU_VX 0xfc00707f 1988 #define MATCH_VAADD_VX 0x24006057 1989 #define MASK_VAADD_VX 0xfc00707f 1990 #define MATCH_VASUBU_VX 0x28006057 1991 #define MASK_VASUBU_VX 0xfc00707f 1992 #define MATCH_VASUB_VX 0x2c006057 1993 #define MASK_VASUB_VX 0xfc00707f 1994 #define MATCH_VMV_S_X 0x42006057 1995 #define MASK_VMV_S_X 0xfff0707f 1996 #define MATCH_VSLIDE1UP_VX 0x38006057 1997 #define MASK_VSLIDE1UP_VX 0xfc00707f 1998 #define MATCH_VSLIDE1DOWN_VX 0x3c006057 1999 #define MASK_VSLIDE1DOWN_VX 0xfc00707f 2000 #define MATCH_VDIVU_VX 0x80006057 2001 #define MASK_VDIVU_VX 0xfc00707f 2002 #define MATCH_VDIV_VX 0x84006057 2003 #define MASK_VDIV_VX 0xfc00707f 2004 #define MATCH_VREMU_VX 0x88006057 2005 #define MASK_VREMU_VX 0xfc00707f 2006 #define MATCH_VREM_VX 0x8c006057 2007 #define MASK_VREM_VX 0xfc00707f 2008 #define MATCH_VMULHU_VX 0x90006057 2009 #define MASK_VMULHU_VX 0xfc00707f 2010 #define MATCH_VMUL_VX 0x94006057 2011 #define MASK_VMUL_VX 0xfc00707f 2012 #define MATCH_VMULHSU_VX 0x98006057 2013 #define MASK_VMULHSU_VX 0xfc00707f 2014 #define MATCH_VMULH_VX 0x9c006057 2015 #define MASK_VMULH_VX 0xfc00707f 2016 #define MATCH_VMADD_VX 0xa4006057 2017 #define MASK_VMADD_VX 0xfc00707f 2018 #define MATCH_VNMSUB_VX 0xac006057 2019 #define MASK_VNMSUB_VX 0xfc00707f 2020 #define MATCH_VMACC_VX 0xb4006057 2021 #define MASK_VMACC_VX 0xfc00707f 2022 #define MATCH_VNMSAC_VX 0xbc006057 2023 #define MASK_VNMSAC_VX 0xfc00707f 2024 #define MATCH_VWADDU_VX 0xc0006057 2025 #define MASK_VWADDU_VX 0xfc00707f 2026 #define MATCH_VWADD_VX 0xc4006057 2027 #define MASK_VWADD_VX 0xfc00707f 2028 #define MATCH_VWSUBU_VX 0xc8006057 2029 #define MASK_VWSUBU_VX 0xfc00707f 2030 #define MATCH_VWSUB_VX 0xcc006057 2031 #define MASK_VWSUB_VX 0xfc00707f 2032 #define MATCH_VWADDU_WX 0xd0006057 2033 #define MASK_VWADDU_WX 0xfc00707f 2034 #define MATCH_VWADD_WX 0xd4006057 2035 #define MASK_VWADD_WX 0xfc00707f 2036 #define MATCH_VWSUBU_WX 0xd8006057 2037 #define MASK_VWSUBU_WX 0xfc00707f 2038 #define MATCH_VWSUB_WX 0xdc006057 2039 #define MASK_VWSUB_WX 0xfc00707f 2040 #define MATCH_VWMULU_VX 0xe0006057 2041 #define MASK_VWMULU_VX 0xfc00707f 2042 #define MATCH_VWMULSU_VX 0xe8006057 2043 #define MASK_VWMULSU_VX 0xfc00707f 2044 #define MATCH_VWMUL_VX 0xec006057 2045 #define MASK_VWMUL_VX 0xfc00707f 2046 #define MATCH_VWMACCU_VX 0xf0006057 2047 #define MASK_VWMACCU_VX 0xfc00707f 2048 #define MATCH_VWMACC_VX 0xf4006057 2049 #define MASK_VWMACC_VX 0xfc00707f 2050 #define MATCH_VWMACCUS_VX 0xf8006057 2051 #define MASK_VWMACCUS_VX 0xfc00707f 2052 #define MATCH_VWMACCSU_VX 0xfc006057 2053 #define MASK_VWMACCSU_VX 0xfc00707f 2054 #define MATCH_VAMOSWAPEI8_V 0x800002f 2055 #define MASK_VAMOSWAPEI8_V 0xf800707f 2056 #define MATCH_VAMOADDEI8_V 0x2f 2057 #define MASK_VAMOADDEI8_V 0xf800707f 2058 #define MATCH_VAMOXOREI8_V 0x2000002f 2059 #define MASK_VAMOXOREI8_V 0xf800707f 2060 #define MATCH_VAMOANDEI8_V 0x6000002f 2061 #define MASK_VAMOANDEI8_V 0xf800707f 2062 #define MATCH_VAMOOREI8_V 0x4000002f 2063 #define MASK_VAMOOREI8_V 0xf800707f 2064 #define MATCH_VAMOMINEI8_V 0x8000002f 2065 #define MASK_VAMOMINEI8_V 0xf800707f 2066 #define MATCH_VAMOMAXEI8_V 0xa000002f 2067 #define MASK_VAMOMAXEI8_V 0xf800707f 2068 #define MATCH_VAMOMINUEI8_V 0xc000002f 2069 #define MASK_VAMOMINUEI8_V 0xf800707f 2070 #define MATCH_VAMOMAXUEI8_V 0xe000002f 2071 #define MASK_VAMOMAXUEI8_V 0xf800707f 2072 #define MATCH_VAMOSWAPEI16_V 0x800502f 2073 #define MASK_VAMOSWAPEI16_V 0xf800707f 2074 #define MATCH_VAMOADDEI16_V 0x502f 2075 #define MASK_VAMOADDEI16_V 0xf800707f 2076 #define MATCH_VAMOXOREI16_V 0x2000502f 2077 #define MASK_VAMOXOREI16_V 0xf800707f 2078 #define MATCH_VAMOANDEI16_V 0x6000502f 2079 #define MASK_VAMOANDEI16_V 0xf800707f 2080 #define MATCH_VAMOOREI16_V 0x4000502f 2081 #define MASK_VAMOOREI16_V 0xf800707f 2082 #define MATCH_VAMOMINEI16_V 0x8000502f 2083 #define MASK_VAMOMINEI16_V 0xf800707f 2084 #define MATCH_VAMOMAXEI16_V 0xa000502f 2085 #define MASK_VAMOMAXEI16_V 0xf800707f 2086 #define MATCH_VAMOMINUEI16_V 0xc000502f 2087 #define MASK_VAMOMINUEI16_V 0xf800707f 2088 #define MATCH_VAMOMAXUEI16_V 0xe000502f 2089 #define MASK_VAMOMAXUEI16_V 0xf800707f 2090 #define MATCH_VAMOSWAPEI32_V 0x800602f 2091 #define MASK_VAMOSWAPEI32_V 0xf800707f 2092 #define MATCH_VAMOADDEI32_V 0x602f 2093 #define MASK_VAMOADDEI32_V 0xf800707f 2094 #define MATCH_VAMOXOREI32_V 0x2000602f 2095 #define MASK_VAMOXOREI32_V 0xf800707f 2096 #define MATCH_VAMOANDEI32_V 0x6000602f 2097 #define MASK_VAMOANDEI32_V 0xf800707f 2098 #define MATCH_VAMOOREI32_V 0x4000602f 2099 #define MASK_VAMOOREI32_V 0xf800707f 2100 #define MATCH_VAMOMINEI32_V 0x8000602f 2101 #define MASK_VAMOMINEI32_V 0xf800707f 2102 #define MATCH_VAMOMAXEI32_V 0xa000602f 2103 #define MASK_VAMOMAXEI32_V 0xf800707f 2104 #define MATCH_VAMOMINUEI32_V 0xc000602f 2105 #define MASK_VAMOMINUEI32_V 0xf800707f 2106 #define MATCH_VAMOMAXUEI32_V 0xe000602f 2107 #define MASK_VAMOMAXUEI32_V 0xf800707f 2108 #define MATCH_VAMOSWAPEI64_V 0x800702f 2109 #define MASK_VAMOSWAPEI64_V 0xf800707f 2110 #define MATCH_VAMOADDEI64_V 0x702f 2111 #define MASK_VAMOADDEI64_V 0xf800707f 2112 #define MATCH_VAMOXOREI64_V 0x2000702f 2113 #define MASK_VAMOXOREI64_V 0xf800707f 2114 #define MATCH_VAMOANDEI64_V 0x6000702f 2115 #define MASK_VAMOANDEI64_V 0xf800707f 2116 #define MATCH_VAMOOREI64_V 0x4000702f 2117 #define MASK_VAMOOREI64_V 0xf800707f 2118 #define MATCH_VAMOMINEI64_V 0x8000702f 2119 #define MASK_VAMOMINEI64_V 0xf800707f 2120 #define MATCH_VAMOMAXEI64_V 0xa000702f 2121 #define MASK_VAMOMAXEI64_V 0xf800707f 2122 #define MATCH_VAMOMINUEI64_V 0xc000702f 2123 #define MASK_VAMOMINUEI64_V 0xf800707f 2124 #define MATCH_VAMOMAXUEI64_V 0xe000702f 2125 #define MASK_VAMOMAXUEI64_V 0xf800707f 2126 #define MATCH_ADD8 0x48000077 2127 #define MASK_ADD8 0xfe00707f 2128 #define MATCH_ADD16 0x40000077 2129 #define MASK_ADD16 0xfe00707f 2130 #define MATCH_ADD64 0xc0001077 2131 #define MASK_ADD64 0xfe00707f 2132 #define MATCH_AVE 0xe0000077 2133 #define MASK_AVE 0xfe00707f 2134 #define MATCH_BITREV 0xe6000077 2135 #define MASK_BITREV 0xfe00707f 2136 #define MATCH_BITREVI 0xe8000077 2137 #define MASK_BITREVI 0xfc00707f 2138 #define MATCH_BPICK 0x3077 2139 #define MASK_BPICK 0x600707f 2140 #define MATCH_CLRS8 0xae000077 2141 #define MASK_CLRS8 0xfff0707f 2142 #define MATCH_CLRS16 0xae800077 2143 #define MASK_CLRS16 0xfff0707f 2144 #define MATCH_CLRS32 0xaf800077 2145 #define MASK_CLRS32 0xfff0707f 2146 #define MATCH_CLO8 0xae300077 2147 #define MASK_CLO8 0xfff0707f 2148 #define MATCH_CLO16 0xaeb00077 2149 #define MASK_CLO16 0xfff0707f 2150 #define MATCH_CLO32 0xafb00077 2151 #define MASK_CLO32 0xfff0707f 2152 #define MATCH_CLZ8 0xae100077 2153 #define MASK_CLZ8 0xfff0707f 2154 #define MATCH_CLZ16 0xae900077 2155 #define MASK_CLZ16 0xfff0707f 2156 #define MATCH_CLZ32 0xaf900077 2157 #define MASK_CLZ32 0xfff0707f 2158 #define MATCH_CMPEQ8 0x4e000077 2159 #define MASK_CMPEQ8 0xfe00707f 2160 #define MATCH_CMPEQ16 0x4c000077 2161 #define MASK_CMPEQ16 0xfe00707f 2162 #define MATCH_CRAS16 0x44000077 2163 #define MASK_CRAS16 0xfe00707f 2164 #define MATCH_CRSA16 0x46000077 2165 #define MASK_CRSA16 0xfe00707f 2166 #define MATCH_INSB 0xac000077 2167 #define MASK_INSB 0xff80707f 2168 #define MATCH_KABS8 0xad000077 2169 #define MASK_KABS8 0xfff0707f 2170 #define MATCH_KABS16 0xad100077 2171 #define MASK_KABS16 0xfff0707f 2172 #define MATCH_KABSW 0xad400077 2173 #define MASK_KABSW 0xfff0707f 2174 #define MATCH_KADD8 0x18000077 2175 #define MASK_KADD8 0xfe00707f 2176 #define MATCH_KADD16 0x10000077 2177 #define MASK_KADD16 0xfe00707f 2178 #define MATCH_KADD64 0x90001077 2179 #define MASK_KADD64 0xfe00707f 2180 #define MATCH_KADDH 0x4001077 2181 #define MASK_KADDH 0xfe00707f 2182 #define MATCH_KADDW 0x1077 2183 #define MASK_KADDW 0xfe00707f 2184 #define MATCH_KCRAS16 0x14000077 2185 #define MASK_KCRAS16 0xfe00707f 2186 #define MATCH_KCRSA16 0x16000077 2187 #define MASK_KCRSA16 0xfe00707f 2188 #define MATCH_KDMBB 0xa001077 2189 #define MASK_KDMBB 0xfe00707f 2190 #define MATCH_KDMBT 0x1a001077 2191 #define MASK_KDMBT 0xfe00707f 2192 #define MATCH_KDMTT 0x2a001077 2193 #define MASK_KDMTT 0xfe00707f 2194 #define MATCH_KDMABB 0xd2001077 2195 #define MASK_KDMABB 0xfe00707f 2196 #define MATCH_KDMABT 0xe2001077 2197 #define MASK_KDMABT 0xfe00707f 2198 #define MATCH_KDMATT 0xf2001077 2199 #define MASK_KDMATT 0xfe00707f 2200 #define MATCH_KHM8 0x8e000077 2201 #define MASK_KHM8 0xfe00707f 2202 #define MATCH_KHMX8 0x9e000077 2203 #define MASK_KHMX8 0xfe00707f 2204 #define MATCH_KHM16 0x86000077 2205 #define MASK_KHM16 0xfe00707f 2206 #define MATCH_KHMX16 0x96000077 2207 #define MASK_KHMX16 0xfe00707f 2208 #define MATCH_KHMBB 0xc001077 2209 #define MASK_KHMBB 0xfe00707f 2210 #define MATCH_KHMBT 0x1c001077 2211 #define MASK_KHMBT 0xfe00707f 2212 #define MATCH_KHMTT 0x2c001077 2213 #define MASK_KHMTT 0xfe00707f 2214 #define MATCH_KMABB 0x5a001077 2215 #define MASK_KMABB 0xfe00707f 2216 #define MATCH_KMABT 0x6a001077 2217 #define MASK_KMABT 0xfe00707f 2218 #define MATCH_KMATT 0x7a001077 2219 #define MASK_KMATT 0xfe00707f 2220 #define MATCH_KMADA 0x48001077 2221 #define MASK_KMADA 0xfe00707f 2222 #define MATCH_KMAXDA 0x4a001077 2223 #define MASK_KMAXDA 0xfe00707f 2224 #define MATCH_KMADS 0x5c001077 2225 #define MASK_KMADS 0xfe00707f 2226 #define MATCH_KMADRS 0x6c001077 2227 #define MASK_KMADRS 0xfe00707f 2228 #define MATCH_KMAXDS 0x7c001077 2229 #define MASK_KMAXDS 0xfe00707f 2230 #define MATCH_KMAR64 0x94001077 2231 #define MASK_KMAR64 0xfe00707f 2232 #define MATCH_KMDA 0x38001077 2233 #define MASK_KMDA 0xfe00707f 2234 #define MATCH_KMXDA 0x3a001077 2235 #define MASK_KMXDA 0xfe00707f 2236 #define MATCH_KMMAC 0x60001077 2237 #define MASK_KMMAC 0xfe00707f 2238 #define MATCH_KMMAC_U 0x70001077 2239 #define MASK_KMMAC_U 0xfe00707f 2240 #define MATCH_KMMAWB 0x46001077 2241 #define MASK_KMMAWB 0xfe00707f 2242 #define MATCH_KMMAWB_U 0x56001077 2243 #define MASK_KMMAWB_U 0xfe00707f 2244 #define MATCH_KMMAWB2 0xce001077 2245 #define MASK_KMMAWB2 0xfe00707f 2246 #define MATCH_KMMAWB2_U 0xde001077 2247 #define MASK_KMMAWB2_U 0xfe00707f 2248 #define MATCH_KMMAWT 0x66001077 2249 #define MASK_KMMAWT 0xfe00707f 2250 #define MATCH_KMMAWT_U 0x76001077 2251 #define MASK_KMMAWT_U 0xfe00707f 2252 #define MATCH_KMMAWT2 0xee001077 2253 #define MASK_KMMAWT2 0xfe00707f 2254 #define MATCH_KMMAWT2_U 0xfe001077 2255 #define MASK_KMMAWT2_U 0xfe00707f 2256 #define MATCH_KMMSB 0x42001077 2257 #define MASK_KMMSB 0xfe00707f 2258 #define MATCH_KMMSB_U 0x52001077 2259 #define MASK_KMMSB_U 0xfe00707f 2260 #define MATCH_KMMWB2 0x8e001077 2261 #define MASK_KMMWB2 0xfe00707f 2262 #define MATCH_KMMWB2_U 0x9e001077 2263 #define MASK_KMMWB2_U 0xfe00707f 2264 #define MATCH_KMMWT2 0xae001077 2265 #define MASK_KMMWT2 0xfe00707f 2266 #define MATCH_KMMWT2_U 0xbe001077 2267 #define MASK_KMMWT2_U 0xfe00707f 2268 #define MATCH_KMSDA 0x4c001077 2269 #define MASK_KMSDA 0xfe00707f 2270 #define MATCH_KMSXDA 0x4e001077 2271 #define MASK_KMSXDA 0xfe00707f 2272 #define MATCH_KMSR64 0x96001077 2273 #define MASK_KMSR64 0xfe00707f 2274 #define MATCH_KSLLW 0x26001077 2275 #define MASK_KSLLW 0xfe00707f 2276 #define MATCH_KSLLIW 0x36001077 2277 #define MASK_KSLLIW 0xfe00707f 2278 #define MATCH_KSLL8 0x6c000077 2279 #define MASK_KSLL8 0xfe00707f 2280 #define MATCH_KSLLI8 0x7c800077 2281 #define MASK_KSLLI8 0xff80707f 2282 #define MATCH_KSLL16 0x64000077 2283 #define MASK_KSLL16 0xfe00707f 2284 #define MATCH_KSLLI16 0x75000077 2285 #define MASK_KSLLI16 0xff00707f 2286 #define MATCH_KSLRA8 0x5e000077 2287 #define MASK_KSLRA8 0xfe00707f 2288 #define MATCH_KSLRA8_U 0x6e000077 2289 #define MASK_KSLRA8_U 0xfe00707f 2290 #define MATCH_KSLRA16 0x56000077 2291 #define MASK_KSLRA16 0xfe00707f 2292 #define MATCH_KSLRA16_U 0x66000077 2293 #define MASK_KSLRA16_U 0xfe00707f 2294 #define MATCH_KSLRAW 0x6e001077 2295 #define MASK_KSLRAW 0xfe00707f 2296 #define MATCH_KSLRAW_U 0x7e001077 2297 #define MASK_KSLRAW_U 0xfe00707f 2298 #define MATCH_KSTAS16 0xc4002077 2299 #define MASK_KSTAS16 0xfe00707f 2300 #define MATCH_KSTSA16 0xc6002077 2301 #define MASK_KSTSA16 0xfe00707f 2302 #define MATCH_KSUB8 0x1a000077 2303 #define MASK_KSUB8 0xfe00707f 2304 #define MATCH_KSUB16 0x12000077 2305 #define MASK_KSUB16 0xfe00707f 2306 #define MATCH_KSUB64 0x92001077 2307 #define MASK_KSUB64 0xfe00707f 2308 #define MATCH_KSUBH 0x6001077 2309 #define MASK_KSUBH 0xfe00707f 2310 #define MATCH_KSUBW 0x2001077 2311 #define MASK_KSUBW 0xfe00707f 2312 #define MATCH_KWMMUL 0x62001077 2313 #define MASK_KWMMUL 0xfe00707f 2314 #define MATCH_KWMMUL_U 0x72001077 2315 #define MASK_KWMMUL_U 0xfe00707f 2316 #define MATCH_MADDR32 0xc4001077 2317 #define MASK_MADDR32 0xfe00707f 2318 #define MATCH_MAXW 0xf2000077 2319 #define MASK_MAXW 0xfe00707f 2320 #define MATCH_MINW 0xf0000077 2321 #define MASK_MINW 0xfe00707f 2322 #define MATCH_MSUBR32 0xc6001077 2323 #define MASK_MSUBR32 0xfe00707f 2324 #define MATCH_MULR64 0xf0001077 2325 #define MASK_MULR64 0xfe00707f 2326 #define MATCH_MULSR64 0xe0001077 2327 #define MASK_MULSR64 0xfe00707f 2328 #define MATCH_PBSAD 0xfc000077 2329 #define MASK_PBSAD 0xfe00707f 2330 #define MATCH_PBSADA 0xfe000077 2331 #define MASK_PBSADA 0xfe00707f 2332 #define MATCH_PKBB16 0xe001077 2333 #define MASK_PKBB16 0xfe00707f 2334 #define MATCH_PKBT16 0x1e001077 2335 #define MASK_PKBT16 0xfe00707f 2336 #define MATCH_PKTT16 0x2e001077 2337 #define MASK_PKTT16 0xfe00707f 2338 #define MATCH_PKTB16 0x3e001077 2339 #define MASK_PKTB16 0xfe00707f 2340 #define MATCH_RADD8 0x8000077 2341 #define MASK_RADD8 0xfe00707f 2342 #define MATCH_RADD16 0x77 2343 #define MASK_RADD16 0xfe00707f 2344 #define MATCH_RADD64 0x80001077 2345 #define MASK_RADD64 0xfe00707f 2346 #define MATCH_RADDW 0x20001077 2347 #define MASK_RADDW 0xfe00707f 2348 #define MATCH_RCRAS16 0x4000077 2349 #define MASK_RCRAS16 0xfe00707f 2350 #define MATCH_RCRSA16 0x6000077 2351 #define MASK_RCRSA16 0xfe00707f 2352 #define MATCH_RSTAS16 0xb4002077 2353 #define MASK_RSTAS16 0xfe00707f 2354 #define MATCH_RSTSA16 0xb6002077 2355 #define MASK_RSTSA16 0xfe00707f 2356 #define MATCH_RSUB8 0xa000077 2357 #define MASK_RSUB8 0xfe00707f 2358 #define MATCH_RSUB16 0x2000077 2359 #define MASK_RSUB16 0xfe00707f 2360 #define MATCH_RSUB64 0x82001077 2361 #define MASK_RSUB64 0xfe00707f 2362 #define MATCH_RSUBW 0x22001077 2363 #define MASK_RSUBW 0xfe00707f 2364 #define MATCH_SCLIP8 0x8c000077 2365 #define MASK_SCLIP8 0xff80707f 2366 #define MATCH_SCLIP16 0x84000077 2367 #define MASK_SCLIP16 0xff00707f 2368 #define MATCH_SCLIP32 0xe4000077 2369 #define MASK_SCLIP32 0xfe00707f 2370 #define MATCH_SCMPLE8 0x1e000077 2371 #define MASK_SCMPLE8 0xfe00707f 2372 #define MATCH_SCMPLE16 0x1c000077 2373 #define MASK_SCMPLE16 0xfe00707f 2374 #define MATCH_SCMPLT8 0xe000077 2375 #define MASK_SCMPLT8 0xfe00707f 2376 #define MATCH_SCMPLT16 0xc000077 2377 #define MASK_SCMPLT16 0xfe00707f 2378 #define MATCH_SLL8 0x5c000077 2379 #define MASK_SLL8 0xfe00707f 2380 #define MATCH_SLLI8 0x7c000077 2381 #define MASK_SLLI8 0xff80707f 2382 #define MATCH_SLL16 0x54000077 2383 #define MASK_SLL16 0xfe00707f 2384 #define MATCH_SLLI16 0x74000077 2385 #define MASK_SLLI16 0xff00707f 2386 #define MATCH_SMAL 0x5e001077 2387 #define MASK_SMAL 0xfe00707f 2388 #define MATCH_SMALBB 0x88001077 2389 #define MASK_SMALBB 0xfe00707f 2390 #define MATCH_SMALBT 0x98001077 2391 #define MASK_SMALBT 0xfe00707f 2392 #define MATCH_SMALTT 0xa8001077 2393 #define MASK_SMALTT 0xfe00707f 2394 #define MATCH_SMALDA 0x8c001077 2395 #define MASK_SMALDA 0xfe00707f 2396 #define MATCH_SMALXDA 0x9c001077 2397 #define MASK_SMALXDA 0xfe00707f 2398 #define MATCH_SMALDS 0x8a001077 2399 #define MASK_SMALDS 0xfe00707f 2400 #define MATCH_SMALDRS 0x9a001077 2401 #define MASK_SMALDRS 0xfe00707f 2402 #define MATCH_SMALXDS 0xaa001077 2403 #define MASK_SMALXDS 0xfe00707f 2404 #define MATCH_SMAR64 0x84001077 2405 #define MASK_SMAR64 0xfe00707f 2406 #define MATCH_SMAQA 0xc8000077 2407 #define MASK_SMAQA 0xfe00707f 2408 #define MATCH_SMAQA_SU 0xca000077 2409 #define MASK_SMAQA_SU 0xfe00707f 2410 #define MATCH_SMAX8 0x8a000077 2411 #define MASK_SMAX8 0xfe00707f 2412 #define MATCH_SMAX16 0x82000077 2413 #define MASK_SMAX16 0xfe00707f 2414 #define MATCH_SMBB16 0x8001077 2415 #define MASK_SMBB16 0xfe00707f 2416 #define MATCH_SMBT16 0x18001077 2417 #define MASK_SMBT16 0xfe00707f 2418 #define MATCH_SMTT16 0x28001077 2419 #define MASK_SMTT16 0xfe00707f 2420 #define MATCH_SMDS 0x58001077 2421 #define MASK_SMDS 0xfe00707f 2422 #define MATCH_SMDRS 0x68001077 2423 #define MASK_SMDRS 0xfe00707f 2424 #define MATCH_SMXDS 0x78001077 2425 #define MASK_SMXDS 0xfe00707f 2426 #define MATCH_SMIN8 0x88000077 2427 #define MASK_SMIN8 0xfe00707f 2428 #define MATCH_SMIN16 0x80000077 2429 #define MASK_SMIN16 0xfe00707f 2430 #define MATCH_SMMUL 0x40001077 2431 #define MASK_SMMUL 0xfe00707f 2432 #define MATCH_SMMUL_U 0x50001077 2433 #define MASK_SMMUL_U 0xfe00707f 2434 #define MATCH_SMMWB 0x44001077 2435 #define MASK_SMMWB 0xfe00707f 2436 #define MATCH_SMMWB_U 0x54001077 2437 #define MASK_SMMWB_U 0xfe00707f 2438 #define MATCH_SMMWT 0x64001077 2439 #define MASK_SMMWT 0xfe00707f 2440 #define MATCH_SMMWT_U 0x74001077 2441 #define MASK_SMMWT_U 0xfe00707f 2442 #define MATCH_SMSLDA 0xac001077 2443 #define MASK_SMSLDA 0xfe00707f 2444 #define MATCH_SMSLXDA 0xbc001077 2445 #define MASK_SMSLXDA 0xfe00707f 2446 #define MATCH_SMSR64 0x86001077 2447 #define MASK_SMSR64 0xfe00707f 2448 #define MATCH_SMUL8 0xa8000077 2449 #define MASK_SMUL8 0xfe00707f 2450 #define MATCH_SMULX8 0xaa000077 2451 #define MASK_SMULX8 0xfe00707f 2452 #define MATCH_SMUL16 0xa0000077 2453 #define MASK_SMUL16 0xfe00707f 2454 #define MATCH_SMULX16 0xa2000077 2455 #define MASK_SMULX16 0xfe00707f 2456 #define MATCH_SRA_U 0x24001077 2457 #define MASK_SRA_U 0xfe00707f 2458 #define MATCH_SRAI_U 0xd4001077 2459 #define MASK_SRAI_U 0xfc00707f 2460 #define MATCH_SRA8 0x58000077 2461 #define MASK_SRA8 0xfe00707f 2462 #define MATCH_SRA8_U 0x68000077 2463 #define MASK_SRA8_U 0xfe00707f 2464 #define MATCH_SRAI8 0x78000077 2465 #define MASK_SRAI8 0xff80707f 2466 #define MATCH_SRAI8_U 0x78800077 2467 #define MASK_SRAI8_U 0xff80707f 2468 #define MATCH_SRA16 0x50000077 2469 #define MASK_SRA16 0xfe00707f 2470 #define MATCH_SRA16_U 0x60000077 2471 #define MASK_SRA16_U 0xfe00707f 2472 #define MATCH_SRAI16 0x70000077 2473 #define MASK_SRAI16 0xff00707f 2474 #define MATCH_SRAI16_U 0x71000077 2475 #define MASK_SRAI16_U 0xff00707f 2476 #define MATCH_SRL8 0x5a000077 2477 #define MASK_SRL8 0xfe00707f 2478 #define MATCH_SRL8_U 0x6a000077 2479 #define MASK_SRL8_U 0xfe00707f 2480 #define MATCH_SRLI8 0x7a000077 2481 #define MASK_SRLI8 0xff80707f 2482 #define MATCH_SRLI8_U 0x7a800077 2483 #define MASK_SRLI8_U 0xff80707f 2484 #define MATCH_SRL16 0x52000077 2485 #define MASK_SRL16 0xfe00707f 2486 #define MATCH_SRL16_U 0x62000077 2487 #define MASK_SRL16_U 0xfe00707f 2488 #define MATCH_SRLI16 0x72000077 2489 #define MASK_SRLI16 0xff00707f 2490 #define MATCH_SRLI16_U 0x73000077 2491 #define MASK_SRLI16_U 0xff00707f 2492 #define MATCH_STAS16 0xf4002077 2493 #define MASK_STAS16 0xfe00707f 2494 #define MATCH_STSA16 0xf6002077 2495 #define MASK_STSA16 0xfe00707f 2496 #define MATCH_SUB8 0x4a000077 2497 #define MASK_SUB8 0xfe00707f 2498 #define MATCH_SUB16 0x42000077 2499 #define MASK_SUB16 0xfe00707f 2500 #define MATCH_SUB64 0xc2001077 2501 #define MASK_SUB64 0xfe00707f 2502 #define MATCH_SUNPKD810 0xac800077 2503 #define MASK_SUNPKD810 0xfff0707f 2504 #define MATCH_SUNPKD820 0xac900077 2505 #define MASK_SUNPKD820 0xfff0707f 2506 #define MATCH_SUNPKD830 0xaca00077 2507 #define MASK_SUNPKD830 0xfff0707f 2508 #define MATCH_SUNPKD831 0xacb00077 2509 #define MASK_SUNPKD831 0xfff0707f 2510 #define MATCH_SUNPKD832 0xad300077 2511 #define MASK_SUNPKD832 0xfff0707f 2512 #define MATCH_SWAP8 0xad800077 2513 #define MASK_SWAP8 0xfff0707f 2514 #define MATCH_UCLIP8 0x8d000077 2515 #define MASK_UCLIP8 0xff80707f 2516 #define MATCH_UCLIP16 0x85000077 2517 #define MASK_UCLIP16 0xff00707f 2518 #define MATCH_UCLIP32 0xf4000077 2519 #define MASK_UCLIP32 0xfe00707f 2520 #define MATCH_UCMPLE8 0x3e000077 2521 #define MASK_UCMPLE8 0xfe00707f 2522 #define MATCH_UCMPLE16 0x3c000077 2523 #define MASK_UCMPLE16 0xfe00707f 2524 #define MATCH_UCMPLT8 0x2e000077 2525 #define MASK_UCMPLT8 0xfe00707f 2526 #define MATCH_UCMPLT16 0x2c000077 2527 #define MASK_UCMPLT16 0xfe00707f 2528 #define MATCH_UKADD8 0x38000077 2529 #define MASK_UKADD8 0xfe00707f 2530 #define MATCH_UKADD16 0x30000077 2531 #define MASK_UKADD16 0xfe00707f 2532 #define MATCH_UKADD64 0xb0001077 2533 #define MASK_UKADD64 0xfe00707f 2534 #define MATCH_UKADDH 0x14001077 2535 #define MASK_UKADDH 0xfe00707f 2536 #define MATCH_UKADDW 0x10001077 2537 #define MASK_UKADDW 0xfe00707f 2538 #define MATCH_UKCRAS16 0x34000077 2539 #define MASK_UKCRAS16 0xfe00707f 2540 #define MATCH_UKCRSA16 0x36000077 2541 #define MASK_UKCRSA16 0xfe00707f 2542 #define MATCH_UKMAR64 0xb4001077 2543 #define MASK_UKMAR64 0xfe00707f 2544 #define MATCH_UKMSR64 0xb6001077 2545 #define MASK_UKMSR64 0xfe00707f 2546 #define MATCH_UKSTAS16 0xe4002077 2547 #define MASK_UKSTAS16 0xfe00707f 2548 #define MATCH_UKSTSA16 0xe6002077 2549 #define MASK_UKSTSA16 0xfe00707f 2550 #define MATCH_UKSUB8 0x3a000077 2551 #define MASK_UKSUB8 0xfe00707f 2552 #define MATCH_UKSUB16 0x32000077 2553 #define MASK_UKSUB16 0xfe00707f 2554 #define MATCH_UKSUB64 0xb2001077 2555 #define MASK_UKSUB64 0xfe00707f 2556 #define MATCH_UKSUBH 0x16001077 2557 #define MASK_UKSUBH 0xfe00707f 2558 #define MATCH_UKSUBW 0x12001077 2559 #define MASK_UKSUBW 0xfe00707f 2560 #define MATCH_UMAR64 0xa4001077 2561 #define MASK_UMAR64 0xfe00707f 2562 #define MATCH_UMAQA 0xcc000077 2563 #define MASK_UMAQA 0xfe00707f 2564 #define MATCH_UMAX8 0x9a000077 2565 #define MASK_UMAX8 0xfe00707f 2566 #define MATCH_UMAX16 0x92000077 2567 #define MASK_UMAX16 0xfe00707f 2568 #define MATCH_UMIN8 0x98000077 2569 #define MASK_UMIN8 0xfe00707f 2570 #define MATCH_UMIN16 0x90000077 2571 #define MASK_UMIN16 0xfe00707f 2572 #define MATCH_UMSR64 0xa6001077 2573 #define MASK_UMSR64 0xfe00707f 2574 #define MATCH_UMUL8 0xb8000077 2575 #define MASK_UMUL8 0xfe00707f 2576 #define MATCH_UMULX8 0xba000077 2577 #define MASK_UMULX8 0xfe00707f 2578 #define MATCH_UMUL16 0xb0000077 2579 #define MASK_UMUL16 0xfe00707f 2580 #define MATCH_UMULX16 0xb2000077 2581 #define MASK_UMULX16 0xfe00707f 2582 #define MATCH_URADD8 0x28000077 2583 #define MASK_URADD8 0xfe00707f 2584 #define MATCH_URADD16 0x20000077 2585 #define MASK_URADD16 0xfe00707f 2586 #define MATCH_URADD64 0xa0001077 2587 #define MASK_URADD64 0xfe00707f 2588 #define MATCH_URADDW 0x30001077 2589 #define MASK_URADDW 0xfe00707f 2590 #define MATCH_URCRAS16 0x24000077 2591 #define MASK_URCRAS16 0xfe00707f 2592 #define MATCH_URCRSA16 0x26000077 2593 #define MASK_URCRSA16 0xfe00707f 2594 #define MATCH_URSTAS16 0xd4002077 2595 #define MASK_URSTAS16 0xfe00707f 2596 #define MATCH_URSTSA16 0xd6002077 2597 #define MASK_URSTSA16 0xfe00707f 2598 #define MATCH_URSUB8 0x2a000077 2599 #define MASK_URSUB8 0xfe00707f 2600 #define MATCH_URSUB16 0x22000077 2601 #define MASK_URSUB16 0xfe00707f 2602 #define MATCH_URSUB64 0xa2001077 2603 #define MASK_URSUB64 0xfe00707f 2604 #define MATCH_URSUBW 0x32001077 2605 #define MASK_URSUBW 0xfe00707f 2606 #define MATCH_WEXTI 0xde000077 2607 #define MASK_WEXTI 0xfe00707f 2608 #define MATCH_WEXT 0xce000077 2609 #define MASK_WEXT 0xfe00707f 2610 #define MATCH_ZUNPKD810 0xacc00077 2611 #define MASK_ZUNPKD810 0xfff0707f 2612 #define MATCH_ZUNPKD820 0xacd00077 2613 #define MASK_ZUNPKD820 0xfff0707f 2614 #define MATCH_ZUNPKD830 0xace00077 2615 #define MASK_ZUNPKD830 0xfff0707f 2616 #define MATCH_ZUNPKD831 0xacf00077 2617 #define MASK_ZUNPKD831 0xfff0707f 2618 #define MATCH_ZUNPKD832 0xad700077 2619 #define MASK_ZUNPKD832 0xfff0707f 2620 #define MATCH_ADD32 0x40002077 2621 #define MASK_ADD32 0xfe00707f 2622 #define MATCH_CRAS32 0x44002077 2623 #define MASK_CRAS32 0xfe00707f 2624 #define MATCH_CRSA32 0x46002077 2625 #define MASK_CRSA32 0xfe00707f 2626 #define MATCH_KABS32 0xad200077 2627 #define MASK_KABS32 0xfff0707f 2628 #define MATCH_KADD32 0x10002077 2629 #define MASK_KADD32 0xfe00707f 2630 #define MATCH_KCRAS32 0x14002077 2631 #define MASK_KCRAS32 0xfe00707f 2632 #define MATCH_KCRSA32 0x16002077 2633 #define MASK_KCRSA32 0xfe00707f 2634 #define MATCH_KDMBB16 0xda001077 2635 #define MASK_KDMBB16 0xfe00707f 2636 #define MATCH_KDMBT16 0xea001077 2637 #define MASK_KDMBT16 0xfe00707f 2638 #define MATCH_KDMTT16 0xfa001077 2639 #define MASK_KDMTT16 0xfe00707f 2640 #define MATCH_KDMABB16 0xd8001077 2641 #define MASK_KDMABB16 0xfe00707f 2642 #define MATCH_KDMABT16 0xe8001077 2643 #define MASK_KDMABT16 0xfe00707f 2644 #define MATCH_KDMATT16 0xf8001077 2645 #define MASK_KDMATT16 0xfe00707f 2646 #define MATCH_KHMBB16 0xdc001077 2647 #define MASK_KHMBB16 0xfe00707f 2648 #define MATCH_KHMBT16 0xec001077 2649 #define MASK_KHMBT16 0xfe00707f 2650 #define MATCH_KHMTT16 0xfc001077 2651 #define MASK_KHMTT16 0xfe00707f 2652 #define MATCH_KMABB32 0x5a002077 2653 #define MASK_KMABB32 0xfe00707f 2654 #define MATCH_KMABT32 0x6a002077 2655 #define MASK_KMABT32 0xfe00707f 2656 #define MATCH_KMATT32 0x7a002077 2657 #define MASK_KMATT32 0xfe00707f 2658 #define MATCH_KMAXDA32 0x4a002077 2659 #define MASK_KMAXDA32 0xfe00707f 2660 #define MATCH_KMDA32 0x38002077 2661 #define MASK_KMDA32 0xfe00707f 2662 #define MATCH_KMXDA32 0x3a002077 2663 #define MASK_KMXDA32 0xfe00707f 2664 #define MATCH_KMADS32 0x5c002077 2665 #define MASK_KMADS32 0xfe00707f 2666 #define MATCH_KMADRS32 0x6c002077 2667 #define MASK_KMADRS32 0xfe00707f 2668 #define MATCH_KMAXDS32 0x7c002077 2669 #define MASK_KMAXDS32 0xfe00707f 2670 #define MATCH_KMSDA32 0x4c002077 2671 #define MASK_KMSDA32 0xfe00707f 2672 #define MATCH_KMSXDA32 0x4e002077 2673 #define MASK_KMSXDA32 0xfe00707f 2674 #define MATCH_KSLL32 0x64002077 2675 #define MASK_KSLL32 0xfe00707f 2676 #define MATCH_KSLLI32 0x84002077 2677 #define MASK_KSLLI32 0xfe00707f 2678 #define MATCH_KSLRA32 0x56002077 2679 #define MASK_KSLRA32 0xfe00707f 2680 #define MATCH_KSLRA32_U 0x66002077 2681 #define MASK_KSLRA32_U 0xfe00707f 2682 #define MATCH_KSTAS32 0xc0002077 2683 #define MASK_KSTAS32 0xfe00707f 2684 #define MATCH_KSTSA32 0xc2002077 2685 #define MASK_KSTSA32 0xfe00707f 2686 #define MATCH_KSUB32 0x12002077 2687 #define MASK_KSUB32 0xfe00707f 2688 #define MATCH_PKBB32 0xe002077 2689 #define MASK_PKBB32 0xfe00707f 2690 #define MATCH_PKBT32 0x1e002077 2691 #define MASK_PKBT32 0xfe00707f 2692 #define MATCH_PKTT32 0x2e002077 2693 #define MASK_PKTT32 0xfe00707f 2694 #define MATCH_PKTB32 0x3e002077 2695 #define MASK_PKTB32 0xfe00707f 2696 #define MATCH_RADD32 0x2077 2697 #define MASK_RADD32 0xfe00707f 2698 #define MATCH_RCRAS32 0x4002077 2699 #define MASK_RCRAS32 0xfe00707f 2700 #define MATCH_RCRSA32 0x6002077 2701 #define MASK_RCRSA32 0xfe00707f 2702 #define MATCH_RSTAS32 0xb0002077 2703 #define MASK_RSTAS32 0xfe00707f 2704 #define MATCH_RSTSA32 0xb2002077 2705 #define MASK_RSTSA32 0xfe00707f 2706 #define MATCH_RSUB32 0x2002077 2707 #define MASK_RSUB32 0xfe00707f 2708 #define MATCH_SLL32 0x54002077 2709 #define MASK_SLL32 0xfe00707f 2710 #define MATCH_SLLI32 0x74002077 2711 #define MASK_SLLI32 0xfe00707f 2712 #define MATCH_SMAX32 0x92002077 2713 #define MASK_SMAX32 0xfe00707f 2714 #define MATCH_SMBT32 0x18002077 2715 #define MASK_SMBT32 0xfe00707f 2716 #define MATCH_SMTT32 0x28002077 2717 #define MASK_SMTT32 0xfe00707f 2718 #define MATCH_SMDS32 0x58002077 2719 #define MASK_SMDS32 0xfe00707f 2720 #define MATCH_SMDRS32 0x68002077 2721 #define MASK_SMDRS32 0xfe00707f 2722 #define MATCH_SMXDS32 0x78002077 2723 #define MASK_SMXDS32 0xfe00707f 2724 #define MATCH_SMIN32 0x90002077 2725 #define MASK_SMIN32 0xfe00707f 2726 #define MATCH_SRA32 0x50002077 2727 #define MASK_SRA32 0xfe00707f 2728 #define MATCH_SRA32_U 0x60002077 2729 #define MASK_SRA32_U 0xfe00707f 2730 #define MATCH_SRAI32 0x70002077 2731 #define MASK_SRAI32 0xfe00707f 2732 #define MATCH_SRAI32_U 0x80002077 2733 #define MASK_SRAI32_U 0xfe00707f 2734 #define MATCH_SRAIW_U 0x34001077 2735 #define MASK_SRAIW_U 0xfe00707f 2736 #define MATCH_SRL32 0x52002077 2737 #define MASK_SRL32 0xfe00707f 2738 #define MATCH_SRL32_U 0x62002077 2739 #define MASK_SRL32_U 0xfe00707f 2740 #define MATCH_SRLI32 0x72002077 2741 #define MASK_SRLI32 0xfe00707f 2742 #define MATCH_SRLI32_U 0x82002077 2743 #define MASK_SRLI32_U 0xfe00707f 2744 #define MATCH_STAS32 0xf0002077 2745 #define MASK_STAS32 0xfe00707f 2746 #define MATCH_STSA32 0xf2002077 2747 #define MASK_STSA32 0xfe00707f 2748 #define MATCH_SUB32 0x42002077 2749 #define MASK_SUB32 0xfe00707f 2750 #define MATCH_UKADD32 0x30002077 2751 #define MASK_UKADD32 0xfe00707f 2752 #define MATCH_UKCRAS32 0x34002077 2753 #define MASK_UKCRAS32 0xfe00707f 2754 #define MATCH_UKCRSA32 0x36002077 2755 #define MASK_UKCRSA32 0xfe00707f 2756 #define MATCH_UKSTAS32 0xe0002077 2757 #define MASK_UKSTAS32 0xfe00707f 2758 #define MATCH_UKSTSA32 0xe2002077 2759 #define MASK_UKSTSA32 0xfe00707f 2760 #define MATCH_UKSUB32 0x32002077 2761 #define MASK_UKSUB32 0xfe00707f 2762 #define MATCH_UMAX32 0xa2002077 2763 #define MASK_UMAX32 0xfe00707f 2764 #define MATCH_UMIN32 0xa0002077 2765 #define MASK_UMIN32 0xfe00707f 2766 #define MATCH_URADD32 0x20002077 2767 #define MASK_URADD32 0xfe00707f 2768 #define MATCH_URCRAS32 0x24002077 2769 #define MASK_URCRAS32 0xfe00707f 2770 #define MATCH_URCRSA32 0x26002077 2771 #define MASK_URCRSA32 0xfe00707f 2772 #define MATCH_URSTAS32 0xd0002077 2773 #define MASK_URSTAS32 0xfe00707f 2774 #define MATCH_URSTSA32 0xd2002077 2775 #define MASK_URSTSA32 0xfe00707f 2776 #define MATCH_URSUB32 0x22002077 2777 #define MASK_URSUB32 0xfe00707f 2778 #define MATCH_VMVNFR_V 0x9e003057 2779 #define MASK_VMVNFR_V 0xfe00707f 2780 #define MATCH_VL1R_V 0x2800007 2781 #define MASK_VL1R_V 0xfff0707f 2782 #define MATCH_VL2R_V 0x6805007 2783 #define MASK_VL2R_V 0xfff0707f 2784 #define MATCH_VL4R_V 0xe806007 2785 #define MASK_VL4R_V 0xfff0707f 2786 #define MATCH_VL8R_V 0x1e807007 2787 #define MASK_VL8R_V 0xfff0707f 2788 #define MATCH_VLE1_V 0x2b00007 2789 #define MASK_VLE1_V 0xfff0707f 2790 #define MATCH_VSE1_V 0x2b00027 2791 #define MASK_VSE1_V 0xfff0707f 2792 #define MATCH_VFREDSUM_VS 0x4001057 2793 #define MASK_VFREDSUM_VS 0xfc00707f 2794 #define MATCH_VFWREDSUM_VS 0xc4001057 2795 #define MASK_VFWREDSUM_VS 0xfc00707f 2796 #define MATCH_VPOPC_M 0x40082057 2797 #define MASK_VPOPC_M 0xfc0ff07f 2798 #define CSR_FFLAGS 0x1 2799 #define CSR_FRM 0x2 2800 #define CSR_FCSR 0x3 2801 #define CSR_USTATUS 0x0 2802 #define CSR_UIE 0x4 2803 #define CSR_UTVEC 0x5 2804 #define CSR_VSTART 0x8 2805 #define CSR_VXSAT 0x9 2806 #define CSR_VXRM 0xa 2807 #define CSR_VCSR 0xf 2808 #define CSR_USCRATCH 0x40 2809 #define CSR_UEPC 0x41 2810 #define CSR_UCAUSE 0x42 2811 #define CSR_UTVAL 0x43 2812 #define CSR_UIP 0x44 2813 #define CSR_CYCLE 0xc00 2814 #define CSR_TIME 0xc01 2815 #define CSR_INSTRET 0xc02 2816 #define CSR_HPMCOUNTER3 0xc03 2817 #define CSR_HPMCOUNTER4 0xc04 2818 #define CSR_HPMCOUNTER5 0xc05 2819 #define CSR_HPMCOUNTER6 0xc06 2820 #define CSR_HPMCOUNTER7 0xc07 2821 #define CSR_HPMCOUNTER8 0xc08 2822 #define CSR_HPMCOUNTER9 0xc09 2823 #define CSR_HPMCOUNTER10 0xc0a 2824 #define CSR_HPMCOUNTER11 0xc0b 2825 #define CSR_HPMCOUNTER12 0xc0c 2826 #define CSR_HPMCOUNTER13 0xc0d 2827 #define CSR_HPMCOUNTER14 0xc0e 2828 #define CSR_HPMCOUNTER15 0xc0f 2829 #define CSR_HPMCOUNTER16 0xc10 2830 #define CSR_HPMCOUNTER17 0xc11 2831 #define CSR_HPMCOUNTER18 0xc12 2832 #define CSR_HPMCOUNTER19 0xc13 2833 #define CSR_HPMCOUNTER20 0xc14 2834 #define CSR_HPMCOUNTER21 0xc15 2835 #define CSR_HPMCOUNTER22 0xc16 2836 #define CSR_HPMCOUNTER23 0xc17 2837 #define CSR_HPMCOUNTER24 0xc18 2838 #define CSR_HPMCOUNTER25 0xc19 2839 #define CSR_HPMCOUNTER26 0xc1a 2840 #define CSR_HPMCOUNTER27 0xc1b 2841 #define CSR_HPMCOUNTER28 0xc1c 2842 #define CSR_HPMCOUNTER29 0xc1d 2843 #define CSR_HPMCOUNTER30 0xc1e 2844 #define CSR_HPMCOUNTER31 0xc1f 2845 #define CSR_VL 0xc20 2846 #define CSR_VTYPE 0xc21 2847 #define CSR_VLENB 0xc22 2848 #define CSR_SSTATUS 0x100 2849 #define CSR_SEDELEG 0x102 2850 #define CSR_SIDELEG 0x103 2851 #define CSR_SIE 0x104 2852 #define CSR_STVEC 0x105 2853 #define CSR_SCOUNTEREN 0x106 2854 #define CSR_SSCRATCH 0x140 2855 #define CSR_SEPC 0x141 2856 #define CSR_SCAUSE 0x142 2857 #define CSR_STVAL 0x143 2858 #define CSR_SIP 0x144 2859 #define CSR_SATP 0x180 2860 #define CSR_VSSTATUS 0x200 2861 #define CSR_VSIE 0x204 2862 #define CSR_VSTVEC 0x205 2863 #define CSR_VSSCRATCH 0x240 2864 #define CSR_VSEPC 0x241 2865 #define CSR_VSCAUSE 0x242 2866 #define CSR_VSTVAL 0x243 2867 #define CSR_VSIP 0x244 2868 #define CSR_VSATP 0x280 2869 #define CSR_HSTATUS 0x600 2870 #define CSR_HEDELEG 0x602 2871 #define CSR_HIDELEG 0x603 2872 #define CSR_HIE 0x604 2873 #define CSR_HTIMEDELTA 0x605 2874 #define CSR_HCOUNTEREN 0x606 2875 #define CSR_HGEIE 0x607 2876 #define CSR_HTVAL 0x643 2877 #define CSR_HIP 0x644 2878 #define CSR_HVIP 0x645 2879 #define CSR_HTINST 0x64a 2880 #define CSR_HGATP 0x680 2881 #define CSR_HGEIP 0xe12 2882 #define CSR_UTVT 0x7 2883 #define CSR_UNXTI 0x45 2884 #define CSR_UINTSTATUS 0x46 2885 #define CSR_USCRATCHCSW 0x48 2886 #define CSR_USCRATCHCSWL 0x49 2887 #define CSR_STVT 0x107 2888 #define CSR_SNXTI 0x145 2889 #define CSR_SINTSTATUS 0x146 2890 #define CSR_SSCRATCHCSW 0x148 2891 #define CSR_SSCRATCHCSWL 0x149 2892 #define CSR_MTVT 0x307 2893 #define CSR_MNXTI 0x345 2894 #define CSR_MINTSTATUS 0x346 2895 #define CSR_MSCRATCHCSW 0x348 2896 #define CSR_MSCRATCHCSWL 0x349 2897 #define CSR_MSTATUS 0x300 2898 #define CSR_MISA 0x301 2899 #define CSR_MEDELEG 0x302 2900 #define CSR_MIDELEG 0x303 2901 #define CSR_MIE 0x304 2902 #define CSR_MTVEC 0x305 2903 #define CSR_MCOUNTEREN 0x306 2904 #define CSR_MCOUNTINHIBIT 0x320 2905 #define CSR_MSCRATCH 0x340 2906 #define CSR_MEPC 0x341 2907 #define CSR_MCAUSE 0x342 2908 #define CSR_MTVAL 0x343 2909 #define CSR_MIP 0x344 2910 #define CSR_MTINST 0x34a 2911 #define CSR_MTVAL2 0x34b 2912 #define CSR_PMPCFG0 0x3a0 2913 #define CSR_PMPCFG1 0x3a1 2914 #define CSR_PMPCFG2 0x3a2 2915 #define CSR_PMPCFG3 0x3a3 2916 #define CSR_PMPADDR0 0x3b0 2917 #define CSR_PMPADDR1 0x3b1 2918 #define CSR_PMPADDR2 0x3b2 2919 #define CSR_PMPADDR3 0x3b3 2920 #define CSR_PMPADDR4 0x3b4 2921 #define CSR_PMPADDR5 0x3b5 2922 #define CSR_PMPADDR6 0x3b6 2923 #define CSR_PMPADDR7 0x3b7 2924 #define CSR_PMPADDR8 0x3b8 2925 #define CSR_PMPADDR9 0x3b9 2926 #define CSR_PMPADDR10 0x3ba 2927 #define CSR_PMPADDR11 0x3bb 2928 #define CSR_PMPADDR12 0x3bc 2929 #define CSR_PMPADDR13 0x3bd 2930 #define CSR_PMPADDR14 0x3be 2931 #define CSR_PMPADDR15 0x3bf 2932 #define CSR_TSELECT 0x7a0 2933 #define CSR_TDATA1 0x7a1 2934 #define CSR_TDATA2 0x7a2 2935 #define CSR_TDATA3 0x7a3 2936 #define CSR_TINFO 0x7a4 2937 #define CSR_TCONTROL 0x7a5 2938 #define CSR_MCONTEXT 0x7a8 2939 #define CSR_SCONTEXT 0x7aa 2940 #define CSR_DCSR 0x7b0 2941 #define CSR_DPC 0x7b1 2942 #define CSR_DSCRATCH0 0x7b2 2943 #define CSR_DSCRATCH1 0x7b3 2944 #define CSR_MCYCLE 0xb00 2945 #define CSR_MINSTRET 0xb02 2946 #define CSR_MHPMCOUNTER3 0xb03 2947 #define CSR_MHPMCOUNTER4 0xb04 2948 #define CSR_MHPMCOUNTER5 0xb05 2949 #define CSR_MHPMCOUNTER6 0xb06 2950 #define CSR_MHPMCOUNTER7 0xb07 2951 #define CSR_MHPMCOUNTER8 0xb08 2952 #define CSR_MHPMCOUNTER9 0xb09 2953 #define CSR_MHPMCOUNTER10 0xb0a 2954 #define CSR_MHPMCOUNTER11 0xb0b 2955 #define CSR_MHPMCOUNTER12 0xb0c 2956 #define CSR_MHPMCOUNTER13 0xb0d 2957 #define CSR_MHPMCOUNTER14 0xb0e 2958 #define CSR_MHPMCOUNTER15 0xb0f 2959 #define CSR_MHPMCOUNTER16 0xb10 2960 #define CSR_MHPMCOUNTER17 0xb11 2961 #define CSR_MHPMCOUNTER18 0xb12 2962 #define CSR_MHPMCOUNTER19 0xb13 2963 #define CSR_MHPMCOUNTER20 0xb14 2964 #define CSR_MHPMCOUNTER21 0xb15 2965 #define CSR_MHPMCOUNTER22 0xb16 2966 #define CSR_MHPMCOUNTER23 0xb17 2967 #define CSR_MHPMCOUNTER24 0xb18 2968 #define CSR_MHPMCOUNTER25 0xb19 2969 #define CSR_MHPMCOUNTER26 0xb1a 2970 #define CSR_MHPMCOUNTER27 0xb1b 2971 #define CSR_MHPMCOUNTER28 0xb1c 2972 #define CSR_MHPMCOUNTER29 0xb1d 2973 #define CSR_MHPMCOUNTER30 0xb1e 2974 #define CSR_MHPMCOUNTER31 0xb1f 2975 #define CSR_MHPMEVENT3 0x323 2976 #define CSR_MHPMEVENT4 0x324 2977 #define CSR_MHPMEVENT5 0x325 2978 #define CSR_MHPMEVENT6 0x326 2979 #define CSR_MHPMEVENT7 0x327 2980 #define CSR_MHPMEVENT8 0x328 2981 #define CSR_MHPMEVENT9 0x329 2982 #define CSR_MHPMEVENT10 0x32a 2983 #define CSR_MHPMEVENT11 0x32b 2984 #define CSR_MHPMEVENT12 0x32c 2985 #define CSR_MHPMEVENT13 0x32d 2986 #define CSR_MHPMEVENT14 0x32e 2987 #define CSR_MHPMEVENT15 0x32f 2988 #define CSR_MHPMEVENT16 0x330 2989 #define CSR_MHPMEVENT17 0x331 2990 #define CSR_MHPMEVENT18 0x332 2991 #define CSR_MHPMEVENT19 0x333 2992 #define CSR_MHPMEVENT20 0x334 2993 #define CSR_MHPMEVENT21 0x335 2994 #define CSR_MHPMEVENT22 0x336 2995 #define CSR_MHPMEVENT23 0x337 2996 #define CSR_MHPMEVENT24 0x338 2997 #define CSR_MHPMEVENT25 0x339 2998 #define CSR_MHPMEVENT26 0x33a 2999 #define CSR_MHPMEVENT27 0x33b 3000 #define CSR_MHPMEVENT28 0x33c 3001 #define CSR_MHPMEVENT29 0x33d 3002 #define CSR_MHPMEVENT30 0x33e 3003 #define CSR_MHPMEVENT31 0x33f 3004 #define CSR_MVENDORID 0xf11 3005 #define CSR_MARCHID 0xf12 3006 #define CSR_MIMPID 0xf13 3007 #define CSR_MHARTID 0xf14 3008 #define CSR_SENTROPY 0x546 3009 #define CSR_HTIMEDELTAH 0x615 3010 #define CSR_CYCLEH 0xc80 3011 #define CSR_TIMEH 0xc81 3012 #define CSR_INSTRETH 0xc82 3013 #define CSR_HPMCOUNTER3H 0xc83 3014 #define CSR_HPMCOUNTER4H 0xc84 3015 #define CSR_HPMCOUNTER5H 0xc85 3016 #define CSR_HPMCOUNTER6H 0xc86 3017 #define CSR_HPMCOUNTER7H 0xc87 3018 #define CSR_HPMCOUNTER8H 0xc88 3019 #define CSR_HPMCOUNTER9H 0xc89 3020 #define CSR_HPMCOUNTER10H 0xc8a 3021 #define CSR_HPMCOUNTER11H 0xc8b 3022 #define CSR_HPMCOUNTER12H 0xc8c 3023 #define CSR_HPMCOUNTER13H 0xc8d 3024 #define CSR_HPMCOUNTER14H 0xc8e 3025 #define CSR_HPMCOUNTER15H 0xc8f 3026 #define CSR_HPMCOUNTER16H 0xc90 3027 #define CSR_HPMCOUNTER17H 0xc91 3028 #define CSR_HPMCOUNTER18H 0xc92 3029 #define CSR_HPMCOUNTER19H 0xc93 3030 #define CSR_HPMCOUNTER20H 0xc94 3031 #define CSR_HPMCOUNTER21H 0xc95 3032 #define CSR_HPMCOUNTER22H 0xc96 3033 #define CSR_HPMCOUNTER23H 0xc97 3034 #define CSR_HPMCOUNTER24H 0xc98 3035 #define CSR_HPMCOUNTER25H 0xc99 3036 #define CSR_HPMCOUNTER26H 0xc9a 3037 #define CSR_HPMCOUNTER27H 0xc9b 3038 #define CSR_HPMCOUNTER28H 0xc9c 3039 #define CSR_HPMCOUNTER29H 0xc9d 3040 #define CSR_HPMCOUNTER30H 0xc9e 3041 #define CSR_HPMCOUNTER31H 0xc9f 3042 #define CSR_MSTATUSH 0x310 3043 #define CSR_MCYCLEH 0xb80 3044 #define CSR_MINSTRETH 0xb82 3045 #define CSR_MHPMCOUNTER3H 0xb83 3046 #define CSR_MHPMCOUNTER4H 0xb84 3047 #define CSR_MHPMCOUNTER5H 0xb85 3048 #define CSR_MHPMCOUNTER6H 0xb86 3049 #define CSR_MHPMCOUNTER7H 0xb87 3050 #define CSR_MHPMCOUNTER8H 0xb88 3051 #define CSR_MHPMCOUNTER9H 0xb89 3052 #define CSR_MHPMCOUNTER10H 0xb8a 3053 #define CSR_MHPMCOUNTER11H 0xb8b 3054 #define CSR_MHPMCOUNTER12H 0xb8c 3055 #define CSR_MHPMCOUNTER13H 0xb8d 3056 #define CSR_MHPMCOUNTER14H 0xb8e 3057 #define CSR_MHPMCOUNTER15H 0xb8f 3058 #define CSR_MHPMCOUNTER16H 0xb90 3059 #define CSR_MHPMCOUNTER17H 0xb91 3060 #define CSR_MHPMCOUNTER18H 0xb92 3061 #define CSR_MHPMCOUNTER19H 0xb93 3062 #define CSR_MHPMCOUNTER20H 0xb94 3063 #define CSR_MHPMCOUNTER21H 0xb95 3064 #define CSR_MHPMCOUNTER22H 0xb96 3065 #define CSR_MHPMCOUNTER23H 0xb97 3066 #define CSR_MHPMCOUNTER24H 0xb98 3067 #define CSR_MHPMCOUNTER25H 0xb99 3068 #define CSR_MHPMCOUNTER26H 0xb9a 3069 #define CSR_MHPMCOUNTER27H 0xb9b 3070 #define CSR_MHPMCOUNTER28H 0xb9c 3071 #define CSR_MHPMCOUNTER29H 0xb9d 3072 #define CSR_MHPMCOUNTER30H 0xb9e 3073 #define CSR_MHPMCOUNTER31H 0xb9f 3074 #define CAUSE_MISALIGNED_FETCH 0x0 3075 #define CAUSE_FETCH_ACCESS 0x1 3076 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 3077 #define CAUSE_BREAKPOINT 0x3 3078 #define CAUSE_MISALIGNED_LOAD 0x4 3079 #define CAUSE_LOAD_ACCESS 0x5 3080 #define CAUSE_MISALIGNED_STORE 0x6 3081 #define CAUSE_STORE_ACCESS 0x7 3082 #define CAUSE_USER_ECALL 0x8 3083 #define CAUSE_SUPERVISOR_ECALL 0x9 3084 #define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa 3085 #define CAUSE_MACHINE_ECALL 0xb 3086 #define CAUSE_FETCH_PAGE_FAULT 0xc 3087 #define CAUSE_LOAD_PAGE_FAULT 0xd 3088 #define CAUSE_STORE_PAGE_FAULT 0xf 3089 #define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 3090 #define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 3091 #define CAUSE_VIRTUAL_INSTRUCTION 0x16 3092 #define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 3093 #endif 3094 #ifdef DECLARE_INSN 3095 DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) 3096 DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) 3097 DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) 3098 DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) 3099 DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) 3100 DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI) 3101 DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM) 3102 DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM) 3103 DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI) 3104 DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR) 3105 DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR) 3106 DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE) 3107 DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME) 3108 DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET) 3109 DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH) 3110 DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH) 3111 DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH) 3112 DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) 3113 DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) 3114 DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) 3115 DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) 3116 DECLARE_INSN(fence_tso, MATCH_FENCE_TSO, MASK_FENCE_TSO) 3117 DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE) 3118 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) 3119 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) 3120 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) 3121 DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) 3122 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) 3123 DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) 3124 DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) 3125 DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) 3126 DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) 3127 DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) 3128 DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) 3129 DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) 3130 DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) 3131 DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) 3132 DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) 3133 DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) 3134 DECLARE_INSN(add, MATCH_ADD, MASK_ADD) 3135 DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) 3136 DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) 3137 DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) 3138 DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) 3139 DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) 3140 DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) 3141 DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) 3142 DECLARE_INSN(or, MATCH_OR, MASK_OR) 3143 DECLARE_INSN(and, MATCH_AND, MASK_AND) 3144 DECLARE_INSN(lb, MATCH_LB, MASK_LB) 3145 DECLARE_INSN(lh, MATCH_LH, MASK_LH) 3146 DECLARE_INSN(lw, MATCH_LW, MASK_LW) 3147 DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) 3148 DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) 3149 DECLARE_INSN(sb, MATCH_SB, MASK_SB) 3150 DECLARE_INSN(sh, MATCH_SH, MASK_SH) 3151 DECLARE_INSN(sw, MATCH_SW, MASK_SW) 3152 DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) 3153 DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) 3154 DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) 3155 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) 3156 DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) 3157 DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) 3158 DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) 3159 DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) 3160 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) 3161 DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) 3162 DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) 3163 DECLARE_INSN(ld, MATCH_LD, MASK_LD) 3164 DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) 3165 DECLARE_INSN(sd, MATCH_SD, MASK_SD) 3166 DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) 3167 DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) 3168 DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) 3169 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) 3170 DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) 3171 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) 3172 DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) 3173 DECLARE_INSN(div, MATCH_DIV, MASK_DIV) 3174 DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) 3175 DECLARE_INSN(rem, MATCH_REM, MASK_REM) 3176 DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) 3177 DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) 3178 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) 3179 DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) 3180 DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) 3181 DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) 3182 DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) 3183 DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) 3184 DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) 3185 DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) 3186 DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) 3187 DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) 3188 DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) 3189 DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) 3190 DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) 3191 DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) 3192 DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) 3193 DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) 3194 DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) 3195 DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) 3196 DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) 3197 DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) 3198 DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) 3199 DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) 3200 DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) 3201 DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) 3202 DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) 3203 DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) 3204 DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA) 3205 DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA) 3206 DECLARE_INSN(hlv_b, MATCH_HLV_B, MASK_HLV_B) 3207 DECLARE_INSN(hlv_bu, MATCH_HLV_BU, MASK_HLV_BU) 3208 DECLARE_INSN(hlv_h, MATCH_HLV_H, MASK_HLV_H) 3209 DECLARE_INSN(hlv_hu, MATCH_HLV_HU, MASK_HLV_HU) 3210 DECLARE_INSN(hlvx_hu, MATCH_HLVX_HU, MASK_HLVX_HU) 3211 DECLARE_INSN(hlv_w, MATCH_HLV_W, MASK_HLV_W) 3212 DECLARE_INSN(hlvx_wu, MATCH_HLVX_WU, MASK_HLVX_WU) 3213 DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) 3214 DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) 3215 DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) 3216 DECLARE_INSN(hlv_wu, MATCH_HLV_WU, MASK_HLV_WU) 3217 DECLARE_INSN(hlv_d, MATCH_HLV_D, MASK_HLV_D) 3218 DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) 3219 DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) 3220 DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) 3221 DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) 3222 DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) 3223 DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) 3224 DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) 3225 DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) 3226 DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) 3227 DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) 3228 DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) 3229 DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) 3230 DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) 3231 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) 3232 DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) 3233 DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) 3234 DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) 3235 DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) 3236 DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) 3237 DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) 3238 DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) 3239 DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) 3240 DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) 3241 DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) 3242 DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) 3243 DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) 3244 DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) 3245 DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) 3246 DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) 3247 DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) 3248 DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) 3249 DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) 3250 DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) 3251 DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) 3252 DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) 3253 DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) 3254 DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) 3255 DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) 3256 DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) 3257 DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) 3258 DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) 3259 DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) 3260 DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) 3261 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) 3262 DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) 3263 DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) 3264 DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) 3265 DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) 3266 DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) 3267 DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) 3268 DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) 3269 DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) 3270 DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) 3271 DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) 3272 DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) 3273 DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) 3274 DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) 3275 DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) 3276 DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) 3277 DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) 3278 DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) 3279 DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) 3280 DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) 3281 DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) 3282 DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) 3283 DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) 3284 DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) 3285 DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) 3286 DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) 3287 DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) 3288 DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) 3289 DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) 3290 DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) 3291 DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) 3292 DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) 3293 DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) 3294 DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) 3295 DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) 3296 DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) 3297 DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) 3298 DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) 3299 DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) 3300 DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) 3301 DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) 3302 DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) 3303 DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) 3304 DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) 3305 DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) 3306 DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) 3307 DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) 3308 DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) 3309 DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) 3310 DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) 3311 DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) 3312 DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) 3313 DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN) 3314 DECLARE_INSN(orn, MATCH_ORN, MASK_ORN) 3315 DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR) 3316 DECLARE_INSN(slo, MATCH_SLO, MASK_SLO) 3317 DECLARE_INSN(sro, MATCH_SRO, MASK_SRO) 3318 DECLARE_INSN(rol, MATCH_ROL, MASK_ROL) 3319 DECLARE_INSN(ror, MATCH_ROR, MASK_ROR) 3320 DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR) 3321 DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) 3322 DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) 3323 DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) 3324 DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC) 3325 DECLARE_INSN(grev, MATCH_GREV, MASK_GREV) 3326 DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI) 3327 DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI) 3328 DECLARE_INSN(rori, MATCH_RORI, MASK_RORI) 3329 DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI) 3330 DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI) 3331 DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI) 3332 DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI) 3333 DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI) 3334 DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI) 3335 DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX) 3336 DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV) 3337 DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL) 3338 DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR) 3339 DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI) 3340 DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ) 3341 DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ) 3342 DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP) 3343 DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B) 3344 DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H) 3345 DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B) 3346 DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H) 3347 DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W) 3348 DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B) 3349 DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H) 3350 DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W) 3351 DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD) 3352 DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD) 3353 DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD) 3354 DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL) 3355 DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR) 3356 DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH) 3357 DECLARE_INSN(min, MATCH_MIN, MASK_MIN) 3358 DECLARE_INSN(minu, MATCH_MINU, MASK_MINU) 3359 DECLARE_INSN(max, MATCH_MAX, MASK_MAX) 3360 DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU) 3361 DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL) 3362 DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL) 3363 DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS) 3364 DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS) 3365 DECLARE_INSN(pack, MATCH_PACK, MASK_PACK) 3366 DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU) 3367 DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH) 3368 DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP) 3369 DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI) 3370 DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI) 3371 DECLARE_INSN(xperm_n, MATCH_XPERM_N, MASK_XPERM_N) 3372 DECLARE_INSN(xperm_b, MATCH_XPERM_B, MASK_XPERM_B) 3373 DECLARE_INSN(xperm_h, MATCH_XPERM_H, MASK_XPERM_H) 3374 DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP) 3375 DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D) 3376 DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D) 3377 DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR) 3378 DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR) 3379 DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW) 3380 DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW) 3381 DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW) 3382 DECLARE_INSN(srow, MATCH_SROW, MASK_SROW) 3383 DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW) 3384 DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW) 3385 DECLARE_INSN(sbclrw, MATCH_SBCLRW, MASK_SBCLRW) 3386 DECLARE_INSN(sbsetw, MATCH_SBSETW, MASK_SBSETW) 3387 DECLARE_INSN(sbinvw, MATCH_SBINVW, MASK_SBINVW) 3388 DECLARE_INSN(sbextw, MATCH_SBEXTW, MASK_SBEXTW) 3389 DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW) 3390 DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW) 3391 DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW) 3392 DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW) 3393 DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW) 3394 DECLARE_INSN(sbclriw, MATCH_SBCLRIW, MASK_SBCLRIW) 3395 DECLARE_INSN(sbsetiw, MATCH_SBSETIW, MASK_SBSETIW) 3396 DECLARE_INSN(sbinviw, MATCH_SBINVIW, MASK_SBINVIW) 3397 DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW) 3398 DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW) 3399 DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW) 3400 DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW) 3401 DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW) 3402 DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW) 3403 DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW) 3404 DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW) 3405 DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW) 3406 DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW) 3407 DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW) 3408 DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW) 3409 DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW) 3410 DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW) 3411 DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW) 3412 DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW) 3413 DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW) 3414 DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW) 3415 DECLARE_INSN(xperm_w, MATCH_XPERM_W, MASK_XPERM_W) 3416 DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) 3417 DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) 3418 DECLARE_INSN(uret, MATCH_URET, MASK_URET) 3419 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) 3420 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) 3421 DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) 3422 DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) 3423 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) 3424 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) 3425 DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) 3426 DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) 3427 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) 3428 DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) 3429 DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) 3430 DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA) 3431 DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL) 3432 DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) 3433 DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA) 3434 DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA) 3435 DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) 3436 DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H) 3437 DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H) 3438 DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H) 3439 DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H) 3440 DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H) 3441 DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H) 3442 DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H) 3443 DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H) 3444 DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S) 3445 DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H) 3446 DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H) 3447 DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H) 3448 DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H) 3449 DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H) 3450 DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H) 3451 DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H) 3452 DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H) 3453 DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H) 3454 DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W) 3455 DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU) 3456 DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X) 3457 DECLARE_INSN(flh, MATCH_FLH, MASK_FLH) 3458 DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH) 3459 DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H) 3460 DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H) 3461 DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H) 3462 DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H) 3463 DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D) 3464 DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H) 3465 DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q) 3466 DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H) 3467 DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H) 3468 DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H) 3469 DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L) 3470 DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU) 3471 DECLARE_INSN(sm4ed, MATCH_SM4ED, MASK_SM4ED) 3472 DECLARE_INSN(sm4ks, MATCH_SM4KS, MASK_SM4KS) 3473 DECLARE_INSN(sm3p0, MATCH_SM3P0, MASK_SM3P0) 3474 DECLARE_INSN(sm3p1, MATCH_SM3P1, MASK_SM3P1) 3475 DECLARE_INSN(sha256sum0, MATCH_SHA256SUM0, MASK_SHA256SUM0) 3476 DECLARE_INSN(sha256sum1, MATCH_SHA256SUM1, MASK_SHA256SUM1) 3477 DECLARE_INSN(sha256sig0, MATCH_SHA256SIG0, MASK_SHA256SIG0) 3478 DECLARE_INSN(sha256sig1, MATCH_SHA256SIG1, MASK_SHA256SIG1) 3479 DECLARE_INSN(aes32esmi, MATCH_AES32ESMI, MASK_AES32ESMI) 3480 DECLARE_INSN(aes32esi, MATCH_AES32ESI, MASK_AES32ESI) 3481 DECLARE_INSN(aes32dsmi, MATCH_AES32DSMI, MASK_AES32DSMI) 3482 DECLARE_INSN(aes32dsi, MATCH_AES32DSI, MASK_AES32DSI) 3483 DECLARE_INSN(sha512sum0r, MATCH_SHA512SUM0R, MASK_SHA512SUM0R) 3484 DECLARE_INSN(sha512sum1r, MATCH_SHA512SUM1R, MASK_SHA512SUM1R) 3485 DECLARE_INSN(sha512sig0l, MATCH_SHA512SIG0L, MASK_SHA512SIG0L) 3486 DECLARE_INSN(sha512sig0h, MATCH_SHA512SIG0H, MASK_SHA512SIG0H) 3487 DECLARE_INSN(sha512sig1l, MATCH_SHA512SIG1L, MASK_SHA512SIG1L) 3488 DECLARE_INSN(sha512sig1h, MATCH_SHA512SIG1H, MASK_SHA512SIG1H) 3489 DECLARE_INSN(aes64ks1i, MATCH_AES64KS1I, MASK_AES64KS1I) 3490 DECLARE_INSN(aes64im, MATCH_AES64IM, MASK_AES64IM) 3491 DECLARE_INSN(aes64ks2, MATCH_AES64KS2, MASK_AES64KS2) 3492 DECLARE_INSN(aes64esm, MATCH_AES64ESM, MASK_AES64ESM) 3493 DECLARE_INSN(aes64es, MATCH_AES64ES, MASK_AES64ES) 3494 DECLARE_INSN(aes64dsm, MATCH_AES64DSM, MASK_AES64DSM) 3495 DECLARE_INSN(aes64ds, MATCH_AES64DS, MASK_AES64DS) 3496 DECLARE_INSN(sha512sum0, MATCH_SHA512SUM0, MASK_SHA512SUM0) 3497 DECLARE_INSN(sha512sum1, MATCH_SHA512SUM1, MASK_SHA512SUM1) 3498 DECLARE_INSN(sha512sig0, MATCH_SHA512SIG0, MASK_SHA512SIG0) 3499 DECLARE_INSN(sha512sig1, MATCH_SHA512SIG1, MASK_SHA512SIG1) 3500 DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) 3501 DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) 3502 DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) 3503 DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) 3504 DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) 3505 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) 3506 DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) 3507 DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) 3508 DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) 3509 DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) 3510 DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) 3511 DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) 3512 DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) 3513 DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) 3514 DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) 3515 DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) 3516 DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) 3517 DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) 3518 DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) 3519 DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) 3520 DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) 3521 DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) 3522 DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) 3523 DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) 3524 DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) 3525 DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) 3526 DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) 3527 DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) 3528 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) 3529 DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) 3530 DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) 3531 DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) 3532 DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) 3533 DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) 3534 DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) 3535 DECLARE_INSN(c_srli_rv32, MATCH_C_SRLI_RV32, MASK_C_SRLI_RV32) 3536 DECLARE_INSN(c_srai_rv32, MATCH_C_SRAI_RV32, MASK_C_SRAI_RV32) 3537 DECLARE_INSN(c_slli_rv32, MATCH_C_SLLI_RV32, MASK_C_SLLI_RV32) 3538 DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) 3539 DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) 3540 DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) 3541 DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) 3542 DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) 3543 DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) 3544 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) 3545 DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) 3546 DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) 3547 DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) 3548 DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) 3549 DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) 3550 DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) 3551 DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) 3552 DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) 3553 DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) 3554 DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) 3555 DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) 3556 DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) 3557 DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) 3558 DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) 3559 DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) 3560 DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) 3561 DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) 3562 DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) 3563 DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) 3564 DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) 3565 DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) 3566 DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) 3567 DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) 3568 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) 3569 DECLARE_INSN(vsetivli, MATCH_VSETIVLI, MASK_VSETIVLI) 3570 DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI) 3571 DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) 3572 DECLARE_INSN(vlm_v, MATCH_VLM_V, MASK_VLM_V) 3573 DECLARE_INSN(vsm_v, MATCH_VSM_V, MASK_VSM_V) 3574 DECLARE_INSN(vle8_v, MATCH_VLE8_V, MASK_VLE8_V) 3575 DECLARE_INSN(vle16_v, MATCH_VLE16_V, MASK_VLE16_V) 3576 DECLARE_INSN(vle32_v, MATCH_VLE32_V, MASK_VLE32_V) 3577 DECLARE_INSN(vle64_v, MATCH_VLE64_V, MASK_VLE64_V) 3578 DECLARE_INSN(vle128_v, MATCH_VLE128_V, MASK_VLE128_V) 3579 DECLARE_INSN(vle256_v, MATCH_VLE256_V, MASK_VLE256_V) 3580 DECLARE_INSN(vle512_v, MATCH_VLE512_V, MASK_VLE512_V) 3581 DECLARE_INSN(vle1024_v, MATCH_VLE1024_V, MASK_VLE1024_V) 3582 DECLARE_INSN(vse8_v, MATCH_VSE8_V, MASK_VSE8_V) 3583 DECLARE_INSN(vse16_v, MATCH_VSE16_V, MASK_VSE16_V) 3584 DECLARE_INSN(vse32_v, MATCH_VSE32_V, MASK_VSE32_V) 3585 DECLARE_INSN(vse64_v, MATCH_VSE64_V, MASK_VSE64_V) 3586 DECLARE_INSN(vse128_v, MATCH_VSE128_V, MASK_VSE128_V) 3587 DECLARE_INSN(vse256_v, MATCH_VSE256_V, MASK_VSE256_V) 3588 DECLARE_INSN(vse512_v, MATCH_VSE512_V, MASK_VSE512_V) 3589 DECLARE_INSN(vse1024_v, MATCH_VSE1024_V, MASK_VSE1024_V) 3590 DECLARE_INSN(vluxei8_v, MATCH_VLUXEI8_V, MASK_VLUXEI8_V) 3591 DECLARE_INSN(vluxei16_v, MATCH_VLUXEI16_V, MASK_VLUXEI16_V) 3592 DECLARE_INSN(vluxei32_v, MATCH_VLUXEI32_V, MASK_VLUXEI32_V) 3593 DECLARE_INSN(vluxei64_v, MATCH_VLUXEI64_V, MASK_VLUXEI64_V) 3594 DECLARE_INSN(vluxei128_v, MATCH_VLUXEI128_V, MASK_VLUXEI128_V) 3595 DECLARE_INSN(vluxei256_v, MATCH_VLUXEI256_V, MASK_VLUXEI256_V) 3596 DECLARE_INSN(vluxei512_v, MATCH_VLUXEI512_V, MASK_VLUXEI512_V) 3597 DECLARE_INSN(vluxei1024_v, MATCH_VLUXEI1024_V, MASK_VLUXEI1024_V) 3598 DECLARE_INSN(vsuxei8_v, MATCH_VSUXEI8_V, MASK_VSUXEI8_V) 3599 DECLARE_INSN(vsuxei16_v, MATCH_VSUXEI16_V, MASK_VSUXEI16_V) 3600 DECLARE_INSN(vsuxei32_v, MATCH_VSUXEI32_V, MASK_VSUXEI32_V) 3601 DECLARE_INSN(vsuxei64_v, MATCH_VSUXEI64_V, MASK_VSUXEI64_V) 3602 DECLARE_INSN(vsuxei128_v, MATCH_VSUXEI128_V, MASK_VSUXEI128_V) 3603 DECLARE_INSN(vsuxei256_v, MATCH_VSUXEI256_V, MASK_VSUXEI256_V) 3604 DECLARE_INSN(vsuxei512_v, MATCH_VSUXEI512_V, MASK_VSUXEI512_V) 3605 DECLARE_INSN(vsuxei1024_v, MATCH_VSUXEI1024_V, MASK_VSUXEI1024_V) 3606 DECLARE_INSN(vlse8_v, MATCH_VLSE8_V, MASK_VLSE8_V) 3607 DECLARE_INSN(vlse16_v, MATCH_VLSE16_V, MASK_VLSE16_V) 3608 DECLARE_INSN(vlse32_v, MATCH_VLSE32_V, MASK_VLSE32_V) 3609 DECLARE_INSN(vlse64_v, MATCH_VLSE64_V, MASK_VLSE64_V) 3610 DECLARE_INSN(vlse128_v, MATCH_VLSE128_V, MASK_VLSE128_V) 3611 DECLARE_INSN(vlse256_v, MATCH_VLSE256_V, MASK_VLSE256_V) 3612 DECLARE_INSN(vlse512_v, MATCH_VLSE512_V, MASK_VLSE512_V) 3613 DECLARE_INSN(vlse1024_v, MATCH_VLSE1024_V, MASK_VLSE1024_V) 3614 DECLARE_INSN(vsse8_v, MATCH_VSSE8_V, MASK_VSSE8_V) 3615 DECLARE_INSN(vsse16_v, MATCH_VSSE16_V, MASK_VSSE16_V) 3616 DECLARE_INSN(vsse32_v, MATCH_VSSE32_V, MASK_VSSE32_V) 3617 DECLARE_INSN(vsse64_v, MATCH_VSSE64_V, MASK_VSSE64_V) 3618 DECLARE_INSN(vsse128_v, MATCH_VSSE128_V, MASK_VSSE128_V) 3619 DECLARE_INSN(vsse256_v, MATCH_VSSE256_V, MASK_VSSE256_V) 3620 DECLARE_INSN(vsse512_v, MATCH_VSSE512_V, MASK_VSSE512_V) 3621 DECLARE_INSN(vsse1024_v, MATCH_VSSE1024_V, MASK_VSSE1024_V) 3622 DECLARE_INSN(vloxei8_v, MATCH_VLOXEI8_V, MASK_VLOXEI8_V) 3623 DECLARE_INSN(vloxei16_v, MATCH_VLOXEI16_V, MASK_VLOXEI16_V) 3624 DECLARE_INSN(vloxei32_v, MATCH_VLOXEI32_V, MASK_VLOXEI32_V) 3625 DECLARE_INSN(vloxei64_v, MATCH_VLOXEI64_V, MASK_VLOXEI64_V) 3626 DECLARE_INSN(vloxei128_v, MATCH_VLOXEI128_V, MASK_VLOXEI128_V) 3627 DECLARE_INSN(vloxei256_v, MATCH_VLOXEI256_V, MASK_VLOXEI256_V) 3628 DECLARE_INSN(vloxei512_v, MATCH_VLOXEI512_V, MASK_VLOXEI512_V) 3629 DECLARE_INSN(vloxei1024_v, MATCH_VLOXEI1024_V, MASK_VLOXEI1024_V) 3630 DECLARE_INSN(vsoxei8_v, MATCH_VSOXEI8_V, MASK_VSOXEI8_V) 3631 DECLARE_INSN(vsoxei16_v, MATCH_VSOXEI16_V, MASK_VSOXEI16_V) 3632 DECLARE_INSN(vsoxei32_v, MATCH_VSOXEI32_V, MASK_VSOXEI32_V) 3633 DECLARE_INSN(vsoxei64_v, MATCH_VSOXEI64_V, MASK_VSOXEI64_V) 3634 DECLARE_INSN(vsoxei128_v, MATCH_VSOXEI128_V, MASK_VSOXEI128_V) 3635 DECLARE_INSN(vsoxei256_v, MATCH_VSOXEI256_V, MASK_VSOXEI256_V) 3636 DECLARE_INSN(vsoxei512_v, MATCH_VSOXEI512_V, MASK_VSOXEI512_V) 3637 DECLARE_INSN(vsoxei1024_v, MATCH_VSOXEI1024_V, MASK_VSOXEI1024_V) 3638 DECLARE_INSN(vle8ff_v, MATCH_VLE8FF_V, MASK_VLE8FF_V) 3639 DECLARE_INSN(vle16ff_v, MATCH_VLE16FF_V, MASK_VLE16FF_V) 3640 DECLARE_INSN(vle32ff_v, MATCH_VLE32FF_V, MASK_VLE32FF_V) 3641 DECLARE_INSN(vle64ff_v, MATCH_VLE64FF_V, MASK_VLE64FF_V) 3642 DECLARE_INSN(vle128ff_v, MATCH_VLE128FF_V, MASK_VLE128FF_V) 3643 DECLARE_INSN(vle256ff_v, MATCH_VLE256FF_V, MASK_VLE256FF_V) 3644 DECLARE_INSN(vle512ff_v, MATCH_VLE512FF_V, MASK_VLE512FF_V) 3645 DECLARE_INSN(vle1024ff_v, MATCH_VLE1024FF_V, MASK_VLE1024FF_V) 3646 DECLARE_INSN(vl1re8_v, MATCH_VL1RE8_V, MASK_VL1RE8_V) 3647 DECLARE_INSN(vl1re16_v, MATCH_VL1RE16_V, MASK_VL1RE16_V) 3648 DECLARE_INSN(vl1re32_v, MATCH_VL1RE32_V, MASK_VL1RE32_V) 3649 DECLARE_INSN(vl1re64_v, MATCH_VL1RE64_V, MASK_VL1RE64_V) 3650 DECLARE_INSN(vl2re8_v, MATCH_VL2RE8_V, MASK_VL2RE8_V) 3651 DECLARE_INSN(vl2re16_v, MATCH_VL2RE16_V, MASK_VL2RE16_V) 3652 DECLARE_INSN(vl2re32_v, MATCH_VL2RE32_V, MASK_VL2RE32_V) 3653 DECLARE_INSN(vl2re64_v, MATCH_VL2RE64_V, MASK_VL2RE64_V) 3654 DECLARE_INSN(vl4re8_v, MATCH_VL4RE8_V, MASK_VL4RE8_V) 3655 DECLARE_INSN(vl4re16_v, MATCH_VL4RE16_V, MASK_VL4RE16_V) 3656 DECLARE_INSN(vl4re32_v, MATCH_VL4RE32_V, MASK_VL4RE32_V) 3657 DECLARE_INSN(vl4re64_v, MATCH_VL4RE64_V, MASK_VL4RE64_V) 3658 DECLARE_INSN(vl8re8_v, MATCH_VL8RE8_V, MASK_VL8RE8_V) 3659 DECLARE_INSN(vl8re16_v, MATCH_VL8RE16_V, MASK_VL8RE16_V) 3660 DECLARE_INSN(vl8re32_v, MATCH_VL8RE32_V, MASK_VL8RE32_V) 3661 DECLARE_INSN(vl8re64_v, MATCH_VL8RE64_V, MASK_VL8RE64_V) 3662 DECLARE_INSN(vs1r_v, MATCH_VS1R_V, MASK_VS1R_V) 3663 DECLARE_INSN(vs2r_v, MATCH_VS2R_V, MASK_VS2R_V) 3664 DECLARE_INSN(vs4r_v, MATCH_VS4R_V, MASK_VS4R_V) 3665 DECLARE_INSN(vs8r_v, MATCH_VS8R_V, MASK_VS8R_V) 3666 DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF) 3667 DECLARE_INSN(vfsub_vf, MATCH_VFSUB_VF, MASK_VFSUB_VF) 3668 DECLARE_INSN(vfmin_vf, MATCH_VFMIN_VF, MASK_VFMIN_VF) 3669 DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF) 3670 DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF) 3671 DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF) 3672 DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF) 3673 DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF) 3674 DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF) 3675 DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F) 3676 DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM) 3677 DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F) 3678 DECLARE_INSN(vmfeq_vf, MATCH_VMFEQ_VF, MASK_VMFEQ_VF) 3679 DECLARE_INSN(vmfle_vf, MATCH_VMFLE_VF, MASK_VMFLE_VF) 3680 DECLARE_INSN(vmflt_vf, MATCH_VMFLT_VF, MASK_VMFLT_VF) 3681 DECLARE_INSN(vmfne_vf, MATCH_VMFNE_VF, MASK_VMFNE_VF) 3682 DECLARE_INSN(vmfgt_vf, MATCH_VMFGT_VF, MASK_VMFGT_VF) 3683 DECLARE_INSN(vmfge_vf, MATCH_VMFGE_VF, MASK_VMFGE_VF) 3684 DECLARE_INSN(vfdiv_vf, MATCH_VFDIV_VF, MASK_VFDIV_VF) 3685 DECLARE_INSN(vfrdiv_vf, MATCH_VFRDIV_VF, MASK_VFRDIV_VF) 3686 DECLARE_INSN(vfmul_vf, MATCH_VFMUL_VF, MASK_VFMUL_VF) 3687 DECLARE_INSN(vfrsub_vf, MATCH_VFRSUB_VF, MASK_VFRSUB_VF) 3688 DECLARE_INSN(vfmadd_vf, MATCH_VFMADD_VF, MASK_VFMADD_VF) 3689 DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF) 3690 DECLARE_INSN(vfmsub_vf, MATCH_VFMSUB_VF, MASK_VFMSUB_VF) 3691 DECLARE_INSN(vfnmsub_vf, MATCH_VFNMSUB_VF, MASK_VFNMSUB_VF) 3692 DECLARE_INSN(vfmacc_vf, MATCH_VFMACC_VF, MASK_VFMACC_VF) 3693 DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF) 3694 DECLARE_INSN(vfmsac_vf, MATCH_VFMSAC_VF, MASK_VFMSAC_VF) 3695 DECLARE_INSN(vfnmsac_vf, MATCH_VFNMSAC_VF, MASK_VFNMSAC_VF) 3696 DECLARE_INSN(vfwadd_vf, MATCH_VFWADD_VF, MASK_VFWADD_VF) 3697 DECLARE_INSN(vfwsub_vf, MATCH_VFWSUB_VF, MASK_VFWSUB_VF) 3698 DECLARE_INSN(vfwadd_wf, MATCH_VFWADD_WF, MASK_VFWADD_WF) 3699 DECLARE_INSN(vfwsub_wf, MATCH_VFWSUB_WF, MASK_VFWSUB_WF) 3700 DECLARE_INSN(vfwmul_vf, MATCH_VFWMUL_VF, MASK_VFWMUL_VF) 3701 DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF) 3702 DECLARE_INSN(vfwnmacc_vf, MATCH_VFWNMACC_VF, MASK_VFWNMACC_VF) 3703 DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF) 3704 DECLARE_INSN(vfwnmsac_vf, MATCH_VFWNMSAC_VF, MASK_VFWNMSAC_VF) 3705 DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV) 3706 DECLARE_INSN(vfredusum_vs, MATCH_VFREDUSUM_VS, MASK_VFREDUSUM_VS) 3707 DECLARE_INSN(vfsub_vv, MATCH_VFSUB_VV, MASK_VFSUB_VV) 3708 DECLARE_INSN(vfredosum_vs, MATCH_VFREDOSUM_VS, MASK_VFREDOSUM_VS) 3709 DECLARE_INSN(vfmin_vv, MATCH_VFMIN_VV, MASK_VFMIN_VV) 3710 DECLARE_INSN(vfredmin_vs, MATCH_VFREDMIN_VS, MASK_VFREDMIN_VS) 3711 DECLARE_INSN(vfmax_vv, MATCH_VFMAX_VV, MASK_VFMAX_VV) 3712 DECLARE_INSN(vfredmax_vs, MATCH_VFREDMAX_VS, MASK_VFREDMAX_VS) 3713 DECLARE_INSN(vfsgnj_vv, MATCH_VFSGNJ_VV, MASK_VFSGNJ_VV) 3714 DECLARE_INSN(vfsgnjn_vv, MATCH_VFSGNJN_VV, MASK_VFSGNJN_VV) 3715 DECLARE_INSN(vfsgnjx_vv, MATCH_VFSGNJX_VV, MASK_VFSGNJX_VV) 3716 DECLARE_INSN(vfmv_f_s, MATCH_VFMV_F_S, MASK_VFMV_F_S) 3717 DECLARE_INSN(vmfeq_vv, MATCH_VMFEQ_VV, MASK_VMFEQ_VV) 3718 DECLARE_INSN(vmfle_vv, MATCH_VMFLE_VV, MASK_VMFLE_VV) 3719 DECLARE_INSN(vmflt_vv, MATCH_VMFLT_VV, MASK_VMFLT_VV) 3720 DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV) 3721 DECLARE_INSN(vfdiv_vv, MATCH_VFDIV_VV, MASK_VFDIV_VV) 3722 DECLARE_INSN(vfmul_vv, MATCH_VFMUL_VV, MASK_VFMUL_VV) 3723 DECLARE_INSN(vfmadd_vv, MATCH_VFMADD_VV, MASK_VFMADD_VV) 3724 DECLARE_INSN(vfnmadd_vv, MATCH_VFNMADD_VV, MASK_VFNMADD_VV) 3725 DECLARE_INSN(vfmsub_vv, MATCH_VFMSUB_VV, MASK_VFMSUB_VV) 3726 DECLARE_INSN(vfnmsub_vv, MATCH_VFNMSUB_VV, MASK_VFNMSUB_VV) 3727 DECLARE_INSN(vfmacc_vv, MATCH_VFMACC_VV, MASK_VFMACC_VV) 3728 DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV) 3729 DECLARE_INSN(vfmsac_vv, MATCH_VFMSAC_VV, MASK_VFMSAC_VV) 3730 DECLARE_INSN(vfnmsac_vv, MATCH_VFNMSAC_VV, MASK_VFNMSAC_VV) 3731 DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V) 3732 DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V) 3733 DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V) 3734 DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V) 3735 DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V) 3736 DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V) 3737 DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V) 3738 DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V) 3739 DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V) 3740 DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V) 3741 DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V) 3742 DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V) 3743 DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V) 3744 DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W) 3745 DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W) 3746 DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W) 3747 DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W) 3748 DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W) 3749 DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W) 3750 DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) 3751 DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) 3752 DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V) 3753 DECLARE_INSN(vfrsqrt7_v, MATCH_VFRSQRT7_V, MASK_VFRSQRT7_V) 3754 DECLARE_INSN(vfrec7_v, MATCH_VFREC7_V, MASK_VFREC7_V) 3755 DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V) 3756 DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV) 3757 DECLARE_INSN(vfwredusum_vs, MATCH_VFWREDUSUM_VS, MASK_VFWREDUSUM_VS) 3758 DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV) 3759 DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS) 3760 DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV) 3761 DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV) 3762 DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV) 3763 DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV) 3764 DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV) 3765 DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV) 3766 DECLARE_INSN(vfwnmsac_vv, MATCH_VFWNMSAC_VV, MASK_VFWNMSAC_VV) 3767 DECLARE_INSN(vadd_vx, MATCH_VADD_VX, MASK_VADD_VX) 3768 DECLARE_INSN(vsub_vx, MATCH_VSUB_VX, MASK_VSUB_VX) 3769 DECLARE_INSN(vrsub_vx, MATCH_VRSUB_VX, MASK_VRSUB_VX) 3770 DECLARE_INSN(vminu_vx, MATCH_VMINU_VX, MASK_VMINU_VX) 3771 DECLARE_INSN(vmin_vx, MATCH_VMIN_VX, MASK_VMIN_VX) 3772 DECLARE_INSN(vmaxu_vx, MATCH_VMAXU_VX, MASK_VMAXU_VX) 3773 DECLARE_INSN(vmax_vx, MATCH_VMAX_VX, MASK_VMAX_VX) 3774 DECLARE_INSN(vand_vx, MATCH_VAND_VX, MASK_VAND_VX) 3775 DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX) 3776 DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX) 3777 DECLARE_INSN(vrgather_vx, MATCH_VRGATHER_VX, MASK_VRGATHER_VX) 3778 DECLARE_INSN(vslideup_vx, MATCH_VSLIDEUP_VX, MASK_VSLIDEUP_VX) 3779 DECLARE_INSN(vslidedown_vx, MATCH_VSLIDEDOWN_VX, MASK_VSLIDEDOWN_VX) 3780 DECLARE_INSN(vadc_vxm, MATCH_VADC_VXM, MASK_VADC_VXM) 3781 DECLARE_INSN(vmadc_vxm, MATCH_VMADC_VXM, MASK_VMADC_VXM) 3782 DECLARE_INSN(vmadc_vx, MATCH_VMADC_VX, MASK_VMADC_VX) 3783 DECLARE_INSN(vsbc_vxm, MATCH_VSBC_VXM, MASK_VSBC_VXM) 3784 DECLARE_INSN(vmsbc_vxm, MATCH_VMSBC_VXM, MASK_VMSBC_VXM) 3785 DECLARE_INSN(vmsbc_vx, MATCH_VMSBC_VX, MASK_VMSBC_VX) 3786 DECLARE_INSN(vmerge_vxm, MATCH_VMERGE_VXM, MASK_VMERGE_VXM) 3787 DECLARE_INSN(vmv_v_x, MATCH_VMV_V_X, MASK_VMV_V_X) 3788 DECLARE_INSN(vmseq_vx, MATCH_VMSEQ_VX, MASK_VMSEQ_VX) 3789 DECLARE_INSN(vmsne_vx, MATCH_VMSNE_VX, MASK_VMSNE_VX) 3790 DECLARE_INSN(vmsltu_vx, MATCH_VMSLTU_VX, MASK_VMSLTU_VX) 3791 DECLARE_INSN(vmslt_vx, MATCH_VMSLT_VX, MASK_VMSLT_VX) 3792 DECLARE_INSN(vmsleu_vx, MATCH_VMSLEU_VX, MASK_VMSLEU_VX) 3793 DECLARE_INSN(vmsle_vx, MATCH_VMSLE_VX, MASK_VMSLE_VX) 3794 DECLARE_INSN(vmsgtu_vx, MATCH_VMSGTU_VX, MASK_VMSGTU_VX) 3795 DECLARE_INSN(vmsgt_vx, MATCH_VMSGT_VX, MASK_VMSGT_VX) 3796 DECLARE_INSN(vsaddu_vx, MATCH_VSADDU_VX, MASK_VSADDU_VX) 3797 DECLARE_INSN(vsadd_vx, MATCH_VSADD_VX, MASK_VSADD_VX) 3798 DECLARE_INSN(vssubu_vx, MATCH_VSSUBU_VX, MASK_VSSUBU_VX) 3799 DECLARE_INSN(vssub_vx, MATCH_VSSUB_VX, MASK_VSSUB_VX) 3800 DECLARE_INSN(vsll_vx, MATCH_VSLL_VX, MASK_VSLL_VX) 3801 DECLARE_INSN(vsmul_vx, MATCH_VSMUL_VX, MASK_VSMUL_VX) 3802 DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX) 3803 DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX) 3804 DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX) 3805 DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX) 3806 DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX) 3807 DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX) 3808 DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX) 3809 DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX) 3810 DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV) 3811 DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV) 3812 DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV) 3813 DECLARE_INSN(vmin_vv, MATCH_VMIN_VV, MASK_VMIN_VV) 3814 DECLARE_INSN(vmaxu_vv, MATCH_VMAXU_VV, MASK_VMAXU_VV) 3815 DECLARE_INSN(vmax_vv, MATCH_VMAX_VV, MASK_VMAX_VV) 3816 DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV) 3817 DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV) 3818 DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV) 3819 DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV) 3820 DECLARE_INSN(vrgatherei16_vv, MATCH_VRGATHEREI16_VV, MASK_VRGATHEREI16_VV) 3821 DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM) 3822 DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM) 3823 DECLARE_INSN(vmadc_vv, MATCH_VMADC_VV, MASK_VMADC_VV) 3824 DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM) 3825 DECLARE_INSN(vmsbc_vvm, MATCH_VMSBC_VVM, MASK_VMSBC_VVM) 3826 DECLARE_INSN(vmsbc_vv, MATCH_VMSBC_VV, MASK_VMSBC_VV) 3827 DECLARE_INSN(vmerge_vvm, MATCH_VMERGE_VVM, MASK_VMERGE_VVM) 3828 DECLARE_INSN(vmv_v_v, MATCH_VMV_V_V, MASK_VMV_V_V) 3829 DECLARE_INSN(vmseq_vv, MATCH_VMSEQ_VV, MASK_VMSEQ_VV) 3830 DECLARE_INSN(vmsne_vv, MATCH_VMSNE_VV, MASK_VMSNE_VV) 3831 DECLARE_INSN(vmsltu_vv, MATCH_VMSLTU_VV, MASK_VMSLTU_VV) 3832 DECLARE_INSN(vmslt_vv, MATCH_VMSLT_VV, MASK_VMSLT_VV) 3833 DECLARE_INSN(vmsleu_vv, MATCH_VMSLEU_VV, MASK_VMSLEU_VV) 3834 DECLARE_INSN(vmsle_vv, MATCH_VMSLE_VV, MASK_VMSLE_VV) 3835 DECLARE_INSN(vsaddu_vv, MATCH_VSADDU_VV, MASK_VSADDU_VV) 3836 DECLARE_INSN(vsadd_vv, MATCH_VSADD_VV, MASK_VSADD_VV) 3837 DECLARE_INSN(vssubu_vv, MATCH_VSSUBU_VV, MASK_VSSUBU_VV) 3838 DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV) 3839 DECLARE_INSN(vsll_vv, MATCH_VSLL_VV, MASK_VSLL_VV) 3840 DECLARE_INSN(vsmul_vv, MATCH_VSMUL_VV, MASK_VSMUL_VV) 3841 DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV) 3842 DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV) 3843 DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV) 3844 DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV) 3845 DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV) 3846 DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV) 3847 DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV) 3848 DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV) 3849 DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS) 3850 DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS) 3851 DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI) 3852 DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI) 3853 DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI) 3854 DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI) 3855 DECLARE_INSN(vxor_vi, MATCH_VXOR_VI, MASK_VXOR_VI) 3856 DECLARE_INSN(vrgather_vi, MATCH_VRGATHER_VI, MASK_VRGATHER_VI) 3857 DECLARE_INSN(vslideup_vi, MATCH_VSLIDEUP_VI, MASK_VSLIDEUP_VI) 3858 DECLARE_INSN(vslidedown_vi, MATCH_VSLIDEDOWN_VI, MASK_VSLIDEDOWN_VI) 3859 DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM) 3860 DECLARE_INSN(vmadc_vim, MATCH_VMADC_VIM, MASK_VMADC_VIM) 3861 DECLARE_INSN(vmadc_vi, MATCH_VMADC_VI, MASK_VMADC_VI) 3862 DECLARE_INSN(vmerge_vim, MATCH_VMERGE_VIM, MASK_VMERGE_VIM) 3863 DECLARE_INSN(vmv_v_i, MATCH_VMV_V_I, MASK_VMV_V_I) 3864 DECLARE_INSN(vmseq_vi, MATCH_VMSEQ_VI, MASK_VMSEQ_VI) 3865 DECLARE_INSN(vmsne_vi, MATCH_VMSNE_VI, MASK_VMSNE_VI) 3866 DECLARE_INSN(vmsleu_vi, MATCH_VMSLEU_VI, MASK_VMSLEU_VI) 3867 DECLARE_INSN(vmsle_vi, MATCH_VMSLE_VI, MASK_VMSLE_VI) 3868 DECLARE_INSN(vmsgtu_vi, MATCH_VMSGTU_VI, MASK_VMSGTU_VI) 3869 DECLARE_INSN(vmsgt_vi, MATCH_VMSGT_VI, MASK_VMSGT_VI) 3870 DECLARE_INSN(vsaddu_vi, MATCH_VSADDU_VI, MASK_VSADDU_VI) 3871 DECLARE_INSN(vsadd_vi, MATCH_VSADD_VI, MASK_VSADD_VI) 3872 DECLARE_INSN(vsll_vi, MATCH_VSLL_VI, MASK_VSLL_VI) 3873 DECLARE_INSN(vmv1r_v, MATCH_VMV1R_V, MASK_VMV1R_V) 3874 DECLARE_INSN(vmv2r_v, MATCH_VMV2R_V, MASK_VMV2R_V) 3875 DECLARE_INSN(vmv4r_v, MATCH_VMV4R_V, MASK_VMV4R_V) 3876 DECLARE_INSN(vmv8r_v, MATCH_VMV8R_V, MASK_VMV8R_V) 3877 DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI) 3878 DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI) 3879 DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI) 3880 DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI) 3881 DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI) 3882 DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI) 3883 DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI) 3884 DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI) 3885 DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS) 3886 DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS) 3887 DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS) 3888 DECLARE_INSN(vredxor_vs, MATCH_VREDXOR_VS, MASK_VREDXOR_VS) 3889 DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS) 3890 DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS) 3891 DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS) 3892 DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS) 3893 DECLARE_INSN(vaaddu_vv, MATCH_VAADDU_VV, MASK_VAADDU_VV) 3894 DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV) 3895 DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV) 3896 DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV) 3897 DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S) 3898 DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8) 3899 DECLARE_INSN(vsext_vf8, MATCH_VSEXT_VF8, MASK_VSEXT_VF8) 3900 DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4) 3901 DECLARE_INSN(vsext_vf4, MATCH_VSEXT_VF4, MASK_VSEXT_VF4) 3902 DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2) 3903 DECLARE_INSN(vsext_vf2, MATCH_VSEXT_VF2, MASK_VSEXT_VF2) 3904 DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM) 3905 DECLARE_INSN(vmandnot_mm, MATCH_VMANDNOT_MM, MASK_VMANDNOT_MM) 3906 DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM) 3907 DECLARE_INSN(vmor_mm, MATCH_VMOR_MM, MASK_VMOR_MM) 3908 DECLARE_INSN(vmxor_mm, MATCH_VMXOR_MM, MASK_VMXOR_MM) 3909 DECLARE_INSN(vmornot_mm, MATCH_VMORNOT_MM, MASK_VMORNOT_MM) 3910 DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM) 3911 DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM) 3912 DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM) 3913 DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M) 3914 DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M) 3915 DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M) 3916 DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M) 3917 DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V) 3918 DECLARE_INSN(vcpop_m, MATCH_VCPOP_M, MASK_VCPOP_M) 3919 DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M) 3920 DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV) 3921 DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV) 3922 DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV) 3923 DECLARE_INSN(vrem_vv, MATCH_VREM_VV, MASK_VREM_VV) 3924 DECLARE_INSN(vmulhu_vv, MATCH_VMULHU_VV, MASK_VMULHU_VV) 3925 DECLARE_INSN(vmul_vv, MATCH_VMUL_VV, MASK_VMUL_VV) 3926 DECLARE_INSN(vmulhsu_vv, MATCH_VMULHSU_VV, MASK_VMULHSU_VV) 3927 DECLARE_INSN(vmulh_vv, MATCH_VMULH_VV, MASK_VMULH_VV) 3928 DECLARE_INSN(vmadd_vv, MATCH_VMADD_VV, MASK_VMADD_VV) 3929 DECLARE_INSN(vnmsub_vv, MATCH_VNMSUB_VV, MASK_VNMSUB_VV) 3930 DECLARE_INSN(vmacc_vv, MATCH_VMACC_VV, MASK_VMACC_VV) 3931 DECLARE_INSN(vnmsac_vv, MATCH_VNMSAC_VV, MASK_VNMSAC_VV) 3932 DECLARE_INSN(vwaddu_vv, MATCH_VWADDU_VV, MASK_VWADDU_VV) 3933 DECLARE_INSN(vwadd_vv, MATCH_VWADD_VV, MASK_VWADD_VV) 3934 DECLARE_INSN(vwsubu_vv, MATCH_VWSUBU_VV, MASK_VWSUBU_VV) 3935 DECLARE_INSN(vwsub_vv, MATCH_VWSUB_VV, MASK_VWSUB_VV) 3936 DECLARE_INSN(vwaddu_wv, MATCH_VWADDU_WV, MASK_VWADDU_WV) 3937 DECLARE_INSN(vwadd_wv, MATCH_VWADD_WV, MASK_VWADD_WV) 3938 DECLARE_INSN(vwsubu_wv, MATCH_VWSUBU_WV, MASK_VWSUBU_WV) 3939 DECLARE_INSN(vwsub_wv, MATCH_VWSUB_WV, MASK_VWSUB_WV) 3940 DECLARE_INSN(vwmulu_vv, MATCH_VWMULU_VV, MASK_VWMULU_VV) 3941 DECLARE_INSN(vwmulsu_vv, MATCH_VWMULSU_VV, MASK_VWMULSU_VV) 3942 DECLARE_INSN(vwmul_vv, MATCH_VWMUL_VV, MASK_VWMUL_VV) 3943 DECLARE_INSN(vwmaccu_vv, MATCH_VWMACCU_VV, MASK_VWMACCU_VV) 3944 DECLARE_INSN(vwmacc_vv, MATCH_VWMACC_VV, MASK_VWMACC_VV) 3945 DECLARE_INSN(vwmaccsu_vv, MATCH_VWMACCSU_VV, MASK_VWMACCSU_VV) 3946 DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX) 3947 DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX) 3948 DECLARE_INSN(vasubu_vx, MATCH_VASUBU_VX, MASK_VASUBU_VX) 3949 DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX) 3950 DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X) 3951 DECLARE_INSN(vslide1up_vx, MATCH_VSLIDE1UP_VX, MASK_VSLIDE1UP_VX) 3952 DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX) 3953 DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX) 3954 DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX) 3955 DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX) 3956 DECLARE_INSN(vrem_vx, MATCH_VREM_VX, MASK_VREM_VX) 3957 DECLARE_INSN(vmulhu_vx, MATCH_VMULHU_VX, MASK_VMULHU_VX) 3958 DECLARE_INSN(vmul_vx, MATCH_VMUL_VX, MASK_VMUL_VX) 3959 DECLARE_INSN(vmulhsu_vx, MATCH_VMULHSU_VX, MASK_VMULHSU_VX) 3960 DECLARE_INSN(vmulh_vx, MATCH_VMULH_VX, MASK_VMULH_VX) 3961 DECLARE_INSN(vmadd_vx, MATCH_VMADD_VX, MASK_VMADD_VX) 3962 DECLARE_INSN(vnmsub_vx, MATCH_VNMSUB_VX, MASK_VNMSUB_VX) 3963 DECLARE_INSN(vmacc_vx, MATCH_VMACC_VX, MASK_VMACC_VX) 3964 DECLARE_INSN(vnmsac_vx, MATCH_VNMSAC_VX, MASK_VNMSAC_VX) 3965 DECLARE_INSN(vwaddu_vx, MATCH_VWADDU_VX, MASK_VWADDU_VX) 3966 DECLARE_INSN(vwadd_vx, MATCH_VWADD_VX, MASK_VWADD_VX) 3967 DECLARE_INSN(vwsubu_vx, MATCH_VWSUBU_VX, MASK_VWSUBU_VX) 3968 DECLARE_INSN(vwsub_vx, MATCH_VWSUB_VX, MASK_VWSUB_VX) 3969 DECLARE_INSN(vwaddu_wx, MATCH_VWADDU_WX, MASK_VWADDU_WX) 3970 DECLARE_INSN(vwadd_wx, MATCH_VWADD_WX, MASK_VWADD_WX) 3971 DECLARE_INSN(vwsubu_wx, MATCH_VWSUBU_WX, MASK_VWSUBU_WX) 3972 DECLARE_INSN(vwsub_wx, MATCH_VWSUB_WX, MASK_VWSUB_WX) 3973 DECLARE_INSN(vwmulu_vx, MATCH_VWMULU_VX, MASK_VWMULU_VX) 3974 DECLARE_INSN(vwmulsu_vx, MATCH_VWMULSU_VX, MASK_VWMULSU_VX) 3975 DECLARE_INSN(vwmul_vx, MATCH_VWMUL_VX, MASK_VWMUL_VX) 3976 DECLARE_INSN(vwmaccu_vx, MATCH_VWMACCU_VX, MASK_VWMACCU_VX) 3977 DECLARE_INSN(vwmacc_vx, MATCH_VWMACC_VX, MASK_VWMACC_VX) 3978 DECLARE_INSN(vwmaccus_vx, MATCH_VWMACCUS_VX, MASK_VWMACCUS_VX) 3979 DECLARE_INSN(vwmaccsu_vx, MATCH_VWMACCSU_VX, MASK_VWMACCSU_VX) 3980 DECLARE_INSN(vamoswapei8_v, MATCH_VAMOSWAPEI8_V, MASK_VAMOSWAPEI8_V) 3981 DECLARE_INSN(vamoaddei8_v, MATCH_VAMOADDEI8_V, MASK_VAMOADDEI8_V) 3982 DECLARE_INSN(vamoxorei8_v, MATCH_VAMOXOREI8_V, MASK_VAMOXOREI8_V) 3983 DECLARE_INSN(vamoandei8_v, MATCH_VAMOANDEI8_V, MASK_VAMOANDEI8_V) 3984 DECLARE_INSN(vamoorei8_v, MATCH_VAMOOREI8_V, MASK_VAMOOREI8_V) 3985 DECLARE_INSN(vamominei8_v, MATCH_VAMOMINEI8_V, MASK_VAMOMINEI8_V) 3986 DECLARE_INSN(vamomaxei8_v, MATCH_VAMOMAXEI8_V, MASK_VAMOMAXEI8_V) 3987 DECLARE_INSN(vamominuei8_v, MATCH_VAMOMINUEI8_V, MASK_VAMOMINUEI8_V) 3988 DECLARE_INSN(vamomaxuei8_v, MATCH_VAMOMAXUEI8_V, MASK_VAMOMAXUEI8_V) 3989 DECLARE_INSN(vamoswapei16_v, MATCH_VAMOSWAPEI16_V, MASK_VAMOSWAPEI16_V) 3990 DECLARE_INSN(vamoaddei16_v, MATCH_VAMOADDEI16_V, MASK_VAMOADDEI16_V) 3991 DECLARE_INSN(vamoxorei16_v, MATCH_VAMOXOREI16_V, MASK_VAMOXOREI16_V) 3992 DECLARE_INSN(vamoandei16_v, MATCH_VAMOANDEI16_V, MASK_VAMOANDEI16_V) 3993 DECLARE_INSN(vamoorei16_v, MATCH_VAMOOREI16_V, MASK_VAMOOREI16_V) 3994 DECLARE_INSN(vamominei16_v, MATCH_VAMOMINEI16_V, MASK_VAMOMINEI16_V) 3995 DECLARE_INSN(vamomaxei16_v, MATCH_VAMOMAXEI16_V, MASK_VAMOMAXEI16_V) 3996 DECLARE_INSN(vamominuei16_v, MATCH_VAMOMINUEI16_V, MASK_VAMOMINUEI16_V) 3997 DECLARE_INSN(vamomaxuei16_v, MATCH_VAMOMAXUEI16_V, MASK_VAMOMAXUEI16_V) 3998 DECLARE_INSN(vamoswapei32_v, MATCH_VAMOSWAPEI32_V, MASK_VAMOSWAPEI32_V) 3999 DECLARE_INSN(vamoaddei32_v, MATCH_VAMOADDEI32_V, MASK_VAMOADDEI32_V) 4000 DECLARE_INSN(vamoxorei32_v, MATCH_VAMOXOREI32_V, MASK_VAMOXOREI32_V) 4001 DECLARE_INSN(vamoandei32_v, MATCH_VAMOANDEI32_V, MASK_VAMOANDEI32_V) 4002 DECLARE_INSN(vamoorei32_v, MATCH_VAMOOREI32_V, MASK_VAMOOREI32_V) 4003 DECLARE_INSN(vamominei32_v, MATCH_VAMOMINEI32_V, MASK_VAMOMINEI32_V) 4004 DECLARE_INSN(vamomaxei32_v, MATCH_VAMOMAXEI32_V, MASK_VAMOMAXEI32_V) 4005 DECLARE_INSN(vamominuei32_v, MATCH_VAMOMINUEI32_V, MASK_VAMOMINUEI32_V) 4006 DECLARE_INSN(vamomaxuei32_v, MATCH_VAMOMAXUEI32_V, MASK_VAMOMAXUEI32_V) 4007 DECLARE_INSN(vamoswapei64_v, MATCH_VAMOSWAPEI64_V, MASK_VAMOSWAPEI64_V) 4008 DECLARE_INSN(vamoaddei64_v, MATCH_VAMOADDEI64_V, MASK_VAMOADDEI64_V) 4009 DECLARE_INSN(vamoxorei64_v, MATCH_VAMOXOREI64_V, MASK_VAMOXOREI64_V) 4010 DECLARE_INSN(vamoandei64_v, MATCH_VAMOANDEI64_V, MASK_VAMOANDEI64_V) 4011 DECLARE_INSN(vamoorei64_v, MATCH_VAMOOREI64_V, MASK_VAMOOREI64_V) 4012 DECLARE_INSN(vamominei64_v, MATCH_VAMOMINEI64_V, MASK_VAMOMINEI64_V) 4013 DECLARE_INSN(vamomaxei64_v, MATCH_VAMOMAXEI64_V, MASK_VAMOMAXEI64_V) 4014 DECLARE_INSN(vamominuei64_v, MATCH_VAMOMINUEI64_V, MASK_VAMOMINUEI64_V) 4015 DECLARE_INSN(vamomaxuei64_v, MATCH_VAMOMAXUEI64_V, MASK_VAMOMAXUEI64_V) 4016 DECLARE_INSN(add8, MATCH_ADD8, MASK_ADD8) 4017 DECLARE_INSN(add16, MATCH_ADD16, MASK_ADD16) 4018 DECLARE_INSN(add64, MATCH_ADD64, MASK_ADD64) 4019 DECLARE_INSN(ave, MATCH_AVE, MASK_AVE) 4020 DECLARE_INSN(bitrev, MATCH_BITREV, MASK_BITREV) 4021 DECLARE_INSN(bitrevi, MATCH_BITREVI, MASK_BITREVI) 4022 DECLARE_INSN(bpick, MATCH_BPICK, MASK_BPICK) 4023 DECLARE_INSN(clrs8, MATCH_CLRS8, MASK_CLRS8) 4024 DECLARE_INSN(clrs16, MATCH_CLRS16, MASK_CLRS16) 4025 DECLARE_INSN(clrs32, MATCH_CLRS32, MASK_CLRS32) 4026 DECLARE_INSN(clo8, MATCH_CLO8, MASK_CLO8) 4027 DECLARE_INSN(clo16, MATCH_CLO16, MASK_CLO16) 4028 DECLARE_INSN(clo32, MATCH_CLO32, MASK_CLO32) 4029 DECLARE_INSN(clz8, MATCH_CLZ8, MASK_CLZ8) 4030 DECLARE_INSN(clz16, MATCH_CLZ16, MASK_CLZ16) 4031 DECLARE_INSN(clz32, MATCH_CLZ32, MASK_CLZ32) 4032 DECLARE_INSN(cmpeq8, MATCH_CMPEQ8, MASK_CMPEQ8) 4033 DECLARE_INSN(cmpeq16, MATCH_CMPEQ16, MASK_CMPEQ16) 4034 DECLARE_INSN(cras16, MATCH_CRAS16, MASK_CRAS16) 4035 DECLARE_INSN(crsa16, MATCH_CRSA16, MASK_CRSA16) 4036 DECLARE_INSN(insb, MATCH_INSB, MASK_INSB) 4037 DECLARE_INSN(kabs8, MATCH_KABS8, MASK_KABS8) 4038 DECLARE_INSN(kabs16, MATCH_KABS16, MASK_KABS16) 4039 DECLARE_INSN(kabsw, MATCH_KABSW, MASK_KABSW) 4040 DECLARE_INSN(kadd8, MATCH_KADD8, MASK_KADD8) 4041 DECLARE_INSN(kadd16, MATCH_KADD16, MASK_KADD16) 4042 DECLARE_INSN(kadd64, MATCH_KADD64, MASK_KADD64) 4043 DECLARE_INSN(kaddh, MATCH_KADDH, MASK_KADDH) 4044 DECLARE_INSN(kaddw, MATCH_KADDW, MASK_KADDW) 4045 DECLARE_INSN(kcras16, MATCH_KCRAS16, MASK_KCRAS16) 4046 DECLARE_INSN(kcrsa16, MATCH_KCRSA16, MASK_KCRSA16) 4047 DECLARE_INSN(kdmbb, MATCH_KDMBB, MASK_KDMBB) 4048 DECLARE_INSN(kdmbt, MATCH_KDMBT, MASK_KDMBT) 4049 DECLARE_INSN(kdmtt, MATCH_KDMTT, MASK_KDMTT) 4050 DECLARE_INSN(kdmabb, MATCH_KDMABB, MASK_KDMABB) 4051 DECLARE_INSN(kdmabt, MATCH_KDMABT, MASK_KDMABT) 4052 DECLARE_INSN(kdmatt, MATCH_KDMATT, MASK_KDMATT) 4053 DECLARE_INSN(khm8, MATCH_KHM8, MASK_KHM8) 4054 DECLARE_INSN(khmx8, MATCH_KHMX8, MASK_KHMX8) 4055 DECLARE_INSN(khm16, MATCH_KHM16, MASK_KHM16) 4056 DECLARE_INSN(khmx16, MATCH_KHMX16, MASK_KHMX16) 4057 DECLARE_INSN(khmbb, MATCH_KHMBB, MASK_KHMBB) 4058 DECLARE_INSN(khmbt, MATCH_KHMBT, MASK_KHMBT) 4059 DECLARE_INSN(khmtt, MATCH_KHMTT, MASK_KHMTT) 4060 DECLARE_INSN(kmabb, MATCH_KMABB, MASK_KMABB) 4061 DECLARE_INSN(kmabt, MATCH_KMABT, MASK_KMABT) 4062 DECLARE_INSN(kmatt, MATCH_KMATT, MASK_KMATT) 4063 DECLARE_INSN(kmada, MATCH_KMADA, MASK_KMADA) 4064 DECLARE_INSN(kmaxda, MATCH_KMAXDA, MASK_KMAXDA) 4065 DECLARE_INSN(kmads, MATCH_KMADS, MASK_KMADS) 4066 DECLARE_INSN(kmadrs, MATCH_KMADRS, MASK_KMADRS) 4067 DECLARE_INSN(kmaxds, MATCH_KMAXDS, MASK_KMAXDS) 4068 DECLARE_INSN(kmar64, MATCH_KMAR64, MASK_KMAR64) 4069 DECLARE_INSN(kmda, MATCH_KMDA, MASK_KMDA) 4070 DECLARE_INSN(kmxda, MATCH_KMXDA, MASK_KMXDA) 4071 DECLARE_INSN(kmmac, MATCH_KMMAC, MASK_KMMAC) 4072 DECLARE_INSN(kmmac_u, MATCH_KMMAC_U, MASK_KMMAC_U) 4073 DECLARE_INSN(kmmawb, MATCH_KMMAWB, MASK_KMMAWB) 4074 DECLARE_INSN(kmmawb_u, MATCH_KMMAWB_U, MASK_KMMAWB_U) 4075 DECLARE_INSN(kmmawb2, MATCH_KMMAWB2, MASK_KMMAWB2) 4076 DECLARE_INSN(kmmawb2_u, MATCH_KMMAWB2_U, MASK_KMMAWB2_U) 4077 DECLARE_INSN(kmmawt, MATCH_KMMAWT, MASK_KMMAWT) 4078 DECLARE_INSN(kmmawt_u, MATCH_KMMAWT_U, MASK_KMMAWT_U) 4079 DECLARE_INSN(kmmawt2, MATCH_KMMAWT2, MASK_KMMAWT2) 4080 DECLARE_INSN(kmmawt2_u, MATCH_KMMAWT2_U, MASK_KMMAWT2_U) 4081 DECLARE_INSN(kmmsb, MATCH_KMMSB, MASK_KMMSB) 4082 DECLARE_INSN(kmmsb_u, MATCH_KMMSB_U, MASK_KMMSB_U) 4083 DECLARE_INSN(kmmwb2, MATCH_KMMWB2, MASK_KMMWB2) 4084 DECLARE_INSN(kmmwb2_u, MATCH_KMMWB2_U, MASK_KMMWB2_U) 4085 DECLARE_INSN(kmmwt2, MATCH_KMMWT2, MASK_KMMWT2) 4086 DECLARE_INSN(kmmwt2_u, MATCH_KMMWT2_U, MASK_KMMWT2_U) 4087 DECLARE_INSN(kmsda, MATCH_KMSDA, MASK_KMSDA) 4088 DECLARE_INSN(kmsxda, MATCH_KMSXDA, MASK_KMSXDA) 4089 DECLARE_INSN(kmsr64, MATCH_KMSR64, MASK_KMSR64) 4090 DECLARE_INSN(ksllw, MATCH_KSLLW, MASK_KSLLW) 4091 DECLARE_INSN(kslliw, MATCH_KSLLIW, MASK_KSLLIW) 4092 DECLARE_INSN(ksll8, MATCH_KSLL8, MASK_KSLL8) 4093 DECLARE_INSN(kslli8, MATCH_KSLLI8, MASK_KSLLI8) 4094 DECLARE_INSN(ksll16, MATCH_KSLL16, MASK_KSLL16) 4095 DECLARE_INSN(kslli16, MATCH_KSLLI16, MASK_KSLLI16) 4096 DECLARE_INSN(kslra8, MATCH_KSLRA8, MASK_KSLRA8) 4097 DECLARE_INSN(kslra8_u, MATCH_KSLRA8_U, MASK_KSLRA8_U) 4098 DECLARE_INSN(kslra16, MATCH_KSLRA16, MASK_KSLRA16) 4099 DECLARE_INSN(kslra16_u, MATCH_KSLRA16_U, MASK_KSLRA16_U) 4100 DECLARE_INSN(kslraw, MATCH_KSLRAW, MASK_KSLRAW) 4101 DECLARE_INSN(kslraw_u, MATCH_KSLRAW_U, MASK_KSLRAW_U) 4102 DECLARE_INSN(kstas16, MATCH_KSTAS16, MASK_KSTAS16) 4103 DECLARE_INSN(kstsa16, MATCH_KSTSA16, MASK_KSTSA16) 4104 DECLARE_INSN(ksub8, MATCH_KSUB8, MASK_KSUB8) 4105 DECLARE_INSN(ksub16, MATCH_KSUB16, MASK_KSUB16) 4106 DECLARE_INSN(ksub64, MATCH_KSUB64, MASK_KSUB64) 4107 DECLARE_INSN(ksubh, MATCH_KSUBH, MASK_KSUBH) 4108 DECLARE_INSN(ksubw, MATCH_KSUBW, MASK_KSUBW) 4109 DECLARE_INSN(kwmmul, MATCH_KWMMUL, MASK_KWMMUL) 4110 DECLARE_INSN(kwmmul_u, MATCH_KWMMUL_U, MASK_KWMMUL_U) 4111 DECLARE_INSN(maddr32, MATCH_MADDR32, MASK_MADDR32) 4112 DECLARE_INSN(maxw, MATCH_MAXW, MASK_MAXW) 4113 DECLARE_INSN(minw, MATCH_MINW, MASK_MINW) 4114 DECLARE_INSN(msubr32, MATCH_MSUBR32, MASK_MSUBR32) 4115 DECLARE_INSN(mulr64, MATCH_MULR64, MASK_MULR64) 4116 DECLARE_INSN(mulsr64, MATCH_MULSR64, MASK_MULSR64) 4117 DECLARE_INSN(pbsad, MATCH_PBSAD, MASK_PBSAD) 4118 DECLARE_INSN(pbsada, MATCH_PBSADA, MASK_PBSADA) 4119 DECLARE_INSN(pkbb16, MATCH_PKBB16, MASK_PKBB16) 4120 DECLARE_INSN(pkbt16, MATCH_PKBT16, MASK_PKBT16) 4121 DECLARE_INSN(pktt16, MATCH_PKTT16, MASK_PKTT16) 4122 DECLARE_INSN(pktb16, MATCH_PKTB16, MASK_PKTB16) 4123 DECLARE_INSN(radd8, MATCH_RADD8, MASK_RADD8) 4124 DECLARE_INSN(radd16, MATCH_RADD16, MASK_RADD16) 4125 DECLARE_INSN(radd64, MATCH_RADD64, MASK_RADD64) 4126 DECLARE_INSN(raddw, MATCH_RADDW, MASK_RADDW) 4127 DECLARE_INSN(rcras16, MATCH_RCRAS16, MASK_RCRAS16) 4128 DECLARE_INSN(rcrsa16, MATCH_RCRSA16, MASK_RCRSA16) 4129 DECLARE_INSN(rstas16, MATCH_RSTAS16, MASK_RSTAS16) 4130 DECLARE_INSN(rstsa16, MATCH_RSTSA16, MASK_RSTSA16) 4131 DECLARE_INSN(rsub8, MATCH_RSUB8, MASK_RSUB8) 4132 DECLARE_INSN(rsub16, MATCH_RSUB16, MASK_RSUB16) 4133 DECLARE_INSN(rsub64, MATCH_RSUB64, MASK_RSUB64) 4134 DECLARE_INSN(rsubw, MATCH_RSUBW, MASK_RSUBW) 4135 DECLARE_INSN(sclip8, MATCH_SCLIP8, MASK_SCLIP8) 4136 DECLARE_INSN(sclip16, MATCH_SCLIP16, MASK_SCLIP16) 4137 DECLARE_INSN(sclip32, MATCH_SCLIP32, MASK_SCLIP32) 4138 DECLARE_INSN(scmple8, MATCH_SCMPLE8, MASK_SCMPLE8) 4139 DECLARE_INSN(scmple16, MATCH_SCMPLE16, MASK_SCMPLE16) 4140 DECLARE_INSN(scmplt8, MATCH_SCMPLT8, MASK_SCMPLT8) 4141 DECLARE_INSN(scmplt16, MATCH_SCMPLT16, MASK_SCMPLT16) 4142 DECLARE_INSN(sll8, MATCH_SLL8, MASK_SLL8) 4143 DECLARE_INSN(slli8, MATCH_SLLI8, MASK_SLLI8) 4144 DECLARE_INSN(sll16, MATCH_SLL16, MASK_SLL16) 4145 DECLARE_INSN(slli16, MATCH_SLLI16, MASK_SLLI16) 4146 DECLARE_INSN(smal, MATCH_SMAL, MASK_SMAL) 4147 DECLARE_INSN(smalbb, MATCH_SMALBB, MASK_SMALBB) 4148 DECLARE_INSN(smalbt, MATCH_SMALBT, MASK_SMALBT) 4149 DECLARE_INSN(smaltt, MATCH_SMALTT, MASK_SMALTT) 4150 DECLARE_INSN(smalda, MATCH_SMALDA, MASK_SMALDA) 4151 DECLARE_INSN(smalxda, MATCH_SMALXDA, MASK_SMALXDA) 4152 DECLARE_INSN(smalds, MATCH_SMALDS, MASK_SMALDS) 4153 DECLARE_INSN(smaldrs, MATCH_SMALDRS, MASK_SMALDRS) 4154 DECLARE_INSN(smalxds, MATCH_SMALXDS, MASK_SMALXDS) 4155 DECLARE_INSN(smar64, MATCH_SMAR64, MASK_SMAR64) 4156 DECLARE_INSN(smaqa, MATCH_SMAQA, MASK_SMAQA) 4157 DECLARE_INSN(smaqa_su, MATCH_SMAQA_SU, MASK_SMAQA_SU) 4158 DECLARE_INSN(smax8, MATCH_SMAX8, MASK_SMAX8) 4159 DECLARE_INSN(smax16, MATCH_SMAX16, MASK_SMAX16) 4160 DECLARE_INSN(smbb16, MATCH_SMBB16, MASK_SMBB16) 4161 DECLARE_INSN(smbt16, MATCH_SMBT16, MASK_SMBT16) 4162 DECLARE_INSN(smtt16, MATCH_SMTT16, MASK_SMTT16) 4163 DECLARE_INSN(smds, MATCH_SMDS, MASK_SMDS) 4164 DECLARE_INSN(smdrs, MATCH_SMDRS, MASK_SMDRS) 4165 DECLARE_INSN(smxds, MATCH_SMXDS, MASK_SMXDS) 4166 DECLARE_INSN(smin8, MATCH_SMIN8, MASK_SMIN8) 4167 DECLARE_INSN(smin16, MATCH_SMIN16, MASK_SMIN16) 4168 DECLARE_INSN(smmul, MATCH_SMMUL, MASK_SMMUL) 4169 DECLARE_INSN(smmul_u, MATCH_SMMUL_U, MASK_SMMUL_U) 4170 DECLARE_INSN(smmwb, MATCH_SMMWB, MASK_SMMWB) 4171 DECLARE_INSN(smmwb_u, MATCH_SMMWB_U, MASK_SMMWB_U) 4172 DECLARE_INSN(smmwt, MATCH_SMMWT, MASK_SMMWT) 4173 DECLARE_INSN(smmwt_u, MATCH_SMMWT_U, MASK_SMMWT_U) 4174 DECLARE_INSN(smslda, MATCH_SMSLDA, MASK_SMSLDA) 4175 DECLARE_INSN(smslxda, MATCH_SMSLXDA, MASK_SMSLXDA) 4176 DECLARE_INSN(smsr64, MATCH_SMSR64, MASK_SMSR64) 4177 DECLARE_INSN(smul8, MATCH_SMUL8, MASK_SMUL8) 4178 DECLARE_INSN(smulx8, MATCH_SMULX8, MASK_SMULX8) 4179 DECLARE_INSN(smul16, MATCH_SMUL16, MASK_SMUL16) 4180 DECLARE_INSN(smulx16, MATCH_SMULX16, MASK_SMULX16) 4181 DECLARE_INSN(sra_u, MATCH_SRA_U, MASK_SRA_U) 4182 DECLARE_INSN(srai_u, MATCH_SRAI_U, MASK_SRAI_U) 4183 DECLARE_INSN(sra8, MATCH_SRA8, MASK_SRA8) 4184 DECLARE_INSN(sra8_u, MATCH_SRA8_U, MASK_SRA8_U) 4185 DECLARE_INSN(srai8, MATCH_SRAI8, MASK_SRAI8) 4186 DECLARE_INSN(srai8_u, MATCH_SRAI8_U, MASK_SRAI8_U) 4187 DECLARE_INSN(sra16, MATCH_SRA16, MASK_SRA16) 4188 DECLARE_INSN(sra16_u, MATCH_SRA16_U, MASK_SRA16_U) 4189 DECLARE_INSN(srai16, MATCH_SRAI16, MASK_SRAI16) 4190 DECLARE_INSN(srai16_u, MATCH_SRAI16_U, MASK_SRAI16_U) 4191 DECLARE_INSN(srl8, MATCH_SRL8, MASK_SRL8) 4192 DECLARE_INSN(srl8_u, MATCH_SRL8_U, MASK_SRL8_U) 4193 DECLARE_INSN(srli8, MATCH_SRLI8, MASK_SRLI8) 4194 DECLARE_INSN(srli8_u, MATCH_SRLI8_U, MASK_SRLI8_U) 4195 DECLARE_INSN(srl16, MATCH_SRL16, MASK_SRL16) 4196 DECLARE_INSN(srl16_u, MATCH_SRL16_U, MASK_SRL16_U) 4197 DECLARE_INSN(srli16, MATCH_SRLI16, MASK_SRLI16) 4198 DECLARE_INSN(srli16_u, MATCH_SRLI16_U, MASK_SRLI16_U) 4199 DECLARE_INSN(stas16, MATCH_STAS16, MASK_STAS16) 4200 DECLARE_INSN(stsa16, MATCH_STSA16, MASK_STSA16) 4201 DECLARE_INSN(sub8, MATCH_SUB8, MASK_SUB8) 4202 DECLARE_INSN(sub16, MATCH_SUB16, MASK_SUB16) 4203 DECLARE_INSN(sub64, MATCH_SUB64, MASK_SUB64) 4204 DECLARE_INSN(sunpkd810, MATCH_SUNPKD810, MASK_SUNPKD810) 4205 DECLARE_INSN(sunpkd820, MATCH_SUNPKD820, MASK_SUNPKD820) 4206 DECLARE_INSN(sunpkd830, MATCH_SUNPKD830, MASK_SUNPKD830) 4207 DECLARE_INSN(sunpkd831, MATCH_SUNPKD831, MASK_SUNPKD831) 4208 DECLARE_INSN(sunpkd832, MATCH_SUNPKD832, MASK_SUNPKD832) 4209 DECLARE_INSN(swap8, MATCH_SWAP8, MASK_SWAP8) 4210 DECLARE_INSN(uclip8, MATCH_UCLIP8, MASK_UCLIP8) 4211 DECLARE_INSN(uclip16, MATCH_UCLIP16, MASK_UCLIP16) 4212 DECLARE_INSN(uclip32, MATCH_UCLIP32, MASK_UCLIP32) 4213 DECLARE_INSN(ucmple8, MATCH_UCMPLE8, MASK_UCMPLE8) 4214 DECLARE_INSN(ucmple16, MATCH_UCMPLE16, MASK_UCMPLE16) 4215 DECLARE_INSN(ucmplt8, MATCH_UCMPLT8, MASK_UCMPLT8) 4216 DECLARE_INSN(ucmplt16, MATCH_UCMPLT16, MASK_UCMPLT16) 4217 DECLARE_INSN(ukadd8, MATCH_UKADD8, MASK_UKADD8) 4218 DECLARE_INSN(ukadd16, MATCH_UKADD16, MASK_UKADD16) 4219 DECLARE_INSN(ukadd64, MATCH_UKADD64, MASK_UKADD64) 4220 DECLARE_INSN(ukaddh, MATCH_UKADDH, MASK_UKADDH) 4221 DECLARE_INSN(ukaddw, MATCH_UKADDW, MASK_UKADDW) 4222 DECLARE_INSN(ukcras16, MATCH_UKCRAS16, MASK_UKCRAS16) 4223 DECLARE_INSN(ukcrsa16, MATCH_UKCRSA16, MASK_UKCRSA16) 4224 DECLARE_INSN(ukmar64, MATCH_UKMAR64, MASK_UKMAR64) 4225 DECLARE_INSN(ukmsr64, MATCH_UKMSR64, MASK_UKMSR64) 4226 DECLARE_INSN(ukstas16, MATCH_UKSTAS16, MASK_UKSTAS16) 4227 DECLARE_INSN(ukstsa16, MATCH_UKSTSA16, MASK_UKSTSA16) 4228 DECLARE_INSN(uksub8, MATCH_UKSUB8, MASK_UKSUB8) 4229 DECLARE_INSN(uksub16, MATCH_UKSUB16, MASK_UKSUB16) 4230 DECLARE_INSN(uksub64, MATCH_UKSUB64, MASK_UKSUB64) 4231 DECLARE_INSN(uksubh, MATCH_UKSUBH, MASK_UKSUBH) 4232 DECLARE_INSN(uksubw, MATCH_UKSUBW, MASK_UKSUBW) 4233 DECLARE_INSN(umar64, MATCH_UMAR64, MASK_UMAR64) 4234 DECLARE_INSN(umaqa, MATCH_UMAQA, MASK_UMAQA) 4235 DECLARE_INSN(umax8, MATCH_UMAX8, MASK_UMAX8) 4236 DECLARE_INSN(umax16, MATCH_UMAX16, MASK_UMAX16) 4237 DECLARE_INSN(umin8, MATCH_UMIN8, MASK_UMIN8) 4238 DECLARE_INSN(umin16, MATCH_UMIN16, MASK_UMIN16) 4239 DECLARE_INSN(umsr64, MATCH_UMSR64, MASK_UMSR64) 4240 DECLARE_INSN(umul8, MATCH_UMUL8, MASK_UMUL8) 4241 DECLARE_INSN(umulx8, MATCH_UMULX8, MASK_UMULX8) 4242 DECLARE_INSN(umul16, MATCH_UMUL16, MASK_UMUL16) 4243 DECLARE_INSN(umulx16, MATCH_UMULX16, MASK_UMULX16) 4244 DECLARE_INSN(uradd8, MATCH_URADD8, MASK_URADD8) 4245 DECLARE_INSN(uradd16, MATCH_URADD16, MASK_URADD16) 4246 DECLARE_INSN(uradd64, MATCH_URADD64, MASK_URADD64) 4247 DECLARE_INSN(uraddw, MATCH_URADDW, MASK_URADDW) 4248 DECLARE_INSN(urcras16, MATCH_URCRAS16, MASK_URCRAS16) 4249 DECLARE_INSN(urcrsa16, MATCH_URCRSA16, MASK_URCRSA16) 4250 DECLARE_INSN(urstas16, MATCH_URSTAS16, MASK_URSTAS16) 4251 DECLARE_INSN(urstsa16, MATCH_URSTSA16, MASK_URSTSA16) 4252 DECLARE_INSN(ursub8, MATCH_URSUB8, MASK_URSUB8) 4253 DECLARE_INSN(ursub16, MATCH_URSUB16, MASK_URSUB16) 4254 DECLARE_INSN(ursub64, MATCH_URSUB64, MASK_URSUB64) 4255 DECLARE_INSN(ursubw, MATCH_URSUBW, MASK_URSUBW) 4256 DECLARE_INSN(wexti, MATCH_WEXTI, MASK_WEXTI) 4257 DECLARE_INSN(wext, MATCH_WEXT, MASK_WEXT) 4258 DECLARE_INSN(zunpkd810, MATCH_ZUNPKD810, MASK_ZUNPKD810) 4259 DECLARE_INSN(zunpkd820, MATCH_ZUNPKD820, MASK_ZUNPKD820) 4260 DECLARE_INSN(zunpkd830, MATCH_ZUNPKD830, MASK_ZUNPKD830) 4261 DECLARE_INSN(zunpkd831, MATCH_ZUNPKD831, MASK_ZUNPKD831) 4262 DECLARE_INSN(zunpkd832, MATCH_ZUNPKD832, MASK_ZUNPKD832) 4263 DECLARE_INSN(add32, MATCH_ADD32, MASK_ADD32) 4264 DECLARE_INSN(cras32, MATCH_CRAS32, MASK_CRAS32) 4265 DECLARE_INSN(crsa32, MATCH_CRSA32, MASK_CRSA32) 4266 DECLARE_INSN(kabs32, MATCH_KABS32, MASK_KABS32) 4267 DECLARE_INSN(kadd32, MATCH_KADD32, MASK_KADD32) 4268 DECLARE_INSN(kcras32, MATCH_KCRAS32, MASK_KCRAS32) 4269 DECLARE_INSN(kcrsa32, MATCH_KCRSA32, MASK_KCRSA32) 4270 DECLARE_INSN(kdmbb16, MATCH_KDMBB16, MASK_KDMBB16) 4271 DECLARE_INSN(kdmbt16, MATCH_KDMBT16, MASK_KDMBT16) 4272 DECLARE_INSN(kdmtt16, MATCH_KDMTT16, MASK_KDMTT16) 4273 DECLARE_INSN(kdmabb16, MATCH_KDMABB16, MASK_KDMABB16) 4274 DECLARE_INSN(kdmabt16, MATCH_KDMABT16, MASK_KDMABT16) 4275 DECLARE_INSN(kdmatt16, MATCH_KDMATT16, MASK_KDMATT16) 4276 DECLARE_INSN(khmbb16, MATCH_KHMBB16, MASK_KHMBB16) 4277 DECLARE_INSN(khmbt16, MATCH_KHMBT16, MASK_KHMBT16) 4278 DECLARE_INSN(khmtt16, MATCH_KHMTT16, MASK_KHMTT16) 4279 DECLARE_INSN(kmabb32, MATCH_KMABB32, MASK_KMABB32) 4280 DECLARE_INSN(kmabt32, MATCH_KMABT32, MASK_KMABT32) 4281 DECLARE_INSN(kmatt32, MATCH_KMATT32, MASK_KMATT32) 4282 DECLARE_INSN(kmaxda32, MATCH_KMAXDA32, MASK_KMAXDA32) 4283 DECLARE_INSN(kmda32, MATCH_KMDA32, MASK_KMDA32) 4284 DECLARE_INSN(kmxda32, MATCH_KMXDA32, MASK_KMXDA32) 4285 DECLARE_INSN(kmads32, MATCH_KMADS32, MASK_KMADS32) 4286 DECLARE_INSN(kmadrs32, MATCH_KMADRS32, MASK_KMADRS32) 4287 DECLARE_INSN(kmaxds32, MATCH_KMAXDS32, MASK_KMAXDS32) 4288 DECLARE_INSN(kmsda32, MATCH_KMSDA32, MASK_KMSDA32) 4289 DECLARE_INSN(kmsxda32, MATCH_KMSXDA32, MASK_KMSXDA32) 4290 DECLARE_INSN(ksll32, MATCH_KSLL32, MASK_KSLL32) 4291 DECLARE_INSN(kslli32, MATCH_KSLLI32, MASK_KSLLI32) 4292 DECLARE_INSN(kslra32, MATCH_KSLRA32, MASK_KSLRA32) 4293 DECLARE_INSN(kslra32_u, MATCH_KSLRA32_U, MASK_KSLRA32_U) 4294 DECLARE_INSN(kstas32, MATCH_KSTAS32, MASK_KSTAS32) 4295 DECLARE_INSN(kstsa32, MATCH_KSTSA32, MASK_KSTSA32) 4296 DECLARE_INSN(ksub32, MATCH_KSUB32, MASK_KSUB32) 4297 DECLARE_INSN(pkbb32, MATCH_PKBB32, MASK_PKBB32) 4298 DECLARE_INSN(pkbt32, MATCH_PKBT32, MASK_PKBT32) 4299 DECLARE_INSN(pktt32, MATCH_PKTT32, MASK_PKTT32) 4300 DECLARE_INSN(pktb32, MATCH_PKTB32, MASK_PKTB32) 4301 DECLARE_INSN(radd32, MATCH_RADD32, MASK_RADD32) 4302 DECLARE_INSN(rcras32, MATCH_RCRAS32, MASK_RCRAS32) 4303 DECLARE_INSN(rcrsa32, MATCH_RCRSA32, MASK_RCRSA32) 4304 DECLARE_INSN(rstas32, MATCH_RSTAS32, MASK_RSTAS32) 4305 DECLARE_INSN(rstsa32, MATCH_RSTSA32, MASK_RSTSA32) 4306 DECLARE_INSN(rsub32, MATCH_RSUB32, MASK_RSUB32) 4307 DECLARE_INSN(sll32, MATCH_SLL32, MASK_SLL32) 4308 DECLARE_INSN(slli32, MATCH_SLLI32, MASK_SLLI32) 4309 DECLARE_INSN(smax32, MATCH_SMAX32, MASK_SMAX32) 4310 DECLARE_INSN(smbt32, MATCH_SMBT32, MASK_SMBT32) 4311 DECLARE_INSN(smtt32, MATCH_SMTT32, MASK_SMTT32) 4312 DECLARE_INSN(smds32, MATCH_SMDS32, MASK_SMDS32) 4313 DECLARE_INSN(smdrs32, MATCH_SMDRS32, MASK_SMDRS32) 4314 DECLARE_INSN(smxds32, MATCH_SMXDS32, MASK_SMXDS32) 4315 DECLARE_INSN(smin32, MATCH_SMIN32, MASK_SMIN32) 4316 DECLARE_INSN(sra32, MATCH_SRA32, MASK_SRA32) 4317 DECLARE_INSN(sra32_u, MATCH_SRA32_U, MASK_SRA32_U) 4318 DECLARE_INSN(srai32, MATCH_SRAI32, MASK_SRAI32) 4319 DECLARE_INSN(srai32_u, MATCH_SRAI32_U, MASK_SRAI32_U) 4320 DECLARE_INSN(sraiw_u, MATCH_SRAIW_U, MASK_SRAIW_U) 4321 DECLARE_INSN(srl32, MATCH_SRL32, MASK_SRL32) 4322 DECLARE_INSN(srl32_u, MATCH_SRL32_U, MASK_SRL32_U) 4323 DECLARE_INSN(srli32, MATCH_SRLI32, MASK_SRLI32) 4324 DECLARE_INSN(srli32_u, MATCH_SRLI32_U, MASK_SRLI32_U) 4325 DECLARE_INSN(stas32, MATCH_STAS32, MASK_STAS32) 4326 DECLARE_INSN(stsa32, MATCH_STSA32, MASK_STSA32) 4327 DECLARE_INSN(sub32, MATCH_SUB32, MASK_SUB32) 4328 DECLARE_INSN(ukadd32, MATCH_UKADD32, MASK_UKADD32) 4329 DECLARE_INSN(ukcras32, MATCH_UKCRAS32, MASK_UKCRAS32) 4330 DECLARE_INSN(ukcrsa32, MATCH_UKCRSA32, MASK_UKCRSA32) 4331 DECLARE_INSN(ukstas32, MATCH_UKSTAS32, MASK_UKSTAS32) 4332 DECLARE_INSN(ukstsa32, MATCH_UKSTSA32, MASK_UKSTSA32) 4333 DECLARE_INSN(uksub32, MATCH_UKSUB32, MASK_UKSUB32) 4334 DECLARE_INSN(umax32, MATCH_UMAX32, MASK_UMAX32) 4335 DECLARE_INSN(umin32, MATCH_UMIN32, MASK_UMIN32) 4336 DECLARE_INSN(uradd32, MATCH_URADD32, MASK_URADD32) 4337 DECLARE_INSN(urcras32, MATCH_URCRAS32, MASK_URCRAS32) 4338 DECLARE_INSN(urcrsa32, MATCH_URCRSA32, MASK_URCRSA32) 4339 DECLARE_INSN(urstas32, MATCH_URSTAS32, MASK_URSTAS32) 4340 DECLARE_INSN(urstsa32, MATCH_URSTSA32, MASK_URSTSA32) 4341 DECLARE_INSN(ursub32, MATCH_URSUB32, MASK_URSUB32) 4342 DECLARE_INSN(vmvnfr_v, MATCH_VMVNFR_V, MASK_VMVNFR_V) 4343 DECLARE_INSN(vl1r_v, MATCH_VL1R_V, MASK_VL1R_V) 4344 DECLARE_INSN(vl2r_v, MATCH_VL2R_V, MASK_VL2R_V) 4345 DECLARE_INSN(vl4r_v, MATCH_VL4R_V, MASK_VL4R_V) 4346 DECLARE_INSN(vl8r_v, MATCH_VL8R_V, MASK_VL8R_V) 4347 DECLARE_INSN(vle1_v, MATCH_VLE1_V, MASK_VLE1_V) 4348 DECLARE_INSN(vse1_v, MATCH_VSE1_V, MASK_VSE1_V) 4349 DECLARE_INSN(vfredsum_vs, MATCH_VFREDSUM_VS, MASK_VFREDSUM_VS) 4350 DECLARE_INSN(vfwredsum_vs, MATCH_VFWREDSUM_VS, MASK_VFWREDSUM_VS) 4351 DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M) 4352 #endif 4353 #ifdef DECLARE_CSR 4354 DECLARE_CSR(fflags, CSR_FFLAGS) 4355 DECLARE_CSR(frm, CSR_FRM) 4356 DECLARE_CSR(fcsr, CSR_FCSR) 4357 DECLARE_CSR(ustatus, CSR_USTATUS) 4358 DECLARE_CSR(uie, CSR_UIE) 4359 DECLARE_CSR(utvec, CSR_UTVEC) 4360 DECLARE_CSR(vstart, CSR_VSTART) 4361 DECLARE_CSR(vxsat, CSR_VXSAT) 4362 DECLARE_CSR(vxrm, CSR_VXRM) 4363 DECLARE_CSR(vcsr, CSR_VCSR) 4364 DECLARE_CSR(uscratch, CSR_USCRATCH) 4365 DECLARE_CSR(uepc, CSR_UEPC) 4366 DECLARE_CSR(ucause, CSR_UCAUSE) 4367 DECLARE_CSR(utval, CSR_UTVAL) 4368 DECLARE_CSR(uip, CSR_UIP) 4369 DECLARE_CSR(cycle, CSR_CYCLE) 4370 DECLARE_CSR(time, CSR_TIME) 4371 DECLARE_CSR(instret, CSR_INSTRET) 4372 DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) 4373 DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) 4374 DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) 4375 DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) 4376 DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) 4377 DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) 4378 DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) 4379 DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) 4380 DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) 4381 DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) 4382 DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) 4383 DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) 4384 DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) 4385 DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) 4386 DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) 4387 DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) 4388 DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) 4389 DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) 4390 DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) 4391 DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) 4392 DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) 4393 DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) 4394 DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) 4395 DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) 4396 DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) 4397 DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) 4398 DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) 4399 DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) 4400 DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) 4401 DECLARE_CSR(vl, CSR_VL) 4402 DECLARE_CSR(vtype, CSR_VTYPE) 4403 DECLARE_CSR(vlenb, CSR_VLENB) 4404 DECLARE_CSR(sstatus, CSR_SSTATUS) 4405 DECLARE_CSR(sedeleg, CSR_SEDELEG) 4406 DECLARE_CSR(sideleg, CSR_SIDELEG) 4407 DECLARE_CSR(sie, CSR_SIE) 4408 DECLARE_CSR(stvec, CSR_STVEC) 4409 DECLARE_CSR(scounteren, CSR_SCOUNTEREN) 4410 DECLARE_CSR(sscratch, CSR_SSCRATCH) 4411 DECLARE_CSR(sepc, CSR_SEPC) 4412 DECLARE_CSR(scause, CSR_SCAUSE) 4413 DECLARE_CSR(stval, CSR_STVAL) 4414 DECLARE_CSR(sip, CSR_SIP) 4415 DECLARE_CSR(satp, CSR_SATP) 4416 DECLARE_CSR(vsstatus, CSR_VSSTATUS) 4417 DECLARE_CSR(vsie, CSR_VSIE) 4418 DECLARE_CSR(vstvec, CSR_VSTVEC) 4419 DECLARE_CSR(vsscratch, CSR_VSSCRATCH) 4420 DECLARE_CSR(vsepc, CSR_VSEPC) 4421 DECLARE_CSR(vscause, CSR_VSCAUSE) 4422 DECLARE_CSR(vstval, CSR_VSTVAL) 4423 DECLARE_CSR(vsip, CSR_VSIP) 4424 DECLARE_CSR(vsatp, CSR_VSATP) 4425 DECLARE_CSR(hstatus, CSR_HSTATUS) 4426 DECLARE_CSR(hedeleg, CSR_HEDELEG) 4427 DECLARE_CSR(hideleg, CSR_HIDELEG) 4428 DECLARE_CSR(hie, CSR_HIE) 4429 DECLARE_CSR(htimedelta, CSR_HTIMEDELTA) 4430 DECLARE_CSR(hcounteren, CSR_HCOUNTEREN) 4431 DECLARE_CSR(hgeie, CSR_HGEIE) 4432 DECLARE_CSR(htval, CSR_HTVAL) 4433 DECLARE_CSR(hip, CSR_HIP) 4434 DECLARE_CSR(hvip, CSR_HVIP) 4435 DECLARE_CSR(htinst, CSR_HTINST) 4436 DECLARE_CSR(hgatp, CSR_HGATP) 4437 DECLARE_CSR(hgeip, CSR_HGEIP) 4438 DECLARE_CSR(utvt, CSR_UTVT) 4439 DECLARE_CSR(unxti, CSR_UNXTI) 4440 DECLARE_CSR(uintstatus, CSR_UINTSTATUS) 4441 DECLARE_CSR(uscratchcsw, CSR_USCRATCHCSW) 4442 DECLARE_CSR(uscratchcswl, CSR_USCRATCHCSWL) 4443 DECLARE_CSR(stvt, CSR_STVT) 4444 DECLARE_CSR(snxti, CSR_SNXTI) 4445 DECLARE_CSR(sintstatus, CSR_SINTSTATUS) 4446 DECLARE_CSR(sscratchcsw, CSR_SSCRATCHCSW) 4447 DECLARE_CSR(sscratchcswl, CSR_SSCRATCHCSWL) 4448 DECLARE_CSR(mtvt, CSR_MTVT) 4449 DECLARE_CSR(mnxti, CSR_MNXTI) 4450 DECLARE_CSR(mintstatus, CSR_MINTSTATUS) 4451 DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW) 4452 DECLARE_CSR(mscratchcswl, CSR_MSCRATCHCSWL) 4453 DECLARE_CSR(mstatus, CSR_MSTATUS) 4454 DECLARE_CSR(misa, CSR_MISA) 4455 DECLARE_CSR(medeleg, CSR_MEDELEG) 4456 DECLARE_CSR(mideleg, CSR_MIDELEG) 4457 DECLARE_CSR(mie, CSR_MIE) 4458 DECLARE_CSR(mtvec, CSR_MTVEC) 4459 DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) 4460 DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT) 4461 DECLARE_CSR(mscratch, CSR_MSCRATCH) 4462 DECLARE_CSR(mepc, CSR_MEPC) 4463 DECLARE_CSR(mcause, CSR_MCAUSE) 4464 DECLARE_CSR(mtval, CSR_MTVAL) 4465 DECLARE_CSR(mip, CSR_MIP) 4466 DECLARE_CSR(mtinst, CSR_MTINST) 4467 DECLARE_CSR(mtval2, CSR_MTVAL2) 4468 DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) 4469 DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) 4470 DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) 4471 DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) 4472 DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) 4473 DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) 4474 DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) 4475 DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) 4476 DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) 4477 DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) 4478 DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) 4479 DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) 4480 DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) 4481 DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) 4482 DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) 4483 DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) 4484 DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) 4485 DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) 4486 DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) 4487 DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) 4488 DECLARE_CSR(tselect, CSR_TSELECT) 4489 DECLARE_CSR(tdata1, CSR_TDATA1) 4490 DECLARE_CSR(tdata2, CSR_TDATA2) 4491 DECLARE_CSR(tdata3, CSR_TDATA3) 4492 DECLARE_CSR(tinfo, CSR_TINFO) 4493 DECLARE_CSR(tcontrol, CSR_TCONTROL) 4494 DECLARE_CSR(mcontext, CSR_MCONTEXT) 4495 DECLARE_CSR(scontext, CSR_SCONTEXT) 4496 DECLARE_CSR(dcsr, CSR_DCSR) 4497 DECLARE_CSR(dpc, CSR_DPC) 4498 DECLARE_CSR(dscratch0, CSR_DSCRATCH0) 4499 DECLARE_CSR(dscratch1, CSR_DSCRATCH1) 4500 DECLARE_CSR(mcycle, CSR_MCYCLE) 4501 DECLARE_CSR(minstret, CSR_MINSTRET) 4502 DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) 4503 DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) 4504 DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) 4505 DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) 4506 DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) 4507 DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) 4508 DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) 4509 DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) 4510 DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) 4511 DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) 4512 DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) 4513 DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) 4514 DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) 4515 DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) 4516 DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) 4517 DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) 4518 DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) 4519 DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) 4520 DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) 4521 DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) 4522 DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) 4523 DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) 4524 DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) 4525 DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) 4526 DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) 4527 DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) 4528 DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) 4529 DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) 4530 DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) 4531 DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) 4532 DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) 4533 DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) 4534 DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) 4535 DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) 4536 DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) 4537 DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) 4538 DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) 4539 DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) 4540 DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) 4541 DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) 4542 DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) 4543 DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) 4544 DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) 4545 DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) 4546 DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) 4547 DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) 4548 DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) 4549 DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) 4550 DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) 4551 DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) 4552 DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) 4553 DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) 4554 DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) 4555 DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) 4556 DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) 4557 DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) 4558 DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) 4559 DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) 4560 DECLARE_CSR(mvendorid, CSR_MVENDORID) 4561 DECLARE_CSR(marchid, CSR_MARCHID) 4562 DECLARE_CSR(mimpid, CSR_MIMPID) 4563 DECLARE_CSR(mhartid, CSR_MHARTID) 4564 DECLARE_CSR(sentropy, CSR_SENTROPY) 4565 DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH) 4566 DECLARE_CSR(cycleh, CSR_CYCLEH) 4567 DECLARE_CSR(timeh, CSR_TIMEH) 4568 DECLARE_CSR(instreth, CSR_INSTRETH) 4569 DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) 4570 DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) 4571 DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) 4572 DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) 4573 DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) 4574 DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) 4575 DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) 4576 DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) 4577 DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) 4578 DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) 4579 DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) 4580 DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) 4581 DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) 4582 DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) 4583 DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) 4584 DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) 4585 DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) 4586 DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) 4587 DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) 4588 DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) 4589 DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) 4590 DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) 4591 DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) 4592 DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) 4593 DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) 4594 DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) 4595 DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) 4596 DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) 4597 DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) 4598 DECLARE_CSR(mstatush, CSR_MSTATUSH) 4599 DECLARE_CSR(mcycleh, CSR_MCYCLEH) 4600 DECLARE_CSR(minstreth, CSR_MINSTRETH) 4601 DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) 4602 DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) 4603 DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) 4604 DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) 4605 DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) 4606 DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) 4607 DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) 4608 DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) 4609 DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) 4610 DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) 4611 DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) 4612 DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) 4613 DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) 4614 DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) 4615 DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) 4616 DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) 4617 DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) 4618 DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) 4619 DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) 4620 DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) 4621 DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) 4622 DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) 4623 DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) 4624 DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) 4625 DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) 4626 DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) 4627 DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) 4628 DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) 4629 DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) 4630 #endif 4631 #ifdef DECLARE_CAUSE 4632 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) 4633 DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) 4634 DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) 4635 DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) 4636 DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) 4637 DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) 4638 DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) 4639 DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) 4640 DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) 4641 DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) 4642 DECLARE_CAUSE("virtual_supervisor_ecall", CAUSE_VIRTUAL_SUPERVISOR_ECALL) 4643 DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) 4644 DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) 4645 DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) 4646 DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) 4647 DECLARE_CAUSE("fetch guest page fault", CAUSE_FETCH_GUEST_PAGE_FAULT) 4648 DECLARE_CAUSE("load guest page fault", CAUSE_LOAD_GUEST_PAGE_FAULT) 4649 DECLARE_CAUSE("virtual instruction", CAUSE_VIRTUAL_INSTRUCTION) 4650 DECLARE_CAUSE("store guest page fault", CAUSE_STORE_GUEST_PAGE_FAULT) 4651 #endif 4652