1 /* $NetBSD: mvgbereg.h,v 1.8 2013/12/23 02:23:25 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2007, 2013 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef _MVGBEREG_H_ 28 #define _MVGBEREG_H_ 29 30 #define MVGBE_SIZE 0x4000 31 32 #define MVGBE_NWINDOW 6 33 #define MVGBE_NREMAP 4 34 35 #define MVGBE_PHY_TIMEOUT 10000 /* msec */ 36 37 /* 38 * Ethernet Unit Registers 39 */ 40 41 #define MVGBE_PRXC(q) (0x1400 + ((q) << 2)) /*Port RX queues Config*/ 42 #define MVGBE_PRXSNP(q) (0x1420 + ((q) << 2)) /* Port RX queues Snoop */ 43 #define MVGBE_PRXF01(q) (0x1440 + ((q) << 2)) /* Port RX Prefetch 0_1 */ 44 #define MVGBE_PRXF23(q) (0x1460 + ((q) << 2)) /* Port RX Prefetch 2_3 */ 45 #define MVGBE_PRXDQA(q) (0x1480 + ((q) << 2)) /*P RXqueues desc Q Addr*/ 46 #define MVGBE_PRXDQS(q) (0x14a0 + ((q) << 2)) /*P RXqueues desc Q Size*/ 47 #define MVGBE_PRXDQTH(q) (0x14c0 + ((q) << 2)) /*P RXqueues desc Q Thrs*/ 48 #define MVGBE_PRXS(q) (0x14e0 + ((q) << 2)) /*Port RX queues Status */ 49 #define MVGBE_PRXSU(q) (0x1500 + ((q) << 2)) /*P RXqueues Stat Update*/ 50 #define MVGBE_PPLBSZ(q) (0x1700 + ((q) << 2)) /* P Pool n Buffer Size */ 51 #define MVGBE_PRXFC 0x1710 /* Port RX Flow Control */ 52 #define MVGBE_PRXTXP 0x1714 /* Port RX_TX Pause */ 53 #define MVGBE_PRXFCG 0x1718 /* Port RX Flow Control Generation */ 54 #define MVGBE_PRXINIT 0x1cc0 /* Port RX Initialization */ 55 #define MVGBE_RXCTRL 0x1d00 /* RX Control */ 56 #define MVGBE_RXHWFWD(n) (0x1d10 + (((n) & ~0x1) << 1)) 57 /* RX Hardware Forwarding (0_1, 2_3,..., 8_9) */ 58 #define MVGBE_RXHWFWDPTR 0x1d30 /* RX Hardware Forwarding Pointer */ 59 #define MVGBE_RXHWFWDTH 0x1d40 /* RX Hardware Forwarding Threshold */ 60 #define MVGBE_RXHWFWDDQA 0x1d44 /* RX Hw Fwd Descriptors Queue Address*/ 61 #define MVGBE_RXHWFWDQS 0x1d48 /* RX Hw Fwd Descriptors Queue Size */ 62 #define MVGBE_RXHWFWDQENB 0x1d4c /* RX Hw Fwd Queue Enable */ 63 #define MVGBE_RXHWFWDACPT 0x1d50 /* RX Hw Forwarding Accepted Counter */ 64 #define MVGBE_RXHWFWDYDSCRD 0x1d54 /* RX Hw Fwd Yellow Discarded Counter */ 65 #define MVGBE_RXHWFWDGDSCRD 0x1d58 /* RX Hw Fwd Green Discarded Counter */ 66 #define MVGBE_RXHWFWDTHDSCRD 0x1d5c /*RX HwFwd Threshold Discarded Counter*/ 67 #define MVGBE_RXHWFWDTXGAP 0x1d6c /*RX Hardware Forwarding TX Access Gap*/ 68 69 /* Ethernet Unit Global Registers */ 70 #define MVGBE_PHYADDR 0x2000 71 #if defined(MV88W8660) 72 #define MVGBE_SMI 0x8010 73 #else 74 #define MVGBE_SMI 0x2004 75 #endif 76 #define MVGBE_EUDA 0x2008 /* Ethernet Unit Default Address */ 77 #define MVGBE_EUDID 0x200c /* Ethernet Unit Default ID */ 78 #define MVGBE_EU 0x2014 /* Ethernet Unit Reserved */ 79 #define MVGBE_EUIC 0x2080 /* Ethernet Unit Interrupt Cause */ 80 #define MVGBE_EUIM 0x2084 /* Ethernet Unit Interrupt Mask */ 81 #define MVGBE_EUEA 0x2094 /* Ethernet Unit Error Address */ 82 #define MVGBE_EUIAE 0x2098 /* Ethernet Unit Internal Addr Error */ 83 #define MVGBE_EUPCR 0x20a0 /* EthernetUnit Port Pads Calibration */ 84 #define MVGBE_EUC 0x20b0 /* Ethernet Unit Control */ 85 86 #define MVGBE_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */ 87 #define MVGBE_S(n) (0x2204 + ((n) << 3)) /* Size */ 88 #define MVGBE_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */ 89 #define MVGBE_BARE 0x2290 /* Base Address Enable */ 90 #define MVGBE_EPAP 0x2294 /* Ethernet Port Access Protect */ 91 92 /* Ethernet Unit Port Registers */ 93 #define MVGBE_PORTR_BASE 0x2400 94 #define MVGBE_PORTR_SIZE 0x400 95 96 #define MVGBE_PXC 0x000 /* Port Configuration */ 97 #define MVGBE_PXCX 0x004 /* Port Configuration Extend */ 98 #define MVGBE_MIISP 0x008 /* MII Serial Parameters */ 99 #define MVGBE_GMIISP 0x00c /* GMII Serial Params */ 100 #define MVGBE_EVLANE 0x010 /* VLAN EtherType */ 101 #define MVGBE_MACAL 0x014 /* MAC Address Low */ 102 #define MVGBE_MACAH 0x018 /* MAC Address High */ 103 #define MVGBE_SDC 0x01c /* SDMA Configuration */ 104 #define MVGBE_DSCP(n) (0x020 + ((n) << 2)) 105 #define MVGBE_PSC 0x03c /* Port Serial Control0 */ 106 #define MVGBE_VPT2P 0x040 /* VLAN Priority Tag to Priority */ 107 #define MVGBE_PS 0x044 /* Ethernet Port Status */ 108 #define MVGBE_TQC 0x048 /* Transmit Queue Command */ 109 #define MVGBE_PSC1 0x04c /* Port Serial Control1 */ 110 #define MVGBE_MH 0x054 /* Marvell Header */ 111 #define MVGBE_MTU 0x058 /* Max Transmit Unit */ 112 #define MVGBE_IC 0x060 /* Port Interrupt Cause */ 113 #define MVGBE_ICE 0x064 /* Port Interrupt Cause Extend */ 114 #define MVGBE_PIM 0x068 /* Port Interrupt Mask */ 115 #define MVGBE_PEIM 0x06c /* Port Extend Interrupt Mask */ 116 #define MVGBE_PRFUT 0x070 /* Port Rx FIFO Urgent Threshold */ 117 #define MVGBE_PTFUT 0x074 /* Port Tx FIFO Urgent Threshold */ 118 #define MVGBE_PXTFTT 0x078 /* Port Tx FIFO Threshold */ 119 #define MVGBE_PMFS 0x07c /* Port Rx Minimal Frame Size */ 120 #define MVGBE_PXDFC 0x084 /* Port Rx Discard Frame Counter */ 121 #define MVGBE_POFC 0x088 /* Port Overrun Frame Counter */ 122 #define MVGBE_PIAE 0x094 /* Port Internal Address Error */ 123 #define MVGBE_AIP0ADR 0x098 /* Arp IP0 Address */ 124 #define MVGBE_AIP1ADR 0x09c /* Arp IP1 Address */ 125 #define MVGBE_SERDESCFG 0x0a0 /* Serdes Configuration */ 126 #define MVGBE_SERDESSTS 0x0a4 /* Serdes Status */ 127 #define MVGBE_ETP 0x0bc /* Ethernet Type Priority */ 128 #define MVGBE_TQFPC 0x0dc /* Transmit Queue Fixed Priority Cfg */ 129 #define MVGBE_OMSCD 0x0f4 /* One mS Clock Divider */ 130 #define MVGBE_PFCCD 0x0f8 /* Periodic Flow Control Clock Divider*/ 131 #define MVGBE_PACC 0x100 /* Port Acceleration Mode */ 132 #define MVGBE_PBMADDR 0x104 /* Port BM Address */ 133 #define MVGBE_PV 0x1bc /* Port Version */ 134 #define MVGBE_CRDP(n) (0x20c + ((n) << 4)) 135 /* Ethernet Current Receive Descriptor Pointers */ 136 #define MVGBE_RQC 0x280 /* Receive Queue Command */ 137 #define MVGBE_TCSDP 0x284 /* Tx Current Served Desc Pointer */ 138 #define MVGBE_TCQDP 0x2c0 /* Tx Current Queue Desc Pointer */ 139 #define MVGBE_TQTBCOUNT(q) (0x300 + ((q) << 4)) 140 /* Transmit Queue Token-Bucket Counter */ 141 #define MVGBE_TQTBCONFIG(q) (0x304 + ((q) << 4)) 142 /* Transmit Queue Token-Bucket Configuration */ 143 #define MVGBE_TQAC(q) (0x308 + ((q) << 4)) 144 /* Transmit Queue Arbiter Configuration */ 145 146 #define MVGBE_PCP2Q(cpu) (0x2540 + ((cpu) << 2)) /* Port CPUn to Queue */ 147 #define MVGBE_PRXITTH(q) (0x2540 + ((q) << 2) /* Port RX Intr Threshold*/ 148 #define MVGBE_PRXTXTIC 0x25a0 /*Port RX_TX Threshold Interrupt Cause*/ 149 #define MVGBE_PRXTXTIM 0x25a4 /*Port RX_TX Threshold Interrupt Mask */ 150 #define MVGBE_PRXTXIC 0x25a8 /* Port RX_TX Interrupt Cause */ 151 #define MVGBE_PRXTXIM 0x25ac /* Port RX_TX Interrupt Mask */ 152 #define MVGBE_PMIC 0x25b0 /* Port Misc Interrupt Cause */ 153 #define MVGBE_PMIM 0x25b4 /* Port Misc Interrupt Mask */ 154 #define MVGBE_PIE 0x25b8 /* Port Interrupt Enable */ 155 156 #define MVGBE_PMACC0 0x2c00 /* Port MAC Control 0 */ 157 #define MVGBE_PMACC1 0x2c04 /* Port MAC Control 1 */ 158 #define MVGBE_PMACC2 0x2c08 /* Port MAC Control 2 */ 159 #define MVGBE_PANC 0x2c0c /* Port Auto-Negotiation Configuration*/ 160 #define MVGBE_PS0 0x2c10 /* Port Status 0 */ 161 #define MVGBE_PSPC 0x2c14 /* Port Serial Parameters Config */ 162 #define MVGBE_PIC_2 0x2c20 /* Port Interrupt Cause */ 163 #define MVGBE_PIM_2 0x2c24 /* Port Interrupt Mask */ 164 #define MVGBE_PPRBSS 0x2c38 /* Port PRBS Status */ 165 #define MVGBE_PPRBSEC 0x2c3c /* Port PRBS Error Counter */ 166 #define MVGBE_PMACC3 0x2c48 /* Port MAC Control 3 */ 167 #define MVGBE_CCFCPST(p) (0x2c58 + ((p) << 2)) /*CCFC Port Speed Timerp*/ 168 #define MVGBE_PMACC4 0x2c90 /* Port MAC Control 4 */ 169 #define MVGBE_PSP1C 0x2c94 /* Port Serial Parameters 1 Config */ 170 #define MVGBE_LPIC0 0x2cc0 /* LowPowerIdle control 0 */ 171 #define MVGBE_LPIC1 0x2cc4 /* LPI control 1 */ 172 #define MVGBE_LPIC2 0x2cc8 /* LPI control 2 */ 173 #define MVGBE_LPIS 0x2ccc /* LPI status */ 174 #define MVGBE_LPIC 0x2cd0 /* LPI counter */ 175 176 #define MVGBE_PPLLC 0x2e04 /* Power and PLL Control */ 177 #define MVGBE_DLE 0x2e8c /* Digital Loopback Enable */ 178 #define MVGBE_RCS 0x2f18 /* Reference Clock Select */ 179 180 /* MAC MIB Counters 0x3000 - 0x307c */ 181 182 /* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */ 183 184 #define MVGBE_PORTDAFR_BASE 0x3400 185 #define MVGBE_PORTDAFR_SIZE 0x400 186 187 #define MVGBE_NDFSMT 0x40 188 #define MVGBE_DFSMT 0x000 189 /* Destination Address Filter Special Multicast Table */ 190 #define MVGBE_NDFOMT 0x40 191 #define MVGBE_DFOMT 0x100 192 /* Destination Address Filter Other Multicast Table */ 193 #define MVGBE_NDFUT 0x4 194 #define MVGBE_DFUT 0x200 195 /* Destination Address Filter Unicast Table */ 196 197 #define MVGBE_PTXDQA(q) (0x3c00 + ((q) << 2)) /*P TXqueues desc Q Addr*/ 198 #define MVGBE_PTXDQS(q) (0x3c20 + ((q) << 2)) /*P TXqueues desc Q Size*/ 199 #define MVGBE_PTXS(q) (0x3c40 + ((q) << 2)) /* Port TX queues Status*/ 200 #define MVGBE_PTXSU(q) (0x3c60 + ((q) << 2)) /*P TXqueues Stat Update*/ 201 #define MVGBE_PTXDI(q) (0x3c80 + ((q) << 2)) /* P TXqueues Desc Index*/ 202 #define MVGBE_TXTBC(q) (0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/ 203 #define MVGBE_PTXINIT 0x3cf0 /* Port TX Initialization */ 204 #define MVGBE_PTXDOSD 0x3cf4 /* Port TX Disable Outstanding Reads */ 205 206 #define MVGBE_TXBADFCS 0x3cc0 /*Tx Bad FCS Transmitted Pckts Counter*/ 207 #define MVGBE_TXDROPPED 0x3cc4 /* Tx Dropped Packets Counter */ 208 #define MVGBE_TXNB 0x3cfc /* Tx Number of New Bytes */ 209 #define MVGBE_TXGB 0x3d00 /* Tx Green Number of Bytes */ 210 #define MVGBE_TXYB 0x3d04 /* Tx Yellow Number of Bytes */ 211 212 /* Tx DMA Packet Modification Registers 0x3d00 - 0x3dff */ 213 214 /* Tx DMA Queue Arbiter Registers 0x3e00 - 0x3eff */ 215 216 217 /* PHY Address (MVGBE_PHYADDR) */ 218 #define MVGBE_PHYADDR_PHYAD_MASK 0x1f 219 #define MVGBE_PHYADDR_PHYAD(port, phy) ((phy) << ((port) * 5)) 220 221 /* SMI register fields (MVGBE_SMI) */ 222 #define MVGBE_SMI_DATA_MASK 0x0000ffff 223 #define MVGBE_SMI_PHYAD(phy) (((phy) & 0x1f) << 16) 224 #define MVGBE_SMI_REGAD(reg) (((reg) & 0x1f) << 21) 225 #define MVGBE_SMI_OPCODE_WRITE (0 << 26) 226 #define MVGBE_SMI_OPCODE_READ (1 << 26) 227 #define MVGBE_SMI_READVALID (1 << 27) 228 #define MVGBE_SMI_BUSY (1 << 28) 229 230 /* Ethernet Unit Default ID (MVGBE_EUDID) */ 231 #define MVGBE_EUDID_DIDR_MASK 0x0000000f 232 #define MVGBE_EUDID_DATTR_MASK 0x00000ff0 233 234 /* Ethernet Unit Reserved (MVGBE_EU) */ 235 #define MVGBE_EU_FASTMDC (1 << 0) 236 #define MVGBE_EU_ACCS (1 << 1) 237 238 /* Ethernet Unit Interrupt Cause (MVGBE_EUIC) */ 239 #define MVGBE_EUIC_ETHERINTSUM (1 << 0) 240 #define MVGBE_EUIC_PARITY (1 << 1) 241 #define MVGBE_EUIC_ADDRVIOL (1 << 2) 242 #define MVGBE_EUIC_ADDRVNOMATCH (1 << 3) 243 #define MVGBE_EUIC_SMIDONE (1 << 4) 244 #define MVGBE_EUIC_COUNTWA (1 << 5) 245 #define MVGBE_EUIC_INTADDRERR (1 << 7) 246 #define MVGBE_EUIC_PORT0DPERR (1 << 9) 247 #define MVGBE_EUIC_TOPDPERR (1 << 12) 248 249 /* Ethernet Unit Internal Addr Error (MVGBE_EUIAE) */ 250 #define MVGBE_EUIAE_INTADDR_MASK 0x000001ff 251 252 /* Ethernet Unit Port Pads Calibration (MVGBE_EUPCR) */ 253 #define MVGBE_EUPCR_DRVN_MASK 0x0000001f 254 #define MVGBE_EUPCR_TUNEEN (1 << 16) 255 #define MVGBE_EUPCR_LOCKN_MASK 0x003e0000 256 #define MVGBE_EUPCR_OFFSET_MASK 0x1f000000 /* Reserved */ 257 #define MVGBE_EUPCR_WREN (1 << 31) 258 259 /* Ethernet Unit Control (MVGBE_EUC) */ 260 #define MVGBE_EUC_PORT0DPPAR (1 << 0) 261 #define MVGBE_EUC_POLLING (1 << 1) 262 #define MVGBE_EUC_TOPDPPAR (1 << 3) 263 #define MVGBE_EUC_PORT0PW (1 << 16) 264 #define MVGBE_EUC_PORTRESET (1 << 24) 265 #define MVGBE_EUC_RAMSINITIALIZATIONCOMPLETED (1 << 25) 266 267 /* Base Address (MVGBE_BASEADDR) */ 268 #define MVGBE_BASEADDR_TARGET(target) ((target) & 0xf) 269 #define MVGBE_BASEADDR_ATTR(attr) (((attr) & 0xff) << 8) 270 #define MVGBE_BASEADDR_BASE(base) ((base) & 0xffff0000) 271 272 /* Size (MVGBE_S) */ 273 #define MVGBE_S_SIZE(size) (((size) - 1) & 0xffff0000) 274 275 /* Base Address Enable (MVGBE_BARE) */ 276 #define MVGBE_BARE_EN_MASK ((1 << MVGBE_NWINDOW) - 1) 277 #define MVGBE_BARE_EN(win) ((1 << (win)) & MVGBE_BARE_EN_MASK) 278 279 /* Ethernet Port Access Protect (MVGBE_EPAP) */ 280 #define MVGBE_EPAP_AC_NAC 0x0 /* No access allowed */ 281 #define MVGBE_EPAP_AC_RO 0x1 /* Read Only */ 282 #define MVGBE_EPAP_AC_FA 0x3 /* Full access (r/w) */ 283 #define MVGBE_EPAP_EPAR(win, ac) ((ac) << ((win) * 2)) 284 285 /* Port Configuration (MVGBE_PXC) */ 286 #define MVGBE_PXC_UPM (1 << 0) /* Uni Promisc mode */ 287 #define MVGBE_PXC_RXQ(q) ((q) << 1) 288 #define MVGBE_PXC_RXQ_MASK MVGBE_PXC_RXQ(7) 289 #define MVGBE_PXC_RXQARP(q) ((q) << 4) 290 #define MVGBE_PXC_RXQARP_MASK MVGBE_PXC_RXQARP(7) 291 #define MVGBE_PXC_RB (1 << 7) /* Rej mode of MAC */ 292 #define MVGBE_PXC_RBIP (1 << 8) 293 #define MVGBE_PXC_RBARP (1 << 9) 294 #define MVGBE_PXC_AMNOTXES (1 << 12) 295 #define MVGBE_PXC_RBARPF (1 << 13) 296 #define MVGBE_PXC_TCPCAPEN (1 << 14) 297 #define MVGBE_PXC_UDPCAPEN (1 << 15) 298 #define MVGBE_PXC_TCPQ(q) ((q) << 16) 299 #define MVGBE_PXC_TCPQ_MASK MVGBE_PXC_TCPQ(7) 300 #define MVGBE_PXC_UDPQ(q) ((q) << 19) 301 #define MVGBE_PXC_UDPQ_MASK MVGBE_PXC_UDPQ(7) 302 #define MVGBE_PXC_BPDUQ(q) ((q) << 22) 303 #define MVGBE_PXC_BPDUQ_MASK MVGBE_PXC_BPDUQ(7) 304 #define MVGBE_PXC_RXCS (1 << 25) 305 306 /* Port Configuration Extend (MVGBE_PXCX) */ 307 #define MVGBE_PXCX_SPAN (1 << 1) 308 #define MVGBE_PXCX_TXCRCDIS (1 << 3) 309 310 /* MII Serial Parameters (MVGBE_MIISP) */ 311 #define MVGBE_MIISP_JAMLENGTH_12KBIT 0x00000000 312 #define MVGBE_MIISP_JAMLENGTH_24KBIT 0x00000001 313 #define MVGBE_MIISP_JAMLENGTH_32KBIT 0x00000002 314 #define MVGBE_MIISP_JAMLENGTH_48KBIT 0x00000003 315 #define MVGBE_MIISP_JAMIPG(x) (((x) & 0x7c) << 0) 316 #define MVGBE_MIISP_IPGJAMTODATA(x) (((x) & 0x7c) << 5) 317 #define MVGBE_MIISP_IPGDATA(x) (((x) & 0x7c) << 10) 318 #define MVGBE_MIISP_DATABLIND(x) (((x) & 0x1f) << 17) 319 320 /* GMII Serial Parameters (MVGBE_GMIISP) */ 321 #define MVGBE_GMIISP_IPGDATA(x) (((x) >> 4) & 0x7) 322 323 /* SDMA Configuration (MVGBE_SDC) */ 324 #define MVGBE_SDC_RIFB (1 << 0) 325 #define MVGBE_SDC_RXBSZ(x) ((x) << 1) 326 #define MVGBE_SDC_RXBSZ_MASK MVGBE_SDC_RXBSZ(7) 327 #define MVGBE_SDC_RXBSZ_1_64BITWORDS MVGBE_SDC_RXBSZ(0) 328 #define MVGBE_SDC_RXBSZ_2_64BITWORDS MVGBE_SDC_RXBSZ(1) 329 #define MVGBE_SDC_RXBSZ_4_64BITWORDS MVGBE_SDC_RXBSZ(2) 330 #define MVGBE_SDC_RXBSZ_8_64BITWORDS MVGBE_SDC_RXBSZ(3) 331 #define MVGBE_SDC_RXBSZ_16_64BITWORDS MVGBE_SDC_RXBSZ(4) 332 #define MVGBE_SDC_BLMR (1 << 4) 333 #define MVGBE_SDC_BLMT (1 << 5) 334 #define MVGBE_SDC_SWAPMODE (1 << 6) 335 #define MVGBE_SDC_IPGINTRX_V1_MASK __BITS(21, 8) 336 #define MVGBE_SDC_IPGINTRX_V2_MASK (__BIT(25) | __BITS(21, 7)) 337 #define MVGBE_SDC_IPGINTRX_V1(x) (((x) << 4) \ 338 & MVGBE_SDC_IPGINTRX_V1_MASK) 339 #define MVGBE_SDC_IPGINTRX_V2(x) ((((x) & 0x8000) << 10) \ 340 | (((x) & 0x7fff) << 7)) 341 #define MVGBE_SDC_IPGINTRX_V1_MAX 0x3fff 342 #define MVGBE_SDC_IPGINTRX_V2_MAX 0xffff 343 #define MVGBE_SDC_TXBSZ(x) ((x) << 22) 344 #define MVGBE_SDC_TXBSZ_MASK MVGBE_SDC_TXBSZ(7) 345 #define MVGBE_SDC_TXBSZ_1_64BITWORDS MVGBE_SDC_TXBSZ(0) 346 #define MVGBE_SDC_TXBSZ_2_64BITWORDS MVGBE_SDC_TXBSZ(1) 347 #define MVGBE_SDC_TXBSZ_4_64BITWORDS MVGBE_SDC_TXBSZ(2) 348 #define MVGBE_SDC_TXBSZ_8_64BITWORDS MVGBE_SDC_TXBSZ(3) 349 #define MVGBE_SDC_TXBSZ_16_64BITWORDS MVGBE_SDC_TXBSZ(4) 350 351 /* Port Serial Control (MVGBE_PSC) */ 352 #define MVGBE_PSC_PORTEN (1 << 0) 353 #define MVGBE_PSC_FLP (1 << 1) /* Force_Link_Pass */ 354 #define MVGBE_PSC_ANDUPLEX (1 << 2) /* auto nego */ 355 #define MVGBE_PSC_ANFC (1 << 3) 356 #define MVGBE_PSC_PAUSEADV (1 << 4) 357 #define MVGBE_PSC_FFCMODE (1 << 5) /* Force FC */ 358 #define MVGBE_PSC_FBPMODE (1 << 7) /* Back pressure */ 359 #define MVGBE_PSC_RESERVED (1 << 9) /* Must be set to 1 */ 360 #define MVGBE_PSC_FLFAIL (1 << 10) /* Force Link Fail */ 361 #define MVGBE_PSC_ANSPEED (1 << 13) 362 #define MVGBE_PSC_DTEADVERT (1 << 14) 363 #define MVGBE_PSC_MRU(x) ((x) << 17) 364 #define MVGBE_PSC_MRU_MASK MVGBE_PSC_MRU(7) 365 #define MVGBE_PSC_MRU_1518 0 366 #define MVGBE_PSC_MRU_1522 1 367 #define MVGBE_PSC_MRU_1552 2 368 #define MVGBE_PSC_MRU_9022 3 369 #define MVGBE_PSC_MRU_9192 4 370 #define MVGBE_PSC_MRU_9700 5 371 #define MVGBE_PSC_SETFULLDX (1 << 21) 372 #define MVGBE_PSC_SETFCEN (1 << 22) 373 #define MVGBE_PSC_SETGMIISPEED (1 << 23) 374 #define MVGBE_PSC_SETMIISPEED (1 << 24) 375 376 /* Ethernet Port Status (MVGBE_PS) */ 377 #define MVGBE_PS_LINKUP (1 << 1) 378 #define MVGBE_PS_FULLDX (1 << 2) 379 #define MVGBE_PS_ENFC (1 << 3) 380 #define MVGBE_PS_GMIISPEED (1 << 4) 381 #define MVGBE_PS_MIISPEED (1 << 5) 382 #define MVGBE_PS_TXINPROG (1 << 7) 383 #define MVGBE_PS_TXFIFOEMP (1 << 10) /* FIFO Empty */ 384 #define MVGBE_PS_RXFIFOEMPTY (1 << 16) 385 /* Armada XP */ 386 #define MVGBE_PS_TXINPROG_MASK (0xff << 0) 387 #define MVGBE_PS_TXINPROG_(q) (1 << ((q) + 0)) 388 #define MVGBE_PS_TXFIFOEMP_MASK (0xff << 8) 389 #define MVGBE_PS_TXFIFOEMP_(q) (1 << ((q) + 8)) 390 391 /* Transmit Queue Command (MVGBE_TQC) */ 392 #define MVGBE_TQC_ENQ(q) (1 << ((q) + 0))/* Enable Q */ 393 #define MVGBE_TQC_DISQ(q) (1 << ((q) + 8))/* Disable Q */ 394 395 /* Port Serial Control 1 (MVGBE_PSC1) */ 396 #define MVGBE_PSC1_PCSLB (1 << 1) 397 #define MVGBE_PSC1_RGMIIEN (1 << 3) /* RGMII */ 398 #define MVGBE_PSC1_PRST (1 << 4) /* Port Reset */ 399 400 /* Port Interrupt Cause (MVGBE_IC) */ 401 #define MVGBE_IC_RXBUF (1 << 0) 402 #define MVGBE_IC_EXTEND (1 << 1) 403 #define MVGBE_IC_RXBUFQ_MASK (0xff << 2) 404 #define MVGBE_IC_RXBUFQ(q) (1 << ((q) + 2)) 405 #define MVGBE_IC_RXERROR (1 << 10) 406 #define MVGBE_IC_RXERRQ_MASK (0xff << 11) 407 #define MVGBE_IC_RXERRQ(q) (1 << ((q) + 11)) 408 #define MVGBE_IC_TXEND(q) (1 << ((q) + 19)) 409 #define MVGBE_IC_ETHERINTSUM (1 << 31) 410 411 /* Port Interrupt Cause Extend (MVGBE_ICE) */ 412 #define MVGBE_ICE_TXBUF_MASK (0xff << + 0) 413 #define MVGBE_ICE_TXBUF(q) (1 << ((q) + 0)) 414 #define MVGBE_ICE_TXERR_MASK (0xff << + 8) 415 #define MVGBE_ICE_TXERR(q) (1 << ((q) + 8)) 416 #define MVGBE_ICE_PHYSTC (1 << 16) 417 #define MVGBE_ICE_PTP (1 << 17) 418 #define MVGBE_ICE_RXOVR (1 << 18) 419 #define MVGBE_ICE_TXUDR (1 << 19) 420 #define MVGBE_ICE_LINKCHG (1 << 20) 421 #define MVGBE_ICE_SERDESREALIGN (1 << 21) 422 #define MVGBE_ICE_INTADDRERR (1 << 23) 423 #define MVGBE_ICE_SYNCCHANGED (1 << 24) 424 #define MVGBE_ICE_PRBSERROR (1 << 25) 425 #define MVGBE_ICE_ETHERINTSUM (1 << 31) 426 427 /* Port Tx FIFO Urgent Threshold (MVGBE_PTFUT) */ 428 #define MVGBE_PTFUT_IPGINTTX_V1_MASK __BITS(17, 4) 429 #define MVGBE_PTFUT_IPGINTTX_V2_MASK __BITS(19, 4) 430 #define MVGBE_PTFUT_IPGINTTX_V1(x) __SHIFTIN(x, MVGBE_PTFUT_IPGINTTX_V1_MASK) 431 #define MVGBE_PTFUT_IPGINTTX_V2(x) __SHIFTIN(x, MVGBE_PTFUT_IPGINTTX_V2_MASK) 432 #define MVGBE_PTFUT_IPGINTTX_V1_MAX 0x3fff 433 #define MVGBE_PTFUT_IPGINTTX_V2_MAX 0xffff 434 435 /* Port Rx Minimal Frame Size (MVGBE_PMFS) */ 436 #define MVGBE_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c) 437 /* RxMFS = 40,44,48,52,56,60,64 bytes */ 438 439 /* Transmit Queue Fixed Priority Configuration */ 440 #define MVGBE_TQFPC_EN(q) (1 << (q)) 441 442 /* Receive Queue Command (MVGBE_RQC) */ 443 #define MVGBE_RQC_ENQ_MASK (0xff << 0) /* Enable Q */ 444 #define MVGBE_RQC_ENQ(n) (1 << (0 + (n))) 445 #define MVGBE_RQC_DISQ_MASK (0xff << 8) /* Disable Q */ 446 #define MVGBE_RQC_DISQ(n) (1 << (8 + (n))) 447 #define MVGBE_RQC_DISQ_DISABLE(q) ((q) << 8) 448 449 /* Destination Address Filter Registers (MVGBE_DF{SM,OM,U}T) */ 450 #define MVGBE_DF(n, x) ((x) << (8 * (n))) 451 #define MVGBE_DF_PASS (1 << 0) 452 #define MVGBE_DF_QUEUE(q) ((q) << 1) 453 #define MVGBE_DF_QUEUE_MASK ((7) << 1) 454 455 456 /* Port Acceleration Mode (MVGBE_PACC) */ 457 #define MVGVE_PACC_ACCELERATIONMODE_MASK 0x7 458 #define MVGVE_PACC_ACCELERATIONMODE_BM 0x0 /* Basic Mode */ 459 #define MVGVE_PACC_ACCELERATIONMODE_EDM 0x1 /* Enhanced Desc Mode */ 460 #define MVGVE_PACC_ACCELERATIONMODE_EDMBM 0x2 /* with BM */ 461 #define MVGVE_PACC_ACCELERATIONMODE_EDMPNC 0x3 /* with PnC */ 462 #define MVGVE_PACC_ACCELERATIONMODE_EDMBPMNC 0x4 /* with BM & PnC */ 463 464 /* Port BM Address (MVGBE_PBMADDR) */ 465 #define MVGBE_PBMADDR_BMADDRESS_MASK 0xfffff800 466 467 /* Ether Type Priority (MVGBE_ETP) */ 468 #define MVGBE_ETP_ETHERTYPEPRIEN (1 << 0) /* EtherType Prio Ena */ 469 #define MVGBE_ETP_ETHERTYPEPRIFRSTEN (1 << 1) 470 #define MVGBE_ETP_ETHERTYPEPRIQ (0x7 << 2) /*EtherType Prio Queue*/ 471 #define MVGBE_ETP_ETHERTYPEPRIVAL (0xffff << 5) /*EtherType Prio Value*/ 472 #define MVGBE_ETP_FORCEUNICSTHIT (1 << 21) /* Force Unicast hit */ 473 474 /* RX Hardware Forwarding (0_1, 2_3,..., 8_9) (MVGBE_RXHWFWD) */ 475 #define MVGBE_RXHWFWD_PORT_BASEADDRESS(p, x) xxxxx 476 477 /* RX Hardware Forwarding Pointer (MVGBE_RXHWFWDPTR) */ 478 #define MVGBE_RXHWFWDPTR_QUEUENO(q) ((q) << 8) /* Queue Number */ 479 #define MVGBE_RXHWFWDPTR_PORTNO(p) ((p) << 11) /* Port Number */ 480 481 /* RX Hardware Forwarding Threshold (MVGBE_RXHWFWDTH) */ 482 #define MVGBE_RXHWFWDTH_DROPRNDGENBITS(n) (((n) & 0x3ff) << 0) 483 #define MVGBE_RXHWFWDTH_DROPTHRESHOLD(n) (((n) & 0xf) << 16) 484 485 /* RX Control (MVGBE_RXCTRL) */ 486 #define MVGBE_RXCTRL_PACKETCOLORSRCSELECT(x) (1 << 0) 487 #define MVGBE_RXCTRL_GEMPORTIDSRCSEL(x) ((x) << 4) 488 #define MVGBE_RXCTRL_TXHWFRWMQSRC(x) (1 << 8) 489 #define MVGBE_RXCTRL_RX_MH_SELECT(x) ((x) << 12) 490 #define MVGBE_RXCTRL_RX_TX_SRC_SELECT (1 << 16) 491 #define MVGBE_RXCTRL_HWFRWDENB (1 << 17) 492 #define MVGBE_RXCTRL_HWFRWDSHORTPOOLID(id) (((id) & 0x3) << 20) 493 #define MVGBE_RXCTRL_HWFRWDLONGPOOLID(id) (((id) & 0x3) << 22) 494 495 /* Port RX queues Configuration (MVGBE_PRXC) */ 496 #define MVGBE_PRXC_POOLIDSHORT(i) (((i) & 0x3) << 4) 497 #define MVGBE_PRXC_POOLIDLONG(i) (((i) & 0x3) << 6) 498 #define MVGBE_PRXC_PACKETOFFSET(o) (((o) & 0xf) << 8) 499 #define MVGBE_PRXC_USERPREFETCHCMND0 (1 << 16) 500 501 /* Port RX queues Snoop (MVGBE_PRXSNP) */ 502 #define MVGBE_PRXSNP_SNOOPNOOFBYTES(b) (((b) & 0x3fff) << 0) 503 #define MVGBE_PRXSNP_L2DEPOSITNOOFBYTES(b) (((b) & 0x3fff) << 16) 504 505 /* Port RX queues Snoop (MVGBE_PRXSNP) */ 506 #define MVGBE_PRXF01_PREFETCHCOMMAND0(c) (((c) & 0xffff) << 0) xxxx 507 #define MVGBE_PRXF01_PREFETCHCOMMAND1(c) (((c) & 0xffff) << 16) xxxx 508 509 /* Port RX queues Descriptors Queue Size (MVGBE_PRXDQS) */ 510 #define MVGBE_PRXDQS_DESCRIPTORSQUEUESIZE(s) (((s) & 0x0003fff) << 0) 511 #define MVGBE_PRXDQS_BUFFERSIZE(s) (((s) & 0xfff80000) << 19) 512 513 /* Port RX queues Descriptors Queue Threshold (MVGBE_PRXDQTH) */ 514 /* Occupied Descriptors Threshold */ 515 #define MVGBE_PRXDQTH_ODT(x) (((x) & 0x3fff) << 0) 516 /* Non Occupied Descriptors Threshold */ 517 #define MVGBE_PRXDQTH_NODT(x) (((x) & 0x3fff) << 16) 518 519 /* Port RX queues Status (MVGBE_PRXS) */ 520 /* Occupied Descriptors Counter */ 521 #define MVGBE_PRXS_ODC(x) (((x) & 0x3fff) << 0) 522 /* Non Occupied Descriptors Counter */ 523 #define MVGBE_PRXS_NODC(x) (((x) & 0x3fff) << 16) 524 525 /* Port RX queues Status Update (MVGBE_PRXSU) */ 526 #define MVGBE_PRXSU_NOOFPROCESSEDDESCRIPTORS(x) (((x) & 0xff) << 0) 527 #define MVGBE_PRXSU_NOOFNEWDESCRIPTORS(x) (((x) & 0xff) << 16) 528 529 /* Port RX Flow Control (MVGBE_PRXFC) */ 530 #define MVGBE_PRXFC_PERPRIOFCGENCONTROL (1 << 0) 531 #define MVGBE_PRXFC_TXPAUSECONTROL (1 << 1) 532 533 /* Port RX_TX Pause (MVGBE_PRXTXP) */ 534 #define MVGBE_PRXTXP_TXPAUSE(x) ((x) & 0xff) 535 536 /* Port RX Flow Control Generation (MVGBE_PRXFCG) */ 537 #define MVGBE_PRXFCG_PERPRIOFCGENDATA (1 << 0) 538 #define MVGBE_PRXFCG_PERPRIOFCGENQNO(x) (((x) & 0x7) << 4) 539 540 /* Port RX Initialization (MVGBE_PRXINIT) */ 541 #define MVGBE_PRXINIT_RXDMAINIT (1 << 0) 542 543 /* TX Number of New Bytes (MVGBE_TXNB) */ 544 #define MVGBE_TXNB_NOOFNEWBYTES(b) (((b) & 0xffff) << 0) 545 #define MVGBE_TXNB_PKTQNO(q) (((q) & 0x7) << 28) 546 #define MVGBE_TXNB_PKTCOLOR (1 << 31) 547 548 /* Port TX queues Descriptors Queue Size (MVGBE_PTXDQS) */ 549 /* Descriptors Queue Size */ 550 #define MVGBE_PTXDQS_DQS(x) (((x) & 0x3fff) << 0) 551 /* Transmitted Buffer Threshold */ 552 #define MVGBE_PTXDQS_TBT(x) (((x) & 0x3fff) << 16) 553 554 /* Port TX queues Status (MVGBE_PTXS) */ 555 /* Pending Descriptors Counter */ 556 #define MVGBE_PTXDQS_PDC(x) (((x) & 0x3fff) << 0) 557 /* Transmitted Buffer Counter */ 558 #define MVGBE_PTXS_TBC(x) (((x) & 0x3fff) << 16) 559 560 /* Port TX queues Status Update (MVGBE_PTXSU) */ 561 /* Number Of Written Descriptoes */ 562 #define MVGBE_PTXSU_NOWD(x) (((x) & 0xff) << 0) 563 /* Number Of Released Buffers */ 564 #define MVGBE_PTXSU_NORB(x) (((x) & 0xff) << 16) 565 566 /* TX Transmitted Buffers Counter (MVGBE_TXTBC) */ 567 /* Transmitted Buffers Counter */ 568 #define MVGBE_TXTBC_TBC(x) (((x) & 0x3fff) << 16) 569 570 /* Port TX Initialization (MVGBE_PTXINIT) */ 571 #define MVGBE_PTXINIT_TXDMAINIT (1 << 0) 572 573 /* Marvell Header (MVGBE_MH) */ 574 #define MVGBE_MH_MHEN (1 << 0) 575 #define MVGBE_MH_DAPREFIX (0x3 << 1) 576 #define MVGBE_MH_SPID (0xf << 4) 577 #define MVGBE_MH_MHMASK (0x3 << 8) 578 #define MVGBE_MH_MHMASK_8QUEUES (0x0 << 8) 579 #define MVGBE_MH_MHMASK_4QUEUES (0x1 << 8) 580 #define MVGBE_MH_MHMASK_2QUEUES (0x3 << 8) 581 #define MVGBE_MH_DSAEN_MASK (0x3 << 10) 582 #define MVGBE_MH_DSAEN_DISABLE (0x0 << 10) 583 #define MVGBE_MH_DSAEN_NONEXTENDED (0x1 << 10) 584 #define MVGBE_MH_DSAEN_EXTENDED (0x2 << 10) 585 586 /* Port Auto-Negotiation Configuration (MVGBE_PANC) */ 587 #define MVGBE_PANC_FORCELINKFAIL (1 << 0) 588 #define MVGBE_PANC_FORCELINKPASS (1 << 1) 589 #define MVGBE_PANC_INBANDANEN (1 << 2) 590 #define MVGBE_PANC_INBANDANBYPASSEN (1 << 3) 591 #define MVGBE_PANC_INBANDRESTARTAN (1 << 4) 592 #define MVGBE_PANC_SETMIISPEED (1 << 5) 593 #define MVGBE_PANC_SETGMIISPEED (1 << 6) 594 #define MVGBE_PANC_ANSPEEDEN (1 << 7) 595 #define MVGBE_PANC_SETFCEN (1 << 8) 596 #define MVGBE_PANC_PAUSEADV (1 << 9) 597 #define MVGBE_PANC_ANFCEN (1 << 11) 598 #define MVGBE_PANC_SETFULLDX (1 << 12) 599 #define MVGBE_PANC_ANDUPLEXEN (1 << 13) 600 #define MVGBE_PANC_RESERVED (1 << 15) 601 602 /* Port MAC Control 0 (MVGBE_PMACC0) */ 603 #define MVGBE_PMACC0_PORTEN (1 << 0) 604 #define MVGBE_PMACC0_PORTTYPE (1 << 1) 605 #define MVGBE_PMACC0_FRAMESIZELIMIT(x) ((((x) >> 1) & 0x7ffc) << 2) 606 #define MVGBE_PMACC0_RESERVED (1 << 15) 607 608 /* Port MAC Control 1 (MVGBE_PMACC1) */ 609 #define MVGBE_PMACC1_PCSLB (1 << 6) 610 611 /* Port MAC Control 2 (MVGBE_PMACC2) */ 612 #define MVGBE_PMACC2_PCSEN (1 << 3) 613 #define MVGBE_PMACC2_RGMIIEN (1 << 4) 614 #define MVGBE_PMACC2_PADDINGDIS (1 << 5) 615 #define MVGBE_PMACC2_PORTMACRESET (1 << 6) 616 #define MVGBE_PMACC2_PRBSCHECKEN (1 << 10) 617 #define MVGBE_PMACC2_PRBSGENEN (1 << 11) 618 #define MVGBE_PMACC2_SDTT_MASK (3 << 12) /* Select Data To Transmit */ 619 #define MVGBE_PMACC2_SDTT_RM (0 << 12) /* Regular Mode */ 620 #define MVGBE_PMACC2_SDTT_PRBS (1 << 12) /* PRBS Mode */ 621 #define MVGBE_PMACC2_SDTT_ZC (2 << 12) /* Zero Constant */ 622 #define MVGBE_PMACC2_SDTT_OC (3 << 12) /* One Constant */ 623 #define MVGBE_PMACC2_RESERVED (3 << 14) 624 625 /* Port MAC Control 3 (MVGBE_PMACC3) */ 626 #define MVGBE_PMACC3_IPG_MASK 0x7f80 627 628 /* Port Interrupt Cause/Mask (MVGBE_PIC_2/MVGBE_PIM_2) */ 629 #define MVGBE_PI_2_INTSUM (1 << 0) 630 #define MVGBE_PI_2_LSC (1 << 1) /* LinkStatus Change */ 631 #define MVGBE_PI_2_ACOP (1 << 2) /* AnCompleted OnPort */ 632 #define MVGBE_PI_2_AOOR (1 << 5) /* AddressOut Of Range */ 633 #define MVGBE_PI_2_SSC (1 << 6) /* SyncStatus Change */ 634 #define MVGBE_PI_2_PRBSEOP (1 << 7) /* QSGMII PRBS error */ 635 #define MVGBE_PI_2_MIBCWA (1 << 15) /* MIB counter wrap around */ 636 #define MVGBE_PI_2_QSGMIIPRBSE (1 << 10) /* QSGMII PRBS error */ 637 #define MVGBE_PI_2_PCSRXPRLPI (1 << 11) /* PCS Rx path received LPI*/ 638 #define MVGBE_PI_2_PCSTXPRLPI (1 << 12) /* PCS Tx path received LPI*/ 639 #define MVGBE_PI_2_MACRXPRLPI (1 << 13) /* MAC Rx path received LPI*/ 640 #define MVGBE_PI_2_MIBCCD (1 << 14) /* MIB counters copy done */ 641 642 /* LPI Control 0 (MVGBE_LPIC0) */ 643 #define MVGBE_LPIC0_LILIMIT(x) (((x) & 0xff) << 0) 644 #define MVGBE_LPIC0_TSLIMIT(x) (((x) & 0xff) << 8) 645 646 /* LPI Control 1 (MVGBE_LPIC1) */ 647 #define MVGBE_LPIC1_LPIRE (1 << 0) /* LPI request enable */ 648 #define MVGBE_LPIC1_LPIRF (1 << 1) /* LPI request force */ 649 #define MVGBE_LPIC1_LPIMM (1 << 2) /* LPI manual mode */ 650 #define MVGBE_LPIC1_TWLIMIT (((x) & 0xfff) << 4) 651 652 /* LPI Status (MVGBE_LPIS) */ 653 #define MVGBE_LPIS_PCSRXPLPIS (1 << 0) /* PCS Rx path LPI status */ 654 #define MVGBE_LPIS_PCSTXPLPIS (1 << 1) /* PCS Tx path LPI status */ 655 #define MVGBE_LPIS_MACRXPLPIS (1 << 2)/* MAC Rx path LP idle status */ 656 #define MVGBE_LPIS_MACTXPLPWS (1 << 3)/* MAC Tx path LP wait status */ 657 #define MVGBE_LPIS_MACTXPLPIS (1 << 4)/* MAC Tx path LP idle status */ 658 659 /* Port PRBS Status (MVGBE_PPRBSS) */ 660 #define MVGBE_PPRBSS_PRBSCHECKLOCKED (1 << 0) 661 #define MVGBE_PPRBSS_PRBSCHECKRDY (1 << 1) 662 663 /* Port Status 0 (MVGBE_PS0) */ 664 #define MVGBE_PS0_LINKUP (1 << 0) 665 #define MVGBE_PS0_GMIISPEED (1 << 1) 666 #define MVGBE_PS0_MIISPEED (1 << 2) 667 #define MVGBE_PS0_FULLDX (1 << 3) 668 #define MVGBE_PS0_RXFCEN (1 << 4) 669 #define MVGBE_PS0_TXFCEN (1 << 5) 670 #define MVGBE_PS0_PRP (1 << 6) /* Port Rx Pause */ 671 #define MVGBE_PS0_PTP (1 << 7) /* Port Tx Pause */ 672 #define MVGBE_PS0_PDP (1 << 8) /*Port is Doing Back-Pressure*/ 673 #define MVGBE_PS0_SYNCFAIL10MS (1 << 10) 674 #define MVGBE_PS0_ANDONE (1 << 11) 675 #define MVGBE_PS0_IBANBA (1 << 12) /* InBand AutoNeg BypassAct */ 676 #define MVGBE_PS0_SYNCOK (1 << 14) 677 678 /* Port CPUn to Queue (MVGBE_PCP2Q) */ 679 #define MVGBE_PCP2Q_RXQAE(q) (1 << ((q) + << 0))/*QueueAccessEnable*/ 680 #define MVGBE_PCP2Q_TXQAE(q) (1 << ((q) + << 8))/*QueueAccessEnable*/ 681 682 /* Port RX_TX Threshold Interrupt Cause/Mask (MVGBE_PRXTXTIC/MVGBE_PRXTXTIM) */ 683 #define MVGBE_PRXTXTI_TBTCQ(q) (1 << ((q) + 0)) 684 #define MVGBE_PRXTXTI_RBICTAPQ(q) (1 << ((q) + 8)) 685 #define MVGBE_PRXTXTI_RDTAQ(q) (1 << ((q) + 16)) 686 #define MVGBE_PRXTXTI_PRXTXICSUMMARY (1 << 29) 687 #define MVGBE_PRXTXTI_PTXERRORSUMMARY (1 << 30) 688 #define MVGBE_PRXTXTI_PMISCICSUMMARY (1 << 31) 689 690 /* Port RX_TX Interrupt Cause/Mask (MVGBE_PRXTXIC/MVGBE_PRXTXIM) */ 691 #define MVGBE_PRXTXI_TBRQ(q) (1 << ((q) + 0)) 692 #define MVGBE_PRXTXI_RPQ(q) (1 << ((q) + 8)) 693 #define MVGBE_PRXTXI_RREQ(q) (1 << ((q) + 16)) 694 #define MVGBE_PRXTXI_PRXTXTHICSUMMARY (1 << 29) 695 #define MVGBE_PRXTXI_PTXERRORSUMMARY (1 << 30) 696 #define MVGBE_PRXTXI_PMISCICSUMMARY (1 << 31) 697 698 /* Port Misc Interrupt Cause/Mask (MVGBE_PMIC/MVGBE_PMIM) */ 699 #define MVGBE_PMI_PHYSTATUSCHNG (1 << 0) 700 #define MVGBE_PMI_LINKCHANGE (1 << 1) 701 #define MVGBE_PMI_PTP (1 << 4) 702 #define MVGBE_PMI_PME (1 << 6) /* Packet Modification Error */ 703 #define MVGBE_PMI_IAE (1 << 7) /* Internal Address Error */ 704 #define MVGBE_PMI_RXOVERRUN (1 << 8) 705 #define MVGBE_PMI_RXCRCERROR (1 << 9) 706 #define MVGBE_PMI_RXLARGEPACKET (1 << 10) 707 #define MVGBE_PMI_TXUNDRN (1 << 11) 708 #define MVGBE_PMI_PRBSERROR (1 << 12) 709 #define MVGBE_PMI_SRSE (1 << 14) /* SerdesRealignSyncError */ 710 #define MVGBE_PMI_RNBTP(q) (1 << ((q) + 16)) /* RxNoBuffersToPool*/ 711 #define MVGBE_PMI_TREQ(q) (1 << ((q) + 24)) /* TxResourceErrorQ */ 712 713 /* Port Interrupt Enable (MVGBE_PIE) */ 714 #define MVGBE_PIE_RXPKTINTRPTENB(q) (1 << ((q) + 0)) 715 #define MVGBE_PIE_TXPKTINTRPTENB(q) (1 << ((q) + 8)) 716 717 /* Power and PLL Control (MVGBE_PPLLC) */ 718 #define MVGBE_PPLLC_REF_FREF_SEL_MASK (0xf << 0) 719 #define MVGBE_PPLLC_PHY_MODE_MASK (7 << 5) 720 #define MVGBE_PPLLC_PHY_MODE_SATA (0 << 5) 721 #define MVGBE_PPLLC_PHY_MODE_SAS (1 << 5) 722 #define MVGBE_PPLLC_PLL_LOCK (1 << 8) 723 #define MVGBE_PPLLC_PU_DFE (1 << 10) 724 #define MVGBE_PPLLC_PU_TX_INTP (1 << 11) 725 #define MVGBE_PPLLC_PU_TX (1 << 12) 726 #define MVGBE_PPLLC_PU_RX (1 << 13) 727 #define MVGBE_PPLLC_PU_PLL (1 << 14) 728 729 /* Digital Loopback Enable (MVGBE_DLE) */ 730 #define MVGBE_DLE_LOCAL_SEL_BITS_MASK (3 << 10) 731 #define MVGBE_DLE_LOCAL_SEL_BITS_10BITS (0 << 10) 732 #define MVGBE_DLE_LOCAL_SEL_BITS_20BITS (1 << 10) 733 #define MVGBE_DLE_LOCAL_SEL_BITS_40BITS (2 << 10) 734 #define MVGBE_DLE_LOCAL_RXPHER_TO_TX_EN (1 << 12) 735 #define MVGBE_DLE_LOCAL_ANA_TX2RX_LPBK_EN (1 << 13) 736 #define MVGBE_DLE_LOCAL_DIG_TX2RX_LPBK_EN (1 << 14) 737 #define MVGBE_DLE_LOCAL_DIG_RX2TX_LPBK_EN (1 << 15) 738 739 /* Reference Clock Select (MVGBE_RCS) */ 740 #define MVGBE_RCS_REFCLK_SEL (1 << 10) 741 742 743 /* 744 * Set the chip's packet size limit to 9022. 745 * (ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) 746 */ 747 #define MVGBE_MRU 9022 748 749 #define MVGBE_RXBUF_ALIGN 32 /* Cache line size */ 750 #define MVGBE_RXBUF_MASK (MVGBE_RXBUF_ALIGN - 1) 751 #define MVGBE_HWHEADER_SIZE 2 752 753 754 /* 755 * DMA descriptors 756 * Despite the documentation saying these descriptors only need to be 757 * aligned to 16-byte bondaries, 32-byte alignment seems to be required 758 * by the hardware. We'll just pad them out to that to make it easier. 759 */ 760 struct mvgbe_tx_desc { 761 #if BYTE_ORDER == BIG_ENDIAN 762 uint16_t bytecnt; /* Descriptor buffer byte count */ 763 uint16_t l4ichk; /* CPU provided TCP Checksum */ 764 uint32_t cmdsts; /* Descriptor command status */ 765 uint32_t nextdescptr; /* Next descriptor pointer */ 766 uint32_t bufptr; /* Descriptor buffer pointer */ 767 #else /* LITTLE_ENDIAN */ 768 uint32_t cmdsts; /* Descriptor command status */ 769 uint16_t l4ichk; /* CPU provided TCP Checksum */ 770 uint16_t bytecnt; /* Descriptor buffer byte count */ 771 uint32_t bufptr; /* Descriptor buffer pointer */ 772 uint32_t nextdescptr; /* Next descriptor pointer */ 773 #endif 774 uint32_t _padding[4]; 775 } __packed; 776 777 struct mvgbe_rx_desc { 778 #if BYTE_ORDER == BIG_ENDIAN 779 uint16_t bytecnt; /* Descriptor buffer byte count */ 780 uint16_t bufsize; /* Buffer size */ 781 uint32_t cmdsts; /* Descriptor command status */ 782 uint32_t nextdescptr; /* Next descriptor pointer */ 783 uint32_t bufptr; /* Descriptor buffer pointer */ 784 #else /* LITTLE_ENDIAN */ 785 uint32_t cmdsts; /* Descriptor command status */ 786 uint16_t bufsize; /* Buffer size */ 787 uint16_t bytecnt; /* Descriptor buffer byte count */ 788 uint32_t bufptr; /* Descriptor buffer pointer */ 789 uint32_t nextdescptr; /* Next descriptor pointer */ 790 #endif 791 uint32_t _padding[4]; 792 } __packed; 793 794 #define MVGBE_ERROR_SUMMARY (1 << 0) 795 #define MVGBE_BUFFER_OWNED_MASK (1 << 31) 796 #define MVGBE_BUFFER_OWNED_BY_HOST (0 << 31) 797 #define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31) 798 799 #define MVGBE_TX_ERROR_CODE_MASK (3 << 1) 800 #define MVGBE_TX_LATE_COLLISION_ERROR (0 << 1) 801 #define MVGBE_TX_UNDERRUN_ERROR (1 << 1) 802 #define MVGBE_TX_EXCESSIVE_COLLISION_ERRO (2 << 1) 803 #define MVGBE_TX_LLC_SNAP_FORMAT (1 << 9) 804 #define MVGBE_TX_IP_NO_FRAG (1 << 10) 805 #define MVGBE_TX_IP_HEADER_LEN(len) ((len) << 11) 806 #define MVGBE_TX_VLAN_TAGGED_FRAME (1 << 15) 807 #define MVGBE_TX_L4_TYPE_TCP (0 << 16) 808 #define MVGBE_TX_L4_TYPE_UDP (1 << 16) 809 #define MVGBE_TX_GENERATE_L4_CHKSUM (1 << 17) 810 #define MVGBE_TX_GENERATE_IP_CHKSUM (1 << 18) 811 #define MVGBE_TX_ZERO_PADDING (1 << 19) 812 #define MVGBE_TX_LAST_DESC (1 << 20) 813 #define MVGBE_TX_FIRST_DESC (1 << 21) 814 #define MVGBE_TX_GENERATE_CRC (1 << 22) 815 #define MVGBE_TX_ENABLE_INTERRUPT (1 << 23) 816 #define MVGBE_TX_AUTO_MODE (1 << 30) 817 818 #define MVGBE_RX_ERROR_CODE_MASK (3 << 1) 819 #define MVGBE_RX_CRC_ERROR (0 << 1) 820 #define MVGBE_RX_OVERRUN_ERROR (1 << 1) 821 #define MVGBE_RX_MAX_FRAME_LEN_ERROR (2 << 1) 822 #define MVGBE_RX_RESOURCE_ERROR (3 << 1) 823 #define MVGBE_RX_L4_CHECKSUM_MASK (0xffff << 3) 824 #define MVGBE_RX_VLAN_TAGGED_FRAME (1 << 19) 825 #define MVGBE_RX_BPDU_FRAME (1 << 20) 826 #define MVGBE_RX_L4_TYPE_MASK (3 << 21) 827 #define MVGBE_RX_L4_TYPE_TCP (0 << 21) 828 #define MVGBE_RX_L4_TYPE_UDP (1 << 21) 829 #define MVGBE_RX_L4_TYPE_OTHER (2 << 21) 830 #define MVGBE_RX_NOT_LLC_SNAP_FORMAT (1 << 23) 831 #define MVGBE_RX_IP_FRAME_TYPE (1 << 24) 832 #define MVGBE_RX_IP_HEADER_OK (1 << 25) 833 #define MVGBE_RX_LAST_DESC (1 << 26) 834 #define MVGBE_RX_FIRST_DESC (1 << 27) 835 #define MVGBE_RX_UNKNOWN_DA (1 << 28) 836 #define MVGBE_RX_ENABLE_INTERRUPT (1 << 29) 837 #define MVGBE_RX_L4_CHECKSUM_OK (1 << 30) 838 839 #define MVGBE_RX_IP_FRAGMENT (1 << 2) 840 841 #endif /* _MVGEREG_H_ */ 842