1 /** 2 * \file mykonos_macros.h 3 * \brief Contains address and miscellaneous macro definitions for Mykonos API 4 * 5 * Mykonos API version: 1.5.1.3565 6 */ 7 8 /** 9 * \page Disclaimer Legal Disclaimer 10 * Copyright 2015-2017 Analog Devices Inc. 11 * Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. 12 * 13 */ 14 15 #ifndef CLEMENTE_TDD_MACROS_H 16 #define CLEMENTE_TDD_MACROS_H 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #define MYKONOS_ADDR_CONFIGURATION_CONTROL_0 0x000 23 #define MYKONOS_ADDR_SPI_CONFIGURATION_CONTROL_1 0x001 24 #define MYKONOS_ADDR_PRODUCT_ID 0x004 25 #define MYKONOS_GPIO_DRV_CTL_0 0x020 26 #define MYKONOS_GPIO_DRV_CTL_1 0x021 27 #define MYKONOS_GPIO_SLEW_CTL_0 0x022 28 #define MYKONOS_GPIO_SLEW_CTL_1 0x023 29 #define MYKONOS_GPIO_SLEW_CTL_2 0x024 30 #define MYKONOS_GPIO_SLEW_CTL_3 0x025 31 32 #define MYKONOS_ADDR_DIGITAL_IO_CONTROL 0x028 33 34 #define MYKONOS_ADDR_SYSREF_PAD_CONFIG 0x040 35 #define MYKONOS_ADDR_TX1_SYNC_PAD_CONFIG 0x041 36 #define MYKONOS_ADDR_TX2_SYNC_PAD_CONFIG 0x042 37 #define MYKONOS_ADDR_RX1_SYNC_CONFIG 0x043 38 #define MYKONOS_ADDR_RX2_SYNC_CONFIG 0x044 39 40 /* Mykonos Framer Registers */ 41 #define MYKONOS_ADDR_FRAMER_RESET 0x059 42 #define MYKONOS_ADDR_FRAMER_CLK_EN 0x05A 43 #define MYKONOS_ADDR_FRAMER_ADDR 0x05B 44 #define MYKONOS_ADDR_FRAMER_DATA 0x05C 45 #define MYKONOS_ADDR_FRAMER_WRITE_EN 0x05D 46 #define MYKONOS_ADDR_FRAMER_SYSREF_FIFO_EN 0x05E 47 #define MYKONOS_ADDR_FRAMER_CONFIG_F 0x05F 48 #define MYKONOS_ADDR_FRAMER_LANE_CTL 0x060 49 #define MYKONOS_ADDR_FRAMER_ADC_XBAR_SEL 0x061 50 #define MYKONOS_ADDR_FRAMER_LANE_XBAR_SEL 0x062 51 #define MYKONOS_ADDR_FRAMER_CONFIG_LOOPBACK_XBAR_REV 0x063 52 #define MYKONOS_ADDR_FRAMER_SYNCN_FILT 0x064 53 #define MYKONOS_ADDR_FRAMER_LMFC_F_OFFSET 0x065 54 #define MYKONOS_ADDR_FRAMER_LMFC_K_OFFSET 0x066 55 #define MYKONOS_ADDR_FRAMER_TEST_CNTR_CTL 0x067 56 #define MYKONOS_ADDR_FRAMER_STATUS_STRB 0x068 57 #define MYKONOS_ADDR_FRAMER_STATUS 0x069 58 #define MYKONOS_ADDR_FRAMER_SYSREF_TO_LMFC_CNTR_STAT 0x06A 59 #define MYKONOS_ADDR_FRAMER_SYSREF_TO_LMFC_ERR_MARGIN 0x06B 60 #define MYKONOS_ADDR_FRAMER_LANE_FIFO_STRB 0x06C 61 #define MYKONOS_ADDR_FRAMER_LANE0_FIFO_RDWR_ADDR 0x06D 62 #define MYKONOS_ADDR_FRAMER_LANE1_FIFO_RDWR_ADDR 0x06E 63 #define MYKONOS_ADDR_FRAMER_LANE2_FIFO_RDWR_ADDR 0x06F 64 #define MYKONOS_ADDR_FRAMER_LANE3_FIFO_RDWR_ADDR 0x070 65 #define MYKONOS_ADDR_FRAMER_PRBS10_CTL 0x071 66 #define MYKONOS_ADDR_FRAMER_PRBS20_CTL 0x072 67 #define MYKONOS_ADDR_FRAMER_PATTERN_GEN_EN 0x073 68 #define MYKONOS_ADDR_FRAMER_PATTERN_GEN_7_TO_0 0x074 69 #define MYKONOS_ADDR_FRAMER_PATTERN_GEN_15_TO_8 0x075 70 #define MYKONOS_ADDR_FRAMER_PATTERN_GEN_19_TO_16 0x076 71 #define MYKONOS_ADDR_FRAMER_CONFIG_JTX_GEN 0x077 72 #define MYKONOS_ADDR_FRAMER_LANE_DATA_CTL 0x078 73 #define MYKONOS_ADDR_FRAMER_DATA_SAMPLE_CTL 0x079 74 75 /* Mykonos Deframer Sub Address Map */ 76 #define MYKONOS_SUBADDR_DEFRAMER_LANE0_ILAS_RECVD 0x00 77 #define MYKONOS_SUBADDR_DEFRAMER_LANE0_ILAS_CFG 0x50 78 79 /* Mykonos Deframer Registers */ 80 #define MYKONOS_ADDR_DEFRAMER_RESET 0x07A 81 #define MYKONOS_ADDR_DEFRAMER_CLK_EN 0x07B 82 #define MYKONOS_ADDR_DEFRAMER_ADDR 0x07C 83 #define MYKONOS_ADDR_DEFRAMER_DATA 0x07D 84 #define MYKONOS_ADDR_DEFRAMER_WR_EN 0x07E 85 #define MYKONOS_ADDR_DEFRAMER_SYSREF_FIFO_EN 0x07F 86 #define MYKONOS_ADDR_DEFRAMER_CONFIG_F 0x080 87 #define MYKONOS_ADDR_DEFRAMER_LANE_FIFO_CTL 0x081 88 #define MYKONOS_ADDR_DEFRAMER_DAC_XBAR_SEL 0x082 89 #define MYKONOS_ADDR_DEFRAMER_LANE_XBAR_SEL 0x083 90 #define MYKONOS_ADDR_DEFRAMER_LMFC_F_OFFSET 0x084 91 #define MYKONOS_ADDR_DEFRAMER_LMFC_K_OFFSET 0x085 92 #define MYKONOS_ADDR_DEFRAMER_CONFIG_SYNC_USER_DATA_CTL 0x086 93 #define MYKONOS_ADDR_DEFRAMER_SYNC_REQ_RETIME 0x087 94 #define MYKONOS_ADDR_DEFRAMER_TEST 0x088 95 #define MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_STRT_DAC_XBAR_REV 0x089 96 #define MYKONOS_ADDR_DEFRAMER_STAT_STRB 0x08A 97 #define MYKONOS_ADDR_DEFRAMER_STAT 0x08B 98 #define MYKONOS_ADDR_DEFRAMER_TEST_ERR_CNT_STAT 0x08C 99 #define MYKONOS_ADDR_DEFRAMER_DET_FIFO_RD_ADDR 0x08D 100 #define MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_ADDR 0x08E 101 #define MYKONOS_ADDR_DEFRAMER_QBLMFC_VS_EXTLMFC_CNTR_STAT 0x08F 102 #define MYKONOS_ADDR_DEFRAMER_DET_FIFO_STAT 0x090 103 #define MYKONOS_ADDR_DEFRAMER_STRT_RD_DEL_STOP_WR 0x091 104 #define MYKONOS_ADDR_DEFRAMER_FIFO_SAMPLE_SPI_ADDR_RD 0x092 105 #define MYKONOS_ADDR_DEFRAMER_FIFO_BYTE_SPI_ADDR_RD 0x093 106 #define MYKONOS_ADDR_DEFRAMER_FIFO_BYTE_SPI_DATA_RD 0x094 107 #define MYKONOS_ADDR_DEFRAMER_SAMPLE0_7_TO_0 0x095 108 #define MYKONOS_ADDR_DEFRAMER_SAMPLE0_15_TO_8 0x096 109 #define MYKONOS_ADDR_DEFRAMER_SAMPLE1_7_TO_0 0x097 110 #define MYKONOS_ADDR_DEFRAMER_SAMPLE1_15_TO_8 0x098 111 #define MYKONOS_ADDR_DEFRAMER_SAMPLE2_7_TO_0 0x099 112 #define MYKONOS_ADDR_DEFRAMER_SAMPLE2_15_TO_8 0x09A 113 #define MYKONOS_ADDR_DEFRAMER_SAMPLE3_7_TO_0 0x09B 114 #define MYKONOS_ADDR_DEFRAMER_SAMPLE3_15_TO_8 0x09C 115 #define MYKONOS_ADDR_DEFRAMER_LANE_FIFO_STRB 0x09D 116 #define MYKONOS_ADDR_DEFRAMER_LANE0_FIFO_RDWR_ADDR 0x09E 117 #define MYKONOS_ADDR_DEFRAMER_LANE1_FIFO_RDWR_ADDR 0x09F 118 #define MYKONOS_ADDR_DEFRAMER_LANE2_FIFO_RDWR_ADDR 0x0A0 119 #define MYKONOS_ADDR_DEFRAMER_LANE3_FIFO_RDWR_ADDR 0x0A1 120 #define MYKONOS_ADDR_DEFRAMER_SYSREF_TO_LMFC_CNTR_STAT 0x0A2 121 #define MYKONOS_ADDR_DEFRAMER_SYSREF_TO_LMFC_ERR_MARGIN 0x0A3 122 #define MYKONOS_ADDR_DEFRAMER_PRBS10_CTL 0x0A4 123 #define MYKONOS_ADDR_DEFRAMER_PRBS20_CTL 0x0A5 124 #define MYKONOS_ADDR_DEFRAMER_PRBS20_STRB_CHKSUM_TYPE 0x0A6 125 #define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_7_TO_0 0x0A7 126 #define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_15_TO_8 0x0A8 127 #define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_23_TO_16 0x0A9 128 #define MYKONOS_ADDR_DEFRAMER_LANE_DATA_CTL 0x0AA 129 #define MYKONOS_ADDR_DEFRAMER_STATUS_2 0x0AB 130 #define MYKONOS_ADDR_DEFRAMER_DET_FIFO_PHASE 0x0AC 131 132 /* Mykonos Serializer Registers */ 133 #define MYKONOS_ADDR_SERIALIZER_CTL_0 0x0B0 134 #define MYKONOS_ADDR_SERIALIZER_CTL_1 0x0B1 135 #define MYKONOS_ADDR_SERIALIZER_CTL_2 0x0B2 136 #define MYKONOS_ADDR_SERIALIZER_CTL_3 0x0B3 137 #define MYKONOS_ADDR_SERIALIZER_HS_DIV_TXSER_CLK_EN 0x0B4 138 #define MYKONOS_ADDR_SERIALIZER_SPECIAL 0x0B5 139 140 /* Mykonos Deserializer Registers */ 141 #define MYKONOS_ADDR_DESERIALIZER_PDET_CTL 0x0BC 142 #define MYKONOS_ADDR_DESERIALIZER_CTL_0 0x0BD 143 #define MYKONOS_ADDR_DESERIALIZER_SIN_SHAPE_0 0x0BE 144 #define MYKONOS_ADDR_DESERIALIZER_SIN_SHAPE_1 0x0BF 145 #define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_0 0x0C1 146 #define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_1 0x0C2 147 #define MYKONOS_ADDR_DESERIALIZER_MISC_CTL 0x0C3 148 #define MYKONOS_ADDR_DESERIALIZER_EQ_HP_EN 0x0C4 149 #define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_1_TO_0 0x0C5 150 #define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_3_TO_2 0x0C6 151 #define MYKONOS_ADDR_DESERIALIZER_HS_DIV_RXCDR_CLK_EN 0x0CD 152 #define MYKONOS_ADDR_DESERIALIZER_SPECIAL 0x0CE 153 #define MYKONOS_ADDR_DESERIALIZER_CDR_CAL_CTL 0x0D0 154 155 #define MYKONOS_ADDR_CONFIGURATION_CONTROL_1 0x100 156 #define MYKONOS_ADDR_CONFIGURATION_CONTROL_2 0x101 157 #define MYKONOS_ADDR_CONFIGURATION_CONTROL_4 0x102 158 #define MYKONOS_ADDR_CONFIGURATION_CONTROL_5 0x103 159 #define MYKONOS_ADDR_DPD_SNIFFER_CONFIGURATION_CONTROL_1 0x104 160 #define MYKONOS_ADDR_DPD_SNIFFER_CONFIGURATION_CONTROL_2 0x105 161 #define MYKONOS_ADDR_DPD_SNIFFER_GPIO_SELECT 0x106 162 #define MYKONOS_ADDR_SNIFFER_CONFIGURATION_CONTROL 0x107 163 #define MYKONOS_ADDR_DPD_CONFIGURATION_CONTROL 0x108 164 #define MYKONOS_ADDR_LOOPBACK_CONFIGURATION_CONTROL 0x109 165 166 #define MYKONOS_ADDR_CLOCK_CONTROL_0 0x117 167 #define MYKONOS_ADDR_CLOCK_CONTROL_1 0x118 168 #define MYKONOS_ADDR_CLOCK_CONTROL_2 0x119 169 #define MYKONOS_ADDR_CLOCK_CONTROL_3 0x11A 170 #define MYKONOS_ADDR_CLOCK_CONTROL_4 0x11B 171 #define MYKONOS_ADDR_CLOCK_CONTROL_5 0x11C 172 173 #define MYKONOS_ADDR_MCS_CONTROL 0x120 174 #define MYKONOS_ADDR_MCS_STATUS 0x121 175 176 /* CLK PLL Registers */ 177 #define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE0 0x141 178 #define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE1 0x142 179 #define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE0 0x143 180 #define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE1 0x144 181 #define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE2 0x145 182 #define MYKONOS_ADDR_CLK_SYNTH_F_VCOTN_BYTE1 0x148 183 #define MYKONOS_ADDR_CLK_SYNTH_BYTE1 0x149 184 #define MYKONOS_ADDR_CLK_SYNTH_BYTE2 0x14A 185 #define MYKONOS_ADDR_CLK_SYNTH_BYTE3 0x14B 186 #define MYKONOS_ADDR_CLK_SYNTH_BYTE5 0x14D 187 #define MYKONOS_ADDR_CLK_SYNTH_BYTE6 0x14E 188 #define MYKONOS_ADDR_CLK_SYNTH_BYTE7 0x14F 189 #define MYKONOS_ADDR_CLK_SYNTH_LF_R3 0x150 190 #define MYKONOS_ADDR_CLK_SYNTH_BYTE9 0x152 191 #define MYKONOS_ADDR_CLK_SYNTH_CAL_STAT 0x154 192 #define MYKONOS_ADDR_CLK_SYNTH_VCO_CAL_REF 0x155 193 #define MYKONOS_ADDR_CLK_SYNTH_VCO_BAND_BYTE1 0x157 194 #define MYKONOS_ADDR_CLK_SYNTH_CAL_CONTROL 0x159 195 #define MYKONOS_ADDR_CLK_SYNTH_VCO_VAR_CTL1 0x15E 196 #define MYKONOS_ADDR_CLK_SYNTH_VCO_VAR_CTL2 0x15F 197 198 /* DPD Registers */ 199 #define MYKONOS_ADDR_TX1_DPD_MODEL_INDIRECT_PTR 0x178 200 #define MYKONOS_ADDR_TX2_DPD_MODEL_INDIRECT_PTR 0x17C 201 #define MYKONOS_ADDR_DPD_RMS_BUF_SIZE 0x180 202 #define MYKONOS_ADDR_TX1_DPD_MODEL_WORKING_PTR 0x188 203 #define MYKONOS_ADDR_TX2_DPD_MODEL_WORKING_PTR 0x18C 204 205 /* Rx NCO Control registers */ 206 #define MYKONOS_ADDR_CALPLL_SDM_CONTROL 0x17F 207 #define MYKONOS_ADDR_RX_NCO_CONTROL 0x190 208 #define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_3 0x191 209 #define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_2 0x192 210 #define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_1 0x193 211 #define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_3 0x194 212 #define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_2 0x195 213 #define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_1 0x196 214 #define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_3 0x197 215 #define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_2 0x198 216 #define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_1 0x199 217 218 #define MYKONOS_ADDR_ENSM_CONFIG_7_0 0x1B0 219 #define MYKONOS_ADDR_CALIBRATION_CONTROL 0x1B2 220 #define MYKONOS_ADDR_ENSM_MANUAL_GAIN_LOCK_GPIO_SELECT 0x1B5 221 #define MYKONOS_ADDR_REFERENCE_CLOCK_CYCLES 0x1C0 222 #define MYKONOS_ADDR_TX_PD_OVERIDE_7_0 0x209 223 #define MYKONOS_ADDR_RCAL_CONTROL 0x224 224 #define MYKONOS_ADDR_REF_PAD_CONFIG1 0x230 225 #define MYKONOS_ADDR_REF_PAD_CONFIG2 0x231 226 227 #define MYKONOS_ADDR_RXSYNTH_CP_CAL_STAT 0x254 228 #define MYKONOS_ADDR_RXSYNTH_VCO_BAND_BYTE1 0x257 229 #define MYKONOS_ADDR_TXSYNTH_CP_CAL_STAT 0x2C4 230 #define MYKONOS_ADDR_TXSYNTH_VCO_BAND_BYTE1 0x2C7 231 #define MYKONOS_ADDR_SNIFF_RXSYNTH_CP_CAL_STAT 0x354 232 #define MYKONOS_ADDR_SNIFF_RXSYNTH_VCO_BAND_BYTE1 0x357 233 #define MYKONOS_ADDR_SNIFF_RXLOGEN_BYTE1 0x380 234 235 #define MYKONOS_ADDR_RX_FILTER_CONFIGURATION 0x410 236 #define MYKONOS_ADDR_RX_FILTER_GAIN 0x411 237 #define MYKONOS_ADDR_DPD_SNIFFER_RX_FILTER_GAIN 0x412 238 239 /* Mykonos Temperature Gain Compensation Registers */ 240 #define MYKONOS_ADDR_RX1_TEMP_GAIN_COMP 0x420 241 #define MYKONOS_ADDR_RX2_TEMP_GAIN_COMP 0x421 242 #define MYKONOS_ADDR_OBS_TEMP_GAIN_COMP 0x422 243 244 /* Mykonos AGC General Registers */ 245 #define MYKONOS_ADDR_AGC_CFG_1 0x42E 246 #define MYKONOS_ADDR_AGC_CFG_2 0x42F 247 #define MYKONOS_ADDR_AGC_GAIN_CHANGE_GPIO_SEL 0x430 248 #define MYKONOS_ADDR_AGC_RX1_MAX_GAIN_INDEX 0x431 249 #define MYKONOS_ADDR_AGC_RX1_MIN_GAIN_INDEX 0x432 250 #define MYKONOS_ADDR_AGC_MANUAL_GAIN_CFG 0x433 251 #define MYKONOS_ADDR_AGC_MANUAL_GAIN_GPIO_SEL 0x434 252 #define MYKONOS_ADDR_AGC_MANUAL_GAIN_INDEX_CH_1 0x435 253 #define MYKONOS_ADDR_AGC_MANUAL_GAIN_INDEX_CH_2 0x436 254 #define MYKONOS_ADDR_AGC_LOCK_LEVEL 0x437 255 #define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_1 0x438 256 #define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_2 0x439 257 #define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_3 0x43A 258 #define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_4 0x43B 259 #define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_5 0x43C 260 #define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_6 0x43D 261 #define MYKONOS_ADDR_AGC_RX1_GAIN_LOCK_DELAY 0x43E 262 #define MYKONOS_ADDR_AGC_RX2_GAIN_LOCK_DELAY 0x43F 263 #define MYKONOS_ADDR_AGC_RX1_ATTACK_DELAY 0x440 264 #define MYKONOS_ADDR_AGC_RX2_ATTACK_DELAY 0x441 265 #define MYKONOS_ADDR_AGC_ULB_THRSH 0x442 266 #define MYKONOS_ADDR_AGC_LLB_THRSH 0x443 267 #define MYKONOS_ADDR_AGC_RX_BLOCK_DET_DECAY 0x444 268 #define MYKONOS_ADDR_AGC_RESET_PD_HIGH_CNT 0x445 269 #define MYKONOS_ADDR_AGC_RX2_MAX_GAIN_INDEX 0x446 270 #define MYKONOS_ADDR_AGC_RX2_MIN_GAIN_INDEX 0x447 271 #define MYKONOS_ADDR_AGC_ORX_SNRX_CFG_1 0x448 272 #define MYKONOS_ADDR_AGC_ORX_SNRX_CFG_2 0x449 273 #define MYKONOS_ADDR_AGC_ORX_SNRX_MAX_GAIN_INDEX 0x44A 274 #define MYKONOS_ADDR_AGC_ORX_SNRX_MIN_GAIN_INDEX 0x44B 275 #define MYKONOS_ADDR_AGC_ORX_SNRX_MANUAL_GAIN_CFG 0x44C 276 #define MYKONOS_ADDR_AGC_ORX_SNRX_GPIO_SEL 0x44D 277 #define MYKONOS_ADDR_AGC_ORX_SNRX_LOCK_LEVEL 0x44E 278 #define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_1 0x44F 279 #define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_2 0x450 280 #define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_3 0x451 281 #define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_4 0x452 282 #define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_5 0x453 283 #define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_6 0x454 284 #define MYKONOS_ADDR_AGC_ORX_SNRX_GAIN_LOCK_DELAY 0x455 285 #define MYKONOS_ADDR_AGC_ORX_SNRX_ATTACK_DELAY 0x456 286 #define MYKONOS_ADDR_AGC_ORX_SNRX_ULB_THRSH 0x457 287 #define MYKONOS_ADDR_AGC_ORX_SNRX_LLB_THRSH 0x458 288 #define MYKONOS_ADDR_AGC_ORX_SNRX_BLOCK_DET_DECAY 0x459 289 #define MYKONOS_ADDR_AGC_ORX_SNRX_RESET_PD_HIGH_CNT 0x45A 290 #define MYKONOS_ADDR_AGC_ORX1_MANUAL_GAIN_INDEX 0x45B 291 #define MYKONOS_ADDR_AGC_ORX2_MANUAL_GAIN_INDEX 0x45C 292 #define MYKONOS_ADDR_AGC_SNRX_MANUAL_GAIN_INDEX 0x45D 293 #define MYKONOS_ADDR_AGC_LOOPBACK1_MANUAL_GAIN_INDEX 0x45E 294 #define MYKONOS_ADDR_AGC_LOOPBACK2_MANUAL_GAIN_INDEX 0x45F 295 #define MYKONOS_ADDR_AGC_ORX_SNRX_ACTIVE 0x460 296 297 /* Mykonos Fast Attack AGC Registers */ 298 #define MYKONOS_ADDR_AGC_FAST_CFG_1 0x468 299 #define MYKONOS_ADDR_AGC_FAST_CFG_2 0x469 300 #define MYKONOS_ADDR_AGC_FAST_ENRGY_LOST_THRSH 0x46A 301 #define MYKONOS_ADDR_AGC_FAST_STRONG_SIG_THRSH 0x46B 302 #define MYKONOS_ADDR_AGC_FAST_SETTING_DELAY 0x46C 303 #define MYKONOS_ADDR_AGC_FAST_OPT_MAX_GAIN 0x46D 304 #define MYKONOS_ADDR_AGC_FAST_ENRGY_DET_CNT 0x46E 305 #define MYKONOS_ADDR_AGC_FAST_AGCLL_UPPER_LIMIT 0x46F 306 #define MYKONOS_ADDR_AGC_FAST_GAIN_LOCK_EXIT_CNT 0x470 307 #define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_CFG_1 0x471 308 #define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_CFG_2 0x472 309 #define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_ENRGY_LOST_THRSH 0x473 310 #define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_STRONG_SIG_THRSH 0x474 311 #define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_SET_DELAY 0x475 312 #define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_OPT_MAX_GAIN 0x476 313 #define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_ENRGY_DET_CNT 0x477 314 #define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_AGCLL_UPPER_LIMIT 0x478 315 #define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_GAIN_LOCK_EXIT_CNT 0x479 316 317 /* Mykonos Slow Loop - Hybrid AGC Registers */ 318 #define MYKONOS_ADDR_AGC_SLOW_LOCK_LEV_THRSH 0x480 319 #define MYKONOS_ADDR_AGC_SLOW_ULB_CNT_THRSH 0x481 320 #define MYKONOS_ADDR_AGC_SLOW_LLB_CNT_THRSH 0x482 321 #define MYKONOS_ADDR_AGC_SLOW_HIGH_OVRG_CNT_THRSH 0x483 322 #define MYKONOS_ADDR_AGC_SLOW_LOW_OVRG_CNT_THRSH 0x484 323 #define MYKONOS_ADDR_AGC_SLOW_VERYLOW_OVRG_CNT_THRSH 0x485 324 #define MYKONOS_ADDR_AGC_SLOW_DIG_SAT_CNT_THRSH 0x486 325 #define MYKONOS_ADDR_AGC_SLOW_UPPER0_THRSH_GAIN_STEP 0x487 326 #define MYKONOS_ADDR_AGC_SLOW_LOWER0_THRSH_GAIN_STEP 0x488 327 #define MYKONOS_ADDR_AGC_SLOW_UPPER1_THRSH_GAIN_STEP 0x489 328 #define MYKONOS_ADDR_AGC_SLOW_LOWER1_THRSH_GAIN_STEP 0x48A 329 #define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_1 0x48B 330 #define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_2 0x48C 331 #define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_3 0x48D 332 #define MYKONOS_ADDR_AGC_SLOW_LOOP_CFG 0x48E 333 #define MYKONOS_ADDR_AGC_SLOW_POWER_THRSH 0x48F 334 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOCK_LEV_THRSH 0x490 335 336 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ULB_CNT_THRSH 0x491 337 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LLB_CNT_THRSH 0x492 338 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_HIGH_OVRG_CNT_THRSH 0x493 339 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_LOW_OVRG_CNT_THRSH 0x494 340 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_VERYLOW_OVRG_CNT_THRSH 0x495 341 342 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_DIG_SAT_CNT_THRSH 0x496 343 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UPPER0_THRSH_GAIN_STEP 0x497 344 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOWER0_THRSH_GAIN_STEP 0x498 345 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UPPER1_THRSH_GAIN_STEP 0x499 346 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOWER1_THRSH_GAIN_STEP 0x49A 347 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_1 0x49B 348 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_2 0x49C 349 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_3 0x49D 350 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOOP_CFG 0x49E 351 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_POWER_THRSH 0x49F 352 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DEL_1 0x4A0 353 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DEL_2 0x4A1 354 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DUR_1 0x4A2 355 #define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DUR_2 0x4A3 356 357 /* Mykonos Gain Control Read Registers */ 358 #define MYKONOS_ADDR_GAIN_CTL_CHANNEL_1 0x4B0 359 #define MYKONOS_ADDR_GAIN_CTL_FAST_ATTK_STATE 0x4B1 360 #define MYKONOS_ADDR_GAIN_CTL_SLOW_LOOP_STATE 0x4B2 361 #define MYKONOS_ADDR_GAIN_CTL_CHANNEL_2 0x4B3 362 #define MYKONOS_ADDR_GAIN_CTL_OVRG_SIGS_CHANNEL_1 0x4B4 363 #define MYKONOS_ADDR_GAIN_CTL_OVRG_SIGS_CHANNEL_2 0x4B5 364 #define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_GAIN 0x4B6 365 #define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_LOOP_STATE 0x4B7 366 #define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_OVRG_SIGS 0x4B8 367 368 /* Mykonos Rx Data Path Overrange Registers */ 369 #define MYKONOS_ADDR_RX_OVRG_DATAPATH_OVRFLW 0x4B9 370 #define MYKONOS_ADDR_RX_OVRG_ORX_SNRX_DATAPATH_OVRFLW 0x4BA 371 372 /* Mykonos RSSI Measurement Registers and Dec Power Measurement Registers*/ 373 #define MYKONOS_ADDR_RSSI_MEAS_DURATION_0_1 0x4C0 374 #define MYKONOS_ADDR_RSSI_MEAS_DURATION_2_3 0x4C1 375 #define MYKONOS_ADDR_RSSI_CFG 0x4C6 376 #define MYKONOS_DEC_POWER_CONFIG_1 0x4C7 377 #define MYKONOS_DEC_POWER_CONFIG_2 0x4C8 378 #define MYKONOS_ADDR_DPD_SNF_RSSI_CFG 0x4CF 379 #define MYKONOS_ADDR_DPD_RSSI_CFG 0x4D6 380 #define MYKONOS_SNIFFER_DEC_POWER_CONFIG_1 0x4D7 381 #define MYKONOS_SNIFFER_DEC_POWER_CONFIG_2 0x4D8 382 #define MYKONOS_CH1_DECIMATED_PWR 0x4DE 383 #define MYKONOS_CH2_DECIMATED_PWR 0x4DF 384 #define MYKONOS_SNIFFER_DECIMATED_PWR 0x4E6 385 386 #define MYKONOS_ADDR_DIGITAL_GAIN_CONFIG 0x4F0 387 #define MYKONOS_ADDR_DPD_SNIFFER_DIGITAL_GAIN_CONFIG 0x4F1 388 #define MYKONOS_ADDR_GAIN_TABLE_ADDR 0x500 389 #define MYKONOS_ADDR_GAIN_TABLE_RX1_FE_GAIN 0x501 390 #define MYKONOS_ADDR_GAIN_TABLE_RX1_EXT_CTL 0x502 391 #define MYKONOS_ADDR_GAIN_TABLE_RX1_DIG_GAIN 0x503 392 #define MYKONOS_ADDR_GAIN_TABLE_RX2_FE_GAIN 0x504 393 #define MYKONOS_ADDR_GAIN_TABLE_RX2_EXT_CTL 0x505 394 #define MYKONOS_ADDR_GAIN_TABLE_RX2_DIG_GAIN 0x506 395 #define MYKONOS_ADDR_GAIN_TABLE_RX3_FE_GAIN 0x507 396 #define MYKONOS_ADDR_GAIN_TABLE_RX3_LNA_ENAB 0x508 397 #define MYKONOS_ADDR_GAIN_TABLE_RX3_DIG_GAIN 0x509 398 #define MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION 0x516 399 #define MYKONOS_ADDR_CH3_GAIN_TABLE_CONFIGURATION 0x517 400 #define MYKONOS_ADDR_RXFE1_LOCM 0x520 401 #define MYKONOS_ADDR_RXFE2_LOCM 0x521 402 #define MYKONOS_ADDR_RXLOOPBACK1_CNTRL_1 0x540 403 #define MYKONOS_ADDR_RXLOOPBACK2_CNTRL_1 0x541 404 #define MYKONOS_ADDR_RX_LOOPBACK1_CNTRL_4 0x546 405 #define MYKONOS_ADDR_RX_LOOPBACK2_CNTRL_4 0x547 406 407 /* Mykonos Overload/Peak Detection Registers */ 408 #define MYKONOS_ADDR_OVRLD_ADC_OVRLD_CFG 0x580 409 #define MYKONOS_ADDR_OVRLD_ADC_OVRLD_UPPER_THRSH 0x581 410 #define MYKONOS_ADDR_OVRLD_ADC_OVRLD_LOWER_THRSH 0x582 411 412 #define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_CFG 0x583 413 #define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_UPPER_THRSH 0x584 414 #define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_LOWER_THRSH 0x585 415 #define MYKONOS_ADDR_OVRLD_PD_DEC_VERYLOW_THRSH 0x586 416 #define MYKONOS_ADDR_ORX_SNRX_OVRLD_ADC_OVRLD_CFG 0x587 417 #define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_CFG 0x58A 418 #define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_UPPER_THRSH 0x58B 419 #define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_LOWER_THRSH 0x58C 420 #define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_VERYLOW_THRSH 0x58D 421 422 #define MYKONOS_ADDR_RX_ADC_FLASH_DELAY 0x5B6 423 #define MYKONOS_ADDR_RX_ADC_FLASH_CTRL 0x5B7 424 #define MYKONOS_ADDR_RX_ADC1_PRFL 0x5DD 425 #define MYKONOS_ADDR_RX_ADC2_PRFL 0x5DE 426 #define MYKONOS_ADDR_ORX_ADC_PRFL 0x5DF 427 428 #define MYKONOS_ADDR_RFDC_MEASURE_COUNT_1 0x631 429 #define MYKONOS_ADDR_RFDC_MEASURE_COUNT_2 0x632 430 #define MYKONOS_ADDR_RFDC_PROGRAM_SHIFT 0x635 431 #define MYKONOS_ADDR_RFDC_CONFIG2 0x636 432 #define MYKONOS_DPD_Sniffer_RFDC_CAL_TRACK_EN 0x642 433 #define MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_1 0x644 434 #define MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_2 0x645 435 #define MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_1 0x650 436 #define MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_2 0x651 437 #define MYKONOS_ADDR_DIGITAL_DC_MIN_CAL_IDX 0x63A 438 #define MYKONOS_ADDR_DIGITAL_DC_OFFSET_SHIFT 0x674 439 #define MYKONOS_ADDR_DIGITAL_DC_OFFSET_CONFIG 0x676 440 #define MYKONOS_DIGITAL_DC_OFFSET_CH3_TRACKING 0x67A 441 #define MYKONOS_ADDR_DIGITAL_DC_OFFSET_SNF 0x67C 442 #define MYKONOS_ADDR_DIGITAL_DC_OFFSET_CH3_DPD_M_SHIFT 0x67D 443 444 #define MYKONOS_ADDR_RX_GAIN_COMP_DELAY 0x710 445 #define MYKONOS_ADDR_RX1_GAIN_COMP_OFFSET 0x711 446 #define MYKONOS_ADDR_RX2_GAIN_COMP_OFFSET 0x712 447 #define MYKONOS_ADDR_RX_GAIN_COMP_CFG 0x713 448 #define MYKONOS_ADDR_RX_SLCR_PIN_CFG 0x714 449 #define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_DELAY 0x715 450 #define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_OFFSET 0x716 451 #define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_CFG 0x717 452 #define MYKONOS_ADDR_DPD_SNF_RX_SLCR_PIN_CFG 0x718 453 454 #define MYKONOS_ADDR_FLOATING_POINT_CFG 0x750 455 #define MYKONOS_ADDR_FLOATING_POINT_RX_CTRL 0x751 456 #define MYKONOS_ADDR_FLOATING_POINT_ORX_CTRL 0x752 457 458 459 #define MYKONOS_ADDR_SNRX_LNA_BIAS_C 0x81B 460 461 462 #define MYKONOS_ADDR_ORX_ADC_FLASH_DELAY 0x846 463 #define MYKONOS_ADDR_ORX_ADC_FLASH_CTRL 0x847 464 465 #define MYKONOS_ADDR_TX_FILTER_CONFIGURATION 0x910 466 #define MYKONOS_ADDR_TX1_ATTENUATION_0_READBACK 0x940 467 #define MYKONOS_ADDR_TX1_ATTENUATION_1_READBACK 0x941 468 #define MYKONOS_ADDR_TX2_ATTENUATION_0_READBACK 0x942 469 #define MYKONOS_ADDR_TX2_ATTENUATION_1_READBACK 0x943 470 #define MYKONOS_ADDR_TX_FILTER_OVERFLOW 0x950 471 472 /* Mykonos PA Protection Block Registers */ 473 #define MYKONOS_ADDR_PA_PROTECTION_CONFIGURATION 0x955 474 #define MYKONOS_ADDR_PA_PROTECTION_ATTEN_CONTROL 0x956 475 #define MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_LSB 0x957 476 #define MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_MSB 0x958 477 #define MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_LSB 0x959 478 #define MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_MSB 0x95A 479 #define MYKONOS_ADDR_TX1_ATTENUATION_0 0x960 480 #define MYKONOS_ADDR_TX1_ATTENUATION_1 0x961 481 #define MYKONOS_ADDR_TX2_ATTENUATION_0 0x962 482 #define MYKONOS_ADDR_TX2_ATTENUATION_1 0x963 483 #define MYKONOS_ADDR_TX1_GAIN_0 0x967 484 #define MYKONOS_ADDR_TX1_GAIN_1 0x968 485 #define MYKONOS_ADDR_TX1_GAIN_2 0x969 486 #define MYKONOS_ADDR_TX2_GAIN_0 0x96A 487 #define MYKONOS_ADDR_TX2_GAIN_1 0x96B 488 #define MYKONOS_ADDR_TX2_GAIN_2 0x96C 489 #define MYKONOS_ADDR_TX_INCR_DECR_WORD 0x96D 490 #define MYKONOS_ADDR_TX_TPC_CONFIG 0x96E 491 #define MYKONOS_ADDR_TX_TPC_GPIO_CFG 0x96F 492 493 #define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_I_MSB 0x9CB 494 #define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_I_LSB 0x9CC 495 #define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_Q_MSB 0x9CD 496 #define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_Q_LSB 0x9CE 497 498 /* Mykonos GPIO Registers */ 499 #define MYKONOS_ADDR_GPIO_3V3_DIR_CTL_7_0 0xB00 500 #define MYKONOS_ADDR_GPIO_3V3_DIR_CTL_15_8 0xB01 501 #define MYKONOS_ADDR_GPIO_3V3_SPI_SRC_7_0 0xB02 502 #define MYKONOS_ADDR_GPIO_3V3_SPI_SRC_15_8 0xB03 503 #define MYKONOS_ADDR_GPIO_3V3_SPI_READ_7_0 0xB04 504 #define MYKONOS_ADDR_GPIO_3V3_SPI_READ_15_8 0xB05 505 #define MYKONOS_ADDR_GPIO_3V3_LSB_SRC_CTL 0xB06 506 #define MYKONOS_ADDR_GPIO_3V3_MSB_SRC_CTL 0xB07 507 508 #define MYKONOS_ADDR_GPIO_DIR_CTL_7_0 0xB20 509 #define MYKONOS_ADDR_GPIO_DIR_CTL_15_8 0xB21 510 #define MYKONOS_ADDR_GPIO_DIR_CTL_18_16 0xB22 511 #define MYKONOS_ADDR_GPIO_SPI_SRC_7_0 0xB23 512 #define MYKONOS_ADDR_GPIO_SPI_SRC_15_8 0xB24 513 #define MYKONOS_ADDR_GPIO_SPI_SRC_18_16 0xB25 514 #define MYKONOS_ADDR_GPIO_SPI_READ_7_0 0xB26 515 #define MYKONOS_ADDR_GPIO_SPI_READ_15_8 0xB27 516 #define MYKONOS_ADDR_GPIO_SPI_READ_18_16 0xB28 517 #define MYKONOS_ADDR_SOURCE_CONTROL_LOWER_BYTE 0xB29 518 #define MYKONOS_ADDR_SOURCE_CONTROL_UPPER_BYTE 0xB2A 519 #define MYKONOS_ADDR_SOURCE_CONTROL_EXTRA_BITS 0xB2B 520 521 #define MYKONOS_ADDR_GPIO_MONITOR_INDEX 0xB40 522 #define MYKONOS_ADDR_GPIO_MONITOR_ENABLE 0xB41 523 524 #define MYKONOS_ADDR_GP_INTERRUPT_MASK_1 0xB42 525 #define MYKONOS_ADDR_GP_INTERRUPT_MASK_0 0xB43 526 #define MYKONOS_ADDR_GP_INTERRUPT_READ_1 0xB44 527 #define MYKONOS_ADDR_GP_INTERRUPT_READ_0 0xB45 528 529 #define MYKONOS_ADDR_PDAUXDAC_MANUAL_CONTROL_5_0 0xB73 530 #define MYKONOS_ADDR_PDAUXDAC_MANUAL_CONTROL_9_6 0xB74 531 #define MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_5_0 0xB75 532 #define MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_9_6 0xB76 533 #define MYKONOS_ADDR_AUX_DAC_LATCH_CONTROL 0xB9F 534 #define MYKONOS_ADDR_AUXDAC_0_WORD_MSB 0xBA0 535 536 #define MYKONOS_ADR_AUX_ADC_CLOCK_DIVIDE 0xBC0 537 #define MYKONOS_ADDR_AUX_ADC_CFG 0xBC1 538 #define MYKONOS_ADDR_AUX_ADC_READ_MSB 0xBC2 539 #define MYKONOS_ADDR_AUX_ADC_READ_LSB 0xBC3 540 #define MYKONOS_ADDR_AUX_ADC_SEL 0xBC4 541 #define MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_0 0xBC5 542 #define MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_1 0xBC6 543 544 #define MYKONOS_ADDR_TEMP_SENSOR_OFFSET 0xBE0 545 #define MYKONOS_ADDR_TEMP_SENSOR_CONTROL_LSB 0xBE1 546 #define MYKONOS_ADDR_TEMP_SENSOR_CONTROL_MSB 0xBE2 547 #define MYKONOS_ADDR_TEMP_SENSOR_READ 0xBE3 548 #define MYKONOS_ADDR_TEMP_SENSOR_CONFIG 0xBE4 549 550 #define MYKONOS_ADDR_DIGITAL_TEST_BYTE_0 0xC40 551 552 /* ARM subsystem registers */ 553 #define MYKONOS_ADDR_ARM_CTL_1 0xD00 554 #define MYKONOS_ADDR_ARM_CTL_2 0xD01 555 #define MYKONOS_ADDR_ARM_ADDR_BYTE_0 0xD02 556 #define MYKONOS_ADDR_ARM_ADDR_BYTE_1 0xD03 557 #define MYKONOS_ADDR_ARM_DATA_BYTE_0 0xD04 558 #define MYKONOS_ADDR_ARM_DATA_BYTE_1 0xD05 559 #define MYKONOS_ADDR_ARM_DATA_BYTE_2 0xD06 560 #define MYKONOS_ADDR_ARM_DATA_BYTE_3 0xD07 561 #define MYKONOS_ADDR_ARM_CLK_CTL 0xD08 562 #define MYKONOS_ADDR_AHB_SPI_BRIDGE 0xD09 563 #define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_0 0xD0A 564 #define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_1 0xD0B 565 #define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_2 0xD0C 566 #define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_3 0xD0D 567 #define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_0 0xD0E 568 #define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_1 0xD0F 569 #define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_2 0xD10 570 #define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_3 0xD11 571 #define MYKONOS_ADDR_ARM_BRIDGE_CLK_CTL 0xD14 572 573 /* ARM mailbox registers */ 574 #define MYKONOS_ADDR_ARM_CMD 0xD30 575 #define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_1 0xD31 576 #define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_2 0xD32 577 #define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_3 0xD33 578 #define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_4 0xD34 579 #define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_5 0xD35 580 #define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_6 0xD36 581 #define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_7 0xD37 582 #define MYKONOS_ADDR_ARM_CMD_STATUS_0 0xD38 583 #define MYKONOS_ADDR_ARM_CMD_STATUS_1 0xD39 584 #define MYKONOS_ADDR_ARM_CMD_STATUS_2 0xD3A 585 #define MYKONOS_ADDR_ARM_CMD_STATUS_3 0xD3B 586 #define MYKONOS_ADDR_ARM_CMD_STATUS_4 0xD3C 587 #define MYKONOS_ADDR_ARM_CMD_STATUS_5 0xD3D 588 #define MYKONOS_ADDR_ARM_CMD_STATUS_6 0xD3E 589 #define MYKONOS_ADDR_ARM_CMD_STATUS_7 0xD3F 590 591 #define MYKONOS_ADDR_ARM_OPCODE_STATE_0 0xD40 592 #define MYKONOS_ADDR_ARM_OPCODE_STATE_1 0xD41 593 #define MYKONOS_ADDR_ARM_OPCODE_STATE_2 0xD42 594 #define MYKONOS_ADDR_ARM_OPCODE_STATE_3 0xD43 595 #define MYKONOS_ADDR_ARM_OPCODE_STATE_4 0xD44 596 #define MYKONOS_ADDR_ARM_OPCODE_STATE_5 0xD45 597 #define MYKONOS_ADDR_ARM_OPCODE_STATE_6 0xD46 598 #define MYKONOS_ADDR_ARM_OPCODE_STATE_7 0xD47 599 600 /* Mykonos Power-Down Override Control Registers */ 601 #define MYKONOS_ADDR_TX_PD_OVERRIDE_CONTROL_7_0 0xD89 602 603 /* Mykonos Observation Framer Registers */ 604 #define MYKONOS_ADDR_OBS_FRAMER_RESET 0xDC0 605 #define MYKONOS_ADDR_OBS_FRAMER_CLK_EN 0xDC1 606 #define MYKONOS_ADDR_OBS_FRAMER_ADDR 0xDC2 607 #define MYKONOS_ADDR_OBS_FRAMER_DATA 0xDC3 608 #define MYKONOS_ADDR_OBS_FRAMER_WRITE_EN 0xDC4 609 #define MYKONOS_ADDR_OBS_FRAMER_SYSREF_FIFO_EN 0xDC5 610 #define MYKONOS_ADDR_OBS_FRAMER_CONFIG_F 0xDC6 611 #define MYKONOS_ADDR_OBS_FRAMER_LANE_CTL 0xDC7 612 #define MYKONOS_ADDR_OBS_FRAMER_ADC_XBAR_SEL 0xDC8 613 #define MYKONOS_ADDR_OBS_FRAMER_LANE_XBAR_SEL 0xDC9 614 #define MYKONOS_ADDR_OBS_FRAMER_CONFIG_LOOPBACK_XBAR_REV 0xDCA 615 #define MYKONOS_ADDR_OBS_FRAMER_SYNCN_FILT 0xDCB 616 #define MYKONOS_ADDR_OBS_FRAMER_LMFC_F_OFFSET 0xDCC 617 #define MYKONOS_ADDR_OBS_FRAMER_LMFC_K_OFFSET 0xDCD 618 #define MYKONOS_ADDR_OBS_FRAMER_TEST_CNTR_CTL 0xDCE 619 #define MYKONOS_ADDR_OBS_FRAMER_STATUS_STRB 0xDCF 620 #define MYKONOS_ADDR_OBS_FRAMER_STATUS 0xDD0 621 #define MYKONOS_ADDR_OBS_FRAMER_SYSREF_TO_LMFC_CNTR_STAT 0xDD1 622 #define MYKONOS_ADDR_OBS_FRAMER_SYSREF_TO_LMFC_ERR_MARGIN 0xDD2 623 #define MYKONOS_ADDR_OBS_FRAMER_LANE_FIFO_STRB 0xDD3 624 #define MYKONOS_ADDR_OBS_FRAMER_LANE0_FIFO_RDWR_ADDR 0xDD4 625 #define MYKONOS_ADDR_OBS_FRAMER_LANE1_FIFO_RDWR_ADDR 0xDD5 626 #define MYKONOS_ADDR_OBS_FRAMER_LANE2_FIFO_RDWR_ADDR 0xDD6 627 #define MYKONOS_ADDR_OBS_FRAMER_LANE3_FIFO_RDWR_ADDR 0xDD7 628 #define MYKONOS_ADDR_OBS_FRAMER_PRBS10_CTL 0xDD8 629 #define MYKONOS_ADDR_OBS_FRAMER_PRBS20_CTL 0xDD9 630 #define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_EN 0xDDA 631 #define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_7_TO_0 0xDDB 632 #define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_15_TO_8 0xDDC 633 #define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_19_TO_16 0xDDD 634 #define MYKONOS_ADDR_OBS_FRAMER_CONFIG_JTX_GEN 0xDDE 635 #define MYKONOS_ADDR_OBS_FRAMER_LANE_DATA_CTL 0xDDF 636 #define MYKONOS_ADDR_OBS_FRAMER_DATA_SAMPLE_CTL 0xDE0 637 638 #define MYKONOS_ADDR_PFIR_COEFF_CTL 0xDFF 639 #define MYKONOS_ADDR_PFIR_COEFF_DATA 0xE00 640 #define MYKONOS_ADDR_PFIR_COEFF_ADDR 0xE01 641 642 /* ARM memory */ 643 #define MYKONOS_ADDR_ARM_START_PROG_ADDR 0x01000000 644 #define MYKONOS_ADDR_ARM_END_PROG_ADDR 0x01017FFF 645 #define MYKONOS_ADDR_ARM_START_DATA_ADDR 0x20000000 646 #define MYKONOS_ADDR_ARM_END_DATA_ADDR 0x2000FFFF 647 #define MYKONOS_ADDR_ARM_BUILD_CHKSUM_ADDR 0x01017FE0 648 #define MYKONOS_ADDR_ARM_CALC_CHKSUM_ADDR 0x01017FE4 649 #define MYKONOS_ADDR_ARM_VERSION 0x01000128 650 #define MYKONOS_ARM_ABORT_OPCODE 0x00 651 #define MYKONOS_ARM_RUNINIT_OPCODE 0x02 652 #define MYKONOS_ARM_RADIOON_OPCODE 0x04 653 #define MYKONOS_ARM_WRITECFG_OPCODE 0x06 654 #define MYKONOS_ARM_READCFG_OPCODE 0x08 655 #define MYKONOS_ARM_SET_OPCODE 0x0A 656 #define MYKONOS_ARM_GET_OPCODE 0x0C 657 658 #define MYKONOS_ARM_OBJECTID_DPDINIT_CONFIG 0x0F 659 #define MYKONOS_ARM_OBJECTID_CLGCINIT_CONFIG 0x10 660 #define MYKONOS_ARM_OBJECTID_VSWRINIT_CONFIG 0x11 661 #define MYKONOS_ARM_OBJECTID_DPDCONFIG 0x24 662 #define MYKONOS_ARM_DPD_RESET 0x02 663 #define MYKONOS_ARM_OBJECTID_GS_TRACKCALS 0x66 664 #define MYKONOS_ARM_OBJECTID_RXQEC_TRACKING 0x20 665 #define MYKONOS_ARM_OBJECTID_ORXQEC_TRACKING 0x21 666 #define MYKONOS_ARM_OBJECTID_TXLOL_TRACKING 0x22 667 #define MYKONOS_ARM_OBJECTID_TXQEC_TRACKING 0x23 668 #define MYKONOS_ARM_OBJECTID_CLGCCONFIG 0x25 669 #define MYKONOS_ARM_OBJECTID_VSWRCONFIG 0x26 670 #define MYKONOS_ARM_OBJECTID_CAL_STATUS 0x42 671 #define MYKONOS_ARM_OBJECTID_INIT_CAL_DONE 0x43 672 #define MYKONOS_ARM_OBJECTID_ORX_MODE 0x61 673 #define MYKONOS_ARM_OBJECTID_TRACKING_CAL_SUSPEND_RESUME 0x65 674 #define MYKONOS_ARM_OBJECTID_TRACKING_CAL_CONTROL 0x66 675 #define MYKONOS_ARM_OBJECTID_TRACKING_CAL_PENDING 0x67 676 #define MYKONOS_ARM_OBJECTID_RADIO_CONTROL 0x81 677 #define MYKONOS_ARM_OBJECTID_CALSCHEDULER 0x83 678 679 #define MYKONOS_ARM_SYSTEMSTATE_POWERUP 0x00 680 #define MYKONOS_ARM_SYSTEMSTATE_READY 0x01 681 #define MYKONOS_ARM_SYSTEMSTATE_IDLE 0x02 682 #define MYKONOS_ARM_SYSTEMSTATE_RADIO_ON 0x03 683 684 #define ORX_TRIGGER_SIGNALID 0x00 685 #define ORX_MODE_0_SIGNALID 0x01 686 #define ORX_MODE_1_SIGNALID 0x02 687 #define ORX_MODE_2_SIGNALID 0x03 688 #define RX1_ENABLE_ACK_SIGNALID 0x04 689 #define RX2_ENABLE_ACK_SIGNALID 0x05 690 #define TX1_ENABLE_ACK_SIGNALID 0x06 691 #define TX2_ENABLE_ACK_SIGNALID 0x07 692 #define ORX1_ENABLE_ACK_SIGNALID 0x08 693 #define ORX2_ENABLE_ACK_SIGNALID 0x09 694 #define SRX_ENABLE_ACK_SIGNALID 0x0A 695 #define TX_OBS_SELECT_SIGNALID 0x0B 696 697 #define DISABLE_DPD_ACTUATOR 0x03 698 #define ENABLE_DPD_ACTUATOR 0x04 699 #define SET_CLGC_DESIRED_GAIN_1 0x05 700 #define SET_CLGC_DESIRED_GAIN_2 0x06 701 #define SET_PATH_DELAY 0x08 702 703 #ifdef __cplusplus 704 } 705 #endif 706 707 #endif 708