xref: /dragonfly/sys/dev/netif/my/if_myreg.h (revision 86d7f5d3)
1 /*
2  * Copyright (c) 2002 Myson Technology Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions, and the following disclaimer,
10  *    without modification, immediately at the beginning of the file.
11  * 2. The name of the author may not be used to endorse or promote products
12  *    derived from this software without specific prior written permission.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  * Written by: yen_cw@myson.com.tw  available at: http://www.myson.com.tw/
27  *
28  * $FreeBSD: src/sys/dev/my/if_myreg.h,v 1.1.2.2 2002/04/17 02:05:27 julian Exp $
29  * $DragonFly: src/sys/dev/netif/my/if_myreg.h,v 1.5 2005/11/28 17:13:43 dillon Exp $
30  *
31  * Myson MTD80x register definitions.
32  *
33  */
34 #define MY_PAR0         0x0     /* physical address 0-3 */
35 #define MY_PAR1         0x04    /* physical address 4-5 */
36 #define MY_MAR0         0x08    /* multicast address 0-3 */
37 #define MY_MAR1         0x0C    /* multicast address 4-7 */
38 #define MY_FAR0         0x10    /* flow-control address 0-3 */
39 #define MY_FAR1         0x14    /* flow-control address 4-5 */
40 #define MY_TCRRCR       0x18    /* receive & transmit configuration */
41 #define MY_BCR          0x1C    /* bus command */
42 #define MY_TXPDR        0x20    /* transmit polling demand */
43 #define MY_RXPDR        0x24    /* receive polling demand */
44 #define MY_RXCWP        0x28    /* receive current word pointer */
45 #define MY_TXLBA        0x2C    /* transmit list base address */
46 #define MY_RXLBA        0x30    /* receive list base address */
47 #define MY_ISR          0x34    /* interrupt status */
48 #define MY_IMR          0x38    /* interrupt mask */
49 #define MY_FTH          0x3C    /* flow control high/low threshold */
50 #define MY_MANAGEMENT   0x40    /* bootrom/eeprom and mii management */
51 #define MY_TALLY        0x44    /* tally counters for crc and mpa */
52 #define MY_TSR          0x48    /* tally counter for transmit status */
53 #define MY_PHYBASE	0x4c
54 
55 /*
56  * Receive Configuration Register
57  */
58 #define MY_RXRUN        0x00008000      /* receive running status */
59 #define MY_EIEN         0x00004000      /* early interrupt enable */
60 #define MY_RFCEN        0x00002000      /* receive flow control packet enable */
61 #define MY_NDFA         0x00001000      /* not defined flow control address */
62 #define MY_RBLEN        0x00000800      /* receive burst length enable */
63 #define MY_RPBLE1       0x00000000      /* 1 word */
64 #define MY_RPBLE4       0x00000100      /* 4 words */
65 #define MY_RPBLE8       0x00000200      /* 8 words */
66 #define MY_RPBLE16      0x00000300      /* 16 words */
67 #define MY_RPBLE32      0x00000400      /* 32 words */
68 #define MY_RPBLE64      0x00000500      /* 64 words */
69 #define MY_RPBLE128     0x00000600      /* 128 words */
70 #define MY_RPBLE512     0x00000700      /* 512 words */
71 #define MY_PROM         0x000000080     /* promiscuous mode */
72 #define MY_AB           0x000000040     /* accept broadcast */
73 #define MY_AM           0x000000020     /* accept mutlicast */
74 #define MY_ARP          0x000000008     /* receive runt pkt */
75 #define MY_ALP          0x000000004     /* receive long pkt */
76 #define MY_SEP          0x000000002     /* receive error pkt */
77 #define MY_RE           0x000000001     /* receive enable */
78 
79 /*
80  * Transmit Configuration Register
81  */
82 #define MY_TXRUN        0x04000000      /* transmit running status */
83 #define MY_Enhanced     0x02000000      /* transmit enhanced mode */
84 #define MY_TFCEN        0x01000000      /* tx flow control packet enable */
85 #define MY_TFT64        0x00000000      /* 64 bytes */
86 #define MY_TFT32        0x00200000      /* 32 bytes */
87 #define MY_TFT128       0x00400000      /* 128 bytes */
88 #define MY_TFT256       0x00600000      /* 256 bytes */
89 #define MY_TFT512       0x00800000      /* 512 bytes */
90 #define MY_TFT768       0x00A00000      /* 768 bytes */
91 #define MY_TFT1024      0x00C00000      /* 1024 bytes */
92 #define MY_TFTSF        0x00E00000      /* store and forward */
93 #define MY_FD           0x00100000      /* full duplex mode */
94 #define MY_PS10         0x00080000      /* port speed is 10M */
95 #define MY_TE           0x00040000      /* transmit enable */
96 #define MY_PS1000       0x00010000      /* port speed is 1000M */
97 /*
98  * Bus Command Register
99  */
100 #define MY_PROG		0x00000200	/* programming */
101 #define MY_RLE          0x00000100      /* read line command enable */
102 #define MY_RME          0x00000080      /* read multiple command enable */
103 #define MY_WIE          0x00000040      /* write and invalidate cmd enable */
104 #define MY_PBL1         0x00000000      /* 1 dword */
105 #define MY_PBL4         0x00000008      /* 4 dwords */
106 #define MY_PBL8         0x00000010      /* 8 dwords */
107 #define MY_PBL16        0x00000018      /* 16 dwords */
108 #define MY_PBL32        0x00000020      /* 32 dwords */
109 #define MY_PBL64        0x00000028      /* 64 dwords */
110 #define MY_PBL128       0x00000030      /* 128 dwords */
111 #define MY_PBL512       0x00000038      /* 512 dwords */
112 #define MY_ABR          0x00000004      /* arbitration rule */
113 #define MY_BLS          0x00000002      /* big/little endian select */
114 #define MY_SWR          0x00000001      /* software reset */
115 
116 /*
117  * Transmit Poll Demand Register
118  */
119 #define MY_TxPollDemand 0x1
120 
121 /*
122  * Receive Poll Demand Register
123  */
124 #define MY_RxPollDemand 0x01
125 
126 /*
127  * Interrupt Status Register
128  */
129 #define MY_RFCON        0x00020000      /* receive flow control xon packet */
130 #define MY_RFCOFF       0x00010000      /* receive flow control xoff packet */
131 #define MY_LSCStatus    0x00008000      /* link status change */
132 #define MY_ANCStatus    0x00004000      /* autonegotiation completed */
133 #define MY_FBE          0x00002000      /* fatal bus error */
134 #define MY_FBEMask      0x00001800
135 #define MY_ParityErr    0x00000000      /* parity error */
136 #define MY_MasterErr    0x00000800      /* master error */
137 #define MY_TargetErr    0x00001000      /* target abort */
138 #define MY_TUNF         0x00000400      /* transmit underflow */
139 #define MY_ROVF         0x00000200      /* receive overflow */
140 #define MY_ETI          0x00000100      /* transmit early int */
141 #define MY_ERI          0x00000080      /* receive early int */
142 #define MY_CNTOVF       0x00000040      /* counter overflow */
143 #define MY_RBU          0x00000020      /* receive buffer unavailable */
144 #define MY_TBU          0x00000010      /* transmit buffer unavilable */
145 #define MY_TI           0x00000008      /* transmit interrupt */
146 #define MY_RI           0x00000004      /* receive interrupt */
147 #define MY_RxErr        0x00000002      /* receive error */
148 
149 /*
150  * Interrupt Mask Register
151  */
152 #define MY_MRFCON       0x00020000      /* receive flow control xon packet */
153 #define MY_MRFCOFF      0x00010000      /* receive flow control xoff packet */
154 #define MY_MLSCStatus   0x00008000      /* link status change */
155 #define MY_MANCStatus   0x00004000      /* autonegotiation completed */
156 #define MY_MFBE         0x00002000      /* fatal bus error */
157 #define MY_MFBEMask     0x00001800
158 #define MY_MTUNF        0x00000400      /* transmit underflow */
159 #define MY_MROVF        0x00000200      /* receive overflow */
160 #define MY_METI         0x00000100      /* transmit early int */
161 #define MY_MERI         0x00000080      /* receive early int */
162 #define MY_MCNTOVF      0x00000040      /* counter overflow */
163 #define MY_MRBU         0x00000020      /* receive buffer unavailable */
164 #define MY_MTBU         0x00000010      /* transmit buffer unavilable */
165 #define MY_MTI          0x00000008      /* transmit interrupt */
166 #define MY_MRI          0x00000004      /* receive interrupt */
167 #define MY_MRxErr       0x00000002      /* receive error */
168 
169 /* 90/1/18 delete */
170 /* #define MY_INTRS MY_FBE|MY_MRBU|MY_TBU|MY_MTI|MY_MRI|MY_METI */
171 #define MY_INTRS MY_MRBU|MY_TBU|MY_MTI|MY_MRI|MY_METI
172 
173 /*
174  * Flow Control High/Low Threshold Register
175  */
176 #define MY_FCHTShift    16      /* flow control high threshold */
177 #define MY_FCLTShift    0       /* flow control low threshold */
178 
179 /*
180  * BootROM/EEPROM/MII Management Register
181  */
182 #define MY_MASK_MIIR_MII_READ   0x00000000
183 #define MY_MASK_MIIR_MII_WRITE  0x00000008
184 #define MY_MASK_MIIR_MII_MDO    0x00000004
185 #define MY_MASK_MIIR_MII_MDI    0x00000002
186 #define MY_MASK_MIIR_MII_MDC    0x00000001
187 
188 /*
189  * Tally Counter for CRC and MPA
190  */
191 #define MY_TCOVF        0x80000000      /* crc tally counter overflow */
192 #define MY_CRCMask      0x7fff0000      /* crc number: bit 16-30 */
193 #define MY_CRCShift     16
194 #define MY_TMOVF        0x00008000      /* mpa tally counter overflow */
195 #define MY_MPAMask      0x00007fff      /* mpa number: bit 0-14 */
196 #define MY_MPAShift     0
197 
198 /*
199  * Tally Counters for transmit status
200  */
201 #define MY_AbortMask      0xff000000    /* transmit abort number */
202 #define MY_AbortShift     24
203 #define MY_LColMask       0x00ff0000    /* transmit late collisions */
204 #define MY_LColShift      16
205 #define MY_NCRMask        0x0000ffff    /* transmit retry number */
206 #define MY_NCRShift       0
207 
208 /*
209  * Myson TX/RX descriptor structure.
210  */
211 
212 struct my_desc {
213         u_int32_t       my_status;
214         u_int32_t       my_ctl;
215         u_int32_t       my_data;
216         u_int32_t       my_next;
217 };
218 
219 /*
220  * for tx/rx descriptors
221  */
222 #define MY_OWNByNIC     0x80000000
223 #define MY_OWNByDriver  0x0
224 
225 /*
226  * receive descriptor 0
227  */
228 #define MY_RXOWN        0x80000000      /* own bit */
229 #define MY_FLNGMASK     0x0fff0000      /* frame length */
230 #define MY_FLNGShift    16
231 #define MY_MARSTATUS    0x00004000      /* multicast address received */
232 #define MY_BARSTATUS    0x00002000      /* broadcast address received */
233 #define MY_PHYSTATUS    0x00001000      /* physical address received */
234 #define MY_RXFSD        0x00000800      /* first descriptor */
235 #define MY_RXLSD        0x00000400      /* last descriptor */
236 #define MY_ES           0x00000080      /* error summary */
237 #define MY_RUNT         0x00000040      /* runt packet received */
238 #define MY_LONG         0x00000020      /* long packet received */
239 #define MY_FAE          0x00000010      /* frame align error */
240 #define MY_CRC          0x00000008      /* crc error */
241 #define MY_RXER         0x00000004      /* receive error */
242 #define MY_RDES0CHECK   0x000078fc      /* only check MAR, BAR, PHY, ES, RUNT,
243                                            LONG, FAE, CRC and RXER bits */
244 
245 /*
246  * receive descriptor 1
247  */
248 #define MY_RXIC         0x00800000      /* interrupt control */
249 #define MY_RBSMASK      0x000007ff      /* receive buffer size */
250 #define MY_RBSShift     0
251 
252 /*
253  * transmit descriptor 0
254  */
255 #define MY_TXERR        0x00008000      /* transmit error */
256 #define MY_JABTO        0x00004000      /* jabber timeout */
257 #define MY_CSL          0x00002000      /* carrier sense lost */
258 #define MY_LC           0x00001000      /* late collision */
259 #define MY_EC           0x00000800      /* excessive collision */
260 #define MY_UDF          0x00000400      /* fifo underflow */
261 #define MY_DFR          0x00000200      /* deferred */
262 #define MY_HF           0x00000100      /* heartbeat fail */
263 #define MY_NCRMASK      0x000000ff      /* collision retry count */
264 #define MY_NCRShift     0
265 
266 /*
267  * tx descriptor 1
268  */
269 #define MY_TXIC         0x80000000      /* interrupt control */
270 #define MY_ETIControl   0x40000000      /* early transmit interrupt */
271 #define MY_TXLD         0x20000000      /* last descriptor */
272 #define MY_TXFD         0x10000000      /* first descriptor */
273 #define MY_CRCDisable   0x00000000      /* crc control */
274 #define MY_CRCEnable    0x08000000
275 #define MY_PADDisable   0x00000000      /* padding control */
276 #define MY_PADEnable    0x04000000
277 #define MY_RetryTxLC	0x02000000	/* retry late collision */
278 #define MY_PKTShift     11              /* transmit pkt size */
279 #define MY_TBSMASK      0x000007ff
280 #define MY_TBSShift     0               /* transmit buffer size */
281 
282 #define MY_MAXFRAGS     1
283 #define MY_RX_LIST_CNT  64
284 #define MY_TX_LIST_CNT  64
285 #define MY_MIN_FRAMELEN 60
286 
287 /*
288  * A transmit 'super descriptor' is actually MY_MAXFRAGS regular
289  * descriptors clumped together. The idea here is to emulate the
290  * multi-fragment descriptor layout found in devices such as the
291  * Texas Instruments ThunderLAN and 3Com boomerang and cylone chips.
292  * The advantage to using this scheme is that it avoids buffer copies.
293  * The disadvantage is that there's a certain amount of overhead due
294  * to the fact that each 'fragment' is 16 bytes long. In my tests,
295  * this limits top speed to about 10.5MB/sec. It should be more like
296  * 11.5MB/sec. However, the upshot is that you can achieve better
297  * results on slower machines: a Pentium 200 can pump out packets at
298  * same speed as a PII 400.
299  */
300 struct my_txdesc {
301         struct my_desc          my_frag[MY_MAXFRAGS];
302 };
303 
304 #define MY_TXSTATUS(x)  x->my_ptr->my_frag[x->my_lastdesc].my_status
305 #define MY_TXCTL(x)     x->my_ptr->my_frag[x->my_lastdesc].my_ctl
306 #define MY_TXDATA(x)    x->my_ptr->my_frag[x->my_lastdesc].my_data
307 #define MY_TXNEXT(x)    x->my_ptr->my_frag[x->my_lastdesc].my_next
308 
309 #define MY_TXOWN(x)     x->my_ptr->my_frag[0].my_status
310 
311 #define MY_UNSENT       0x1234
312 
313 struct my_list_data {
314         struct my_desc          my_rx_list[MY_RX_LIST_CNT];
315         struct my_txdesc        my_tx_list[MY_TX_LIST_CNT];
316 };
317 
318 struct my_chain {
319         struct my_txdesc        *my_ptr;
320         struct mbuf             *my_mbuf;
321         struct my_chain         *my_nextdesc;
322         u_int8_t                my_lastdesc;
323 };
324 
325 struct my_chain_onefrag {
326         struct my_desc          *my_ptr;
327         struct mbuf             *my_mbuf;
328         struct my_chain_onefrag *my_nextdesc;
329         u_int8_t                my_rlast;
330 };
331 
332 struct my_chain_data {
333         struct my_chain_onefrag my_rx_chain[MY_RX_LIST_CNT];
334         struct my_chain         my_tx_chain[MY_TX_LIST_CNT];
335 
336         struct my_chain_onefrag *my_rx_head;
337 
338         struct my_chain         *my_tx_head;
339         struct my_chain         *my_tx_tail;
340         struct my_chain         *my_tx_free;
341 };
342 
343 struct my_type {
344         u_int16_t               my_vid;
345         u_int16_t               my_did;
346         char                    *my_name;
347 };
348 
349 #define MY_FLAG_FORCEDELAY      1
350 #define MY_FLAG_SCHEDDELAY      2
351 #define MY_FLAG_DELAYTIMEO      3
352 
353 struct my_softc {
354         struct arpcom           arpcom;         /* interface info */
355         struct ifmedia          ifmedia;        /* media info */
356         bus_space_handle_t      my_bhandle;
357         bus_space_tag_t         my_btag;
358         struct my_type          *my_info;       /* adapter info */
359         struct my_type          *my_pinfo;      /* phy info */
360 	struct resource		*my_res;
361 	struct resource		*my_irq;
362 	void			*my_intrhand;
363         u_int8_t                my_unit;        /* interface number */
364         u_int8_t                my_phy_addr;    /* PHY address */
365         u_int8_t                my_tx_pend;     /* TX pending */
366         u_int8_t                my_want_auto;
367         u_int8_t                my_autoneg;
368         u_int16_t               my_txthresh;
369 	u_int8_t		my_stats_no_timeout;
370         caddr_t                 my_ldata_ptr;
371         struct my_list_data     *my_ldata;
372         struct my_chain_data    my_cdata;
373 	device_t		my_miibus;
374 
375 };
376 
377 /*
378  * register space access macros
379  */
380 #define CSR_WRITE_4(sc, reg, val)       \
381         bus_space_write_4(sc->my_btag, sc->my_bhandle, reg, val)
382 #define CSR_WRITE_2(sc, reg, val)       \
383         bus_space_write_2(sc->my_btag, sc->my_bhandle, reg, val)
384 #define CSR_WRITE_1(sc, reg, val)       \
385         bus_space_write_1(sc->my_btag, sc->my_bhandle, reg, val)
386 
387 #define CSR_READ_4(sc, reg)     \
388         bus_space_read_4(sc->my_btag, sc->my_bhandle, reg)
389 #define CSR_READ_2(sc, reg)     \
390         bus_space_read_2(sc->my_btag, sc->my_bhandle, reg)
391 #define CSR_READ_1(sc, reg)     \
392         bus_space_read_1(sc->my_btag, sc->my_bhandle, reg)
393 
394 #define MY_TIMEOUT              1000
395 
396 /*
397  * General constants that are fun to know.
398  *
399  * MYSON PCI vendor ID
400  */
401 #define MYSONVENDORID           0x1516
402 
403 /*
404  * MYSON device IDs.
405  */
406 #define MTD800ID                0x0800
407 #define MTD803ID                0x0803
408 #define MTD891ID                0x0891
409 
410 /*
411  * ST+OP+PHYAD+REGAD+TA
412  */
413 #define MY_OP_READ      0x6000  /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
414 #define MY_OP_WRITE     0x5002  /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
415 
416 /*
417  * Constansts for Myson PHY
418  */
419 #define MysonPHYID0     0x0300
420 
421 /*
422  * Constansts for Seeq 80225 PHY
423  */
424 #define SeeqPHYID0      0x0016
425 
426 #define SEEQ_MIIRegister18      18
427 #define SEEQ_SPD_DET_100        0x80
428 #define SEEQ_DPLX_DET_FULL      0x40
429 
430 /*
431  * Constansts for Ahdoc 101 PHY
432  */
433 #define AhdocPHYID0     0x0022
434 
435 #define AHDOC_DiagnosticReg     18
436 #define AHDOC_DPLX_FULL         0x0800
437 #define AHDOC_Speed_100         0x0400
438 
439 /*
440  * Constansts for Marvell 88E1000/88E1000S PHY and LevelOne PHY
441  */
442 #define MarvellPHYID0           0x0141
443 #define LevelOnePHYID0		0x0013
444 
445 #define Marvell_SpecificStatus  17
446 #define Marvell_Speed1000       0x8000
447 #define Marvell_Speed100        0x4000
448 #define Marvell_FullDuplex      0x2000
449 
450 /*
451  * PCI low memory base and low I/O base register, and
452  * other PCI registers. Note: some are only available on
453  * the 3c905B, in particular those that related to power management.
454  */
455 #define MY_PCI_VENDOR_ID        0x00
456 #define MY_PCI_DEVICE_ID        0x02
457 #define MY_PCI_COMMAND          0x04
458 #define MY_PCI_STATUS           0x06
459 #define MY_PCI_CLASSCODE        0x09
460 #define MY_PCI_LATENCY_TIMER    0x0D
461 #define MY_PCI_HEADER_TYPE      0x0E
462 #define MY_PCI_LOIO             0x10
463 #define MY_PCI_LOMEM            0x14
464 #define MY_PCI_BIOSROM          0x30
465 #define MY_PCI_INTLINE          0x3C
466 #define MY_PCI_INTPIN           0x3D
467 #define MY_PCI_MINGNT           0x3E
468 #define MY_PCI_MINLAT           0x0F
469 #define MY_PCI_RESETOPT         0x48
470 #define MY_PCI_EEPROM_DATA      0x4C
471 
472 #define PHY_UNKNOWN             3
473 
474 #define MY_PHYADDR_MIN          0x00
475 #define MY_PHYADDR_MAX          0x1F
476 
477 #define PHY_BMCR                0x00
478 #define PHY_BMSR                0x01
479 #define PHY_VENID               0x02
480 #define PHY_DEVID               0x03
481 #define PHY_ANAR                0x04
482 #define PHY_LPAR                0x05
483 #define PHY_ANEXP               0x06
484 #define PHY_NPTR                0x07
485 #define PHY_LPNPR               0x08
486 #define PHY_1000CR              0x09
487 #define PHY_1000SR              0x0a
488 
489 #define PHY_ANAR_NEXTPAGE       0x8000
490 #define PHY_ANAR_RSVD0          0x4000
491 #define PHY_ANAR_TLRFLT         0x2000
492 #define PHY_ANAR_RSVD1          0x1000
493 #define PHY_ANAR_RSVD2          0x0800
494 #define PHY_ANAR_RSVD3          0x0400
495 #define PHY_ANAR_100BT4         0x0200L
496 #define PHY_ANAR_100BTXFULL     0x0100
497 #define PHY_ANAR_100BTXHALF     0x0080
498 #define PHY_ANAR_10BTFULL       0x0040
499 #define PHY_ANAR_10BTHALF       0x0020
500 #define PHY_ANAR_PROTO4         0x0010
501 #define PHY_ANAR_PROTO3         0x0008
502 #define PHY_ANAR_PROTO2         0x0004
503 #define PHY_ANAR_PROTO1         0x0002
504 #define PHY_ANAR_PROTO0         0x0001
505 
506 #define PHY_1000SR_1000BTXFULL  0x0800
507 #define PHY_1000SR_1000BTXHALF  0x0400
508 
509 /*
510  * These are the register definitions for the PHY (physical layer
511  * interface chip).
512  */
513 /*
514  * PHY BMCR Basic Mode Control Register
515  */
516 #define PHY_BMCR_RESET                  0x8000
517 #define PHY_BMCR_LOOPBK                 0x4000
518 #define PHY_BMCR_SPEEDSEL               0x2000
519 #define PHY_BMCR_AUTONEGENBL            0x1000
520 #define PHY_BMCR_RSVD0                  0x0800  /* write as zero */
521 #define PHY_BMCR_ISOLATE                0x0400
522 #define PHY_BMCR_AUTONEGRSTR            0x0200
523 #define PHY_BMCR_DUPLEX                 0x0100
524 #define PHY_BMCR_COLLTEST               0x0080
525 #define PHY_BMCR_1000                   0x0040  /* only used for Marvell PHY */
526 #define PHY_BMCR_RSVD2                  0x0020  /* write as zero, don't care */
527 #define PHY_BMCR_RSVD3                  0x0010  /* write as zero, don't care */
528 #define PHY_BMCR_RSVD4                  0x0008  /* write as zero, don't care */
529 #define PHY_BMCR_RSVD5                  0x0004  /* write as zero, don't care */
530 #define PHY_BMCR_RSVD6                  0x0002  /* write as zero, don't care */
531 #define PHY_BMCR_RSVD7                  0x0001  /* write as zero, don't care */
532 
533 /*
534  * RESET: 1 == software reset, 0 == normal operation
535  * Resets status and control registers to default values.
536  * Relatches all hardware config values.
537  *
538  * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
539  *
540  * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
541  * Link speed is selected byt his bit or if auto-negotiation if bit
542  * 12 (AUTONEGENBL) is set (in which case the value of this register
543  * is ignored).
544  *
545  * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
546  * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
547  * determine speed and mode. Should be cleared and then set if PHY configured
548  * for no autoneg on startup.
549  *
550  * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
551  *
552  * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
553  *
554  * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
555  *
556  * COLLTEST: 1 == collision test enabled, 0 == normal operation
557  */
558 
559 /*
560  * PHY, BMSR Basic Mode Status Register
561  */
562 #define PHY_BMSR_100BT4                 0x8000
563 #define PHY_BMSR_100BTXFULL             0x4000
564 #define PHY_BMSR_100BTXHALF             0x2000
565 #define PHY_BMSR_10BTFULL               0x1000
566 #define PHY_BMSR_10BTHALF               0x0800
567 #define PHY_BMSR_RSVD1                  0x0400  /* write as zero, don't care */
568 #define PHY_BMSR_RSVD2                  0x0200  /* write as zero, don't care */
569 #define PHY_BMSR_RSVD3                  0x0100  /* write as zero, don't care */
570 #define PHY_BMSR_RSVD4                  0x0080  /* write as zero, don't care */
571 #define PHY_BMSR_MFPRESUP               0x0040
572 #define PHY_BMSR_AUTONEGCOMP            0x0020
573 #define PHY_BMSR_REMFAULT               0x0010
574 #define PHY_BMSR_CANAUTONEG             0x0008
575 #define PHY_BMSR_LINKSTAT               0x0004
576 #define PHY_BMSR_JABBER                 0x0002
577 #define PHY_BMSR_EXTENDED               0x0001
578 
579 
580