xref: /dragonfly/sys/platform/pc64/icu/icu_abi.c (revision db2ec6f8)
1 /*
2  * Copyright (c) 1991 The Regents of the University of California.
3  * Copyright (c) 2005,2008 The DragonFly Project.
4  * All rights reserved.
5  *
6  * This code is derived from software contributed to The DragonFly Project
7  * by Matthew Dillon <dillon@backplane.com>
8  *
9  * This code is derived from software contributed to Berkeley by
10  * William Jolitz.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  *
16  * 1. Redistributions of source code must retain the above copyright
17  *    notice, this list of conditions and the following disclaimer.
18  * 2. Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in
20  *    the documentation and/or other materials provided with the
21  *    distribution.
22  * 3. Neither the name of The DragonFly Project nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific, prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
30  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
32  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
34  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37  * SUCH DAMAGE.
38  */
39 
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/machintr.h>
44 #include <sys/interrupt.h>
45 #include <sys/rman.h>
46 #include <sys/bus.h>
47 
48 #include <machine/segments.h>
49 #include <machine/md_var.h>
50 #include <machine/intr_machdep.h>
51 #include <machine/globaldata.h>
52 #include <machine/smp.h>
53 #include <machine/msi_var.h>
54 
55 #include <machine_base/icu/elcr_var.h>
56 
57 #include <machine_base/icu/icu.h>
58 #include <machine_base/icu/icu_abi.h>
59 #include <machine_base/icu/icu_ipl.h>
60 #include <machine_base/apic/ioapic.h>
61 
62 extern inthand_t
63 	IDTVEC(icu_intr0),	IDTVEC(icu_intr1),
64 	IDTVEC(icu_intr2),	IDTVEC(icu_intr3),
65 	IDTVEC(icu_intr4),	IDTVEC(icu_intr5),
66 	IDTVEC(icu_intr6),	IDTVEC(icu_intr7),
67 	IDTVEC(icu_intr8),	IDTVEC(icu_intr9),
68 	IDTVEC(icu_intr10),	IDTVEC(icu_intr11),
69 	IDTVEC(icu_intr12),	IDTVEC(icu_intr13),
70 	IDTVEC(icu_intr14),	IDTVEC(icu_intr15);
71 
72 static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
73 	&IDTVEC(icu_intr0),	&IDTVEC(icu_intr1),
74 	&IDTVEC(icu_intr2),	&IDTVEC(icu_intr3),
75 	&IDTVEC(icu_intr4),	&IDTVEC(icu_intr5),
76 	&IDTVEC(icu_intr6),	&IDTVEC(icu_intr7),
77 	&IDTVEC(icu_intr8),	&IDTVEC(icu_intr9),
78 	&IDTVEC(icu_intr10),	&IDTVEC(icu_intr11),
79 	&IDTVEC(icu_intr12),	&IDTVEC(icu_intr13),
80 	&IDTVEC(icu_intr14),	&IDTVEC(icu_intr15)
81 };
82 
83 static struct icu_irqmap {
84 	int			im_type;	/* ICU_IMT_ */
85 	enum intr_trigger	im_trig;
86 	int			im_msi_base;
87 	uint32_t		im_flags;	/* ICU_IMF_ */
88 } icu_irqmaps[MAXCPU][IDT_HWI_VECTORS];
89 
90 static struct lwkt_token icu_irqmap_tok =
91 	LWKT_TOKEN_INITIALIZER(icu_irqmap_token);
92 
93 #define ICU_IMT_UNUSED		0	/* KEEP THIS */
94 #define ICU_IMT_RESERVED	1
95 #define ICU_IMT_LEGACY		2
96 #define ICU_IMT_SYSCALL		3
97 #define ICU_IMT_MSI		4
98 #define ICU_IMT_MSIX		5
99 
100 #define ICU_IMT_ISHWI(map)	((map)->im_type != ICU_IMT_RESERVED && \
101 				 (map)->im_type != ICU_IMT_SYSCALL)
102 
103 #define ICU_IMF_CONF		0x1
104 
105 extern void	ICU_INTREN(int);
106 extern void	ICU_INTRDIS(int);
107 
108 extern int	imcr_present;
109 
110 static void	icu_abi_intr_enable(int);
111 static void	icu_abi_intr_disable(int);
112 static void	icu_abi_intr_setup(int, int);
113 static void	icu_abi_intr_teardown(int);
114 
115 static void	icu_abi_legacy_intr_config(int, enum intr_trigger,
116 		    enum intr_polarity);
117 static int	icu_abi_legacy_intr_cpuid(int);
118 static int	icu_abi_legacy_intr_find(int, enum intr_trigger,
119 		    enum intr_polarity);
120 static int	icu_abi_legacy_intr_find_bygsi(int, enum intr_trigger,
121 		    enum intr_polarity);
122 
123 static int	icu_abi_msi_alloc(int [], int, int);
124 static void	icu_abi_msi_release(const int [], int, int);
125 static void	icu_abi_msi_map(int, uint64_t *, uint32_t *, int);
126 static int	icu_abi_msix_alloc(int *, int);
127 static void	icu_abi_msix_release(int, int);
128 
129 static int	icu_abi_msi_alloc_intern(int, const char *,
130 		    int [], int, int);
131 static void	icu_abi_msi_release_intern(int, const char *,
132 		    const int [], int, int);
133 
134 static void	icu_abi_finalize(void);
135 static void	icu_abi_cleanup(void);
136 static void	icu_abi_setdefault(void);
137 static void	icu_abi_stabilize(void);
138 static void	icu_abi_initmap(void);
139 static void	icu_abi_rman_setup(struct rman *);
140 
141 struct machintr_abi MachIntrABI_ICU = {
142 	MACHINTR_ICU,
143 	.intr_disable	= icu_abi_intr_disable,
144 	.intr_enable	= icu_abi_intr_enable,
145 	.intr_setup	= icu_abi_intr_setup,
146 	.intr_teardown	= icu_abi_intr_teardown,
147 
148 	.legacy_intr_config = icu_abi_legacy_intr_config,
149 	.legacy_intr_cpuid = icu_abi_legacy_intr_cpuid,
150 	.legacy_intr_find = icu_abi_legacy_intr_find,
151 	.legacy_intr_find_bygsi = icu_abi_legacy_intr_find_bygsi,
152 
153 	.msi_alloc	= icu_abi_msi_alloc,
154 	.msi_release	= icu_abi_msi_release,
155 	.msi_map	= icu_abi_msi_map,
156 	.msix_alloc	= icu_abi_msix_alloc,
157 	.msix_release	= icu_abi_msix_release,
158 
159 	.finalize	= icu_abi_finalize,
160 	.cleanup	= icu_abi_cleanup,
161 	.setdefault	= icu_abi_setdefault,
162 	.stabilize	= icu_abi_stabilize,
163 	.initmap	= icu_abi_initmap,
164 	.rman_setup	= icu_abi_rman_setup
165 };
166 
167 static int	icu_abi_msi_start;	/* NOTE: for testing only */
168 
169 /*
170  * WARNING!  SMP builds can use the ICU now so this code must be MP safe.
171  */
172 
173 static void
icu_abi_intr_enable(int irq)174 icu_abi_intr_enable(int irq)
175 {
176 	const struct icu_irqmap *map;
177 
178 	KASSERT(irq >= 0 && irq < IDT_HWI_VECTORS,
179 	    ("icu enable, invalid irq %d", irq));
180 
181 	map = &icu_irqmaps[mycpuid][irq];
182 	KASSERT(ICU_IMT_ISHWI(map),
183 	    ("icu enable, not hwi irq %d, type %d, cpu%d",
184 	     irq, map->im_type, mycpuid));
185 	if (map->im_type != ICU_IMT_LEGACY)
186 		return;
187 
188 	ICU_INTREN(irq);
189 }
190 
191 static void
icu_abi_intr_disable(int irq)192 icu_abi_intr_disable(int irq)
193 {
194 	const struct icu_irqmap *map;
195 
196 	KASSERT(irq >= 0 && irq < IDT_HWI_VECTORS,
197 	    ("icu disable, invalid irq %d", irq));
198 
199 	map = &icu_irqmaps[mycpuid][irq];
200 	KASSERT(ICU_IMT_ISHWI(map),
201 	    ("icu disable, not hwi irq %d, type %d, cpu%d",
202 	     irq, map->im_type, mycpuid));
203 	if (map->im_type != ICU_IMT_LEGACY)
204 		return;
205 
206 	ICU_INTRDIS(irq);
207 }
208 
209 /*
210  * Called before interrupts are physically enabled
211  */
212 static void
icu_abi_stabilize(void)213 icu_abi_stabilize(void)
214 {
215 	int intr;
216 
217 	for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
218 		ICU_INTRDIS(intr);
219 	ICU_INTREN(ICU_IRQ_SLAVE);
220 }
221 
222 /*
223  * Called after interrupts physically enabled but before the
224  * critical section is released.
225  */
226 static void
icu_abi_cleanup(void)227 icu_abi_cleanup(void)
228 {
229 	bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
230 }
231 
232 /*
233  * Called after stablize and cleanup; critical section is not
234  * held and interrupts are not physically disabled.
235  */
236 static void
icu_abi_finalize(void)237 icu_abi_finalize(void)
238 {
239 	KKASSERT(MachIntrABI.type == MACHINTR_ICU);
240 	KKASSERT(!ioapic_enable);
241 
242 	/*
243 	 * If an IMCR is present, programming bit 0 disconnects the 8259
244 	 * from the BSP.  The 8259 may still be connected to LINT0 on the
245 	 * BSP's LAPIC.
246 	 *
247 	 * If we are running SMP the LAPIC is active, try to use virtual
248 	 * wire mode so we can use other interrupt sources within the LAPIC
249 	 * in addition to the 8259.
250 	 */
251 	if (imcr_present) {
252 		outb(0x22, 0x70);
253 		outb(0x23, 0x01);
254 	}
255 }
256 
257 static void
icu_abi_intr_setup(int intr,int flags)258 icu_abi_intr_setup(int intr, int flags)
259 {
260 	const struct icu_irqmap *map;
261 	register_t ef;
262 
263 	KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS,
264 	    ("icu setup, invalid irq %d", intr));
265 
266 	map = &icu_irqmaps[mycpuid][intr];
267 	KASSERT(ICU_IMT_ISHWI(map),
268 	    ("icu setup, not hwi irq %d, type %d, cpu%d",
269 	     intr, map->im_type, mycpuid));
270 	if (map->im_type != ICU_IMT_LEGACY)
271 		return;
272 
273 	ef = read_rflags();
274 	cpu_disable_intr();
275 
276 	ICU_INTREN(intr);
277 
278 	write_rflags(ef);
279 }
280 
281 static void
icu_abi_intr_teardown(int intr)282 icu_abi_intr_teardown(int intr)
283 {
284 	const struct icu_irqmap *map;
285 	register_t ef;
286 
287 	KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS,
288 	    ("icu teardown, invalid irq %d", intr));
289 
290 	map = &icu_irqmaps[mycpuid][intr];
291 	KASSERT(ICU_IMT_ISHWI(map),
292 	    ("icu teardown, not hwi irq %d, type %d, cpu%d",
293 	     intr, map->im_type, mycpuid));
294 	if (map->im_type != ICU_IMT_LEGACY)
295 		return;
296 
297 	ef = read_rflags();
298 	cpu_disable_intr();
299 
300 	ICU_INTRDIS(intr);
301 
302 	write_rflags(ef);
303 }
304 
305 static void
icu_abi_setdefault(void)306 icu_abi_setdefault(void)
307 {
308 	int intr;
309 
310 	for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
311 		if (intr == ICU_IRQ_SLAVE)
312 			continue;
313 		setidt_global(IDT_OFFSET + intr, icu_intr[intr],
314 		    SDT_SYSIGT, SEL_KPL, 0);
315 	}
316 }
317 
318 static void
icu_abi_initmap(void)319 icu_abi_initmap(void)
320 {
321 	int cpu;
322 
323 	kgetenv_int("hw.icu.msi_start", &icu_abi_msi_start);
324 	icu_abi_msi_start &= ~0x1f;	/* MUST be 32 aligned */
325 
326 	/*
327 	 * NOTE: ncpus is not ready yet
328 	 */
329 	for (cpu = 0; cpu < MAXCPU; ++cpu) {
330 		int i;
331 
332 		if (cpu != 0) {
333 			for (i = 0; i < ICU_HWI_VECTORS; ++i)
334 				icu_irqmaps[cpu][i].im_type = ICU_IMT_RESERVED;
335 		} else {
336 			for (i = 0; i < ICU_HWI_VECTORS; ++i)
337 				icu_irqmaps[cpu][i].im_type = ICU_IMT_LEGACY;
338 			icu_irqmaps[cpu][ICU_IRQ_SLAVE].im_type =
339 			    ICU_IMT_RESERVED;
340 
341 			if (elcr_found) {
342 				for (i = 0; i < ICU_HWI_VECTORS; ++i) {
343 					icu_irqmaps[cpu][i].im_trig =
344 					    elcr_read_trigger(i);
345 				}
346 			} else {
347 				/*
348 				 * NOTE: Trigger mode does not matter at all
349 				 */
350 				for (i = 0; i < ICU_HWI_VECTORS; ++i) {
351 					icu_irqmaps[cpu][i].im_trig =
352 					    INTR_TRIGGER_EDGE;
353 				}
354 			}
355 		}
356 
357 		for (i = 0; i < IDT_HWI_VECTORS; ++i)
358 			icu_irqmaps[cpu][i].im_msi_base = -1;
359 
360 		icu_irqmaps[cpu][IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type =
361 		    ICU_IMT_SYSCALL;
362 	}
363 }
364 
365 static void
icu_abi_legacy_intr_config(int irq,enum intr_trigger trig,enum intr_polarity pola __unused)366 icu_abi_legacy_intr_config(int irq, enum intr_trigger trig,
367     enum intr_polarity pola __unused)
368 {
369 	struct icu_irqmap *map;
370 
371 	KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
372 
373 	KKASSERT(irq >= 0 && irq < IDT_HWI_VECTORS);
374 	map = &icu_irqmaps[0][irq];
375 
376 	KKASSERT(map->im_type == ICU_IMT_LEGACY);
377 
378 	/* TODO: Check whether it is configured or not */
379 	map->im_flags |= ICU_IMF_CONF;
380 
381 	if (trig == map->im_trig)
382 		return;
383 
384 	if (bootverbose) {
385 		kprintf("ICU: irq %d, %s -> %s\n", irq,
386 			intr_str_trigger(map->im_trig),
387 			intr_str_trigger(trig));
388 	}
389 	map->im_trig = trig;
390 
391 	if (!elcr_found) {
392 		if (bootverbose)
393 			kprintf("ICU: no ELCR, skip irq %d config\n", irq);
394 		return;
395 	}
396 	elcr_write_trigger(irq, map->im_trig);
397 }
398 
399 static int
icu_abi_legacy_intr_cpuid(int irq __unused)400 icu_abi_legacy_intr_cpuid(int irq __unused)
401 {
402 	return 0;
403 }
404 
405 static void
icu_abi_rman_setup(struct rman * rm)406 icu_abi_rman_setup(struct rman *rm)
407 {
408 	int start, end, i;
409 
410 	KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU,
411 	    ("invalid rman cpuid %d", rm->rm_cpuid));
412 
413 	start = end = -1;
414 	for (i = 0; i < IDT_HWI_VECTORS; ++i) {
415 		const struct icu_irqmap *map = &icu_irqmaps[rm->rm_cpuid][i];
416 
417 		if (start < 0) {
418 			if (ICU_IMT_ISHWI(map))
419 				start = end = i;
420 		} else {
421 			if (ICU_IMT_ISHWI(map)) {
422 				end = i;
423 			} else {
424 				KKASSERT(end >= 0);
425 				if (bootverbose) {
426 					kprintf("ICU: rman cpu%d %d - %d\n",
427 					    rm->rm_cpuid, start, end);
428 				}
429 				if (rman_manage_region(rm, start, end)) {
430 					panic("rman_manage_region"
431 					    "(cpu%d %d - %d)", rm->rm_cpuid,
432 					    start, end);
433 				}
434 				start = end = -1;
435 			}
436 		}
437 	}
438 	if (start >= 0) {
439 		KKASSERT(end >= 0);
440 		if (bootverbose) {
441 			kprintf("ICU: rman cpu%d %d - %d\n",
442 			    rm->rm_cpuid, start, end);
443 		}
444 		if (rman_manage_region(rm, start, end)) {
445 			panic("rman_manage_region(cpu%d %d - %d)",
446 			    rm->rm_cpuid, start, end);
447 		}
448 	}
449 }
450 
451 static int
icu_abi_msi_alloc_intern(int type,const char * desc,int intrs[],int count,int cpuid)452 icu_abi_msi_alloc_intern(int type, const char *desc,
453     int intrs[], int count, int cpuid)
454 {
455 	int i, error;
456 
457 	KASSERT(cpuid >= 0 && cpuid < ncpus,
458 	    ("invalid cpuid %d", cpuid));
459 
460 	KASSERT(count > 0 && count <= 32, ("invalid count %d", count));
461 	KASSERT(powerof2(count), ("count %d is not power of 2", count));
462 
463 	lwkt_gettoken(&icu_irqmap_tok);
464 
465 	/*
466 	 * NOTE:
467 	 * Since IDT_OFFSET is 32, which is the maximum valid 'count',
468 	 * we do not need to find out the first properly aligned
469 	 * interrupt vector.
470 	 */
471 
472 	error = EMSGSIZE;
473 	for (i = icu_abi_msi_start; i < IDT_HWI_VECTORS; i += count) {
474 		int j;
475 
476 		if (icu_irqmaps[cpuid][i].im_type != ICU_IMT_UNUSED)
477 			continue;
478 
479 		for (j = 1; j < count; ++j) {
480 			if (icu_irqmaps[cpuid][i + j].im_type != ICU_IMT_UNUSED)
481 				break;
482 		}
483 		if (j != count)
484 			continue;
485 
486 		for (j = 0; j < count; ++j) {
487 			struct icu_irqmap *map;
488 			int intr = i + j;
489 
490 			map = &icu_irqmaps[cpuid][intr];
491 			KASSERT(map->im_msi_base < 0,
492 			    ("intr %d, stale %s-base %d",
493 			     intr, desc, map->im_msi_base));
494 
495 			map->im_type = type;
496 			map->im_msi_base = i;
497 
498 			intrs[j] = intr;
499 			msi_setup(intr, cpuid);
500 
501 			if (bootverbose) {
502 				kprintf("alloc %s intr %d on cpu%d\n",
503 				    desc, intr, cpuid);
504 			}
505 		}
506 		error = 0;
507 		break;
508 	}
509 
510 	lwkt_reltoken(&icu_irqmap_tok);
511 
512 	return error;
513 }
514 
515 static void
icu_abi_msi_release_intern(int type,const char * desc,const int intrs[],int count,int cpuid)516 icu_abi_msi_release_intern(int type, const char *desc,
517     const int intrs[], int count, int cpuid)
518 {
519 	int i, msi_base = -1, intr_next = -1, mask;
520 
521 	KASSERT(cpuid >= 0 && cpuid < ncpus,
522 	    ("invalid cpuid %d", cpuid));
523 
524 	KASSERT(count > 0 && count <= 32, ("invalid count %d", count));
525 
526 	mask = count - 1;
527 	KASSERT((count & mask) == 0, ("count %d is not power of 2", count));
528 
529 	lwkt_gettoken(&icu_irqmap_tok);
530 
531 	for (i = 0; i < count; ++i) {
532 		struct icu_irqmap *map;
533 		int intr = intrs[i];
534 
535 		KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS,
536 		    ("invalid intr %d", intr));
537 
538 		map = &icu_irqmaps[cpuid][intr];
539 		KASSERT(map->im_type == type,
540 		    ("trying to release non-%s intr %d, type %d", desc,
541 		     intr, map->im_type));
542 		KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr,
543 		    ("intr %d, invalid %s-base %d", intr, desc,
544 		     map->im_msi_base));
545 		KASSERT((map->im_msi_base & mask) == 0,
546 		    ("intr %d, %s-base %d is not properly aligned %d",
547 		     intr, desc, map->im_msi_base, count));
548 
549 		if (msi_base < 0) {
550 			msi_base = map->im_msi_base;
551 		} else {
552 			KASSERT(map->im_msi_base == msi_base,
553 			    ("intr %d, inconsistent %s-base, "
554 			     "was %d, now %d",
555 			     intr, desc, msi_base, map->im_msi_base));
556 		}
557 
558 		if (intr_next < intr)
559 			intr_next = intr;
560 
561 		map->im_type = ICU_IMT_UNUSED;
562 		map->im_msi_base = -1;
563 
564 		if (bootverbose) {
565 			kprintf("release %s intr %d on cpu%d\n",
566 			    desc, intr, cpuid);
567 		}
568 	}
569 
570 	KKASSERT(intr_next > 0);
571 	KKASSERT(msi_base >= 0);
572 
573 	++intr_next;
574 	if (intr_next < IDT_HWI_VECTORS) {
575 		const struct icu_irqmap *map = &icu_irqmaps[cpuid][intr_next];
576 
577 		if (map->im_type == type) {
578 			KASSERT(map->im_msi_base != msi_base,
579 			    ("more than %d %s was allocated", count, desc));
580 		}
581 	}
582 
583 	lwkt_reltoken(&icu_irqmap_tok);
584 }
585 
586 static int
icu_abi_msi_alloc(int intrs[],int count,int cpuid)587 icu_abi_msi_alloc(int intrs[], int count, int cpuid)
588 {
589 	return icu_abi_msi_alloc_intern(ICU_IMT_MSI, "MSI",
590 	    intrs, count, cpuid);
591 }
592 
593 static void
icu_abi_msi_release(const int intrs[],int count,int cpuid)594 icu_abi_msi_release(const int intrs[], int count, int cpuid)
595 {
596 	icu_abi_msi_release_intern(ICU_IMT_MSI, "MSI",
597 	    intrs, count, cpuid);
598 }
599 
600 static int
icu_abi_msix_alloc(int * intr,int cpuid)601 icu_abi_msix_alloc(int *intr, int cpuid)
602 {
603 	return icu_abi_msi_alloc_intern(ICU_IMT_MSIX, "MSI-X",
604 	    intr, 1, cpuid);
605 }
606 
607 static void
icu_abi_msix_release(int intr,int cpuid)608 icu_abi_msix_release(int intr, int cpuid)
609 {
610 	icu_abi_msi_release_intern(ICU_IMT_MSIX, "MSI-X",
611 	    &intr, 1, cpuid);
612 }
613 
614 static void
icu_abi_msi_map(int intr,uint64_t * addr,uint32_t * data,int cpuid)615 icu_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid)
616 {
617 	const struct icu_irqmap *map;
618 
619 	KASSERT(cpuid >= 0 && cpuid < ncpus,
620 	    ("invalid cpuid %d", cpuid));
621 
622 	KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS,
623 	    ("invalid intr %d", intr));
624 
625 	lwkt_gettoken(&icu_irqmap_tok);
626 
627 	map = &icu_irqmaps[cpuid][intr];
628 	KASSERT(map->im_type == ICU_IMT_MSI ||
629 	    map->im_type == ICU_IMT_MSIX,
630 	    ("trying to map non-MSI/MSI-X intr %d, type %d", intr, map->im_type));
631 	KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr,
632 	    ("intr %d, invalid %s-base %d", intr,
633 	     map->im_type == ICU_IMT_MSI ? "MSI" : "MSI-X",
634 	     map->im_msi_base));
635 
636 	msi_map(map->im_msi_base, addr, data, cpuid);
637 
638 	if (bootverbose) {
639 		kprintf("map %s intr %d on cpu%d\n",
640 		    map->im_type == ICU_IMT_MSI ? "MSI" : "MSI-X",
641 		    intr, cpuid);
642 	}
643 
644 	lwkt_reltoken(&icu_irqmap_tok);
645 }
646 
647 static int
icu_abi_legacy_intr_find(int irq,enum intr_trigger trig,enum intr_polarity pola __unused)648 icu_abi_legacy_intr_find(int irq, enum intr_trigger trig,
649     enum intr_polarity pola __unused)
650 {
651 	const struct icu_irqmap *map;
652 
653 #ifdef INVARIANTS
654 	if (trig == INTR_TRIGGER_CONFORM) {
655 		KKASSERT(pola == INTR_POLARITY_CONFORM);
656 	} else {
657 		KKASSERT(trig == INTR_TRIGGER_EDGE ||
658 		    trig == INTR_TRIGGER_LEVEL);
659 		KKASSERT(pola == INTR_POLARITY_HIGH ||
660 		    pola == INTR_POLARITY_LOW);
661 	}
662 #endif
663 
664 	if (irq < 0 || irq >= ICU_HWI_VECTORS)
665 		return -1;
666 
667 	map = &icu_irqmaps[0][irq];
668 	if (map->im_type == ICU_IMT_LEGACY) {
669 		if ((map->im_flags & ICU_IMF_CONF) &&
670 		    trig != INTR_TRIGGER_CONFORM) {
671 			if (map->im_trig != trig)
672 				return -1;
673 		}
674 		return irq;
675 	}
676 	return -1;
677 }
678 
679 static int
icu_abi_legacy_intr_find_bygsi(int gsi,enum intr_trigger trig,enum intr_polarity pola)680 icu_abi_legacy_intr_find_bygsi(int gsi, enum intr_trigger trig,
681     enum intr_polarity pola)
682 {
683 	/* GSI and IRQ has 1:1 mapping */
684 	return icu_abi_legacy_intr_find(gsi, trig, pola);
685 }
686