xref: /netbsd/sys/dev/ic/ncr53c9xvar.h (revision 2b1e3d1e)
1 /*	$NetBSD: ncr53c9xvar.h,v 1.57 2022/01/01 21:07:14 andvar Exp $	*/
2 
3 /*-
4  * Copyright (c) 1997 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9  * NASA Ames Research Center.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  * POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 /*
34  * Copyright (c) 1994 Peter Galbavy.  All rights reserved.
35  *
36  * Redistribution and use in source and binary forms, with or without
37  * modification, are permitted provided that the following conditions
38  * are met:
39  * 1. Redistributions of source code must retain the above copyright
40  *    notice, this list of conditions and the following disclaimer.
41  * 2. Redistributions in binary form must reproduce the above copyright
42  *    notice, this list of conditions and the following disclaimer in the
43  *    documentation and/or other materials provided with the distribution.
44  * 3. All advertising materials mentioning features or use of this software
45  *    must display the following acknowledgement:
46  *	This product includes software developed by Peter Galbavy.
47  * 4. The name of the author may not be used to endorse or promote products
48  *    derived from this software without specific prior written permission.
49  *
50  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
51  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
52  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
53  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
54  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
55  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
56  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
57  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
59  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60  */
61 
62 #ifndef _DEV_IC_NCR53C9XVAR_H_
63 #define _DEV_IC_NCR53C9XVAR_H_
64 
65 #include <sys/mutex.h>
66 
67 /* Set this to 1 for normal debug, or 2 for per-target tracing. */
68 /* #define NCR53C9X_DEBUG		1 */
69 
70 /* Wide or differential can have 16 targets */
71 #define NCR_NLUN		8
72 
73 #define	NCR_ABORT_TIMEOUT	2000	/* time to wait for abort */
74 #define	NCR_SENSE_TIMEOUT	1000	/* time to wait for sense */
75 
76 #define FREQTOCCF(freq)	(((freq + 4) / 5))
77 
78 /*
79  * NCR 53c9x variants.  Note, these values are used as indexes into
80  * a table; don't modify them unless you know what you're doing.
81  */
82 #define	NCR_VARIANT_ESP100		0
83 #define	NCR_VARIANT_ESP100A		1
84 #define	NCR_VARIANT_ESP200		2
85 #define	NCR_VARIANT_NCR53C94		3
86 #define	NCR_VARIANT_NCR53C96		4
87 #define	NCR_VARIANT_ESP406		5
88 #define	NCR_VARIANT_FAS408		6
89 #define	NCR_VARIANT_FAS216		7
90 #define	NCR_VARIANT_AM53C974		8
91 #define	NCR_VARIANT_FAS366		9
92 #define	NCR_VARIANT_NCR53C90_86C01	10
93 #define	NCR_VARIANT_MAX			11
94 
95 /*
96  * ECB. Holds additional information for each SCSI command Comments: We
97  * need a separate scsi command block because we may need to overwrite it
98  * with a request sense command.  Basically, we refrain from fiddling with
99  * the scsipi_xfer struct (except do the expected updating of return values).
100  * We'll generally update: xs->{flags,resid,error,sense,status} and
101  * occasionally xs->retries.
102  */
103 struct ncr53c9x_ecb {
104 	TAILQ_ENTRY(ncr53c9x_ecb) chain;
105 	struct scsipi_xfer *xs;	/* SCSI xfer ctrl block from above */
106 	int flags;
107 #define	ECB_ALLOC		0x01
108 #define	ECB_READY		0x02
109 #define	ECB_SENSE		0x04
110 #define	ECB_ABORT		0x40
111 #define	ECB_RESET		0x80
112 #define	ECB_TENTATIVE_DONE	0x100
113 	int timeout;
114 
115 	struct {
116 		u_char	msg[3];			/* Selection Id msg and tags */
117 		struct scsipi_generic cmd;	/* SCSI command block */
118 	} cmd;
119 	uint8_t	*daddr;		/* Saved data pointer */
120 	int	 clen;		/* Size of command in cmd.cmd */
121 	int	 dleft;		/* Residue */
122 	u_char	 stat;		/* SCSI status byte */
123 	u_char	 tag[2];	/* TAG bytes */
124 	u_char	 pad[1];
125 
126 #if NCR53C9X_DEBUG > 1
127 	char trace[1000];
128 #endif
129 };
130 #if NCR53C9X_DEBUG > 1
131 #define ECB_TRACE(ecb, msg, a, b) do { \
132 	const char *f = "[" msg "]"; \
133 	size_t n = strlen((ecb)->trace); \
134 	if (n >= (sizeof((ecb)->trace)-100)) \
135 		break; \
136 	snprintf((ecb)->trace + n, sizeof((ecb)->trace) - n, f,  a, b); \
137 } while(0)
138 #else
139 #define ECB_TRACE(ecb, msg, a, b)
140 #endif
141 
142 /*
143  * Some info about each (possible) target and LUN on the SCSI bus.
144  *
145  * SCSI I and II devices can have up to 8 LUNs, each with up to 256
146  * outstanding tags.  SCSI III devices have 64-bit LUN identifiers
147  * that can be sparsely allocated.
148  *
149  * Since SCSI II devices can have up to 8 LUNs, we use an array
150  * of 8 pointers to ncr53c9x_linfo structures for fast lookup.
151  * Longer LUNs need to traverse the linked list.
152  */
153 
154 struct ncr53c9x_linfo {
155 	int64_t			lun;
156 	LIST_ENTRY(ncr53c9x_linfo) link;
157 	time_t			last_used;
158 	uint8_t			used;	/* # slots in use */
159 	uint8_t			avail;	/* where to start scanning */
160 	uint8_t			busy;
161 	struct ncr53c9x_ecb	*untagged;
162 	struct ncr53c9x_ecb	*queued[256];
163 };
164 
165 struct ncr53c9x_tinfo {
166 	int	cmds;		/* # of commands processed */
167 	int	dconns;		/* # of disconnects */
168 	int	touts;		/* # of timeouts */
169 	int	perrs;		/* # of parity errors */
170 	int	senses;		/* # of request sense commands sent */
171 	uint8_t	flags;
172 #define T_NEGOTIATE	0x02	/* (Re)Negotiate synchronous options */
173 #define T_SYNCMODE	0x08	/* SYNC mode has been negotiated */
174 #define T_SYNCHOFF	0x10	/* SYNC mode for is permanently off */
175 #define T_RSELECTOFF	0x20	/* RE-SELECT mode is off */
176 #define T_TAG		0x40	/* Turn on TAG QUEUEs */
177 #define T_WIDE		0x80	/* Negotiate wide options */
178 #define T_WDTRSENT	0x04	/* WDTR message has been sent to */
179 	uint8_t	period;		/* Period suggestion */
180 	uint8_t	offset;		/* Offset suggestion */
181 	uint8_t	cfg3;		/* per target config 3  */
182 	uint8_t	nextag;		/* Next available tag */
183 	uint8_t	width;		/* width suggesion */
184 	LIST_HEAD(lun_list, ncr53c9x_linfo) luns;
185 	struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */
186 };
187 
188 /* Look up a lun in a tinfo */
189 #define TINFO_LUN(t, l) (					\
190 	(((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL))		\
191 		? ((t)->lun[(l)])				\
192 		: ncr53c9x_lunsearch((t), (int64_t)(l))		\
193 )
194 
195 /* Register a linenumber (for debugging) */
196 #define LOGLINE(p)
197 
198 #define NCR_SHOWECBS	0x01
199 #define NCR_SHOWINTS	0x02
200 #define NCR_SHOWCMDS	0x04
201 #define NCR_SHOWMISC	0x08
202 #define NCR_SHOWTRAC	0x10
203 #define NCR_SHOWSTART	0x20
204 #define NCR_SHOWPHASE	0x40
205 #define NCR_SHOWDMA	0x80
206 #define NCR_SHOWCCMDS	0x100
207 #define NCR_SHOWMSGS	0x200
208 
209 #ifdef NCR53C9X_DEBUG
210 extern int ncr53c9x_debug;
211 #define NCR_ECBS(str)	\
212 	do {if (ncr53c9x_debug & NCR_SHOWECBS) printf str;} while (0)
213 #define NCR_MISC(str)	\
214 	do {if (ncr53c9x_debug & NCR_SHOWMISC) printf str;} while (0)
215 #define NCR_INTS(str)	\
216 	do {if (ncr53c9x_debug & NCR_SHOWINTS) printf str;} while (0)
217 #define NCR_TRACE(str)	\
218 	do {if (ncr53c9x_debug & NCR_SHOWTRAC) printf str;} while (0)
219 #define NCR_CMDS(str)	\
220 	do {if (ncr53c9x_debug & NCR_SHOWCMDS) printf str;} while (0)
221 #define NCR_START(str)	\
222 	do {if (ncr53c9x_debug & NCR_SHOWSTART) printf str;}while (0)
223 #define NCR_PHASE(str)	\
224 	do {if (ncr53c9x_debug & NCR_SHOWPHASE) printf str;}while (0)
225 #define NCR_DMA(str)	\
226 	do {if (ncr53c9x_debug & NCR_SHOWDMA) printf str;}while (0)
227 #define NCR_MSGS(str)	\
228 	do {if (ncr53c9x_debug & NCR_SHOWMSGS) printf str;}while (0)
229 #else
230 #define NCR_ECBS(str)
231 #define NCR_MISC(str)
232 #define NCR_INTS(str)
233 #define NCR_TRACE(str)
234 #define NCR_CMDS(str)
235 #define NCR_START(str)
236 #define NCR_PHASE(str)
237 #define NCR_DMA(str)
238 #define NCR_MSGS(str)
239 #endif
240 
241 #define NCR_MAX_MSG_LEN 8
242 
243 struct ncr53c9x_softc;
244 
245 /*
246  * Function switch used as glue to MD code.
247  */
248 struct ncr53c9x_glue {
249 	/* Mandatory entry points. */
250 	uint8_t	(*gl_read_reg)(struct ncr53c9x_softc *, int);
251 	void	(*gl_write_reg)(struct ncr53c9x_softc *, int, uint8_t);
252 	int	(*gl_dma_isintr)(struct ncr53c9x_softc *);
253 	void	(*gl_dma_reset)(struct ncr53c9x_softc *);
254 	int	(*gl_dma_intr)(struct ncr53c9x_softc *);
255 	int	(*gl_dma_setup)(struct ncr53c9x_softc *,
256 		    uint8_t **, size_t *, int, size_t *);
257 	void	(*gl_dma_go)(struct ncr53c9x_softc *);
258 	void	(*gl_dma_stop)(struct ncr53c9x_softc *);
259 	int	(*gl_dma_isactive)(struct ncr53c9x_softc *);
260 
261 	/* Optional entry points. */
262 	void	(*gl_clear_latched_intr)(struct ncr53c9x_softc *);
263 };
264 
265 struct ncr53c9x_softc {
266 	device_t sc_dev;			/* us as a device */
267 
268 	struct evcnt sc_intrcnt;		/* intr count */
269 	struct scsipi_adapter sc_adapter;	/* out scsipi adapter */
270 	struct scsipi_channel sc_channel;	/* our scsipi channel */
271 	device_t sc_child;		/* attached scsibus, if any */
272 	struct callout sc_watchdog;		/* periodic timer */
273 
274 	const struct ncr53c9x_glue *sc_glue;	/* glue to MD code */
275 
276 	int	sc_cfflags;			/* Copy of config flags */
277 
278 	/* register defaults */
279 	uint8_t	sc_cfg1;			/* Config 1 */
280 	uint8_t	sc_cfg2;			/* Config 2, not ESP100 */
281 	uint8_t	sc_cfg3;			/* Config 3, ESP200,FAS */
282 	uint8_t	sc_cfg3_fscsi;			/* Chip-specific FSCSI bit */
283 	uint8_t	sc_cfg4;			/* Config 4, only ESP200 */
284 	uint8_t	sc_cfg5;			/* Config 5, only ESP200 */
285 	uint8_t	sc_ccf;				/* Clock Conversion */
286 	uint8_t	sc_timeout;
287 
288 	/* register copies, see espreadregs() */
289 	uint8_t	sc_espintr;
290 	uint8_t	sc_espstat;
291 	uint8_t	sc_espstep;
292 	uint8_t  sc_espstat2;
293 	uint8_t	sc_espfflags;
294 
295 	/* Lists of command blocks */
296 	TAILQ_HEAD(ecb_list, ncr53c9x_ecb)
297 		ready_list;
298 
299 	struct ncr53c9x_ecb *sc_nexus;		/* Current command */
300 	int	sc_ntarg;
301 	struct ncr53c9x_tinfo *sc_tinfo;
302 
303 	/* Data about the current nexus (updated for every cmd switch) */
304 	uint8_t	*sc_dp;		/* Current data pointer */
305 	ssize_t	sc_dleft;	/* Data left to transfer */
306 
307 	/* Adapter state */
308 	int	sc_phase;	/* Copy of what bus phase we are in */
309 	int	sc_prevphase;	/* Copy of what bus phase we were in */
310 	uint8_t	sc_state;	/* State applicable to the adapter */
311 	uint8_t	sc_flags;	/* See below */
312 	uint8_t	sc_selid;
313 	uint8_t	sc_lastcmd;
314 
315 	/* Message stuff */
316 	uint16_t sc_msgify;	/* IDENTIFY msg associated with this nexus */
317 	uint16_t sc_msgout;	/* What message is on its way out? */
318 	uint16_t sc_msgpriq;	/* One or more messages to send (encoded) */
319 	uint16_t sc_msgoutq;	/* What messages have been sent so far? */
320 
321 	uint8_t	*sc_omess;	/* MSGOUT buffer */
322 	uint8_t	*sc_omp;	/* Message pointer (for multibyte messages) */
323 	size_t	sc_omlen;
324 	uint8_t	*sc_imess;	/* MSGIN buffer */
325 	uint8_t	*sc_imp;	/* Message pointer (for multibyte messages) */
326 	size_t	sc_imlen;
327 
328 	uint8_t	*sc_cmdp;	/* Command pointer (for DMAed commands) */
329 	size_t	sc_cmdlen;	/* Size of command in transit */
330 
331 	/* Hardware attributes */
332 	int sc_freq;		/* SCSI bus frequency in MHz */
333 	int sc_id;		/* Our SCSI id */
334 	int sc_rev;		/* Chip revision */
335 	int sc_features;	/* Chip features */
336 	int sc_minsync;		/* Minimum sync period / 4 */
337 	int sc_maxxfer;		/* Maximum transfer size */
338 
339 	kmutex_t sc_lock;	/* driver mutex */
340 };
341 
342 /* values for sc_state */
343 #define NCR_IDLE	1	/* waiting for something to do */
344 #define NCR_SELECTING	2	/* SCSI command is arbiting  */
345 #define NCR_RESELECTED	3	/* Has been reselected */
346 #define NCR_IDENTIFIED	4	/* Has gotten IFY but not TAG */
347 #define NCR_CONNECTED	5	/* Actively using the SCSI bus */
348 #define	NCR_DISCONNECT	6	/* MSG_DISCONNECT received */
349 #define	NCR_CMDCOMPLETE	7	/* MSG_CMDCOMPLETE received */
350 #define	NCR_CLEANING	8
351 #define NCR_SBR		9	/* Expect a SCSI RST because we commanded it */
352 
353 /* values for sc_flags */
354 #define NCR_DROP_MSGI	0x01	/* Discard all msgs (parity err detected) */
355 #define NCR_ABORTING	0x02	/* Bailing out */
356 #define NCR_DOINGDMA	0x04	/* The FIFO data path is active! */
357 #define NCR_SYNCHNEGO	0x08	/* Synch negotiation in progress. */
358 #define NCR_ICCS	0x10	/* Expect status phase results */
359 #define NCR_WAITI	0x20	/* Waiting for non-DMA data to arrive */
360 #define	NCR_ATN		0x40	/* ATN asserted */
361 #define	NCR_EXPECT_ILLCMD	0x80	/* Expect Illegal Command Interrupt */
362 
363 /* values for sc_features */
364 #define	NCR_F_HASCFG3	0x01	/* chip has CFG3 register */
365 #define	NCR_F_FASTSCSI	0x02	/* chip supports Fast mode */
366 #define	NCR_F_DMASELECT 0x04	/*      can do dmaselect */
367 #define	NCR_F_SELATN3	0x08	/* chip supports SELATN3 command */
368 
369 /* values for sc_msgout */
370 #define SEND_DEV_RESET		0x0001
371 #define SEND_PARITY_ERROR	0x0002
372 #define SEND_INIT_DET_ERR	0x0004
373 #define SEND_REJECT		0x0008
374 #define SEND_IDENTIFY		0x0010
375 #define SEND_ABORT		0x0020
376 #define SEND_WDTR		0x0040
377 #define SEND_SDTR		0x0080
378 #define SEND_TAG		0x0100
379 
380 /* SCSI Status codes */
381 #define ST_MASK			0x3e /* bit 0,6,7 is reserved */
382 
383 /* phase bits */
384 #define IOI			0x01
385 #define CDI			0x02
386 #define MSGI			0x04
387 
388 /* Information transfer phases */
389 #define DATA_OUT_PHASE		(0)
390 #define DATA_IN_PHASE		(IOI)
391 #define COMMAND_PHASE		(CDI)
392 #define STATUS_PHASE		(CDI|IOI)
393 #define MESSAGE_OUT_PHASE	(MSGI|CDI)
394 #define MESSAGE_IN_PHASE	(MSGI|CDI|IOI)
395 
396 #define PHASE_MASK		(MSGI|CDI|IOI)
397 
398 /* Some pseudo phases for getphase()*/
399 #define BUSFREE_PHASE		0x100	/* Re/Selection no longer valid */
400 #define INVALID_PHASE		0x101	/* Re/Selection valid, but no REQ yet */
401 #define PSEUDO_PHASE		0x100	/* "pseudo" bit */
402 
403 /*
404  * Macros to read and write the chip's registers.
405  */
406 #define	NCR_READ_REG(sc, reg)		\
407 	(*(sc)->sc_glue->gl_read_reg)((sc), (reg))
408 #define	NCR_WRITE_REG(sc, reg, val)	\
409 	(*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
410 
411 #ifdef NCR53C9X_DEBUG
412 #define	NCRCMD(sc, cmd) do {						\
413 	if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0)			\
414 		printf("<CMD:0x%x %d>", (unsigned int)cmd, __LINE__);	\
415 	sc->sc_lastcmd = cmd;						\
416 	NCR_WRITE_REG(sc, NCR_CMD, cmd);				\
417 } while (/* CONSTCOND */ 0)
418 #else
419 #define	NCRCMD(sc, cmd)		NCR_WRITE_REG(sc, NCR_CMD, cmd)
420 #endif
421 
422 /*
423  * DMA macros for NCR53c9x
424  */
425 #define	NCRDMA_ISINTR(sc)	(*(sc)->sc_glue->gl_dma_isintr)((sc))
426 #define	NCRDMA_RESET(sc)	(*(sc)->sc_glue->gl_dma_reset)((sc))
427 #define	NCRDMA_INTR(sc)		(*(sc)->sc_glue->gl_dma_intr)((sc))
428 #define	NCRDMA_SETUP(sc, addr, len, datain, dmasize)	\
429      (*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize))
430 #define	NCRDMA_GO(sc)		(*(sc)->sc_glue->gl_dma_go)((sc))
431 #define	NCRDMA_ISACTIVE(sc)	(*(sc)->sc_glue->gl_dma_isactive)((sc))
432 
433 /*
434  * Macro to convert the chip register Clock Per Byte value to
435  * Synchronous Transfer Period.
436  */
437 #define	ncr53c9x_cpb2stp(sc, cpb)	\
438 	((250 * (cpb)) / (sc)->sc_freq)
439 
440 void	ncr53c9x_attach(struct ncr53c9x_softc *);
441 int	ncr53c9x_detach(struct ncr53c9x_softc *, int);
442 void	ncr53c9x_scsipi_request(struct scsipi_channel *chan,
443 	    scsipi_adapter_req_t req, void *);
444 void	ncr53c9x_reset(struct ncr53c9x_softc *);
445 int	ncr53c9x_intr(void *);
446 void	ncr53c9x_init(struct ncr53c9x_softc *, int);
447 void	ncr53c9x_abort(struct ncr53c9x_softc *, struct ncr53c9x_ecb *);
448 
449 #endif /* _DEV_IC_NCR53C9XVAR_H_ */
450