/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 122 struct NEONLdStTableEntry { struct 123 uint16_t PseudoOpc; 124 uint16_t RealOpc; 125 bool IsLoad; 126 bool isUpdating; 127 bool hasWritebackOperand; 128 uint8_t RegSpacing; // One of type NEONRegSpacing 129 uint8_t NumRegs; // D registers loaded or stored 130 uint8_t RegElts; // elements per D register; used for lane ops 136 bool copyAllListRegs; [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 122 struct NEONLdStTableEntry { struct 123 uint16_t PseudoOpc; 124 uint16_t RealOpc; 125 bool IsLoad; 126 bool isUpdating; 127 bool hasWritebackOperand; 128 uint8_t RegSpacing; // One of type NEONRegSpacing 129 uint8_t NumRegs; // D registers loaded or stored 130 uint8_t RegElts; // elements per D register; used for lane ops 136 bool copyAllListRegs; [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 122 struct NEONLdStTableEntry { struct 123 uint16_t PseudoOpc; 124 uint16_t RealOpc; 125 bool IsLoad; 126 bool isUpdating; 127 bool hasWritebackOperand; 128 uint8_t RegSpacing; // One of type NEONRegSpacing 129 uint8_t NumRegs; // D registers loaded or stored 130 uint8_t RegElts; // elements per D register; used for lane ops 136 bool copyAllListRegs; [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 122 struct NEONLdStTableEntry { struct 123 uint16_t PseudoOpc; 124 uint16_t RealOpc; 125 bool IsLoad; 126 bool isUpdating; 127 bool hasWritebackOperand; 128 uint8_t RegSpacing; // One of type NEONRegSpacing 129 uint8_t NumRegs; // D registers loaded or stored 130 uint8_t RegElts; // elements per D register; used for lane ops 136 bool copyAllListRegs; [all …]
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 122 struct NEONLdStTableEntry { struct 123 uint16_t PseudoOpc; 124 uint16_t RealOpc; 125 bool IsLoad; 126 bool isUpdating; 127 bool hasWritebackOperand; 128 uint8_t RegSpacing; // One of type NEONRegSpacing 129 uint8_t NumRegs; // D registers loaded or stored 130 uint8_t RegElts; // elements per D register; used for lane ops 136 bool copyAllListRegs; [all …]
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 122 struct NEONLdStTableEntry { struct 123 uint16_t PseudoOpc; 124 uint16_t RealOpc; 125 bool IsLoad; 126 bool isUpdating; 127 bool hasWritebackOperand; 128 uint8_t RegSpacing; // One of type NEONRegSpacing 129 uint8_t NumRegs; // D registers loaded or stored 130 uint8_t RegElts; // elements per D register; used for lane ops 136 bool copyAllListRegs; [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 154 struct NEONLdStTableEntry { struct 155 uint16_t PseudoOpc; 156 uint16_t RealOpc; 157 bool IsLoad; 158 bool isUpdating; 159 bool hasWritebackOperand; 160 uint8_t RegSpacing; // One of type NEONRegSpacing 161 uint8_t NumRegs; // D registers loaded or stored 162 uint8_t RegElts; // elements per D register; used for lane ops 168 bool copyAllListRegs; [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 154 struct NEONLdStTableEntry { struct 155 uint16_t PseudoOpc; 156 uint16_t RealOpc; 157 bool IsLoad; 158 bool isUpdating; 159 bool hasWritebackOperand; 160 uint8_t RegSpacing; // One of type NEONRegSpacing 161 uint8_t NumRegs; // D registers loaded or stored 162 uint8_t RegElts; // elements per D register; used for lane ops 168 bool copyAllListRegs; [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 154 unsigned fastMaterializeAlloca(const AllocaInst *AI) override; 155 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, 156 const LoadInst *LI) override; 157 bool fastLowerArguments() override; 159 #include "ARMGenFastISel.inc" 163 bool SelectLoad(const Instruction *I); 164 bool SelectStore(const Instruction *I); 168 bool SelectFPExt(const Instruction *I); 171 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode); in operator <()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 154 struct NEONLdStTableEntry { struct 155 uint16_t PseudoOpc; 156 uint16_t RealOpc; 157 bool IsLoad; 158 bool isUpdating; 159 bool hasWritebackOperand; 160 uint8_t RegSpacing; // One of type NEONRegSpacing 161 uint8_t NumRegs; // D registers loaded or stored 162 uint8_t RegElts; // elements per D register; used for lane ops 168 bool copyAllListRegs; [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 154 struct NEONLdStTableEntry { struct 155 uint16_t PseudoOpc; 156 uint16_t RealOpc; 157 bool IsLoad; 158 bool isUpdating; 159 bool hasWritebackOperand; 160 uint8_t RegSpacing; // One of type NEONRegSpacing 161 uint8_t NumRegs; // D registers loaded or stored 162 uint8_t RegElts; // elements per D register; used for lane ops 168 bool copyAllListRegs; [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 154 struct NEONLdStTableEntry { struct 155 uint16_t PseudoOpc; 156 uint16_t RealOpc; 157 bool IsLoad; 158 bool isUpdating; 159 bool hasWritebackOperand; 160 uint8_t RegSpacing; // One of type NEONRegSpacing 161 uint8_t NumRegs; // D registers loaded or stored 162 uint8_t RegElts; // elements per D register; used for lane ops 168 bool copyAllListRegs; [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 154 struct NEONLdStTableEntry { struct 155 uint16_t PseudoOpc; 156 uint16_t RealOpc; 157 bool IsLoad; 158 bool isUpdating; 159 bool hasWritebackOperand; 160 uint8_t RegSpacing; // One of type NEONRegSpacing 161 uint8_t NumRegs; // D registers loaded or stored 162 uint8_t RegElts; // elements per D register; used for lane ops 168 bool copyAllListRegs; [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 155 struct NEONLdStTableEntry { struct 156 uint16_t PseudoOpc; 157 uint16_t RealOpc; 158 bool IsLoad; 159 bool isUpdating; 160 bool hasWritebackOperand; 161 uint8_t RegSpacing; // One of type NEONRegSpacing 162 uint8_t NumRegs; // D registers loaded or stored 163 uint8_t RegElts; // elements per D register; used for lane ops 169 bool copyAllListRegs; [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 154 struct NEONLdStTableEntry { struct 155 uint16_t PseudoOpc; 156 uint16_t RealOpc; 157 bool IsLoad; 158 bool isUpdating; 159 bool hasWritebackOperand; 160 uint8_t RegSpacing; // One of type NEONRegSpacing 161 uint8_t NumRegs; // D registers loaded or stored 162 uint8_t RegElts; // elements per D register; used for lane ops 168 bool copyAllListRegs; [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 154 struct NEONLdStTableEntry { struct 155 uint16_t PseudoOpc; 156 uint16_t RealOpc; 157 bool IsLoad; 158 bool isUpdating; 159 bool hasWritebackOperand; 160 uint8_t RegSpacing; // One of type NEONRegSpacing 161 uint8_t NumRegs; // D registers loaded or stored 162 uint8_t RegElts; // elements per D register; used for lane ops 168 bool copyAllListRegs; [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 154 struct NEONLdStTableEntry { struct 155 uint16_t PseudoOpc; 156 uint16_t RealOpc; 157 bool IsLoad; 158 bool isUpdating; 159 bool hasWritebackOperand; 160 uint8_t RegSpacing; // One of type NEONRegSpacing 161 uint8_t NumRegs; // D registers loaded or stored 162 uint8_t RegElts; // elements per D register; used for lane ops 168 bool copyAllListRegs; [all …]
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