xref: /dragonfly/sys/dev/netif/nge/if_nge.c (revision fcf6efef)
1 /*
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2000, 2001
4  *	Bill Paul <wpaul@bsdi.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *	This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $
34  */
35 
36 /*
37  * National Semiconductor DP83820/DP83821 gigabit ethernet driver
38  * for FreeBSD. Datasheets are available from:
39  *
40  * http://www.national.com/ds/DP/DP83820.pdf
41  * http://www.national.com/ds/DP/DP83821.pdf
42  *
43  * These chips are used on several low cost gigabit ethernet NICs
44  * sold by D-Link, Addtron, SMC and Asante. Both parts are
45  * virtually the same, except the 83820 is a 64-bit/32-bit part,
46  * while the 83821 is 32-bit only.
47  *
48  * Many cards also use National gigE transceivers, such as the
49  * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
50  * contains a full register description that applies to all of these
51  * components:
52  *
53  * http://www.national.com/ds/DP/DP83861.pdf
54  *
55  * Written by Bill Paul <wpaul@bsdi.com>
56  * BSDi Open Source Solutions
57  */
58 
59 /*
60  * The NatSemi DP83820 and 83821 controllers are enhanced versions
61  * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
62  * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
63  * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
64  * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
65  * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
66  * matching buffers, one perfect address filter buffer and interrupt
67  * moderation. The 83820 supports both 64-bit and 32-bit addressing
68  * and data transfers: the 64-bit support can be toggled on or off
69  * via software. This affects the size of certain fields in the DMA
70  * descriptors.
71  *
72  * There are two bugs/misfeatures in the 83820/83821 that I have
73  * discovered so far:
74  *
75  * - Receive buffers must be aligned on 64-bit boundaries, which means
76  *   you must resort to copying data in order to fix up the payload
77  *   alignment.
78  *
79  * - In order to transmit jumbo frames larger than 8170 bytes, you have
80  *   to turn off transmit checksum offloading, because the chip can't
81  *   compute the checksum on an outgoing frame unless it fits entirely
82  *   within the TX FIFO, which is only 8192 bytes in size. If you have
83  *   TX checksum offload enabled and you transmit attempt to transmit a
84  *   frame larger than 8170 bytes, the transmitter will wedge.
85  *
86  * To work around the latter problem, TX checksum offload is disabled
87  * if the user selects an MTU larger than 8152 (8170 - 18).
88  */
89 
90 #include "opt_ifpoll.h"
91 
92 #include <sys/param.h>
93 #include <sys/systm.h>
94 #include <sys/sockio.h>
95 #include <sys/mbuf.h>
96 #include <sys/malloc.h>
97 #include <sys/kernel.h>
98 #include <sys/interrupt.h>
99 #include <sys/socket.h>
100 #include <sys/serialize.h>
101 #include <sys/bus.h>
102 #include <sys/rman.h>
103 
104 #include <net/if.h>
105 #include <net/ifq_var.h>
106 #include <net/if_arp.h>
107 #include <net/ethernet.h>
108 #include <net/if_dl.h>
109 #include <net/if_media.h>
110 #include <net/if_poll.h>
111 #include <net/if_types.h>
112 #include <net/vlan/if_vlan_var.h>
113 #include <net/vlan/if_vlan_ether.h>
114 
115 #include <net/bpf.h>
116 
117 #include <vm/vm.h>              /* for vtophys */
118 #include <vm/pmap.h>            /* for vtophys */
119 
120 #include <dev/netif/mii_layer/mii.h>
121 #include <dev/netif/mii_layer/miivar.h>
122 
123 #include "pcidevs.h"
124 #include <bus/pci/pcireg.h>
125 #include <bus/pci/pcivar.h>
126 
127 #define NGE_USEIOSPACE
128 
129 #include "if_ngereg.h"
130 
131 
132 /* "controller miibus0" required.  See GENERIC if you get errors here. */
133 #include "miibus_if.h"
134 
135 #define NGE_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
136 
137 /*
138  * Various supported device vendors/types and their names.
139  */
140 static struct nge_type nge_devs[] = {
141 	{ PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820,
142 	    "National Semiconductor Gigabit Ethernet" },
143 	{ 0, 0, NULL }
144 };
145 
146 static int	nge_probe(device_t);
147 static int	nge_attach(device_t);
148 static int	nge_detach(device_t);
149 
150 static int	nge_alloc_jumbo_mem(struct nge_softc *);
151 static struct nge_jslot
152 		*nge_jalloc(struct nge_softc *);
153 static void	nge_jfree(void *);
154 static void	nge_jref(void *);
155 
156 static int	nge_newbuf(struct nge_softc *, struct nge_desc *,
157 			   struct mbuf *);
158 static int	nge_encap(struct nge_softc *, struct mbuf *, uint32_t *);
159 static void	nge_rxeof(struct nge_softc *);
160 static void	nge_txeof(struct nge_softc *);
161 static void	nge_intr(void *);
162 static void	nge_tick(void *);
163 static void	nge_start(struct ifnet *, struct ifaltq_subque *);
164 static int	nge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
165 static void	nge_init(void *);
166 static void	nge_stop(struct nge_softc *);
167 static void	nge_watchdog(struct ifnet *);
168 static void	nge_shutdown(device_t);
169 static int	nge_ifmedia_upd(struct ifnet *);
170 static void	nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
171 
172 static void	nge_delay(struct nge_softc *);
173 static void	nge_eeprom_idle(struct nge_softc *);
174 static void	nge_eeprom_putbyte(struct nge_softc *, int);
175 static void	nge_eeprom_getword(struct nge_softc *, int, uint16_t *);
176 static void	nge_read_eeprom(struct nge_softc *, void *, int, int);
177 
178 static void	nge_mii_sync(struct nge_softc *);
179 static void	nge_mii_send(struct nge_softc *, uint32_t, int);
180 static int	nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
181 static int	nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
182 
183 static int	nge_miibus_readreg(device_t, int, int);
184 static int	nge_miibus_writereg(device_t, int, int, int);
185 static void	nge_miibus_statchg(device_t);
186 
187 static void	nge_setmulti(struct nge_softc *);
188 static void	nge_reset(struct nge_softc *);
189 static int	nge_list_rx_init(struct nge_softc *);
190 static int	nge_list_tx_init(struct nge_softc *);
191 #ifdef IFPOLL_ENABLE
192 static void	nge_npoll(struct ifnet *, struct ifpoll_info *);
193 static void	nge_npoll_compat(struct ifnet *, void *, int);
194 #endif
195 
196 #ifdef NGE_USEIOSPACE
197 #define NGE_RES			SYS_RES_IOPORT
198 #define NGE_RID			NGE_PCI_LOIO
199 #else
200 #define NGE_RES			SYS_RES_MEMORY
201 #define NGE_RID			NGE_PCI_LOMEM
202 #endif
203 
204 static device_method_t nge_methods[] = {
205 	/* Device interface */
206 	DEVMETHOD(device_probe,		nge_probe),
207 	DEVMETHOD(device_attach,	nge_attach),
208 	DEVMETHOD(device_detach,	nge_detach),
209 	DEVMETHOD(device_shutdown,	nge_shutdown),
210 
211 	/* bus interface */
212 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
213 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
214 
215 	/* MII interface */
216 	DEVMETHOD(miibus_readreg,	nge_miibus_readreg),
217 	DEVMETHOD(miibus_writereg,	nge_miibus_writereg),
218 	DEVMETHOD(miibus_statchg,	nge_miibus_statchg),
219 
220 	DEVMETHOD_END
221 };
222 
223 static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc));
224 static devclass_t nge_devclass;
225 
226 DECLARE_DUMMY_MODULE(if_nge);
227 MODULE_DEPEND(if_nge, miibus, 1, 1, 1);
228 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, NULL, NULL);
229 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, NULL, NULL);
230 
231 #define NGE_SETBIT(sc, reg, x)				\
232 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
233 
234 #define NGE_CLRBIT(sc, reg, x)				\
235 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
236 
237 #define SIO_SET(x)					\
238 	CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
239 
240 #define SIO_CLR(x)					\
241 	CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
242 
243 static void
nge_delay(struct nge_softc * sc)244 nge_delay(struct nge_softc *sc)
245 {
246 	int idx;
247 
248 	for (idx = (300 / 33) + 1; idx > 0; idx--)
249 		CSR_READ_4(sc, NGE_CSR);
250 }
251 
252 static void
nge_eeprom_idle(struct nge_softc * sc)253 nge_eeprom_idle(struct nge_softc *sc)
254 {
255 	int i;
256 
257 	SIO_SET(NGE_MEAR_EE_CSEL);
258 	nge_delay(sc);
259 	SIO_SET(NGE_MEAR_EE_CLK);
260 	nge_delay(sc);
261 
262 	for (i = 0; i < 25; i++) {
263 		SIO_CLR(NGE_MEAR_EE_CLK);
264 		nge_delay(sc);
265 		SIO_SET(NGE_MEAR_EE_CLK);
266 		nge_delay(sc);
267 	}
268 
269 	SIO_CLR(NGE_MEAR_EE_CLK);
270 	nge_delay(sc);
271 	SIO_CLR(NGE_MEAR_EE_CSEL);
272 	nge_delay(sc);
273 	CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
274 }
275 
276 /*
277  * Send a read command and address to the EEPROM, check for ACK.
278  */
279 static void
nge_eeprom_putbyte(struct nge_softc * sc,int addr)280 nge_eeprom_putbyte(struct nge_softc *sc, int addr)
281 {
282 	int d, i;
283 
284 	d = addr | NGE_EECMD_READ;
285 
286 	/*
287 	 * Feed in each bit and stobe the clock.
288 	 */
289 	for (i = 0x400; i; i >>= 1) {
290 		if (d & i)
291 			SIO_SET(NGE_MEAR_EE_DIN);
292 		else
293 			SIO_CLR(NGE_MEAR_EE_DIN);
294 		nge_delay(sc);
295 		SIO_SET(NGE_MEAR_EE_CLK);
296 		nge_delay(sc);
297 		SIO_CLR(NGE_MEAR_EE_CLK);
298 		nge_delay(sc);
299 	}
300 }
301 
302 /*
303  * Read a word of data stored in the EEPROM at address 'addr.'
304  */
305 static void
nge_eeprom_getword(struct nge_softc * sc,int addr,uint16_t * dest)306 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest)
307 {
308 	int i;
309 	uint16_t word = 0;
310 
311 	/* Force EEPROM to idle state. */
312 	nge_eeprom_idle(sc);
313 
314 	/* Enter EEPROM access mode. */
315 	nge_delay(sc);
316 	SIO_CLR(NGE_MEAR_EE_CLK);
317 	nge_delay(sc);
318 	SIO_SET(NGE_MEAR_EE_CSEL);
319 	nge_delay(sc);
320 
321 	/*
322 	 * Send address of word we want to read.
323 	 */
324 	nge_eeprom_putbyte(sc, addr);
325 
326 	/*
327 	 * Start reading bits from EEPROM.
328 	 */
329 	for (i = 0x8000; i; i >>= 1) {
330 		SIO_SET(NGE_MEAR_EE_CLK);
331 		nge_delay(sc);
332 		if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
333 			word |= i;
334 		nge_delay(sc);
335 		SIO_CLR(NGE_MEAR_EE_CLK);
336 		nge_delay(sc);
337 	}
338 
339 	/* Turn off EEPROM access mode. */
340 	nge_eeprom_idle(sc);
341 
342 	*dest = word;
343 }
344 
345 /*
346  * Read a sequence of words from the EEPROM.
347  */
348 static void
nge_read_eeprom(struct nge_softc * sc,void * dest,int off,int cnt)349 nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt)
350 {
351 	int i;
352 	uint16_t word = 0, *ptr;
353 
354 	for (i = 0; i < cnt; i++) {
355 		nge_eeprom_getword(sc, off + i, &word);
356 		ptr = (uint16_t *)((uint8_t *)dest + (i * 2));
357 		*ptr = word;
358 	}
359 }
360 
361 /*
362  * Sync the PHYs by setting data bit and strobing the clock 32 times.
363  */
364 static void
nge_mii_sync(struct nge_softc * sc)365 nge_mii_sync(struct nge_softc *sc)
366 {
367 	int i;
368 
369 	SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA);
370 
371 	for (i = 0; i < 32; i++) {
372 		SIO_SET(NGE_MEAR_MII_CLK);
373 		DELAY(1);
374 		SIO_CLR(NGE_MEAR_MII_CLK);
375 		DELAY(1);
376 	}
377 }
378 
379 /*
380  * Clock a series of bits through the MII.
381  */
382 static void
nge_mii_send(struct nge_softc * sc,uint32_t bits,int cnt)383 nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt)
384 {
385 	int i;
386 
387 	SIO_CLR(NGE_MEAR_MII_CLK);
388 
389 	for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
390                 if (bits & i)
391 			SIO_SET(NGE_MEAR_MII_DATA);
392                 else
393 			SIO_CLR(NGE_MEAR_MII_DATA);
394 		DELAY(1);
395 		SIO_CLR(NGE_MEAR_MII_CLK);
396 		DELAY(1);
397 		SIO_SET(NGE_MEAR_MII_CLK);
398 	}
399 }
400 
401 /*
402  * Read an PHY register through the MII.
403  */
404 static int
nge_mii_readreg(struct nge_softc * sc,struct nge_mii_frame * frame)405 nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame)
406 {
407 	int ack, i;
408 
409 	/*
410 	 * Set up frame for RX.
411 	 */
412 	frame->mii_stdelim = NGE_MII_STARTDELIM;
413 	frame->mii_opcode = NGE_MII_READOP;
414 	frame->mii_turnaround = 0;
415 	frame->mii_data = 0;
416 
417 	CSR_WRITE_4(sc, NGE_MEAR, 0);
418 
419 	/*
420  	 * Turn on data xmit.
421 	 */
422 	SIO_SET(NGE_MEAR_MII_DIR);
423 
424 	nge_mii_sync(sc);
425 
426 	/*
427 	 * Send command/address info.
428 	 */
429 	nge_mii_send(sc, frame->mii_stdelim, 2);
430 	nge_mii_send(sc, frame->mii_opcode, 2);
431 	nge_mii_send(sc, frame->mii_phyaddr, 5);
432 	nge_mii_send(sc, frame->mii_regaddr, 5);
433 
434 	/* Idle bit */
435 	SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA));
436 	DELAY(1);
437 	SIO_SET(NGE_MEAR_MII_CLK);
438 	DELAY(1);
439 
440 	/* Turn off xmit. */
441 	SIO_CLR(NGE_MEAR_MII_DIR);
442 	/* Check for ack */
443 	SIO_CLR(NGE_MEAR_MII_CLK);
444 	DELAY(1);
445 	ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
446 	SIO_SET(NGE_MEAR_MII_CLK);
447 	DELAY(1);
448 
449 	/*
450 	 * Now try reading data bits. If the ack failed, we still
451 	 * need to clock through 16 cycles to keep the PHY(s) in sync.
452 	 */
453 	if (ack) {
454 		for(i = 0; i < 16; i++) {
455 			SIO_CLR(NGE_MEAR_MII_CLK);
456 			DELAY(1);
457 			SIO_SET(NGE_MEAR_MII_CLK);
458 			DELAY(1);
459 		}
460 		goto fail;
461 	}
462 
463 	for (i = 0x8000; i; i >>= 1) {
464 		SIO_CLR(NGE_MEAR_MII_CLK);
465 		DELAY(1);
466 		if (!ack) {
467 			if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
468 				frame->mii_data |= i;
469 			DELAY(1);
470 		}
471 		SIO_SET(NGE_MEAR_MII_CLK);
472 		DELAY(1);
473 	}
474 
475 fail:
476 	SIO_CLR(NGE_MEAR_MII_CLK);
477 	DELAY(1);
478 	SIO_SET(NGE_MEAR_MII_CLK);
479 	DELAY(1);
480 
481 	if (ack)
482 		return(1);
483 	return(0);
484 }
485 
486 /*
487  * Write to a PHY register through the MII.
488  */
489 static int
nge_mii_writereg(struct nge_softc * sc,struct nge_mii_frame * frame)490 nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame)
491 {
492 	/*
493 	 * Set up frame for TX.
494 	 */
495 
496 	frame->mii_stdelim = NGE_MII_STARTDELIM;
497 	frame->mii_opcode = NGE_MII_WRITEOP;
498 	frame->mii_turnaround = NGE_MII_TURNAROUND;
499 
500 	/*
501  	 * Turn on data output.
502 	 */
503 	SIO_SET(NGE_MEAR_MII_DIR);
504 
505 	nge_mii_sync(sc);
506 
507 	nge_mii_send(sc, frame->mii_stdelim, 2);
508 	nge_mii_send(sc, frame->mii_opcode, 2);
509 	nge_mii_send(sc, frame->mii_phyaddr, 5);
510 	nge_mii_send(sc, frame->mii_regaddr, 5);
511 	nge_mii_send(sc, frame->mii_turnaround, 2);
512 	nge_mii_send(sc, frame->mii_data, 16);
513 
514 	/* Idle bit. */
515 	SIO_SET(NGE_MEAR_MII_CLK);
516 	DELAY(1);
517 	SIO_CLR(NGE_MEAR_MII_CLK);
518 	DELAY(1);
519 
520 	/*
521 	 * Turn off xmit.
522 	 */
523 	SIO_CLR(NGE_MEAR_MII_DIR);
524 
525 	return(0);
526 }
527 
528 static int
nge_miibus_readreg(device_t dev,int phy,int reg)529 nge_miibus_readreg(device_t dev, int phy, int reg)
530 {
531 	struct nge_softc *sc = device_get_softc(dev);
532 	struct nge_mii_frame frame;
533 
534 	bzero((char *)&frame, sizeof(frame));
535 
536 	frame.mii_phyaddr = phy;
537 	frame.mii_regaddr = reg;
538 	nge_mii_readreg(sc, &frame);
539 
540 	return(frame.mii_data);
541 }
542 
543 static int
nge_miibus_writereg(device_t dev,int phy,int reg,int data)544 nge_miibus_writereg(device_t dev, int phy, int reg, int data)
545 {
546 	struct nge_softc *sc = device_get_softc(dev);
547 	struct nge_mii_frame frame;
548 
549 	bzero((char *)&frame, sizeof(frame));
550 
551 	frame.mii_phyaddr = phy;
552 	frame.mii_regaddr = reg;
553 	frame.mii_data = data;
554 	nge_mii_writereg(sc, &frame);
555 
556 	return(0);
557 }
558 
559 static void
nge_miibus_statchg(device_t dev)560 nge_miibus_statchg(device_t dev)
561 {
562 	struct nge_softc *sc = device_get_softc(dev);
563 	struct mii_data *mii;
564 	int status;
565 
566 	if (sc->nge_tbi) {
567 		if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
568 		    == IFM_AUTO) {
569 			status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
570 			if (status == 0 || status & NGE_TBIANAR_FDX) {
571 				NGE_SETBIT(sc, NGE_TX_CFG,
572 				    (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
573 				NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
574 			} else {
575 				NGE_CLRBIT(sc, NGE_TX_CFG,
576 				    (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
577 				NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
578 			}
579 		} else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
580 			!= IFM_FDX) {
581 			NGE_CLRBIT(sc, NGE_TX_CFG,
582 			    (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
583 			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
584 		} else {
585 			NGE_SETBIT(sc, NGE_TX_CFG,
586 			    (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
587 			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
588 		}
589 	} else {
590 		mii = device_get_softc(sc->nge_miibus);
591 
592 		if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
593 		        NGE_SETBIT(sc, NGE_TX_CFG,
594 			    (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
595 			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
596 		} else {
597 			NGE_CLRBIT(sc, NGE_TX_CFG,
598 			    (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
599 			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
600 		}
601 
602 		/* If we have a 1000Mbps link, set the mode_1000 bit. */
603 		if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
604 		    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
605 			NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
606 		} else {
607 			NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
608 		}
609 	}
610 }
611 
612 static void
nge_setmulti(struct nge_softc * sc)613 nge_setmulti(struct nge_softc *sc)
614 {
615 	struct ifnet *ifp = &sc->arpcom.ac_if;
616 	struct ifmultiaddr *ifma;
617 	uint32_t filtsave, h = 0, i;
618 	int bit, index;
619 
620 	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
621 		NGE_CLRBIT(sc, NGE_RXFILT_CTL,
622 		    NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH);
623 		NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
624 		return;
625 	}
626 
627 	/*
628 	 * We have to explicitly enable the multicast hash table
629 	 * on the NatSemi chip if we want to use it, which we do.
630 	 * We also have to tell it that we don't want to use the
631 	 * hash table for matching unicast addresses.
632 	 */
633 	NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
634 	NGE_CLRBIT(sc, NGE_RXFILT_CTL,
635 	    NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH);
636 
637 	filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
638 
639 	/* first, zot all the existing hash bits */
640 	for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
641 		CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
642 		CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
643 	}
644 
645 	/*
646 	 * From the 11 bits returned by the crc routine, the top 7
647 	 * bits represent the 16-bit word in the mcast hash table
648 	 * that needs to be updated, and the lower 4 bits represent
649 	 * which bit within that byte needs to be set.
650 	 */
651 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
652 		if (ifma->ifma_addr->sa_family != AF_LINK)
653 			continue;
654 		h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
655 		    ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
656 		index = (h >> 4) & 0x7F;
657 		bit = h & 0xF;
658 		CSR_WRITE_4(sc, NGE_RXFILT_CTL,
659 		    NGE_FILTADDR_MCAST_LO + (index * 2));
660 		NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
661 	}
662 
663 	CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
664 }
665 
666 static void
nge_reset(struct nge_softc * sc)667 nge_reset(struct nge_softc *sc)
668 {
669 	int i;
670 
671 	NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
672 
673 	for (i = 0; i < NGE_TIMEOUT; i++) {
674 		if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0)
675 			break;
676 	}
677 
678 	if (i == NGE_TIMEOUT)
679 		kprintf("nge%d: reset never completed\n", sc->nge_unit);
680 
681 	/* Wait a little while for the chip to get its brains in order. */
682 	DELAY(1000);
683 
684 	/*
685 	 * If this is a NetSemi chip, make sure to clear
686 	 * PME mode.
687 	 */
688 	CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
689 	CSR_WRITE_4(sc, NGE_CLKRUN, 0);
690 }
691 
692 /*
693  * Probe for an NatSemi chip. Check the PCI vendor and device
694  * IDs against our list and return a device name if we find a match.
695  */
696 static int
nge_probe(device_t dev)697 nge_probe(device_t dev)
698 {
699 	struct nge_type	*t;
700 	uint16_t vendor, product;
701 
702 	vendor = pci_get_vendor(dev);
703 	product = pci_get_device(dev);
704 
705 	for (t = nge_devs; t->nge_name != NULL; t++) {
706 		if (vendor == t->nge_vid && product == t->nge_did) {
707 			device_set_desc(dev, t->nge_name);
708 			return(0);
709 		}
710 	}
711 
712 	return(ENXIO);
713 }
714 
715 /*
716  * Attach the interface. Allocate softc structures, do ifmedia
717  * setup and ethernet/BPF attach.
718  */
719 static int
nge_attach(device_t dev)720 nge_attach(device_t dev)
721 {
722 	struct nge_softc *sc;
723 	struct ifnet *ifp;
724 	uint8_t eaddr[ETHER_ADDR_LEN];
725 	uint32_t		command;
726 	int error = 0, rid, unit;
727 	const char		*sep = "";
728 
729 	sc = device_get_softc(dev);
730 	unit = device_get_unit(dev);
731 	callout_init(&sc->nge_stat_timer);
732 	lwkt_serialize_init(&sc->nge_jslot_serializer);
733 
734 	/*
735 	 * Handle power management nonsense.
736 	 */
737 	command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF;
738 	if (command == 0x01) {
739 		command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4);
740 		if (command & NGE_PSTATE_MASK) {
741 			uint32_t		iobase, membase, irq;
742 
743 			/* Save important PCI config data. */
744 			iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
745 			membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
746 			irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
747 
748 			/* Reset the power state. */
749 			kprintf("nge%d: chip is in D%d power mode "
750 			"-- setting to D0\n", unit, command & NGE_PSTATE_MASK);
751 			command &= 0xFFFFFFFC;
752 			pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4);
753 
754 			/* Restore PCI config data. */
755 			pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
756 			pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
757 			pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
758 		}
759 	}
760 
761 	/*
762 	 * Map control/status registers.
763 	 */
764 	command = pci_read_config(dev, PCIR_COMMAND, 4);
765 	command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
766 	pci_write_config(dev, PCIR_COMMAND, command, 4);
767 	command = pci_read_config(dev, PCIR_COMMAND, 4);
768 
769 #ifdef NGE_USEIOSPACE
770 	if (!(command & PCIM_CMD_PORTEN)) {
771 		kprintf("nge%d: failed to enable I/O ports!\n", unit);
772 		error = ENXIO;
773 		return(error);
774 	}
775 #else
776 	if (!(command & PCIM_CMD_MEMEN)) {
777 		kprintf("nge%d: failed to enable memory mapping!\n", unit);
778 		error = ENXIO;
779 		return(error);
780 	}
781 #endif
782 
783 	rid = NGE_RID;
784 	sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
785 
786 	if (sc->nge_res == NULL) {
787 		kprintf("nge%d: couldn't map ports/memory\n", unit);
788 		error = ENXIO;
789 		return(error);
790 	}
791 
792 	sc->nge_btag = rman_get_bustag(sc->nge_res);
793 	sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
794 
795 	/* Allocate interrupt */
796 	rid = 0;
797 	sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
798 	    RF_SHAREABLE | RF_ACTIVE);
799 
800 	if (sc->nge_irq == NULL) {
801 		kprintf("nge%d: couldn't map interrupt\n", unit);
802 		error = ENXIO;
803 		goto fail;
804 	}
805 
806 	/* Reset the adapter. */
807 	nge_reset(sc);
808 
809 	/*
810 	 * Get station address from the EEPROM.
811 	 */
812 	nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1);
813 	nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1);
814 	nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1);
815 
816 	sc->nge_unit = unit;
817 
818 	sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
819 	    M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
820 
821 	if (sc->nge_ldata == NULL) {
822 		kprintf("nge%d: no memory for list buffers!\n", unit);
823 		error = ENXIO;
824 		goto fail;
825 	}
826 
827 	/* Try to allocate memory for jumbo buffers. */
828 	if (nge_alloc_jumbo_mem(sc)) {
829 		kprintf("nge%d: jumbo buffer allocation failed\n",
830                     sc->nge_unit);
831 		error = ENXIO;
832 		goto fail;
833 	}
834 
835 	ifp = &sc->arpcom.ac_if;
836 	ifp->if_softc = sc;
837 	if_initname(ifp, "nge", unit);
838 	ifp->if_mtu = ETHERMTU;
839 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
840 	ifp->if_ioctl = nge_ioctl;
841 	ifp->if_start = nge_start;
842 #ifdef IFPOLL_ENABLE
843 	ifp->if_npoll = nge_npoll;
844 #endif
845 	ifp->if_watchdog = nge_watchdog;
846 	ifp->if_init = nge_init;
847 	ifp->if_baudrate = 1000000000;
848 	ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1);
849 	ifq_set_ready(&ifp->if_snd);
850 	ifp->if_hwassist = NGE_CSUM_FEATURES;
851 	ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING;
852 	ifp->if_capenable = ifp->if_capabilities;
853 
854 	/*
855 	 * Do MII setup.
856 	 */
857 	if (mii_phy_probe(dev, &sc->nge_miibus,
858 			  nge_ifmedia_upd, nge_ifmedia_sts)) {
859 		if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
860 			sc->nge_tbi = 1;
861 			device_printf(dev, "Using TBI\n");
862 
863 			sc->nge_miibus = dev;
864 
865 			ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
866 				nge_ifmedia_sts);
867 #define	ADD(m, c)	ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
868 #define PRINT(s)	kprintf("%s%s", sep, s); sep = ", "
869 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
870 			device_printf(dev, " ");
871 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
872 			PRINT("1000baseSX");
873 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
874 			PRINT("1000baseSX-FDX");
875 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
876 			PRINT("auto");
877 
878 			kprintf("\n");
879 #undef ADD
880 #undef PRINT
881 			ifmedia_set(&sc->nge_ifmedia,
882 				IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
883 
884 			CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
885 				| NGE_GPIO_GP4_OUT
886 				| NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
887 				| NGE_GPIO_GP3_OUTENB
888 				| NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
889 
890 		} else {
891 			kprintf("nge%d: MII without any PHY!\n", sc->nge_unit);
892 			error = ENXIO;
893 			goto fail;
894 		}
895 	}
896 
897 	/*
898 	 * Call MI attach routine.
899 	 */
900 	ether_ifattach(ifp, eaddr, NULL);
901 
902 	ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->nge_irq));
903 
904 #ifdef IFPOLL_ENABLE
905 	ifpoll_compat_setup(&sc->nge_npoll, NULL, NULL, device_get_unit(dev),
906 	    ifp->if_serializer);
907 #endif
908 
909 	error = bus_setup_intr(dev, sc->nge_irq, INTR_MPSAFE,
910 			       nge_intr, sc, &sc->nge_intrhand,
911 			       ifp->if_serializer);
912 	if (error) {
913 		ether_ifdetach(ifp);
914 		device_printf(dev, "couldn't set up irq\n");
915 		goto fail;
916 	}
917 
918 	return(0);
919 fail:
920 	nge_detach(dev);
921 	return(error);
922 }
923 
924 static int
nge_detach(device_t dev)925 nge_detach(device_t dev)
926 {
927 	struct nge_softc *sc = device_get_softc(dev);
928 	struct ifnet *ifp = &sc->arpcom.ac_if;
929 
930 	if (device_is_attached(dev)) {
931 		lwkt_serialize_enter(ifp->if_serializer);
932 		nge_reset(sc);
933 		nge_stop(sc);
934 		bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
935 		lwkt_serialize_exit(ifp->if_serializer);
936 
937 		ether_ifdetach(ifp);
938 	}
939 
940 	if (sc->nge_miibus)
941 		device_delete_child(dev, sc->nge_miibus);
942 	bus_generic_detach(dev);
943 
944 	if (sc->nge_irq)
945 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
946 	if (sc->nge_res)
947 		bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
948 	if (sc->nge_ldata) {
949 		contigfree(sc->nge_ldata, sizeof(struct nge_list_data),
950 			   M_DEVBUF);
951 	}
952 	if (sc->nge_cdata.nge_jumbo_buf)
953 		contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
954 
955 	return(0);
956 }
957 
958 /*
959  * Initialize the transmit descriptors.
960  */
961 static int
nge_list_tx_init(struct nge_softc * sc)962 nge_list_tx_init(struct nge_softc *sc)
963 {
964 	struct nge_list_data *ld;
965 	struct nge_ring_data *cd;
966 	int i;
967 
968 	cd = &sc->nge_cdata;
969 	ld = sc->nge_ldata;
970 
971 	for (i = 0; i < NGE_TX_LIST_CNT; i++) {
972 		if (i == (NGE_TX_LIST_CNT - 1)) {
973 			ld->nge_tx_list[i].nge_nextdesc =
974 			    &ld->nge_tx_list[0];
975 			ld->nge_tx_list[i].nge_next =
976 			    vtophys(&ld->nge_tx_list[0]);
977 		} else {
978 			ld->nge_tx_list[i].nge_nextdesc =
979 			    &ld->nge_tx_list[i + 1];
980 			ld->nge_tx_list[i].nge_next =
981 			    vtophys(&ld->nge_tx_list[i + 1]);
982 		}
983 		ld->nge_tx_list[i].nge_mbuf = NULL;
984 		ld->nge_tx_list[i].nge_ptr = 0;
985 		ld->nge_tx_list[i].nge_ctl = 0;
986 	}
987 
988 	cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
989 
990 	return(0);
991 }
992 
993 
994 /*
995  * Initialize the RX descriptors and allocate mbufs for them. Note that
996  * we arrange the descriptors in a closed ring, so that the last descriptor
997  * points back to the first.
998  */
999 static int
nge_list_rx_init(struct nge_softc * sc)1000 nge_list_rx_init(struct nge_softc *sc)
1001 {
1002 	struct nge_list_data *ld;
1003 	struct nge_ring_data *cd;
1004 	int i;
1005 
1006 	ld = sc->nge_ldata;
1007 	cd = &sc->nge_cdata;
1008 
1009 	for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1010 		if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1011 			return(ENOBUFS);
1012 		if (i == (NGE_RX_LIST_CNT - 1)) {
1013 			ld->nge_rx_list[i].nge_nextdesc =
1014 			    &ld->nge_rx_list[0];
1015 			ld->nge_rx_list[i].nge_next =
1016 			    vtophys(&ld->nge_rx_list[0]);
1017 		} else {
1018 			ld->nge_rx_list[i].nge_nextdesc =
1019 			    &ld->nge_rx_list[i + 1];
1020 			ld->nge_rx_list[i].nge_next =
1021 			    vtophys(&ld->nge_rx_list[i + 1]);
1022 		}
1023 	}
1024 
1025 	cd->nge_rx_prod = 0;
1026 
1027 	return(0);
1028 }
1029 
1030 /*
1031  * Initialize an RX descriptor and attach an MBUF cluster.
1032  */
1033 static int
nge_newbuf(struct nge_softc * sc,struct nge_desc * c,struct mbuf * m)1034 nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m)
1035 {
1036 	struct mbuf *m_new = NULL;
1037 	struct nge_jslot *buf;
1038 
1039 	if (m == NULL) {
1040 		MGETHDR(m_new, M_NOWAIT, MT_DATA);
1041 		if (m_new == NULL) {
1042 			kprintf("nge%d: no memory for rx list "
1043 			    "-- packet dropped!\n", sc->nge_unit);
1044 			return(ENOBUFS);
1045 		}
1046 
1047 		/* Allocate the jumbo buffer */
1048 		buf = nge_jalloc(sc);
1049 		if (buf == NULL) {
1050 #ifdef NGE_VERBOSE
1051 			kprintf("nge%d: jumbo allocation failed "
1052 			    "-- packet dropped!\n", sc->nge_unit);
1053 #endif
1054 			m_freem(m_new);
1055 			return(ENOBUFS);
1056 		}
1057 		/* Attach the buffer to the mbuf */
1058 		m_new->m_ext.ext_arg = buf;
1059 		m_new->m_ext.ext_buf = buf->nge_buf;
1060 		m_new->m_ext.ext_free = nge_jfree;
1061 		m_new->m_ext.ext_ref = nge_jref;
1062 		m_new->m_ext.ext_size = NGE_JUMBO_FRAMELEN;
1063 
1064 		m_new->m_data = m_new->m_ext.ext_buf;
1065 		m_new->m_flags |= M_EXT;
1066 		m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1067 	} else {
1068 		m_new = m;
1069 		m_new->m_len = m_new->m_pkthdr.len = NGE_JLEN;
1070 		m_new->m_data = m_new->m_ext.ext_buf;
1071 	}
1072 
1073 	m_adj(m_new, sizeof(uint64_t));
1074 
1075 	c->nge_mbuf = m_new;
1076 	c->nge_ptr = vtophys(mtod(m_new, caddr_t));
1077 	c->nge_ctl = m_new->m_len;
1078 	c->nge_extsts = 0;
1079 
1080 	return(0);
1081 }
1082 
1083 static int
nge_alloc_jumbo_mem(struct nge_softc * sc)1084 nge_alloc_jumbo_mem(struct nge_softc *sc)
1085 {
1086 	caddr_t ptr;
1087 	int i;
1088 	struct nge_jslot *entry;
1089 
1090 	/* Grab a big chunk o' storage. */
1091 	sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
1092 	    M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1093 
1094 	if (sc->nge_cdata.nge_jumbo_buf == NULL) {
1095 		kprintf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
1096 		return(ENOBUFS);
1097 	}
1098 
1099 	SLIST_INIT(&sc->nge_jfree_listhead);
1100 
1101 	/*
1102 	 * Now divide it up into 9K pieces and save the addresses
1103 	 * in an array.
1104 	 */
1105 	ptr = sc->nge_cdata.nge_jumbo_buf;
1106 	for (i = 0; i < NGE_JSLOTS; i++) {
1107 		entry = &sc->nge_cdata.nge_jslots[i];
1108 		entry->nge_sc = sc;
1109 		entry->nge_buf = ptr;
1110 		entry->nge_inuse = 0;
1111 		entry->nge_slot = i;
1112 		SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link);
1113 		ptr += NGE_JLEN;
1114 	}
1115 
1116 	return(0);
1117 }
1118 
1119 
1120 /*
1121  * Allocate a jumbo buffer.
1122  */
1123 static struct nge_jslot *
nge_jalloc(struct nge_softc * sc)1124 nge_jalloc(struct nge_softc *sc)
1125 {
1126 	struct nge_jslot *entry;
1127 
1128 	lwkt_serialize_enter(&sc->nge_jslot_serializer);
1129 	entry = SLIST_FIRST(&sc->nge_jfree_listhead);
1130 	if (entry) {
1131 		SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jslot_link);
1132 		entry->nge_inuse = 1;
1133 	} else {
1134 #ifdef NGE_VERBOSE
1135 		kprintf("nge%d: no free jumbo buffers\n", sc->nge_unit);
1136 #endif
1137 	}
1138 	lwkt_serialize_exit(&sc->nge_jslot_serializer);
1139 	return(entry);
1140 }
1141 
1142 /*
1143  * Adjust usage count on a jumbo buffer. In general this doesn't
1144  * get used much because our jumbo buffers don't get passed around
1145  * a lot, but it's implemented for correctness.
1146  */
1147 static void
nge_jref(void * arg)1148 nge_jref(void *arg)
1149 {
1150 	struct nge_jslot *entry = (struct nge_jslot *)arg;
1151 	struct nge_softc *sc = entry->nge_sc;
1152 
1153 	if (sc == NULL)
1154 		panic("nge_jref: can't find softc pointer!");
1155 
1156 	if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry)
1157 		panic("nge_jref: asked to reference buffer "
1158 		    "that we don't manage!");
1159 	else if (entry->nge_inuse == 0)
1160 		panic("nge_jref: buffer already free!");
1161 	else
1162 		atomic_add_int(&entry->nge_inuse, 1);
1163 }
1164 
1165 /*
1166  * Release a jumbo buffer.
1167  */
1168 static void
nge_jfree(void * arg)1169 nge_jfree(void *arg)
1170 {
1171 	struct nge_jslot *entry = (struct nge_jslot *)arg;
1172 	struct nge_softc *sc = entry->nge_sc;
1173 
1174 	if (sc == NULL)
1175 		panic("nge_jref: can't find softc pointer!");
1176 
1177 	if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) {
1178 		panic("nge_jref: asked to reference buffer "
1179 		    "that we don't manage!");
1180 	} else if (entry->nge_inuse == 0) {
1181 		panic("nge_jref: buffer already free!");
1182 	} else {
1183 		lwkt_serialize_enter(&sc->nge_jslot_serializer);
1184 		atomic_subtract_int(&entry->nge_inuse, 1);
1185 		if (entry->nge_inuse == 0) {
1186 			SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
1187 					  entry, jslot_link);
1188 		}
1189 		lwkt_serialize_exit(&sc->nge_jslot_serializer);
1190 	}
1191 }
1192 /*
1193  * A frame has been uploaded: pass the resulting mbuf chain up to
1194  * the higher level protocols.
1195  */
1196 static void
nge_rxeof(struct nge_softc * sc)1197 nge_rxeof(struct nge_softc *sc)
1198 {
1199         struct mbuf *m;
1200         struct ifnet *ifp = &sc->arpcom.ac_if;
1201 	struct nge_desc *cur_rx;
1202 	int i, total_len = 0;
1203 	uint32_t rxstat;
1204 
1205 	i = sc->nge_cdata.nge_rx_prod;
1206 
1207 	while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1208 		struct mbuf *m0 = NULL;
1209 		uint32_t extsts;
1210 
1211 #ifdef IFPOLL_ENABLE
1212 		if (ifp->if_flags & IFF_NPOLLING) {
1213 			if (sc->rxcycles <= 0)
1214 				break;
1215 			sc->rxcycles--;
1216 		}
1217 #endif /* IFPOLL_ENABLE */
1218 
1219 		cur_rx = &sc->nge_ldata->nge_rx_list[i];
1220 		rxstat = cur_rx->nge_rxstat;
1221 		extsts = cur_rx->nge_extsts;
1222 		m = cur_rx->nge_mbuf;
1223 		cur_rx->nge_mbuf = NULL;
1224 		total_len = NGE_RXBYTES(cur_rx);
1225 		NGE_INC(i, NGE_RX_LIST_CNT);
1226 		/*
1227 		 * If an error occurs, update stats, clear the
1228 		 * status word and leave the mbuf cluster in place:
1229 		 * it should simply get re-used next time this descriptor
1230 	 	 * comes up in the ring.
1231 		 */
1232 		if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) {
1233 			IFNET_STAT_INC(ifp, ierrors, 1);
1234 			nge_newbuf(sc, cur_rx, m);
1235 			continue;
1236 		}
1237 
1238 		/*
1239 		 * Ok. NatSemi really screwed up here. This is the
1240 		 * only gigE chip I know of with alignment constraints
1241 		 * on receive buffers. RX buffers must be 64-bit aligned.
1242 		 */
1243 #ifdef __x86_64__
1244 		/*
1245 		 * By popular demand, ignore the alignment problems
1246 		 * on the Intel x86 platform. The performance hit
1247 		 * incurred due to unaligned accesses is much smaller
1248 		 * than the hit produced by forcing buffer copies all
1249 		 * the time, especially with jumbo frames. We still
1250 		 * need to fix up the alignment everywhere else though.
1251 		 */
1252 		if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
1253 #endif
1254 			m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1255 				      total_len + ETHER_ALIGN, 0, ifp);
1256 			nge_newbuf(sc, cur_rx, m);
1257 			if (m0 == NULL) {
1258 				kprintf("nge%d: no receive buffers "
1259 				    "available -- packet dropped!\n",
1260 				    sc->nge_unit);
1261 				IFNET_STAT_INC(ifp, ierrors, 1);
1262 				continue;
1263 			}
1264 			m_adj(m0, ETHER_ALIGN);
1265 			m = m0;
1266 #ifdef __x86_64__
1267 		} else {
1268 			m->m_pkthdr.rcvif = ifp;
1269 			m->m_pkthdr.len = m->m_len = total_len;
1270 		}
1271 #endif
1272 
1273 		IFNET_STAT_INC(ifp, ipackets, 1);
1274 
1275 		/* Do IP checksum checking. */
1276 		if (extsts & NGE_RXEXTSTS_IPPKT)
1277 			m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1278 		if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1279 			m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1280 		if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1281 		    (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) ||
1282 		    (extsts & NGE_RXEXTSTS_UDPPKT &&
1283 		    (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) {
1284 			m->m_pkthdr.csum_flags |=
1285 			    CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
1286 			    CSUM_FRAG_NOT_CHECKED;
1287 			m->m_pkthdr.csum_data = 0xffff;
1288 		}
1289 
1290 		/*
1291 		 * If we received a packet with a vlan tag, pass it
1292 		 * to vlan_input() instead of ether_input().
1293 		 */
1294 		if (extsts & NGE_RXEXTSTS_VLANPKT) {
1295 			m->m_flags |= M_VLANTAG;
1296 			m->m_pkthdr.ether_vlantag =
1297 				(extsts & NGE_RXEXTSTS_VTCI);
1298 		}
1299 		ifp->if_input(ifp, m, NULL, -1);
1300 	}
1301 
1302 	sc->nge_cdata.nge_rx_prod = i;
1303 }
1304 
1305 /*
1306  * A frame was downloaded to the chip. It's safe for us to clean up
1307  * the list buffers.
1308  */
1309 static void
nge_txeof(struct nge_softc * sc)1310 nge_txeof(struct nge_softc *sc)
1311 {
1312 	struct ifnet *ifp = &sc->arpcom.ac_if;
1313 	struct nge_desc *cur_tx = NULL;
1314 	uint32_t idx;
1315 
1316 	/* Clear the timeout timer. */
1317 	ifp->if_timer = 0;
1318 
1319 	/*
1320 	 * Go through our tx list and free mbufs for those
1321 	 * frames that have been transmitted.
1322 	 */
1323 	idx = sc->nge_cdata.nge_tx_cons;
1324 	while (idx != sc->nge_cdata.nge_tx_prod) {
1325 		cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1326 
1327 		if (NGE_OWNDESC(cur_tx))
1328 			break;
1329 
1330 		if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1331 			sc->nge_cdata.nge_tx_cnt--;
1332 			NGE_INC(idx, NGE_TX_LIST_CNT);
1333 			continue;
1334 		}
1335 
1336 		if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1337 			IFNET_STAT_INC(ifp, oerrors, 1);
1338 			if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1339 				IFNET_STAT_INC(ifp, collisions, 1);
1340 			if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1341 				IFNET_STAT_INC(ifp, collisions, 1);
1342 		}
1343 
1344 		IFNET_STAT_INC(ifp, collisions,
1345 		    (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16);
1346 
1347 		IFNET_STAT_INC(ifp, opackets, 1);
1348 		if (cur_tx->nge_mbuf != NULL) {
1349 			m_freem(cur_tx->nge_mbuf);
1350 			cur_tx->nge_mbuf = NULL;
1351 		}
1352 
1353 		sc->nge_cdata.nge_tx_cnt--;
1354 		NGE_INC(idx, NGE_TX_LIST_CNT);
1355 		ifp->if_timer = 0;
1356 	}
1357 
1358 	sc->nge_cdata.nge_tx_cons = idx;
1359 
1360 	if (cur_tx != NULL)
1361 		ifq_clr_oactive(&ifp->if_snd);
1362 }
1363 
1364 static void
nge_tick(void * xsc)1365 nge_tick(void *xsc)
1366 {
1367 	struct nge_softc *sc = xsc;
1368 	struct ifnet *ifp = &sc->arpcom.ac_if;
1369 	struct mii_data *mii;
1370 
1371 	lwkt_serialize_enter(ifp->if_serializer);
1372 
1373 	if (sc->nge_tbi) {
1374 		if (sc->nge_link == 0) {
1375 			if (CSR_READ_4(sc, NGE_TBI_BMSR)
1376 			    & NGE_TBIBMSR_ANEG_DONE) {
1377 				kprintf("nge%d: gigabit link up\n",
1378 				    sc->nge_unit);
1379 				nge_miibus_statchg(sc->nge_miibus);
1380 				sc->nge_link++;
1381 				if (!ifq_is_empty(&ifp->if_snd))
1382 					if_devstart(ifp);
1383 			}
1384 		}
1385 	} else {
1386 		mii = device_get_softc(sc->nge_miibus);
1387 		mii_tick(mii);
1388 
1389 		if (sc->nge_link == 0) {
1390 			if (mii->mii_media_status & IFM_ACTIVE &&
1391 			    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1392 				sc->nge_link++;
1393 				if (IFM_SUBTYPE(mii->mii_media_active)
1394 				    == IFM_1000_T)
1395 					kprintf("nge%d: gigabit link up\n",
1396 					    sc->nge_unit);
1397 				if (!ifq_is_empty(&ifp->if_snd))
1398 					if_devstart(ifp);
1399 			}
1400 		}
1401 	}
1402 	callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1403 
1404 	lwkt_serialize_exit(ifp->if_serializer);
1405 }
1406 
1407 #ifdef IFPOLL_ENABLE
1408 
1409 static void
nge_npoll_compat(struct ifnet * ifp,void * arg __unused,int count)1410 nge_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
1411 {
1412 	struct nge_softc *sc = ifp->if_softc;
1413 
1414 	ASSERT_SERIALIZED(ifp->if_serializer);
1415 
1416 	/*
1417 	 * On the nge, reading the status register also clears it.
1418 	 * So before returning to intr mode we must make sure that all
1419 	 * possible pending sources of interrupts have been served.
1420 	 * In practice this means run to completion the *eof routines,
1421 	 * and then call the interrupt routine
1422 	 */
1423 	sc->rxcycles = count;
1424 	nge_rxeof(sc);
1425 	nge_txeof(sc);
1426 	if (!ifq_is_empty(&ifp->if_snd))
1427 		if_devstart(ifp);
1428 
1429 	if (sc->nge_npoll.ifpc_stcount-- == 0) {
1430 		uint32_t status;
1431 
1432 		sc->nge_npoll.ifpc_stcount = sc->nge_npoll.ifpc_stfrac;
1433 
1434 		/* Reading the ISR register clears all interrupts. */
1435 		status = CSR_READ_4(sc, NGE_ISR);
1436 
1437 		if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1438 			nge_rxeof(sc);
1439 
1440 		if (status & (NGE_ISR_RX_IDLE))
1441 			NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1442 
1443 		if (status & NGE_ISR_SYSERR) {
1444 			nge_reset(sc);
1445 			nge_init(sc);
1446 		}
1447 	}
1448 }
1449 
1450 static void
nge_npoll(struct ifnet * ifp,struct ifpoll_info * info)1451 nge_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1452 {
1453 	struct nge_softc *sc = ifp->if_softc;
1454 
1455 	ASSERT_SERIALIZED(ifp->if_serializer);
1456 
1457 	if (info != NULL) {
1458 		int cpuid = sc->nge_npoll.ifpc_cpuid;
1459 
1460 		info->ifpi_rx[cpuid].poll_func = nge_npoll_compat;
1461 		info->ifpi_rx[cpuid].arg = NULL;
1462 		info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1463 
1464 		if (ifp->if_flags & IFF_RUNNING) {
1465 			/* disable interrupts */
1466 			CSR_WRITE_4(sc, NGE_IER, 0);
1467 			sc->nge_npoll.ifpc_stcount = 0;
1468 		}
1469 		ifq_set_cpuid(&ifp->if_snd, cpuid);
1470 	} else {
1471 		if (ifp->if_flags & IFF_RUNNING) {
1472 			/* enable interrupts */
1473 			CSR_WRITE_4(sc, NGE_IER, 1);
1474 		}
1475 		ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->nge_irq));
1476 	}
1477 }
1478 
1479 #endif /* IFPOLL_ENABLE */
1480 
1481 static void
nge_intr(void * arg)1482 nge_intr(void *arg)
1483 {
1484 	struct nge_softc *sc = arg;
1485 	struct ifnet *ifp = &sc->arpcom.ac_if;
1486 	uint32_t status;
1487 
1488 	/* Supress unwanted interrupts */
1489 	if (!(ifp->if_flags & IFF_UP)) {
1490 		nge_stop(sc);
1491 		return;
1492 	}
1493 
1494 	/* Disable interrupts. */
1495 	CSR_WRITE_4(sc, NGE_IER, 0);
1496 
1497 	/* Data LED on for TBI mode */
1498 	if(sc->nge_tbi)
1499 		 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1500 			     | NGE_GPIO_GP3_OUT);
1501 
1502 	for (;;) {
1503 		/* Reading the ISR register clears all interrupts. */
1504 		status = CSR_READ_4(sc, NGE_ISR);
1505 
1506 		if ((status & NGE_INTRS) == 0)
1507 			break;
1508 
1509 		if ((status & NGE_ISR_TX_DESC_OK) ||
1510 		    (status & NGE_ISR_TX_ERR) ||
1511 		    (status & NGE_ISR_TX_OK) ||
1512 		    (status & NGE_ISR_TX_IDLE))
1513 			nge_txeof(sc);
1514 
1515 		if ((status & NGE_ISR_RX_DESC_OK) ||
1516 		    (status & NGE_ISR_RX_ERR) ||
1517 		    (status & NGE_ISR_RX_OFLOW) ||
1518 		    (status & NGE_ISR_RX_FIFO_OFLOW) ||
1519 		    (status & NGE_ISR_RX_IDLE) ||
1520 		    (status & NGE_ISR_RX_OK))
1521 			nge_rxeof(sc);
1522 
1523 		if ((status & NGE_ISR_RX_IDLE))
1524 			NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1525 
1526 		if (status & NGE_ISR_SYSERR) {
1527 			nge_reset(sc);
1528 			ifp->if_flags &= ~IFF_RUNNING;
1529 			nge_init(sc);
1530 		}
1531 
1532 #ifdef notyet
1533 		/* mii_tick should only be called once per second */
1534 		if (status & NGE_ISR_PHY_INTR) {
1535 			sc->nge_link = 0;
1536 			nge_tick_serialized(sc);
1537 		}
1538 #endif
1539 	}
1540 
1541 	/* Re-enable interrupts. */
1542 	CSR_WRITE_4(sc, NGE_IER, 1);
1543 
1544 	if (!ifq_is_empty(&ifp->if_snd))
1545 		if_devstart(ifp);
1546 
1547 	/* Data LED off for TBI mode */
1548 
1549 	if(sc->nge_tbi)
1550 		CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1551 			    & ~NGE_GPIO_GP3_OUT);
1552 }
1553 
1554 /*
1555  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1556  * pointers to the fragment pointers.
1557  */
1558 static int
nge_encap(struct nge_softc * sc,struct mbuf * m_head,uint32_t * txidx)1559 nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1560 {
1561 	struct nge_desc *f = NULL;
1562 	struct mbuf *m;
1563 	int frag, cur, cnt = 0;
1564 
1565 	/*
1566  	 * Start packing the mbufs in this chain into
1567 	 * the fragment pointers. Stop when we run out
1568  	 * of fragments or hit the end of the mbuf chain.
1569 	 */
1570 	cur = frag = *txidx;
1571 
1572 	for (m = m_head; m != NULL; m = m->m_next) {
1573 		if (m->m_len != 0) {
1574 			if ((NGE_TX_LIST_CNT -
1575 			    (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
1576 				break;
1577 			f = &sc->nge_ldata->nge_tx_list[frag];
1578 			f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1579 			f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1580 			if (cnt != 0)
1581 				f->nge_ctl |= NGE_CMDSTS_OWN;
1582 			cur = frag;
1583 			NGE_INC(frag, NGE_TX_LIST_CNT);
1584 			cnt++;
1585 		}
1586 	}
1587 	/* Caller should make sure that 'm_head' is not excessive fragmented */
1588 	KASSERT(m == NULL, ("too many fragments"));
1589 
1590 	sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1591 	if (m_head->m_pkthdr.csum_flags) {
1592 		if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1593 			sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1594 			    NGE_TXEXTSTS_IPCSUM;
1595 		if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1596 			sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1597 			    NGE_TXEXTSTS_TCPCSUM;
1598 		if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1599 			sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1600 			    NGE_TXEXTSTS_UDPCSUM;
1601 	}
1602 
1603 	if (m_head->m_flags & M_VLANTAG) {
1604 		sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
1605 			(NGE_TXEXTSTS_VLANPKT|m_head->m_pkthdr.ether_vlantag);
1606 	}
1607 
1608 	sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1609 	sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1610 	sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1611 	sc->nge_cdata.nge_tx_cnt += cnt;
1612 	*txidx = frag;
1613 
1614 	return(0);
1615 }
1616 
1617 /*
1618  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1619  * to the mbuf data regions directly in the transmit lists. We also save a
1620  * copy of the pointers since the transmit list fragment pointers are
1621  * physical addresses.
1622  */
1623 
1624 static void
nge_start(struct ifnet * ifp,struct ifaltq_subque * ifsq)1625 nge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1626 {
1627 	struct nge_softc *sc = ifp->if_softc;
1628 	struct mbuf *m_head = NULL, *m_defragged;
1629 	uint32_t idx;
1630 	int need_trans;
1631 
1632 	ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1633 
1634 	if (!sc->nge_link) {
1635 		ifq_purge(&ifp->if_snd);
1636 		return;
1637 	}
1638 
1639 	idx = sc->nge_cdata.nge_tx_prod;
1640 
1641 	if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1642 		return;
1643 
1644 	need_trans = 0;
1645 	while (sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1646 		struct mbuf *m;
1647 		int cnt;
1648 
1649 		m_defragged = NULL;
1650 		m_head = ifq_dequeue(&ifp->if_snd);
1651 		if (m_head == NULL)
1652 			break;
1653 
1654 again:
1655 		cnt = 0;
1656 		for (m = m_head; m != NULL; m = m->m_next)
1657 			++cnt;
1658 		if ((NGE_TX_LIST_CNT -
1659 		    (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) {
1660 			if (m_defragged != NULL) {
1661 				/*
1662 				 * Even after defragmentation, there
1663 				 * are still too many fragments, so
1664 				 * drop this packet.
1665 				 */
1666 				m_freem(m_head);
1667 				ifq_set_oactive(&ifp->if_snd);
1668 				break;
1669 			}
1670 
1671 			m_defragged = m_defrag(m_head, M_NOWAIT);
1672 			if (m_defragged == NULL) {
1673 				m_freem(m_head);
1674 				continue;
1675 			}
1676 			m_head = m_defragged;
1677 
1678 			/* Recount # of fragments */
1679 			goto again;
1680 		}
1681 
1682 		nge_encap(sc, m_head, &idx);
1683 		need_trans = 1;
1684 
1685 		ETHER_BPF_MTAP(ifp, m_head);
1686 	}
1687 
1688 	if (!need_trans)
1689 		return;
1690 
1691 	/* Transmit */
1692 	sc->nge_cdata.nge_tx_prod = idx;
1693 	NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1694 
1695 	/*
1696 	 * Set a timeout in case the chip goes out to lunch.
1697 	 */
1698 	ifp->if_timer = 5;
1699 }
1700 
1701 static void
nge_init(void * xsc)1702 nge_init(void *xsc)
1703 {
1704 	struct nge_softc *sc = xsc;
1705 	struct ifnet *ifp = &sc->arpcom.ac_if;
1706 	struct mii_data *mii;
1707 
1708 	if (ifp->if_flags & IFF_RUNNING) {
1709 		return;
1710 	}
1711 
1712 	/*
1713 	 * Cancel pending I/O and free all RX/TX buffers.
1714 	 */
1715 	nge_stop(sc);
1716 	callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1717 
1718 	if (sc->nge_tbi)
1719 		mii = NULL;
1720 	else
1721 		mii = device_get_softc(sc->nge_miibus);
1722 
1723 	/* Set MAC address */
1724 	CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1725 	CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1726 	    ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1727 	CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1728 	CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1729 	    ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1730 	CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1731 	CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1732 	    ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1733 
1734 	/* Init circular RX list. */
1735 	if (nge_list_rx_init(sc) == ENOBUFS) {
1736 		kprintf("nge%d: initialization failed: no "
1737 			"memory for rx buffers\n", sc->nge_unit);
1738 		nge_stop(sc);
1739 		return;
1740 	}
1741 
1742 	/*
1743 	 * Init tx descriptors.
1744 	 */
1745 	nge_list_tx_init(sc);
1746 
1747 	/*
1748 	 * For the NatSemi chip, we have to explicitly enable the
1749 	 * reception of ARP frames, as well as turn on the 'perfect
1750 	 * match' filter where we store the station address, otherwise
1751 	 * we won't receive unicasts meant for this host.
1752 	 */
1753 	NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1754 	NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1755 
1756 	 /* If we want promiscuous mode, set the allframes bit. */
1757 	if (ifp->if_flags & IFF_PROMISC)
1758 		NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1759 	else
1760 		NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1761 
1762 	/*
1763 	 * Set the capture broadcast bit to capture broadcast frames.
1764 	 */
1765 	if (ifp->if_flags & IFF_BROADCAST)
1766 		NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1767 	else
1768 		NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1769 
1770 	/*
1771 	 * Load the multicast filter.
1772 	 */
1773 	nge_setmulti(sc);
1774 
1775 	/* Turn the receive filter on */
1776 	NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1777 
1778 	/*
1779 	 * Load the address of the RX and TX lists.
1780 	 */
1781 	CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1782 	    vtophys(&sc->nge_ldata->nge_rx_list[0]));
1783 	CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1784 	    vtophys(&sc->nge_ldata->nge_tx_list[0]));
1785 
1786 	/* Set RX configuration */
1787 	CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1788 	/*
1789 	 * Enable hardware checksum validation for all IPv4
1790 	 * packets, do not reject packets with bad checksums.
1791 	 */
1792 	CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1793 
1794 	/*
1795 	 * Tell the chip to detect and strip VLAN tag info from
1796 	 * received frames. The tag will be provided in the extsts
1797 	 * field in the RX descriptors.
1798 	 */
1799 	NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1800 	    NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1801 
1802 	/* Set TX configuration */
1803 	CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1804 
1805 	/*
1806 	 * Enable TX IPv4 checksumming on a per-packet basis.
1807 	 */
1808 	CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1809 
1810 	/*
1811 	 * Tell the chip to insert VLAN tags on a per-packet basis as
1812 	 * dictated by the code in the frame encapsulation routine.
1813 	 */
1814 	NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1815 
1816 	/* Set full/half duplex mode. */
1817 	if (sc->nge_tbi) {
1818 		if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1819 		    == IFM_FDX) {
1820 			NGE_SETBIT(sc, NGE_TX_CFG,
1821 			    (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1822 			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1823 		} else {
1824 			NGE_CLRBIT(sc, NGE_TX_CFG,
1825 			    (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1826 			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1827 		}
1828 	} else {
1829 		if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1830 			NGE_SETBIT(sc, NGE_TX_CFG,
1831 			    (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1832 			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1833 		} else {
1834 			NGE_CLRBIT(sc, NGE_TX_CFG,
1835 			    (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1836 			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1837 		}
1838 	}
1839 
1840 	/*
1841 	 * Enable the delivery of PHY interrupts based on
1842 	 * link/speed/duplex status changes. Also enable the
1843 	 * extsts field in the DMA descriptors (needed for
1844 	 * TCP/IP checksum offload on transmit).
1845 	 */
1846 	NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD |
1847 	    NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB);
1848 
1849 	/*
1850 	 * Configure interrupt holdoff (moderation). We can
1851 	 * have the chip delay interrupt delivery for a certain
1852 	 * period. Units are in 100us, and the max setting
1853 	 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1854 	 */
1855 	CSR_WRITE_4(sc, NGE_IHR, 0x01);
1856 
1857 	/*
1858 	 * Enable interrupts.
1859 	 */
1860 	CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1861 #ifdef IFPOLL_ENABLE
1862 	/*
1863 	 * ... only enable interrupts if we are not polling, make sure
1864 	 * they are off otherwise.
1865 	 */
1866 	if (ifp->if_flags & IFF_NPOLLING) {
1867 		CSR_WRITE_4(sc, NGE_IER, 0);
1868 		sc->nge_npoll.ifpc_stcount = 0;
1869 	} else
1870 #endif /* IFPOLL_ENABLE */
1871 	CSR_WRITE_4(sc, NGE_IER, 1);
1872 
1873 	/* Enable receiver and transmitter. */
1874 	NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE);
1875 	NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1876 
1877 	nge_ifmedia_upd(ifp);
1878 
1879 	ifp->if_flags |= IFF_RUNNING;
1880 	ifq_clr_oactive(&ifp->if_snd);
1881 }
1882 
1883 /*
1884  * Set media options.
1885  */
1886 static int
nge_ifmedia_upd(struct ifnet * ifp)1887 nge_ifmedia_upd(struct ifnet *ifp)
1888 {
1889 	struct nge_softc *sc = ifp->if_softc;
1890 	struct mii_data *mii;
1891 
1892 	if (sc->nge_tbi) {
1893 		if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1894 		     == IFM_AUTO) {
1895 			CSR_WRITE_4(sc, NGE_TBI_ANAR,
1896 				CSR_READ_4(sc, NGE_TBI_ANAR)
1897 					| NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1898 					| NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1899 			CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1900 				| NGE_TBIBMCR_RESTART_ANEG);
1901 			CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1902 		} else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1903 			    & IFM_GMASK) == IFM_FDX) {
1904 			NGE_SETBIT(sc, NGE_TX_CFG,
1905 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1906 			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1907 
1908 			CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1909 			CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1910 		} else {
1911 			NGE_CLRBIT(sc, NGE_TX_CFG,
1912 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1913 			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1914 
1915 			CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1916 			CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1917 		}
1918 
1919 		CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1920 			    & ~NGE_GPIO_GP3_OUT);
1921 	} else {
1922 		mii = device_get_softc(sc->nge_miibus);
1923 		sc->nge_link = 0;
1924 		if (mii->mii_instance) {
1925 			struct mii_softc	*miisc;
1926 			for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1927 			    miisc = LIST_NEXT(miisc, mii_list))
1928 				mii_phy_reset(miisc);
1929 		}
1930 		mii_mediachg(mii);
1931 	}
1932 
1933 	return(0);
1934 }
1935 
1936 /*
1937  * Report current media status.
1938  */
1939 static void
nge_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1940 nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1941 {
1942 	struct nge_softc *sc = ifp->if_softc;
1943 	struct mii_data *mii;
1944 
1945 	if (sc->nge_tbi) {
1946 		ifmr->ifm_status = IFM_AVALID;
1947 		ifmr->ifm_active = IFM_ETHER;
1948 
1949 		if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)
1950 			ifmr->ifm_status |= IFM_ACTIVE;
1951 		if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
1952 			ifmr->ifm_active |= IFM_LOOP;
1953 		if (!(CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)) {
1954 			ifmr->ifm_active |= IFM_NONE;
1955 			ifmr->ifm_status = 0;
1956 			return;
1957 		}
1958 		ifmr->ifm_active |= IFM_1000_SX;
1959 		if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1960 		    == IFM_AUTO) {
1961 			ifmr->ifm_active |= IFM_AUTO;
1962 			if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1963 			    & NGE_TBIANAR_FDX) {
1964 				ifmr->ifm_active |= IFM_FDX;
1965 			}else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1966 				  & NGE_TBIANAR_HDX) {
1967 				ifmr->ifm_active |= IFM_HDX;
1968 			}
1969 		} else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1970 			== IFM_FDX)
1971 			ifmr->ifm_active |= IFM_FDX;
1972 		else
1973 			ifmr->ifm_active |= IFM_HDX;
1974 
1975 	} else {
1976 		mii = device_get_softc(sc->nge_miibus);
1977 		mii_pollstat(mii);
1978 		ifmr->ifm_active = mii->mii_media_active;
1979 		ifmr->ifm_status = mii->mii_media_status;
1980 	}
1981 }
1982 
1983 static int
nge_ioctl(struct ifnet * ifp,u_long command,caddr_t data,struct ucred * cr)1984 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1985 {
1986 	struct nge_softc *sc = ifp->if_softc;
1987 	struct ifreq *ifr = (struct ifreq *) data;
1988 	struct mii_data *mii;
1989 	int error = 0;
1990 
1991 	switch(command) {
1992 	case SIOCSIFMTU:
1993 		if (ifr->ifr_mtu > NGE_JUMBO_MTU) {
1994 			error = EINVAL;
1995 		} else {
1996 			ifp->if_mtu = ifr->ifr_mtu;
1997 			/*
1998 			 * Workaround: if the MTU is larger than
1999 			 * 8152 (TX FIFO size minus 64 minus 18), turn off
2000 			 * TX checksum offloading.
2001 			 */
2002 			if (ifr->ifr_mtu >= 8152)
2003 				ifp->if_hwassist = 0;
2004 			else
2005 				ifp->if_hwassist = NGE_CSUM_FEATURES;
2006 		}
2007 		break;
2008 	case SIOCSIFFLAGS:
2009 		if (ifp->if_flags & IFF_UP) {
2010 			if (ifp->if_flags & IFF_RUNNING &&
2011 			    ifp->if_flags & IFF_PROMISC &&
2012 			    !(sc->nge_if_flags & IFF_PROMISC)) {
2013 				NGE_SETBIT(sc, NGE_RXFILT_CTL,
2014 				    NGE_RXFILTCTL_ALLPHYS|
2015 				    NGE_RXFILTCTL_ALLMULTI);
2016 			} else if (ifp->if_flags & IFF_RUNNING &&
2017 			    !(ifp->if_flags & IFF_PROMISC) &&
2018 			    sc->nge_if_flags & IFF_PROMISC) {
2019 				NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2020 				    NGE_RXFILTCTL_ALLPHYS);
2021 				if (!(ifp->if_flags & IFF_ALLMULTI))
2022 					NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2023 					    NGE_RXFILTCTL_ALLMULTI);
2024 			} else {
2025 				ifp->if_flags &= ~IFF_RUNNING;
2026 				nge_init(sc);
2027 			}
2028 		} else {
2029 			if (ifp->if_flags & IFF_RUNNING)
2030 				nge_stop(sc);
2031 		}
2032 		sc->nge_if_flags = ifp->if_flags;
2033 		error = 0;
2034 		break;
2035 	case SIOCADDMULTI:
2036 	case SIOCDELMULTI:
2037 		nge_setmulti(sc);
2038 		error = 0;
2039 		break;
2040 	case SIOCGIFMEDIA:
2041 	case SIOCSIFMEDIA:
2042 		if (sc->nge_tbi) {
2043 			error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
2044 					      command);
2045 		} else {
2046 			mii = device_get_softc(sc->nge_miibus);
2047 			error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
2048 					      command);
2049 		}
2050 		break;
2051 	default:
2052 		error = ether_ioctl(ifp, command, data);
2053 		break;
2054 	}
2055 	return(error);
2056 }
2057 
2058 static void
nge_watchdog(struct ifnet * ifp)2059 nge_watchdog(struct ifnet *ifp)
2060 {
2061 	struct nge_softc *sc = ifp->if_softc;
2062 
2063 	IFNET_STAT_INC(ifp, oerrors, 1);
2064 	kprintf("nge%d: watchdog timeout\n", sc->nge_unit);
2065 
2066 	nge_stop(sc);
2067 	nge_reset(sc);
2068 	ifp->if_flags &= ~IFF_RUNNING;
2069 	nge_init(sc);
2070 
2071 	if (!ifq_is_empty(&ifp->if_snd))
2072 		if_devstart(ifp);
2073 }
2074 
2075 /*
2076  * Stop the adapter and free any mbufs allocated to the
2077  * RX and TX lists.
2078  */
2079 static void
nge_stop(struct nge_softc * sc)2080 nge_stop(struct nge_softc *sc)
2081 {
2082 	struct ifnet *ifp = &sc->arpcom.ac_if;
2083 	struct ifmedia_entry *ifm;
2084 	struct mii_data *mii;
2085 	int i, itmp, mtmp, dtmp;
2086 
2087 	ifp->if_timer = 0;
2088 	if (sc->nge_tbi)
2089 		mii = NULL;
2090 	else
2091 		mii = device_get_softc(sc->nge_miibus);
2092 
2093 	callout_stop(&sc->nge_stat_timer);
2094 	CSR_WRITE_4(sc, NGE_IER, 0);
2095 	CSR_WRITE_4(sc, NGE_IMR, 0);
2096 	NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2097 	DELAY(1000);
2098 	CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2099 	CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2100 
2101 	/*
2102 	 * Isolate/power down the PHY, but leave the media selection
2103 	 * unchanged so that things will be put back to normal when
2104 	 * we bring the interface back up.
2105 	 */
2106 	itmp = ifp->if_flags;
2107 	ifp->if_flags |= IFF_UP;
2108 
2109 	if (sc->nge_tbi)
2110 		ifm = sc->nge_ifmedia.ifm_cur;
2111 	else
2112 		ifm = mii->mii_media.ifm_cur;
2113 
2114 	mtmp = ifm->ifm_media;
2115 	dtmp = ifm->ifm_data;
2116 	ifm->ifm_media = IFM_ETHER|IFM_NONE;
2117 	ifm->ifm_data = MII_MEDIA_NONE;
2118 
2119 	if (!sc->nge_tbi)
2120 		mii_mediachg(mii);
2121 	ifm->ifm_media = mtmp;
2122 	ifm->ifm_data = dtmp;
2123 	ifp->if_flags = itmp;
2124 
2125 	sc->nge_link = 0;
2126 
2127 	/*
2128 	 * Free data in the RX lists.
2129 	 */
2130 	for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2131 		if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2132 			m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2133 			sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2134 		}
2135 	}
2136 	bzero(&sc->nge_ldata->nge_rx_list,
2137 		sizeof(sc->nge_ldata->nge_rx_list));
2138 
2139 	/*
2140 	 * Free the TX list buffers.
2141 	 */
2142 	for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2143 		if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2144 			m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2145 			sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2146 		}
2147 	}
2148 
2149 	bzero(&sc->nge_ldata->nge_tx_list,
2150 		sizeof(sc->nge_ldata->nge_tx_list));
2151 
2152 	ifp->if_flags &= ~IFF_RUNNING;
2153 	ifq_clr_oactive(&ifp->if_snd);
2154 }
2155 
2156 /*
2157  * Stop all chip I/O so that the kernel's probe routines don't
2158  * get confused by errant DMAs when rebooting.
2159  */
2160 static void
nge_shutdown(device_t dev)2161 nge_shutdown(device_t dev)
2162 {
2163 	struct nge_softc *sc = device_get_softc(dev);
2164 	struct ifnet *ifp = &sc->arpcom.ac_if;
2165 
2166 	lwkt_serialize_enter(ifp->if_serializer);
2167 	nge_reset(sc);
2168 	nge_stop(sc);
2169 	lwkt_serialize_exit(ifp->if_serializer);
2170 }
2171 
2172