1 /* $NetBSD: nouveau_abi16.h,v 1.3 2021/12/18 23:45:32 riastradh Exp $ */ 2 3 /* SPDX-License-Identifier: MIT */ 4 #ifndef __NOUVEAU_ABI16_H__ 5 #define __NOUVEAU_ABI16_H__ 6 7 #define ABI16_IOCTL_ARGS \ 8 struct drm_device *dev, void *data, struct drm_file *file_priv 9 10 int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS); 11 int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS); 12 int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS); 13 int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS); 14 int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS); 15 int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS); 16 17 struct nouveau_abi16_ntfy { 18 struct nvif_object object; 19 struct list_head head; 20 struct nvkm_mm_node *node; 21 }; 22 23 struct nouveau_abi16_chan { 24 struct list_head head; 25 struct nouveau_channel *chan; 26 struct list_head notifiers; 27 struct nouveau_bo *ntfy; 28 struct nouveau_vma *ntfy_vma; 29 struct nvkm_mm heap; 30 }; 31 32 struct nouveau_abi16 { 33 struct nvif_device device; 34 struct list_head channels; 35 u64 handles; 36 }; 37 38 struct nouveau_abi16 *nouveau_abi16_get(struct drm_file *); 39 int nouveau_abi16_put(struct nouveau_abi16 *, int); 40 void nouveau_abi16_fini(struct nouveau_abi16 *); 41 s32 nouveau_abi16_swclass(struct nouveau_drm *); 42 int nouveau_abi16_usif(struct drm_file *, void *data, u32 size); 43 44 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 45 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 46 47 struct drm_nouveau_channel_alloc { 48 uint32_t fb_ctxdma_handle; 49 uint32_t tt_ctxdma_handle; 50 51 int channel; 52 uint32_t pushbuf_domains; 53 54 /* Notifier memory */ 55 uint32_t notifier_handle; 56 57 /* DRM-enforced subchannel assignments */ 58 struct { 59 uint32_t handle; 60 uint32_t grclass; 61 } subchan[8]; 62 uint32_t nr_subchan; 63 }; 64 65 struct drm_nouveau_channel_free { 66 int channel; 67 }; 68 69 struct drm_nouveau_grobj_alloc { 70 int channel; 71 uint32_t handle; 72 int class; 73 }; 74 75 struct drm_nouveau_notifierobj_alloc { 76 uint32_t channel; 77 uint32_t handle; 78 uint32_t size; 79 uint32_t offset; 80 }; 81 82 struct drm_nouveau_gpuobj_free { 83 int channel; 84 uint32_t handle; 85 }; 86 87 #define NOUVEAU_GETPARAM_PCI_VENDOR 3 88 #define NOUVEAU_GETPARAM_PCI_DEVICE 4 89 #define NOUVEAU_GETPARAM_BUS_TYPE 5 90 #define NOUVEAU_GETPARAM_FB_SIZE 8 91 #define NOUVEAU_GETPARAM_AGP_SIZE 9 92 #define NOUVEAU_GETPARAM_CHIPSET_ID 11 93 #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 94 #define NOUVEAU_GETPARAM_GRAPH_UNITS 13 95 #define NOUVEAU_GETPARAM_PTIMER_TIME 14 96 #define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 97 #define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16 98 struct drm_nouveau_getparam { 99 uint64_t param; 100 uint64_t value; 101 }; 102 103 struct drm_nouveau_setparam { 104 uint64_t param; 105 uint64_t value; 106 }; 107 108 #define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam) 109 #define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam) 110 #define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc) 111 #define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free) 112 #define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc) 113 #define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc) 114 #define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free) 115 116 #endif 117