1 /*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16
17 #include "qemu/osdep.h"
18
19 #include "hw/arm/boot.h"
20 #include "hw/arm/npcm7xx.h"
21 #include "hw/char/serial.h"
22 #include "hw/loader.h"
23 #include "hw/misc/unimp.h"
24 #include "hw/qdev-clock.h"
25 #include "hw/qdev-properties.h"
26 #include "qapi/error.h"
27 #include "qemu/bswap.h"
28 #include "qemu/units.h"
29 #include "sysemu/sysemu.h"
30 #include "target/arm/cpu-qom.h"
31
32 /*
33 * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
34 * that aren't handled by any device.
35 */
36 #define NPCM7XX_MMIO_BA (0x80000000)
37 #define NPCM7XX_MMIO_SZ (0x7ffd0000)
38
39 /* OTP key storage and fuse strap array */
40 #define NPCM7XX_OTP1_BA (0xf0189000)
41 #define NPCM7XX_OTP2_BA (0xf018a000)
42
43 /* Core system modules. */
44 #define NPCM7XX_L2C_BA (0xf03fc000)
45 #define NPCM7XX_CPUP_BA (0xf03fe000)
46 #define NPCM7XX_GCR_BA (0xf0800000)
47 #define NPCM7XX_CLK_BA (0xf0801000)
48 #define NPCM7XX_MC_BA (0xf0824000)
49 #define NPCM7XX_RNG_BA (0xf000b000)
50
51 /* USB Host modules */
52 #define NPCM7XX_EHCI_BA (0xf0806000)
53 #define NPCM7XX_OHCI_BA (0xf0807000)
54
55 /* ADC Module */
56 #define NPCM7XX_ADC_BA (0xf000c000)
57
58 /* Internal AHB SRAM */
59 #define NPCM7XX_RAM3_BA (0xc0008000)
60 #define NPCM7XX_RAM3_SZ (4 * KiB)
61
62 /* Memory blocks at the end of the address space */
63 #define NPCM7XX_RAM2_BA (0xfffd0000)
64 #define NPCM7XX_RAM2_SZ (128 * KiB)
65 #define NPCM7XX_ROM_BA (0xffff0000)
66 #define NPCM7XX_ROM_SZ (64 * KiB)
67
68 /* SDHCI Modules */
69 #define NPCM7XX_MMC_BA (0xf0842000)
70
71 /* Clock configuration values to be fixed up when bypassing bootloader */
72
73 /* Run PLL1 at 1600 MHz */
74 #define NPCM7XX_PLLCON1_FIXUP_VAL (0x00402101)
75 /* Run the CPU from PLL1 and UART from PLL2 */
76 #define NPCM7XX_CLKSEL_FIXUP_VAL (0x004aaba9)
77
78 /*
79 * Interrupt lines going into the GIC. This does not include internal Cortex-A9
80 * interrupts.
81 */
82 enum NPCM7xxInterrupt {
83 NPCM7XX_ADC_IRQ = 0,
84 NPCM7XX_UART0_IRQ = 2,
85 NPCM7XX_UART1_IRQ,
86 NPCM7XX_UART2_IRQ,
87 NPCM7XX_UART3_IRQ,
88 NPCM7XX_GMAC1_IRQ = 14,
89 NPCM7XX_EMC1RX_IRQ = 15,
90 NPCM7XX_EMC1TX_IRQ,
91 NPCM7XX_GMAC2_IRQ,
92 NPCM7XX_MMC_IRQ = 26,
93 NPCM7XX_PSPI2_IRQ = 28,
94 NPCM7XX_PSPI1_IRQ = 31,
95 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
96 NPCM7XX_TIMER1_IRQ,
97 NPCM7XX_TIMER2_IRQ,
98 NPCM7XX_TIMER3_IRQ,
99 NPCM7XX_TIMER4_IRQ,
100 NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */
101 NPCM7XX_TIMER6_IRQ,
102 NPCM7XX_TIMER7_IRQ,
103 NPCM7XX_TIMER8_IRQ,
104 NPCM7XX_TIMER9_IRQ,
105 NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */
106 NPCM7XX_TIMER11_IRQ,
107 NPCM7XX_TIMER12_IRQ,
108 NPCM7XX_TIMER13_IRQ,
109 NPCM7XX_TIMER14_IRQ,
110 NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
111 NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
112 NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
113 NPCM7XX_EHCI_IRQ = 61,
114 NPCM7XX_OHCI_IRQ = 62,
115 NPCM7XX_SMBUS0_IRQ = 64,
116 NPCM7XX_SMBUS1_IRQ,
117 NPCM7XX_SMBUS2_IRQ,
118 NPCM7XX_SMBUS3_IRQ,
119 NPCM7XX_SMBUS4_IRQ,
120 NPCM7XX_SMBUS5_IRQ,
121 NPCM7XX_SMBUS6_IRQ,
122 NPCM7XX_SMBUS7_IRQ,
123 NPCM7XX_SMBUS8_IRQ,
124 NPCM7XX_SMBUS9_IRQ,
125 NPCM7XX_SMBUS10_IRQ,
126 NPCM7XX_SMBUS11_IRQ,
127 NPCM7XX_SMBUS12_IRQ,
128 NPCM7XX_SMBUS13_IRQ,
129 NPCM7XX_SMBUS14_IRQ,
130 NPCM7XX_SMBUS15_IRQ,
131 NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
132 NPCM7XX_PWM1_IRQ, /* PWM module 1 */
133 NPCM7XX_MFT0_IRQ = 96, /* MFT module 0 */
134 NPCM7XX_MFT1_IRQ, /* MFT module 1 */
135 NPCM7XX_MFT2_IRQ, /* MFT module 2 */
136 NPCM7XX_MFT3_IRQ, /* MFT module 3 */
137 NPCM7XX_MFT4_IRQ, /* MFT module 4 */
138 NPCM7XX_MFT5_IRQ, /* MFT module 5 */
139 NPCM7XX_MFT6_IRQ, /* MFT module 6 */
140 NPCM7XX_MFT7_IRQ, /* MFT module 7 */
141 NPCM7XX_EMC2RX_IRQ = 114,
142 NPCM7XX_EMC2TX_IRQ,
143 NPCM7XX_GPIO0_IRQ = 116,
144 NPCM7XX_GPIO1_IRQ,
145 NPCM7XX_GPIO2_IRQ,
146 NPCM7XX_GPIO3_IRQ,
147 NPCM7XX_GPIO4_IRQ,
148 NPCM7XX_GPIO5_IRQ,
149 NPCM7XX_GPIO6_IRQ,
150 NPCM7XX_GPIO7_IRQ,
151 };
152
153 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
154 #define NPCM7XX_NUM_IRQ (160)
155
156 /* Register base address for each Timer Module */
157 static const hwaddr npcm7xx_tim_addr[] = {
158 0xf0008000,
159 0xf0009000,
160 0xf000a000,
161 };
162
163 /* Register base address for each 16550 UART */
164 static const hwaddr npcm7xx_uart_addr[] = {
165 0xf0001000,
166 0xf0002000,
167 0xf0003000,
168 0xf0004000,
169 };
170
171 /* Direct memory-mapped access to SPI0 CS0-1. */
172 static const hwaddr npcm7xx_fiu0_flash_addr[] = {
173 0x80000000, /* CS0 */
174 0x88000000, /* CS1 */
175 };
176
177 /* Direct memory-mapped access to SPI3 CS0-3. */
178 static const hwaddr npcm7xx_fiu3_flash_addr[] = {
179 0xa0000000, /* CS0 */
180 0xa8000000, /* CS1 */
181 0xb0000000, /* CS2 */
182 0xb8000000, /* CS3 */
183 };
184
185 /* Register base address for each PWM Module */
186 static const hwaddr npcm7xx_pwm_addr[] = {
187 0xf0103000,
188 0xf0104000,
189 };
190
191 /* Register base address for each MFT Module */
192 static const hwaddr npcm7xx_mft_addr[] = {
193 0xf0180000,
194 0xf0181000,
195 0xf0182000,
196 0xf0183000,
197 0xf0184000,
198 0xf0185000,
199 0xf0186000,
200 0xf0187000,
201 };
202
203 /* Direct memory-mapped access to each SMBus Module. */
204 static const hwaddr npcm7xx_smbus_addr[] = {
205 0xf0080000,
206 0xf0081000,
207 0xf0082000,
208 0xf0083000,
209 0xf0084000,
210 0xf0085000,
211 0xf0086000,
212 0xf0087000,
213 0xf0088000,
214 0xf0089000,
215 0xf008a000,
216 0xf008b000,
217 0xf008c000,
218 0xf008d000,
219 0xf008e000,
220 0xf008f000,
221 };
222
223 /* Register base address for each EMC Module */
224 static const hwaddr npcm7xx_emc_addr[] = {
225 0xf0825000,
226 0xf0826000,
227 };
228
229 /* Register base address for each PSPI Module */
230 static const hwaddr npcm7xx_pspi_addr[] = {
231 0xf0200000,
232 0xf0201000,
233 };
234
235 /* Register base address for each GMAC Module */
236 static const hwaddr npcm7xx_gmac_addr[] = {
237 0xf0802000,
238 0xf0804000,
239 };
240
241 static const struct {
242 hwaddr regs_addr;
243 uint32_t unconnected_pins;
244 uint32_t reset_pu;
245 uint32_t reset_pd;
246 uint32_t reset_osrc;
247 uint32_t reset_odsc;
248 } npcm7xx_gpio[] = {
249 {
250 .regs_addr = 0xf0010000,
251 .reset_pu = 0xff03ffff,
252 .reset_pd = 0x00fc0000,
253 }, {
254 .regs_addr = 0xf0011000,
255 .unconnected_pins = 0x0000001e,
256 .reset_pu = 0xfefffe07,
257 .reset_pd = 0x010001e0,
258 }, {
259 .regs_addr = 0xf0012000,
260 .reset_pu = 0x780fffff,
261 .reset_pd = 0x07f00000,
262 .reset_odsc = 0x00700000,
263 }, {
264 .regs_addr = 0xf0013000,
265 .reset_pu = 0x00fc0000,
266 .reset_pd = 0xff000000,
267 }, {
268 .regs_addr = 0xf0014000,
269 .reset_pu = 0xffffffff,
270 }, {
271 .regs_addr = 0xf0015000,
272 .reset_pu = 0xbf83f801,
273 .reset_pd = 0x007c0000,
274 .reset_osrc = 0x000000f1,
275 .reset_odsc = 0x3f9f80f1,
276 }, {
277 .regs_addr = 0xf0016000,
278 .reset_pu = 0xfc00f801,
279 .reset_pd = 0x000007fe,
280 .reset_odsc = 0x00000800,
281 }, {
282 .regs_addr = 0xf0017000,
283 .unconnected_pins = 0xffffff00,
284 .reset_pu = 0x0000007f,
285 .reset_osrc = 0x0000007f,
286 .reset_odsc = 0x0000007f,
287 },
288 };
289
290 static const struct {
291 const char *name;
292 hwaddr regs_addr;
293 int cs_count;
294 const hwaddr *flash_addr;
295 } npcm7xx_fiu[] = {
296 {
297 .name = "fiu0",
298 .regs_addr = 0xfb000000,
299 .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr),
300 .flash_addr = npcm7xx_fiu0_flash_addr,
301 }, {
302 .name = "fiu3",
303 .regs_addr = 0xc0000000,
304 .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr),
305 .flash_addr = npcm7xx_fiu3_flash_addr,
306 },
307 };
308
npcm7xx_write_board_setup(ARMCPU * cpu,const struct arm_boot_info * info)309 static void npcm7xx_write_board_setup(ARMCPU *cpu,
310 const struct arm_boot_info *info)
311 {
312 uint32_t board_setup[] = {
313 0xe59f0010, /* ldr r0, clk_base_addr */
314 0xe59f1010, /* ldr r1, pllcon1_value */
315 0xe5801010, /* str r1, [r0, #16] */
316 0xe59f100c, /* ldr r1, clksel_value */
317 0xe5801004, /* str r1, [r0, #4] */
318 0xe12fff1e, /* bx lr */
319 NPCM7XX_CLK_BA,
320 NPCM7XX_PLLCON1_FIXUP_VAL,
321 NPCM7XX_CLKSEL_FIXUP_VAL,
322 };
323 int i;
324
325 for (i = 0; i < ARRAY_SIZE(board_setup); i++) {
326 board_setup[i] = tswap32(board_setup[i]);
327 }
328 rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup),
329 info->board_setup_addr);
330 }
331
npcm7xx_write_secondary_boot(ARMCPU * cpu,const struct arm_boot_info * info)332 static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
333 const struct arm_boot_info *info)
334 {
335 /*
336 * The default smpboot stub halts the secondary CPU with a 'wfi'
337 * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel
338 * does not send an IPI to wake it up, so the second CPU fails to boot. So
339 * we need to provide our own smpboot stub that can not use 'wfi', it has
340 * to spin the secondary CPU until the first CPU writes to the SCRPAD reg.
341 */
342 uint32_t smpboot[] = {
343 0xe59f2018, /* ldr r2, bootreg_addr */
344 0xe3a00000, /* mov r0, #0 */
345 0xe5820000, /* str r0, [r2] */
346 0xe320f002, /* wfe */
347 0xe5921000, /* ldr r1, [r2] */
348 0xe1110001, /* tst r1, r1 */
349 0x0afffffb, /* beq <wfe> */
350 0xe12fff11, /* bx r1 */
351 NPCM7XX_SMP_BOOTREG_ADDR,
352 };
353 int i;
354
355 for (i = 0; i < ARRAY_SIZE(smpboot); i++) {
356 smpboot[i] = tswap32(smpboot[i]);
357 }
358
359 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
360 NPCM7XX_SMP_LOADER_START);
361 }
362
363 static struct arm_boot_info npcm7xx_binfo = {
364 .loader_start = NPCM7XX_LOADER_START,
365 .smp_loader_start = NPCM7XX_SMP_LOADER_START,
366 .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR,
367 .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR,
368 .write_secondary_boot = npcm7xx_write_secondary_boot,
369 .board_id = -1,
370 .board_setup_addr = NPCM7XX_BOARD_SETUP_ADDR,
371 .write_board_setup = npcm7xx_write_board_setup,
372 };
373
npcm7xx_load_kernel(MachineState * machine,NPCM7xxState * soc)374 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
375 {
376 npcm7xx_binfo.ram_size = machine->ram_size;
377
378 arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo);
379 }
380
npcm7xx_init_fuses(NPCM7xxState * s)381 static void npcm7xx_init_fuses(NPCM7xxState *s)
382 {
383 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
384 uint32_t value;
385
386 /*
387 * The initial mask of disabled modules indicates the chip derivative (e.g.
388 * NPCM750 or NPCM730).
389 */
390 value = cpu_to_le32(nc->disabled_modules);
391 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
392 sizeof(value));
393 }
394
npcm7xx_write_adc_calibration(NPCM7xxState * s)395 static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
396 {
397 /* Both ADC and the fuse array must have realized. */
398 QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
399 npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
400 NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
401 }
402
npcm7xx_irq(NPCM7xxState * s,int n)403 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
404 {
405 return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
406 }
407
npcm7xx_init(Object * obj)408 static void npcm7xx_init(Object *obj)
409 {
410 NPCM7xxState *s = NPCM7XX(obj);
411 int i;
412
413 for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) {
414 object_initialize_child(obj, "cpu[*]", &s->cpu[i],
415 ARM_CPU_TYPE_NAME("cortex-a9"));
416 }
417
418 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
419 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR);
420 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
421 "power-on-straps");
422 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
423 object_initialize_child(obj, "otp1", &s->key_storage,
424 TYPE_NPCM7XX_KEY_STORAGE);
425 object_initialize_child(obj, "otp2", &s->fuse_array,
426 TYPE_NPCM7XX_FUSE_ARRAY);
427 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
428 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
429 object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
430
431 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
432 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
433 }
434
435 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
436 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO);
437 }
438
439 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) {
440 object_initialize_child(obj, "smbus[*]", &s->smbus[i],
441 TYPE_NPCM7XX_SMBUS);
442 }
443
444 object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI);
445 object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI);
446
447 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
448 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
449 object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
450 TYPE_NPCM7XX_FIU);
451 }
452
453 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
454 object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
455 }
456
457 for (i = 0; i < ARRAY_SIZE(s->mft); i++) {
458 object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MFT);
459 }
460
461 for (i = 0; i < ARRAY_SIZE(s->emc); i++) {
462 object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
463 }
464
465 for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
466 object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
467 }
468
469 for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
470 object_initialize_child(obj, "gmac[*]", &s->gmac[i], TYPE_NPCM_GMAC);
471 }
472
473 object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
474 }
475
npcm7xx_realize(DeviceState * dev,Error ** errp)476 static void npcm7xx_realize(DeviceState *dev, Error **errp)
477 {
478 NPCM7xxState *s = NPCM7XX(dev);
479 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
480 int i;
481
482 if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) {
483 error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64
484 " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB);
485 return;
486 }
487
488 /* CPUs */
489 for (i = 0; i < nc->num_cpus; i++) {
490 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
491 arm_build_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
492 &error_abort);
493 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
494 NPCM7XX_GIC_CPU_IF_ADDR, &error_abort);
495 object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true,
496 &error_abort);
497
498 /* Disable security extensions. */
499 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false,
500 &error_abort);
501
502 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
503 return;
504 }
505 }
506
507 /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */
508 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus,
509 &error_abort);
510 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ,
511 &error_abort);
512 sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort);
513 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA);
514
515 for (i = 0; i < nc->num_cpus; i++) {
516 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
517 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
518 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus,
519 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
520 }
521
522 /* L2 cache controller */
523 sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL);
524
525 /* System Global Control Registers (GCR). Can fail due to user input. */
526 object_property_set_int(OBJECT(&s->gcr), "disabled-modules",
527 nc->disabled_modules, &error_abort);
528 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram));
529 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
530 return;
531 }
532 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA);
533
534 /* Clock Control Registers (CLK). Cannot fail. */
535 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort);
536 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
537
538 /* OTP key storage and fuse strap array. Cannot fail. */
539 sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort);
540 sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA);
541 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort);
542 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
543 npcm7xx_init_fuses(s);
544
545 /* Fake Memory Controller (MC). Cannot fail. */
546 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
547 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
548
549 /* ADC Modules. Cannot fail. */
550 qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
551 DEVICE(&s->clk), "adc-clock"));
552 sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
553 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
554 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
555 npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
556 npcm7xx_write_adc_calibration(s);
557
558 /* Timer Modules (TIM). Cannot fail. */
559 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
560 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
561 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]);
562 int first_irq;
563 int j;
564
565 /* Connect the timer clock. */
566 qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
567 DEVICE(&s->clk), "timer-clock"));
568
569 sysbus_realize(sbd, &error_abort);
570 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
571
572 first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL;
573 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) {
574 qemu_irq irq = npcm7xx_irq(s, first_irq + j);
575 sysbus_connect_irq(sbd, j, irq);
576 }
577
578 /* IRQ for watchdogs */
579 sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL,
580 npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i));
581 /* GPIO that connects clk module with watchdog */
582 qdev_connect_gpio_out_named(DEVICE(&s->tim[i]),
583 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0,
584 qdev_get_gpio_in_named(DEVICE(&s->clk),
585 NPCM7XX_WATCHDOG_RESET_GPIO_IN, i));
586 }
587
588 /* UART0..3 (16550 compatible) */
589 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) {
590 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2,
591 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200,
592 serial_hd(i), DEVICE_LITTLE_ENDIAN);
593 }
594
595 /* Random Number Generator. Cannot fail. */
596 sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort);
597 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA);
598
599 /* GPIO modules. Cannot fail. */
600 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gpio) != ARRAY_SIZE(s->gpio));
601 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
602 Object *obj = OBJECT(&s->gpio[i]);
603
604 object_property_set_uint(obj, "reset-pullup",
605 npcm7xx_gpio[i].reset_pu, &error_abort);
606 object_property_set_uint(obj, "reset-pulldown",
607 npcm7xx_gpio[i].reset_pd, &error_abort);
608 object_property_set_uint(obj, "reset-osrc",
609 npcm7xx_gpio[i].reset_osrc, &error_abort);
610 object_property_set_uint(obj, "reset-odsc",
611 npcm7xx_gpio[i].reset_odsc, &error_abort);
612 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
613 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_gpio[i].regs_addr);
614 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
615 npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i));
616 }
617
618 /* SMBus modules. Cannot fail. */
619 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_smbus_addr) != ARRAY_SIZE(s->smbus));
620 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) {
621 Object *obj = OBJECT(&s->smbus[i]);
622
623 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
624 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_smbus_addr[i]);
625 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
626 npcm7xx_irq(s, NPCM7XX_SMBUS0_IRQ + i));
627 }
628
629 /* USB Host */
630 object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true,
631 &error_abort);
632 sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort);
633 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA);
634 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0,
635 npcm7xx_irq(s, NPCM7XX_EHCI_IRQ));
636
637 object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0",
638 &error_abort);
639 object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort);
640 sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort);
641 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA);
642 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
643 npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
644
645 /* PWM Modules. Cannot fail. */
646 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
647 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
648 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
649
650 qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
651 DEVICE(&s->clk), "apb3-clock"));
652 sysbus_realize(sbd, &error_abort);
653 sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
654 sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
655 }
656
657 /* MFT Modules. Cannot fail. */
658 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_mft_addr) != ARRAY_SIZE(s->mft));
659 for (i = 0; i < ARRAY_SIZE(s->mft); i++) {
660 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->mft[i]);
661
662 qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in",
663 qdev_get_clock_out(DEVICE(&s->clk),
664 "apb4-clock"));
665 sysbus_realize(sbd, &error_abort);
666 sysbus_mmio_map(sbd, 0, npcm7xx_mft_addr[i]);
667 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, NPCM7XX_MFT0_IRQ + i));
668 }
669
670 /*
671 * EMC Modules. Cannot fail.
672 * Use the available NIC configurations in order, allowing 'emc0' and
673 * 'emc1' to by used as aliases for the model= parameter to override.
674 *
675 * This works around the inability to specify the netdev property for the
676 * emc device: it's not pluggable and thus the -device option can't be
677 * used.
678 */
679 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_emc_addr) != ARRAY_SIZE(s->emc));
680 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->emc) != 2);
681 for (i = 0; i < ARRAY_SIZE(s->emc); i++) {
682 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->emc[i]);
683 char alias[6];
684
685 s->emc[i].emc_num = i;
686 snprintf(alias, sizeof(alias), "emc%u", i);
687 qemu_configure_nic_device(DEVICE(sbd), true, alias);
688
689 /*
690 * The device exists regardless of whether it's connected to a QEMU
691 * netdev backend. So always instantiate it even if there is no
692 * backend.
693 */
694 sysbus_realize(sbd, &error_abort);
695 sysbus_mmio_map(sbd, 0, npcm7xx_emc_addr[i]);
696 int tx_irq = i == 0 ? NPCM7XX_EMC1TX_IRQ : NPCM7XX_EMC2TX_IRQ;
697 int rx_irq = i == 0 ? NPCM7XX_EMC1RX_IRQ : NPCM7XX_EMC2RX_IRQ;
698 /*
699 * N.B. The values for the second argument sysbus_connect_irq are
700 * chosen to match the registration order in npcm7xx_emc_realize.
701 */
702 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, tx_irq));
703 sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq));
704 }
705
706 /*
707 * GMAC Modules. Cannot fail.
708 */
709 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gmac_addr) != ARRAY_SIZE(s->gmac));
710 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->gmac) != 2);
711 for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
712 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]);
713
714 qemu_configure_nic_device(DEVICE(sbd), false, NULL);
715 /*
716 * The device exists regardless of whether it's connected to a QEMU
717 * netdev backend. So always instantiate it even if there is no
718 * backend.
719 */
720 sysbus_realize(sbd, &error_abort);
721 sysbus_mmio_map(sbd, 0, npcm7xx_gmac_addr[i]);
722 int irq = i == 0 ? NPCM7XX_GMAC1_IRQ : NPCM7XX_GMAC2_IRQ;
723 /*
724 * N.B. The values for the second argument sysbus_connect_irq are
725 * chosen to match the registration order in npcm7xx_emc_realize.
726 */
727 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq));
728 }
729
730 /*
731 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
732 * specified, but this is a programming error.
733 */
734 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
735 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
736 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]);
737 int j;
738
739 object_property_set_int(OBJECT(sbd), "cs-count",
740 npcm7xx_fiu[i].cs_count, &error_abort);
741 sysbus_realize(sbd, &error_abort);
742
743 sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr);
744 for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) {
745 sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]);
746 }
747 }
748
749 /* RAM2 (SRAM) */
750 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
751 NPCM7XX_RAM2_SZ, &error_abort);
752 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram);
753
754 /* RAM3 (SRAM) */
755 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3",
756 NPCM7XX_RAM3_SZ, &error_abort);
757 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3);
758
759 /* Internal ROM */
760 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ,
761 &error_abort);
762 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom);
763
764 /* SDHCI */
765 sysbus_realize(SYS_BUS_DEVICE(&s->mmc), &error_abort);
766 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc), 0, NPCM7XX_MMC_BA);
767 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
768 npcm7xx_irq(s, NPCM7XX_MMC_IRQ));
769
770 /* PSPI */
771 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi));
772 for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
773 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]);
774 int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ;
775
776 sysbus_realize(sbd, &error_abort);
777 sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]);
778 sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq));
779 }
780
781 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB);
782 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
783 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
784 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
785 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
786 create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB);
787 create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
788 create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
789 create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
790 create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB);
791 create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB);
792 create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB);
793 create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB);
794 create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB);
795 create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB);
796 create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB);
797 create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB);
798 create_unimplemented_device("npcm7xx.usbd[3]", 0xf0833000, 4 * KiB);
799 create_unimplemented_device("npcm7xx.usbd[4]", 0xf0834000, 4 * KiB);
800 create_unimplemented_device("npcm7xx.usbd[5]", 0xf0835000, 4 * KiB);
801 create_unimplemented_device("npcm7xx.usbd[6]", 0xf0836000, 4 * KiB);
802 create_unimplemented_device("npcm7xx.usbd[7]", 0xf0837000, 4 * KiB);
803 create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * KiB);
804 create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * KiB);
805 create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * KiB);
806 create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * KiB);
807 create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * KiB);
808 create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * KiB);
809 create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * KiB);
810 create_unimplemented_device("npcm7xx.secacc", 0xf085b000, 4 * KiB);
811 create_unimplemented_device("npcm7xx.spixcs0", 0xf8000000, 16 * MiB);
812 create_unimplemented_device("npcm7xx.spixcs1", 0xf9000000, 16 * MiB);
813 create_unimplemented_device("npcm7xx.spix", 0xfb001000, 4 * KiB);
814 }
815
816 static Property npcm7xx_properties[] = {
817 DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION,
818 MemoryRegion *),
819 DEFINE_PROP_END_OF_LIST(),
820 };
821
npcm7xx_class_init(ObjectClass * oc,void * data)822 static void npcm7xx_class_init(ObjectClass *oc, void *data)
823 {
824 DeviceClass *dc = DEVICE_CLASS(oc);
825
826 dc->realize = npcm7xx_realize;
827 dc->user_creatable = false;
828 device_class_set_props(dc, npcm7xx_properties);
829 }
830
npcm730_class_init(ObjectClass * oc,void * data)831 static void npcm730_class_init(ObjectClass *oc, void *data)
832 {
833 NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
834
835 /* NPCM730 is optimized for data center use, so no graphics, etc. */
836 nc->disabled_modules = 0x00300395;
837 nc->num_cpus = 2;
838 }
839
npcm750_class_init(ObjectClass * oc,void * data)840 static void npcm750_class_init(ObjectClass *oc, void *data)
841 {
842 NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
843
844 /* NPCM750 has 2 cores and a full set of peripherals */
845 nc->disabled_modules = 0x00000000;
846 nc->num_cpus = 2;
847 }
848
849 static const TypeInfo npcm7xx_soc_types[] = {
850 {
851 .name = TYPE_NPCM7XX,
852 .parent = TYPE_DEVICE,
853 .instance_size = sizeof(NPCM7xxState),
854 .instance_init = npcm7xx_init,
855 .class_size = sizeof(NPCM7xxClass),
856 .class_init = npcm7xx_class_init,
857 .abstract = true,
858 }, {
859 .name = TYPE_NPCM730,
860 .parent = TYPE_NPCM7XX,
861 .class_init = npcm730_class_init,
862 }, {
863 .name = TYPE_NPCM750,
864 .parent = TYPE_NPCM7XX,
865 .class_init = npcm750_class_init,
866 },
867 };
868
869 DEFINE_TYPES(npcm7xx_soc_types);
870