1 /*- 2 * Copyright (c) 1986 MICOM-Interlan, Inc., Boxborough Mass 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * %sccs.include.redist.c% 7 * 8 * @(#)npreg.h 7.4 (Berkeley) 05/09/91 9 */ 10 11 /* 12 * Merged header file for MICOM-Interlan NP100. 13 */ 14 15 /* 16 * np100.h version 1.3 17 * 18 * This version retrieved: 8/18/86 @ 18:58:44 19 * This delta created: 8/18/86 @ 18:27:32 20 */ 21 /* 22 * Typedefs for the VAX 23 */ 24 25 typedef short sign16; /* 16 bit signed value */ 26 typedef unsigned short unsign16; /* 16 bit unsigned value */ 27 typedef unsigned unsign32; /* 32 bit unsigned value */ 28 typedef long paddr_t; /* Physical addresses */ 29 30 31 /* 32 * Tunables 33 */ 34 35 36 #define NUMCQE 40 /* Number of CQE's per board */ 37 38 /* Host configuration word in Status Block */ 39 40 /* 41 * To disable the lock/unlock internal function calls clear the 0x8000 42 * bit in the host configuration word (HOSTCONF) 43 */ 44 45 #define HOSTCONF 0x0109 /* See above */ 46 #define LOWBYTE 1 47 #define HIGHBYTE 0 48 #define BUFFMAPPED 0 49 50 /* 51 * Memory mapping definintions for PM68DUAL hardware. 52 */ 53 54 #ifdef PM68DUAL 55 #define PISHMEM 0x200000 56 #define PISHMEMSIZE 2 57 #define PIOFF 0x8000 /* change this to unique mem add. */ 58 #define PIWINDOW MBUSBUFR + PIOFF 59 #define WINDOWSIZE 2 60 #endif 61 #define NPMAXXFR 32768 /* Maximum number of bytes / read */ 62 63 /* 64 * Define the protocols supported by the NP Driver. 65 */ 66 67 #define NONE 0x00 /* No protocols active for a process */ 68 #define NPMAINT 0x01 /* Maintenance protocol, superusers only */ 69 #define NPNTS 0x02 /* NTS Terminal Server */ 70 #define NPIDP 0x04 /* Direct Datalink Access */ 71 #define NPDLA 0x04 /* Direct Datalink Access */ 72 #define NPXNS 0x06 /* Xerox NS ITP */ 73 #define NPTCP 0x08 /* TCP/IP */ 74 #define NPISO 0x0A /* ISO */ 75 #define NPCLCONN 0xFF /* Closed connection, i.e. no protocol */ 76 77 /* 78 * Convert the protocol to a value used in the Device Protocol Mask field 79 * of the Shared Memory Status Block. 80 */ 81 82 #define PROTOMASK(x) ( 1 << (x) ) 83 84 /* 85 * Special requests handled by the NP Driver 86 */ 87 88 #define OS_STP 03400 /* Shut down connection on I Board */ 89 #define NPSTOP 3 /* Conversion from above (OS_STP) */ 90 #define NPCHNGP 50 /* Change the protocol on a connection */ 91 #define NPCHNGB 51 /* Change the Board number */ 92 93 /* 94 * Miscellaneous 95 */ 96 97 #define ON 0x8000 /* Used for Command Q's scan and change flag */ 98 #define UBADDRMASK 0x3FFFF /* 18 bit UNIBUS address */ 99 #define INTMASK 0xFFFFFFFC /* Used for address validation */ 100 #define CMDMASK 0xFFFF /* Mask ioctl cmd field (see ioctl.h) */ 101 #define NPPSADDR 0x324 /* Pointer to addr of on-board panic string */ 102 #define PANLEN 133 /* length of the panic buffer */ 103 104 /* 105 * Map function code from user to I-Board format 106 */ 107 108 #define FUNCTMAP(x) (((x) << 6) | 077) /* Maps user function to NP funcs */ 109 110 /* 111 * Round up to a 16 byte boundary 112 */ 113 114 #define ROUND16(x) (((x) + 15) & (~0x0F)) /* Round to 16 byte boundary */ 115 #define ADDR24 1 /* Used by iomalloc() to specify 24 bit address */ 116 117 #define NPERRSHIFT 8 /* Used in function ReqDone() */ 118 #define NPOK 0 119 120 #define LOWORD(X) (((ushort *)&(X))[0]) 121 #define HIWORD(X) (((ushort *)&(X))[1]) 122 123 /* Everyday flag settings */ 124 125 #define NPSET 1 126 #define NPCLEAR 0 127 128 /* 129 * Command Queue Elements are the primary data structure for passing data 130 * between the driver and the device. 131 */ 132 133 struct CQE { 134 135 struct npreq *cqe_reqid;/* Address of asssociated npreq */ 136 union { 137 unsign32 cqe_Famid; /* Family ID (Process ID) - wn */ 138 unsign16 cqe_PrtSig[2]; /* port and signal - tn */ 139 } u1; 140 #define cqe_famid u1.cqe_Famid 141 #define cqe_port u1.cqe_PrtSig[0] 142 #define cqe_signal u1.cqe_PrtSig[1] 143 unsign16 cqe_func; /* I/O function to be performed */ 144 #ifdef mc68000 145 char cqe_prot; /* Protocol type for I/O request */ 146 char cqe_lenrpb; /* Length of the RPB in bytes */ 147 #else 148 char cqe_lenrpb; /* Length of the RPB in bytes */ 149 char cqe_prot; /* Protocol type for I/O request */ 150 #endif 151 union { 152 unsign16 cqe_ustS[2]; /* Protocol status return */ 153 unsign32 cqe_ustL; /* Protocol status return */ 154 } u2; 155 #define cqe_ust0 u2.cqe_ustS[0] 156 #define cqe_ust1 u2.cqe_ustS[1] 157 #define cqe_usts u2.cqe_ustL 158 unsign16 cqe_devrsv; /* Reserved for use by device only! */ 159 #ifdef mc68000 160 char cqe_char; /* CQE characteristics */ 161 char cqe_sts; /* Status return from device to user */ 162 char cqe_wind; /* Buffer mapping window size (page units) */ 163 char cqe_nbuf; /* Number of data buffers for I/O */ 164 #else 165 char cqe_sts; /* Status return from device to user */ 166 char cqe_char; /* CQE characteristics */ 167 char cqe_nbuf; /* Number of data buffers for I/O */ 168 char cqe_wind; /* Buffer mapping window size (page units) */ 169 #endif 170 unsign16 cqe_bcnt; /* Total number of bytes in the data buffer */ 171 union { 172 unsign16 cqe_Unused; /* Unused */ 173 struct { 174 char cqe_Maxbcnt; /* Maximum size of buffer */ 175 char cqe_Bflags; /* Used by the SPI */ 176 } s; 177 } u3; 178 #define cqe_unused u3.cqe_Unused 179 #define cqe_maxbcnt u3.s.cqe_Maxbcnt 180 #define cqe_bflags u3.s.cqe_Bflags 181 unsign16 cqe_dma[2]; /* Address of the MULTIBUS data buffer */ 182 unsign16 rpb1; /* Word 1 of protocol parameters */ 183 unsign16 rpb2; /* Word 2 of protocol parameters */ 184 unsign16 rpb3; /* Word 3 of protocol parameters */ 185 unsign16 rpb4; /* Word 4 of protocol parameters */ 186 unsign16 rpb5; /* Word 5 of protocol parameters */ 187 unsign16 rpb6; /* Word 6 of protocol parameters */ 188 unsign16 rpb7; /* Word 7 of protocol parameters */ 189 unsign16 rpb8; /* Word 8 of protocol parameters */ 190 unsign16 rpb9; /* Word 9 of protocol parameters */ 191 unsign16 rpb10; /* Word 10 of protocol parameters */ 192 unsign16 rpb11; /* Word 11 of protocol parameters */ 193 unsign16 rpb12; /* Word 12 of protocol parameters */ 194 195 }; 196 197 /* 198 * NP Driver Request structure contains information about a request 199 * maintained solely by the driver. One per CQE, plus a header. 200 */ 201 202 struct npreq { 203 204 struct npreq *forw; /* Forward pointer for active list */ 205 struct npreq *back; /* Backward pointer for active list */ 206 struct npreq *free; /* Next member on free list */ 207 struct CQE *element; /* CQE associated with this request */ 208 int flags; /* Always useful */ 209 int reqcnt; /* Request count for reqtab */ 210 int bufoffset; /* Offset into buffer for turns */ 211 int bytecnt; /* Number of bytes to transfer */ 212 caddr_t virtmem; /* Virtual address of buffer */ 213 int mapbase; /* Address of the mapping register */ 214 int mapsize; /* Size of mapped area */ 215 caddr_t bufaddr; /* Address of the user buffer */ 216 struct buf buf; /* Buf structure needed for mem. mgmt */ 217 struct proc *procp; /* Pointer to process of requestor */ 218 caddr_t user; /* Structure passed by user from itpuser.h */ 219 int (*intr)(); /* Ptr to routine to call at interrupt time */ 220 int int_param; /* Paramater to be used by above routine */ 221 }; 222 223 /* 224 * Npmaster structure, one per device, is used for boardwise centralization 225 * of relevant information including queues, I/O addresses and request pools. 226 */ 227 228 struct npmaster { 229 230 struct npmaster *next; /* Linked list of these, NULL terminator */ 231 struct npspace *shmemp; /* Shared memory address (driver <-> device) */ 232 struct uba_device *devp; /* UBA Device for this unit */ 233 struct NPREG *iobase; /* I/O base address for this board */ 234 struct npreq *reqtab; /* Header for pool of CQE requests */ 235 int iomapbase; /* Base index of I/O map reg's allocated */ 236 int flags; /* State of the Board */ 237 int unit; /* Unit number of this device */ 238 int vector; /* Interrupt vector for this unit */ 239 }; 240 241 struct NPREG { 242 unsign16 CSR0; /* Control Status Register 0 */ 243 unsign16 CSR1; /* Control Status Register 1 */ 244 unsign16 CSR2; /* Control Status Register 2 */ 245 unsign16 CSR3; /* Control Status Register 3 */ 246 247 }; 248 249 /* 250 * The following structures are used for communicating with the 251 * Intelligent Board and are located in Shared Memory. 252 */ 253 254 /* 255 * Status Block 256 */ 257 258 struct NpStat{ 259 260 unsign16 sb_drw; /* Device Request Word */ 261 unsign16 sb_hcw; /* Host Configuration Word */ 262 unsign16 sb_dcw; /* Device Configuration Word */ 263 unsign16 sb_dpm; /* Device Protocol Mask */ 264 unsign16 sb_dcq; /* Offset to Device CQ */ 265 unsign16 sb_hcq; /* Offset to Host CQ */ 266 }; 267 268 /* 269 * Command Queue, two per device. One is owned by the driver and the other 270 * is owned by the device. 271 */ 272 273 struct CmdQue { 274 275 unsign16 scanflag; /* Scan Flag, MSB set if being scanned */ 276 unsign16 chngflag; /* Change Flag, MSB set by initiator */ 277 unsign16 cq_wrap; /* Offset to last CQE entry +2 */ 278 unsign16 cq_add; /* Offset to add a CQE to the queue */ 279 unsign16 cq_rem; /* Offset to remove a CQE from the queue */ 280 unsign16 cq_cqe[NUMCQE]; /* Command Queue Element Offsets */ 281 }; 282 283 /* 284 * Structure of the shared memory area per board. Declared this way to avoid 285 * compiler word alignment vagaries when computing offsets. 286 */ 287 288 struct npspace { 289 290 struct NpStat statblock; /* Status Block */ 291 struct CmdQue devcq; /* Device's Command Queue */ 292 struct CmdQue hostcq; /* Host's Command Queue */ 293 struct CQE elements[NUMCQE]; /* Shared Command Queue Elements */ 294 unsign16 filler[8]; /* Here for 16 byte alignment */ 295 }; 296 297 /* 298 * Structure of array of base addresses of I-Board controllers 299 * (See global data definitions in np.c) 300 */ 301 302 struct npbase { 303 caddr_t baseaddr; 304 }; 305 306 /* State of the NP Driver as kept in NpState */ 307 308 #define ICPAVAIL 0x01 /* ICP is waiting for a request */ 309 310 /* Tells ICP Process that there are no more requests for this board */ 311 312 #define BRDDONE 1 313 314 /* Flags used by the driver (npreq structure) to monitor status of requests */ 315 316 #define REQDONE 0x01 /* Request completed */ 317 #define IOIFC 0x02 /* Internal Function Code Request */ 318 #define IOERR 0x04 /* Error on Request */ 319 #define NPPEND 0x08 /* Unused at this time */ 320 #define IOABORT 0x10 /* Request aborted by ICP */ 321 #define KERNREQ 0x20 /* Request was from the kernel */ 322 #define WANTREQ 0x40 /* Process is waiting for a npreq structure */ 323 #define NPUIO 0x80 /* Process doing physio */ 324 #define REQALOC 0x100 /* Request has been allocated */ 325 #define REQUSE 0x200 /* Request is in request queue */ 326 327 /* Service Request Commands from the Intelligent Board */ 328 329 #define NOREQ 0x00 /* No service requested */ 330 #define NPLOAD 0x01 /* Dump request */ 331 #define NPDUMP 0x02 /* Load request */ 332 #define NPPANIC 0x100 /* Panic request */ 333 334 /* Definitions of Status returned from the I-Board */ 335 336 #define NPDONE 0x01 /* Normal completion */ 337 #define NPIFC 0x00 /* Internal Function Code request */ 338 #define NPPERR 0x80 /* Protocol error */ 339 #define NPMERR 0x82 /* Memory allocation failure on I-Board */ 340 341 /* Definitions of IFC type requests from I-Board */ 342 343 #define NPLOCK 0x64 /* Lock the process's data area */ 344 #define NPUNLOCK 0xA4 /* Unlock the process */ 345 #define NPREMAP 0x124 /* Window turn */ 346 347 /* Definition of flags for the Npmaster structure */ 348 349 #define CSRPEND 0x01 /* CSR0 command pending */ 350 #define PANICREQ 0x02 /* Panic request */ 351 #define DUMPREQ 0x04 /* Dump request */ 352 #define LOADREQ 0x08 /* Load request */ 353 #define BOARDREQ 0x10 /* Any request by the board */ 354 #define BADBOARD 0x20 /* Board disabled */ 355 #define AVAILABLE 0x40 /* Board available */ 356 #define BRDRESET 0x80 /* Board is being reset */ 357 #define PANIC1 0x100 /* Driver wants panic address */ 358 #define PANIC2 0x200 /* Driver wants panic string */ 359 #define PANIC3 0x400 /* Clear first byte of panic string */ 360 #define LSTCMD 0x800 /* Clear last command during NPIO */ 361 #define SCANNING 0x1000 /* We are scanning for cqe's */ 362 363 /* 364 * Debugging Constants 365 */ 366 367 #define DEBENTRY 0x0001 /* debug entry points */ 368 #define DEBMEM 0x0002 /* debug memory */ 369 #define DEBREQ 0x0004 /* debug requests */ 370 #define DEBCQE 0x0008 /* debug cqe's */ 371 #define DEBCQ 0x0010 /* debug cq's */ 372 #define DEBMAINT 0x0020 /* debug maintainance requests */ 373 #define DEBINTR 0x0040 /* debug interrupt routines */ 374 #define DEBINIT 0x0080 /* debug initialization routines */ 375 #define DEBIFC 0x0100 /* debug Internal function codes */ 376 #define DEBIOCTL 0x0200 /* debug ioctl calls */ 377 #define DEBOPEN 0x0400 /* debug open calls */ 378 #define DEBIO 0x0800 /* debug read & write calls */ 379 #define DEBCSR 0x1000 /* debug CSR commands */ 380 #define DEBLOCK 0x2000 /* debug lock / unlock calls */ 381 #define NOBOARD 0x4000 /* debug user/host interface */ 382 #define DEBCANCEL 0x8000 /* debug cancel command */ 383 384 /* 385 * npreg.h version 1.3 386 * 387 * This version retrieved: 8/18/86 @ 18:58:46 388 * This delta created: 8/18/86 @ 18:27:42 389 */ 390 391 /* 392 * NPREG.H 393 * 394 * This file contain definitions of specific hardware interest 395 * to be used when communicating with the NI1510 Network Processor 396 * Board. More complete information can be found in the NI1510 397 * Multibus compatible Ethernet Communications Processor Hardware 398 * Specification. 399 */ 400 401 /* 402 * npcmd.h version 1.3 403 * 404 * This version retrieved: 8/18/86 @ 18:58:45 405 * This delta created: 8/18/86 @ 18:27:38 406 */ 407 #ifdef KERNEL 408 # define IoVOID 0 409 #else 410 # define IoVOID IOC_VOID 411 #endif 412 413 #define NPRESET (IoVOID|0x01) /* reset the board */ 414 #define NPSTART (IoVOID|0x04) /* start board execution */ 415 #define NPGPANIC (IoVOID|0x05) /* Get panic message */ 416 #define NPINIT (IoVOID|0x06) /* initialize software on board */ 417 #define NPSTATS (IoVOID|0x07) 418 #define NPRCSR0 (IoVOID|0x08) /* read CSR0 */ 419 #define NPRCSR1 (IoVOID|0x09) /* read CSR1 */ 420 #define NPRCSR2 (IoVOID|0x0a) /* read CSR2 */ 421 #define NPRCSR3 (IoVOID|0x0b) /* read CSR3 */ 422 #define NPWCSR0 (IoVOID|0x0c) /* write CSR0 */ 423 #define NPWCSR1 (IoVOID|0x0d) /* write CSR1 */ 424 #define NPWCSR2 (IoVOID|0x0e) /* write CSR2 */ 425 #define NPWCSR3 (IoVOID|0x0f) /* write CSR3 */ 426 #define NPPOLL (IoVOID|0x10) 427 #define NPKILL (IoVOID|0x11) 428 #define NPSETPROT (IoVOID|0x12) /* set the protocol to use */ 429 #define NPSETBOARD (IoVOID|0x13) /* set board to use */ 430 #define NPSETNPDEB (IoVOID|0x14) /* set nc debuging level */ 431 #define NPSETADDR (IoVOID|0x15) /* set host address */ 432 #define NPNETBOOT (IoVOID|0x16) /* boot from the network */ 433 #define NPSETLAST (IoVOID|0x17) /* set last command flag in NPIO */ 434 #define NPCLRICNT (IoVOID|0x18) /* clear interupt count */ 435 #define NPGETICNT (IoVOID|0x19) /* get interupt count */ 436 #define NPGETIVEC (IoVOID|0x1a) /* get interupt vector */ 437 #define NPMAPMEM (IoVOID|0x1b) /* map user memory to shmem */ 438 439 #define NP_SET 1031 /* set memory mapping */ 440 #define NP_USET 1032 /* unset memory mapping */ 441 442 struct np_mem { 443 long mem_type; 444 char *mem_addr; 445 long mem_count; 446 } ; 447 448 #define NNPCNN 4 /* Number of connections per board */ 449 #define NPUNIT(a) ((minor(a) >> 4) & 0x0F) 450 #define NPCONN(a) ((minor(a)) & 0x03) 451 452 #define TRUE 1 453 #define FALSE 0 454 455 #define IBOOTADDR 0xF8000l /* Addr of 80186 Boot ROM */ 456 #define INETBOOT 0xF8087l 457 #define IXEQADDR 0x400 /* Where to begin Board image XEQ */ 458 #define DIAGTIME 1200 /* Time for timeout /HZ seconds */ 459 460 #define DELAYTIME 1000000L /* delay count */ 461 #define NPDELAY(N) {register int n = (N) >> 1; while(--n > 0); } 462 463 /* Handy macros for talking to the Board */ 464 465 #define RESET(x) (WCSR3(x->iobase,0xff)) 466 #define CLEARINT(x) {unsign16 y; y = RCSR2(x->iobase); } 467 #define INTNI(x) (WCSR1(x->iobase,0xFF)) 468 469 /* Command and Status Register (CSR) Definitions */ 470 471 /* 472 * CSR0 is the only direct means for data transfer between the host processor 473 * and the 3510. Access is controlled by the 80186 who sets the CSR1 Enable and 474 * Ready bits to allow writing here. Writing to this register will always 475 * result in an interrupt to the 80186. 476 */ 477 478 /* 479 * Bit definitions for CSR1. 480 */ 481 482 #define NPRFU 0x01 /* Reserved for Future Use */ 483 #define NPHOK 0x02 /* Hardware OK */ 484 #define NPLAN 0x04 /* Logic 0 indicates operational LAN exists */ 485 #define NP_IP 0x08 /* Interrupt pending from this board */ 486 #define NP_IE 0x10 /* Interrupts enabled for this board */ 487 #define NPRDR 0x20 /* Set when 80186 writes data into CSR0 */ 488 #define NPRDY 0x40 /* CSR0 ready to accept data */ 489 #define NPENB 0x80 /* CSR0 available for use by the host */ 490 491 /* 492 * Bit defintions for CSR0 Command Block 493 */ 494 495 #define NPLST 0x20 /* Last Command */ 496 #define NPCMD 0x80 /* Shared Memory Address */ 497 #define NPBGN 0x200 /* Begin Execution in On-Board Memory */ 498 #define NPCBI 0x800 /* Interrupt at completion of Command Block */ 499 #define NPDMP 0x2000 /* Dump 80186 On-Board Memory to Multibus */ 500 #define NPLD 0x8000 /* Load 80186 On-board Memory from Multibus */ 501 502 /* 503 * CSR0 Count definitions. These are the lengths of the Command Blocks for the 504 * CSR0 commands above (not counting the Command Word itself). 505 */ 506 507 #define LSTCNT 0 508 #define CMDCNT 2 509 #define BGNCNT 2 510 #define CBICNT 1 511 #define DMPCNT 5 512 #define LDCNT 5 513 #define IOCNT 5 514 515 /* Macros for reading and writing CSR's (Control and Status Registers) */ 516 517 #define WCSR0(x,y) ((x)->CSR0 = y) 518 #define WCSR1(x,y) ((x)->CSR1 = y) 519 #define WCSR2(x,y) ((x)->CSR2 = y) 520 #define WCSR3(x,y) ((x)->CSR3 = y) 521 522 #define RCSR0(x) ((x)->CSR0) 523 #define RCSR1(x) ((x)->CSR1) 524 #define RCSR2(x) ((x)->CSR2) 525 #define RCSR3(x) ((x)->CSR3) 526 527 struct npconn { 528 529 struct npmaster *unit; /* Unit number (board) of this connection */ 530 unsign16 protocol; /* Protocol used on this connection */ 531 struct buf np_wbuf; /* write buf structure for raw access */ 532 struct buf np_rbuf; /* read buf structure for raw access */ 533 }; 534 535 /* ICP Board Requests */ 536 537 #define ICPLOAD 0x02 538 #define ICPDUMP 0x03 539 #define ICPPANIC 0x05 540 #define ICPPOLL 0x10 541 542 /* 543 * npdebug.h version 1.3 544 * 545 * This version retrieved: 8/18/86 @ 18:58:46 546 * This delta created: 8/18/86 @ 18:27:39 547 */ 548 549 /* 550 * Debugging Constants 551 */ 552 553 #define DEBENTRY 0x0001 /* debug entry points */ 554 #define DEBMEM 0x0002 /* debug memory */ 555 #define DEBREQ 0x0004 /* debug requests */ 556 #define DEBCQE 0x0008 /* debug cqe's */ 557 #define DEBCQ 0x0010 /* debug cq's */ 558 #define DEBMAINT 0x0020 /* debug maintainance requests */ 559 #define DEBINTR 0x0040 /* debug interrupt routines */ 560 #define DEBINIT 0x0080 /* debug initialization routines */ 561 #define DEBIFC 0x0100 /* debug Internal function codes */ 562 #define DEBIOCTL 0x0200 /* debug ioctl calls */ 563 #define DEBOPEN 0x0400 /* debug open calls */ 564 #define DEBIO 0x0800 /* debug read & write calls */ 565 #define DEBCSR 0x1000 /* debug CSR commands */ 566 #define DEBLOCK 0x2000 /* debug lock / unlock calls */ 567