1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _PLATFORM_REQUEST_HANDLER_UTILS_H_ 25 #define _PLATFORM_REQUEST_HANDLER_UTILS_H_ 26 27 //_PCONTROL 28 //_PCONTROL response from driver to SBIOS 29 #define NV_PB_PFM_REQ_HNDLR_PCTRL_RES 3:0 30 #define NV_PB_PFM_REQ_HNDLR_PCTRL_RES_CHANGE_EVENT (0) 31 #define NV_PB_PFM_REQ_HNDLR_PCTRL_RES_VPSTATE_INFO (1) 32 #define NV_PB_PFM_REQ_HNDLR_PCTRL_RES_VPSTATE_SET (2) 33 #define NV_PB_PFM_REQ_HNDLR_PCTRL_RES_VPSTATE_UPDATE (3) 34 #define NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED 7:4 35 #define NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED_BITS (0) 36 #define NV_PB_PFM_REQ_HNDLR_PCTRL_LAST_VPSTATE_LIMIT 15:8 37 #define NV_PB_PFM_REQ_HNDLR_PCTRL_INDEX_PSTATE 15:8 38 #define NV_PB_PFM_REQ_HNDLR_PCTRL_SLOW_EXT_VPSTATE 23:16 39 #define NV_PB_PFM_REQ_HNDLR_PCTRL_FAST_VPSTATE 31:24 40 #define NV_PB_PFM_REQ_HNDLR_PCTRL_MAPPING_VPSTATE 31:24 41 42 //_PCONTROL request from SBIOS to driver 43 #define NV_PB_PFM_REQ_HNDLR_PCTRL_REQ 3:0 44 #define NV_PB_PFM_REQ_HNDLR_PCTRL_REQ_NO_ACTION (0) 45 #define NV_PB_PFM_REQ_HNDLR_PCTRL_REQ_VPSTATE_INFO (1) 46 #define NV_PB_PFM_REQ_HNDLR_PCTRL_REQ_VPSTATE_SET (2) 47 #define NV_PB_PFM_REQ_HNDLR_PCTRL_REQ_VPSTATE_UPDATE (3) 48 #define NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED1 7:4 49 #define NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED1_BITS (0) 50 #define NV_PB_PFM_REQ_HNDLR_PCTRL_INDEX_PSTATE 15:8 51 #define NV_PB_PFM_REQ_HNDLR_PCTRL_MAX_VPSTATE_LEVEL 15:8 52 #define NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED2 30:16 53 #define NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED2_BITS (0) 54 #define NV_PB_PFM_REQ_HNDLR_PCTRL_BIT_31 31:31 55 #define NV_PB_PFM_REQ_HNDLR_PCTRL_BIT_31_ZERO (0) 56 57 /* 58 * NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO 59 * 60 * GPU EDPpeak Limit information for platform 61 * 62 * ulVersion 63 * (Major(16 bits):Minor(16 bits), current v1.0) 64 * Little endian format 0x00, 0x00, 0x01, 0x00 65 * limitLast 66 * last requested platform limit 67 * limitMin 68 * Minimum allowed limit value on EDPp policy on both AC and DC 69 * limitRated 70 * Rated/default allowed limit value on EDPp policy on AC 71 * limitMax 72 * Maximum allowed limit value on EDPp policy on AC 73 * limitCurr 74 * Current resultant limit effective on EDPp policy on AC and DC 75 * limitBattRated 76 * Default/rated allowed limit on EDPp policy on DC 77 * limitBattMax 78 * Maximum allowed limit on EDPp policy on DC 79 * rsvd 80 * Reserved 81 */ 82 typedef struct NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1 { 83 NvU32 ulVersion; 84 NvU32 limitLast; 85 NvU32 limitMin; 86 NvU32 limitRated; 87 NvU32 limitMax; 88 NvU32 limitCurr; 89 NvU32 limitBattRated; 90 NvU32 limitBattMax; 91 NvU32 rsvd; 92 } NV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1, *PNV0000_CTRL_PFM_REQ_HNDLR_EDPP_LIMIT_INFO_V1; 93 94 /* 95 * NV0000_CTRL_PFM_REQ_HNDLR_PSHAREDATA 96 * 97 * This structure represents a block of PSHARE data from SBIOS 98 * 99 * status 100 * settings per spec 101 * ulVersion 102 * (Major(16 bits):Minor(16 bits), current v1.0) 103 * Little endian format 0x00, 0x00, 0x01, 0x00 104 * tGpu 105 * GPU temperature (not provided by system) 106 * 107 * ctgp 108 * Configurable TGP limit 109 */ 110 typedef struct NV0000_CTRL_PFM_REQ_HNDLR_PSHAREDATA { 111 // Header to sensor structure 112 NvU32 status; 113 NvU32 ulVersion; 114 115 NvU32 tGpu; 116 NvU32 ctgp; 117 } NV0000_CTRL_PFM_REQ_HNDLR_PSHAREDATA, *PNV0000_CTRL_PFM_REQ_HNDLR_PSHAREDATA; 118 119 /* 120 * Begin defines for access to ACPI calls, these 121 * are used in the RM, so we'd like to get them 122 * in, even though the CTRL call is not ready. 123 * NV0000_CTRL_CMD_CALL_PFM_REQ_HNDLR_ACPI 124 * 125 * This command is used to send ACPI commands for PlatformRequestHandler compliant SBIOS 126 * to the RM to be executed by system BIOS. Results of those SBIOS 127 * command are returned through this interface. 128 * 129 * cmd 130 * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_TYPE 131 * Gets system configuration Information. 132 * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT 133 * Gets bit mask of supported functions 134 * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PCONTROL 135 * Sets GPU power control features. 136 * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHARESTATUS 137 * Gets System PShare Status 138 * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPL 139 * Execute ACPI GETPPL command. 140 * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPL 141 * Execute ACPI SETPPL command. 142 * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS 143 * Get sensor information and capabilities. 144 * input 145 * Used for single DWORD (32 bit) values as input to 146 * the requested ACPI call. 147 * 148 */ 149 typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CTRL 150 { 151 NvU32 cmd; 152 NvU32 input; 153 } NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CTRL; 154 155 /* 156 * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_OUTPUT 157 * 158 * This structure represents the output from a single ACPI call. 159 * 160 * result 161 * The ACPI return code for the operation attempted. 162 * pBuffer 163 * This field returns a pointer the buffer of data requested. 164 * bufferSz 165 * This field returns the size of returned data in above pBuffer. 166 */ 167 typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_OUTPUT 168 { 169 NvU32 result[2]; 170 NvU8 *pBuffer; 171 NvU16 bufferSz; 172 } NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_OUTPUT; 173 174 175 /* 176 * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS 177 * 178 * This structure represents a parameter block of data to describe an 179 * ACPI request, and return it's output. 180 * 181 * ctrl 182 * The ACPI request for the operation attempted. 183 * output 184 * Output structure from the executed ACPI command. 185 */ 186 typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS 187 { 188 NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CTRL ctrl; 189 NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_OUTPUT output; 190 } NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS; 191 192 /* 193 * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX 194 * 195 * Used for PPL and TRL calls, which have up to three input DWORDs and three 196 * output DWORDs. 197 */ 198 #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX_MAX_SZ (3U) 199 200 typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX 201 { 202 NvU32 pfmreqhndlrFunc; 203 NvU16 inSize; 204 NvU16 outSize; 205 NvU32 input[NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX_MAX_SZ]; 206 NvU32 output[NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX_MAX_SZ]; 207 } NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX; 208 209 #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_TYPE 8:0 210 #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT (GPS_FUNC_SUPPORT) 211 #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PCONTROL (GPS_FUNC_PCONTROL) 212 #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHARESTATUS (GPS_FUNC_PSHARESTATUS) 213 #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPL (GPS_FUNC_GETPPL) 214 #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPL (GPS_FUNC_SETPPL) 215 #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETTRL (GPS_FUNC_GETTRL) 216 #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETTRL (GPS_FUNC_SETTRL) 217 #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPM (GPS_FUNC_GETPPM) 218 #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPM (GPS_FUNC_SETPPM) 219 #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS (GPS_FUNC_PSHAREPARAMS) 220 #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETEDPPLIMITINFO (GPS_FUNC_SETEDPPLIMITINFO) 221 #define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETEDPPLIMIT (GPS_FUNC_GETEDPPLIMIT) 222 223 // PFM_REQ_HNDLR_SUPPORT output 224 #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SUPPORT_AVAIL 0:0 225 #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PCONTROL_AVAIL 28:28 226 #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PSHARESTATUS_AVAIL 32:32 227 #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETPPL_AVAIL 36:36 228 #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETPPL_AVAIL 37:37 229 #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETTRL_AVAIL 38:38 230 #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETTRL_AVAIL 39:39 231 #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETPPM_AVAIL 40:40 232 #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETPPM_AVAIL 41:41 233 #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PSHAREPARAMS_AVAIL 42:42 234 #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_INFOEDPPLIMIT_AVAIL 43:43 235 #define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETEDPPLIMIT_AVAIL 44:44 236 237 // PFM_REQ_HNDLR_PCONTROL 238 #define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE 3:0 239 #define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE_EVENT_RESP (0x00) // input only 240 #define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE_EVENT_DONE (0x00) // output only 241 #define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE_VPSTATE_INFO (0x01) // input & output 242 #define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE_NEW_VP_STATE (0x02) // input & output 243 #define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE_UPDATE_VP_STATE (0x03) // input & output 244 #define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_VPSTATE_LIMIT 15:8 // input request type 0, 2, or 3; output request type 2 245 #define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_PSTATE_IDX 15:8 // input request type 1; output request type 1 246 #define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_SLOWEST_VPSTATE 23:16 // input only 247 #define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_FASTEST_VPSTATE 31:24 // input request type 0, 2, or 3 248 #define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_VPSTATE_MAPPING 31:24 // input request type 1 249 250 // PFM_REQ_HNDLR_PSHARESTATUS 251 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT 0:0 // output only 252 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT_NOT_PENDING (0) 253 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT_PENDING (1) 254 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_DO_NOT_USE 19:1 255 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT 20:20 // output only 256 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT_DISABLE (0) 257 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT_ENABLE (1) 258 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE 21:21 // output only 259 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE_FALSE (0) 260 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE_TRUE (1) 261 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE 22:22 // output only 262 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE_DISABLE (0) 263 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE_ENABLE (1) 264 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_GETEDPPEAKLIMIT_SET 25:25 // output only 265 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_GETEDPPEAKLIMIT_SET_FALSE (0U) 266 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_GETEDPPEAKLIMIT_SET_TRUE (1U) 267 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_SETEDPPEAKLIMITINFO_SET 26:26 // output only 268 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_SETEDPPEAKLIMITINFO_SET_FALSE (0U) 269 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLATFORM_SETEDPPEAKLIMITINFO_SET_TRUE (1U) 270 271 // Shared by GETPPL, SETPPL 272 #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_COUNT (3) 273 #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_VERSION_IDX (0) 274 #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MINOR 15:0 // input & output 275 #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MAJOR 31:16 // input & output 276 #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MAJOR_V1 (1) // input & output 277 #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT1_IDX (1) // input & output 278 #define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT2_IDX (2) // input & output 279 280 // Shared by GETTRL, SETTRL 281 #define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_COUNT (2) 282 #define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_VERSION_IDX (0) 283 #define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MINOR 15:0 // input & output 284 #define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MAJOR 31:16 // input & output 285 #define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MAJOR_V1 (1) // input & output 286 #define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_FREQ_MHZ_IDX (1) // input & output 287 288 // Shared by GETPPM, SETPPM 289 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_COUNT (2) 290 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_VERSION_IDX (0) 291 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MINOR 15:0 // input & output 292 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MAJOR 31:16 // input & output 293 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MAJOR_V1 (1) // input & output 294 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_IDX (1) // input & output 295 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_INDEX 7:0 // output 296 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_AVAILABLE_MASK 15:8 // output 297 298 // Shared by INFOEDPPLIMIT and SETEDPPLIMIT 299 #define NV0000_CTRL_PFM_REQ_HNDLR_EDPP_VERSION_V10 (0x10000U) // input & output 300 301 // 302 // PFM_REQ_HNDLR_PSHARE_PARAMS 303 // status bits 304 // 305 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_QUERY_TYPE 3:0 // input & output 306 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_QUERY_TYPE_CURRENT_INFO (0x00) 307 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_QUERY_TYPE_SUPPORTED_FIELDS (0x01) 308 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_QUERY_TYPE_CURRENT_LIMITS (0x02) 309 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_TGPU 8:8 // input & output 310 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_TGPU_FALSE (0) 311 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_TGPU_TRUE (1) 312 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_DO_NOT_USE 14:9 // input & output 313 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_CTGP 15:15 // input & output 314 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_CTGP_FALSE (0) 315 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_CTGP_TRUE (1) 316 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_PPMD 16:16 // input & output 317 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_PPMD_FALSE (0) 318 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_PPMD_TRUE (1) 319 320 // 321 // A mapping from ACPI DSM and SW support dsm version. 322 // The SW might emulate 1x based on other parameters 323 // 324 #define NV0000_CTRL_PFM_REQ_HNDLR_ACPI_REVISION_SW_1X (0x00000100) 325 #define NV0000_CTRL_PFM_REQ_HNDLR_ACPI_REVISION_SW_2X (0x00000200) 326 327 328 #endif // _PLATFORM_REQUEST_HANDLER_UTILS_H_ 329 330