1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 #pragma once 24 25 #include <nvtypes.h> 26 27 // 28 // This file was generated with FINN, an NVIDIA coding tool. 29 // Source file: ctrl/ctrl0000/ctrl0000system.finn 30 // 31 32 #include "ctrl/ctrlxxxx.h" 33 #include "ctrl/ctrl0000/ctrl0000base.h" 34 35 /* NV01_ROOT (client) system control commands and parameters */ 36 37 /* 38 * NV0000_CTRL_CMD_SYSTEM_GET_FEATURES 39 * 40 * This command returns a mask of supported features for the SYSTEM category 41 * of the 0000 class. 42 * 43 * Valid features include: 44 * 45 * NV0000_CTRL_GET_FEATURES_SLI 46 * When this bit is set, SLI is supported. 47 * NV0000_CTRL_GET_FEATURES_UEFI 48 * When this bit is set, it is a UEFI system. 49 * NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 50 * When this bit is set, EFI has initialized core channel 51 * 52 * Possible status values returned are: 53 * NV_OK 54 * NV_ERR_INVALID_STATE 55 */ 56 #define NV0000_CTRL_CMD_SYSTEM_GET_FEATURES (0x1f0U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID" */ 57 58 #define NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID (0xF0U) 59 60 typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS { 61 NvU32 featuresMask; 62 } NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS; 63 64 65 66 /* Valid feature values */ 67 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI 0:0 68 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U) 69 #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U) 70 71 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI 1:1 72 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_FALSE (0x00000000U) 73 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_TRUE (0x00000001U) 74 75 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2 76 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U) 77 #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U) 78 79 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING 3:3 80 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE (0x00000000U) 81 #define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE (0x00000001U) 82 83 /* 84 * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION 85 * 86 * This command returns the current driver information. 87 * The first time this is called the size of strings is 88 * set with the greater of NV_BUILD_BRANCH_VERSION and 89 * NV_DISPLAY_DRIVER_TITLE. The client then allocates memory 90 * of size sizeOfStrings for pVersionBuffer and pTitleBuffer 91 * and calls the command again to receive driver info. 92 * 93 * sizeOfStrings 94 * This field returns the size in bytes of the pVersionBuffer and 95 * pTitleBuffer strings. 96 * pDriverVersionBuffer 97 * This field returns the version (NV_VERSION_STRING). 98 * pVersionBuffer 99 * This field returns the version (NV_BUILD_BRANCH_VERSION). 100 * pTitleBuffer 101 * This field returns the title (NV_DISPLAY_DRIVER_TITLE). 102 * changelistNumber 103 * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). 104 * officialChangelistNumber 105 * This field returns the last official changelist value 106 * (NV_LAST_OFFICIAL_CHANGELIST_NUM). 107 * 108 * Possible status values returned are: 109 * NV_OK 110 * NV_ERR_INVALID_PARAM_STRUCT 111 */ 112 113 #define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */ 114 115 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID (0x1U) 116 117 typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS { 118 NvU32 sizeOfStrings; 119 NV_DECLARE_ALIGNED(NvP64 pDriverVersionBuffer, 8); 120 NV_DECLARE_ALIGNED(NvP64 pVersionBuffer, 8); 121 NV_DECLARE_ALIGNED(NvP64 pTitleBuffer, 8); 122 NvU32 changelistNumber; 123 NvU32 officialChangelistNumber; 124 } NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS; 125 126 /* 127 * NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO 128 * 129 * This command returns system CPU information. 130 * 131 * type 132 * This field returns the processor type. 133 * Legal processor types include: 134 * Intel processors: 135 * P55 : P55C - MMX 136 * P6 : PPro 137 * P2 : PentiumII 138 * P2XC : Xeon & Celeron 139 * CELA : Celeron-A 140 * P3 : Pentium-III 141 * P3_INTL2 : Pentium-III w/integrated L2 (fullspeed, on die, 256K) 142 * P4 : Pentium 4 143 * CORE2 : Core2 Duo Conroe 144 * AMD processors 145 * K62 : K6-2 w/ 3DNow 146 * IDT/Centaur processors 147 * C6 : WinChip C6 148 * C62 : WinChip 2 w/ 3DNow 149 * Cyrix processors 150 * GX : MediaGX 151 * M1 : 6x86 152 * M2 : M2 153 * MGX : MediaGX w/ MMX 154 * Transmeta processors 155 * TM_CRUSOE : Transmeta Crusoe(tm) 156 * PowerPC processors 157 * PPC603 : PowerPC 603 158 * PPC604 : PowerPC 604 159 * PPC750 : PowerPC 750 160 * 161 * capabilities 162 * This field returns the capabilities of the processor. 163 * Legal processor capabilities include: 164 * MMX : supports MMX 165 * SSE : supports SSE 166 * 3DNOW : supports 3DNow 167 * SSE2 : supports SSE2 168 * SFENCE : supports SFENCE 169 * WRITE_COMBINING : supports write-combining 170 * ALTIVEC : supports ALTIVEC 171 * PUT_NEEDS_IO : requires OUT inst w/PUT updates 172 * NEEDS_WC_WORKAROUND : requires workaround for P4 write-combining bug 173 * 3DNOW_EXT : supports 3DNow Extensions 174 * MMX_EXT : supports MMX Extensions 175 * CMOV : supports CMOV 176 * CLFLUSH : supports CLFLUSH 177 * SSE3 : supports SSE3 178 * NEEDS_WAR_124888 : requires write to GPU while spinning on 179 * : GPU value 180 * HT : support hyper-threading 181 * clock 182 * This field returns the processor speed in MHz. 183 * L1DataCacheSize 184 * This field returns the level 1 data (or unified) cache size 185 * in kilobytes. 186 * L2DataCacheSize 187 * This field returns the level 2 data (or unified) cache size 188 * in kilobytes. 189 * dataCacheLineSize 190 * This field returns the bytes per line in the level 1 data cache. 191 * numLogicalCpus 192 * This field returns the number of logical processors. On Intel x86 193 * systems that support it, this value will incorporate the current state 194 * of HyperThreading. 195 * numPhysicalCpus 196 * This field returns the number of physical processors. 197 * name 198 * This field returns the CPU name in ASCII string format. 199 * family 200 * Vendor defined Family and Extended Family combined 201 * model 202 * Vendor defined Model and Extended Model combined 203 * stepping 204 * Silicon stepping 205 * bCCEnabled 206 * Confidentail compute enabled/disabled state 207 * 208 * Possible status values returned are: 209 * NV_OK 210 * NV_ERR_INVALID_PARAM_STRUCT 211 */ 212 #define NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO (0x102U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID" */ 213 214 #define NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID (0x2U) 215 216 typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { 217 NvU32 type; /* processor type */ 218 NvU32 capabilities; /* processor caps */ 219 NvU32 clock; /* processor speed (MHz) */ 220 NvU32 L1DataCacheSize; /* L1 dcache size (KB) */ 221 NvU32 L2DataCacheSize; /* L2 dcache size (KB) */ 222 NvU32 dataCacheLineSize; /* L1 dcache bytes/line */ 223 NvU32 numLogicalCpus; /* logial processor cnt */ 224 NvU32 numPhysicalCpus; /* physical processor cnt*/ 225 NvU8 name[52]; /* embedded cpu name */ 226 NvU32 family; /* Vendor defined Family and Extended Family combined */ 227 NvU32 model; /* Vendor defined Model and Extended Model combined */ 228 NvU8 stepping; /* Silicon stepping */ 229 NvU32 coresOnDie; /* cpu cores per die */ 230 NvBool bCCEnabled; /* CC enabled on cpu */ 231 } NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS; 232 233 // Macros for CPU family information 234 #define NV0000_CTRL_SYSTEM_CPU_FAMILY 3:0 235 #define NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY 11:4 236 237 // Macros for CPU model information 238 #define NV0000_CTRL_SYSTEM_CPU_MODEL 3:0 239 #define NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL 7:4 240 241 // Macros for AMD CPU information 242 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY 0xF 243 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY 0xA 244 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL 0x0 245 #define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL 0x4 246 247 // Macros for Intel CPU information 248 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY 0x6 249 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY 0x0 250 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL 0x7 251 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL 0xA 252 #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL 0x9 253 254 /* processor type values */ 255 #define NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN (0x00000000U) 256 /* Intel types */ 257 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P5 (0x00000001U) 258 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P55 (0x00000002U) 259 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P6 (0x00000003U) 260 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P2 (0x00000004U) 261 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC (0x00000005U) 262 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CELA (0x00000006U) 263 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P3 (0x00000007U) 264 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 (0x00000008U) 265 #define NV0000_CTRL_SYSTEM_CPU_TYPE_P4 (0x00000009U) 266 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 (0x00000010U) 267 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H (0x00000011U) 268 #define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM (0x00000012U) 269 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM (0x00000013U) 270 #define NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR (0x00000014U) 271 /* AMD types */ 272 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K5 (0x00000030U) 273 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K6 (0x00000031U) 274 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K62 (0x00000032U) 275 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K63 (0x00000033U) 276 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K7 (0x00000034U) 277 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K8 (0x00000035U) 278 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K10 (0x00000036U) 279 #define NV0000_CTRL_SYSTEM_CPU_TYPE_K11 (0x00000037U) 280 #define NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN (0x00000038U) 281 /* IDT/Centaur types */ 282 #define NV0000_CTRL_SYSTEM_CPU_TYPE_C6 (0x00000060U) 283 #define NV0000_CTRL_SYSTEM_CPU_TYPE_C62 (0x00000061U) 284 /* Cyrix types */ 285 #define NV0000_CTRL_SYSTEM_CPU_TYPE_GX (0x00000070U) 286 #define NV0000_CTRL_SYSTEM_CPU_TYPE_M1 (0x00000071U) 287 #define NV0000_CTRL_SYSTEM_CPU_TYPE_M2 (0x00000072U) 288 #define NV0000_CTRL_SYSTEM_CPU_TYPE_MGX (0x00000073U) 289 /* Transmeta types */ 290 #define NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE (0x00000080U) 291 /* IBM types */ 292 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 (0x00000090U) 293 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 (0x00000091U) 294 #define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 (0x00000092U) 295 #define NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN (0x00000093U) 296 /* Unknown ARM architecture CPU type */ 297 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN (0xA0000000U) 298 /* ARM Ltd types */ 299 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 (0xA0000009U) 300 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 (0xA000000FU) 301 /* NVIDIA types */ 302 #define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 (0xA0001000U) 303 #define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 (0xA0002000U) 304 305 /* Generic types */ 306 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U) 307 #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC (0xA00FF001U) 308 309 /* processor capabilities */ 310 #define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U) 311 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE (0x00000002U) 312 #define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW (0x00000004U) 313 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 (0x00000008U) 314 #define NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE (0x00000010U) 315 #define NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING (0x00000020U) 316 #define NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC (0x00000040U) 317 #define NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO (0x00000080U) 318 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND (0x00000100U) 319 #define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT (0x00000200U) 320 #define NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT (0x00000400U) 321 #define NV0000_CTRL_SYSTEM_CPU_CAP_CMOV (0x00000800U) 322 #define NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH (0x00001000U) 323 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 (0x00002000U) /* deprecated */ 324 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 (0x00004000U) 325 #define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 (0x00008000U) 326 #define NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE (0x00010000U) 327 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 (0x00020000U) 328 #define NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 (0x00040000U) 329 #define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000U) 330 #define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000U) 331 332 /* 333 * NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO 334 * 335 * This command returns system chipset information. 336 * 337 * vendorId 338 * This parameter returns the vendor identification for the chipset. 339 * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset 340 * cannot be identified. 341 * deviceId 342 * This parameter returns the device identification for the chipset. 343 * A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset 344 * cannot be identified. 345 * subSysVendorId 346 * This parameter returns the subsystem vendor identification for the 347 * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the 348 * chipset cannot be identified. 349 * subSysDeviceId 350 * This parameter returns the subsystem device identification for the 351 * chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the 352 * chipset cannot be identified. 353 * HBvendorId 354 * This parameter returns the vendor identification for the chipset's 355 * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates 356 * the chipset's host bridge cannot be identified. 357 * HBdeviceId 358 * This parameter returns the device identification for the chipset's 359 * host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates 360 * the chipset's host bridge cannot be identified. 361 * HBsubSysVendorId 362 * This parameter returns the subsystem vendor identification for the 363 * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID 364 * indicates the chipset's host bridge cannot be identified. 365 * HBsubSysDeviceId 366 * This parameter returns the subsystem device identification for the 367 * chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID 368 * indicates the chipset's host bridge cannot be identified. 369 * sliBondId 370 * This parameter returns the SLI bond identification for the chipset. 371 * vendorNameString 372 * This parameter returns the vendor name string. 373 * chipsetNameString 374 * This parameter returns the vendor name string. 375 * sliBondNameString 376 * This parameter returns the SLI bond name string. 377 * flag 378 * This parameter specifies NV0000_CTRL_SYSTEM_CHIPSET_FLAG_XXX flags: 379 * _HAS_RESIZABLE_BAR_ISSUE_YES: Chipset where the use of resizable BAR1 380 * should be disabled - bug 3440153 381 * 382 * Possible status values returned are: 383 * NV_OK 384 * NV_ERR_INVALID_PARAM_STRUCT 385 * NV_ERR_INVALID_ARGUMENT 386 * NV_ERR_OPERATING_SYSTEM 387 */ 388 #define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */ 389 390 /* maximum name string length */ 391 #define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U) 392 393 /* invalid id */ 394 #define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU) 395 396 #define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U) 397 398 typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS { 399 NvU16 vendorId; 400 NvU16 deviceId; 401 NvU16 subSysVendorId; 402 NvU16 subSysDeviceId; 403 NvU16 HBvendorId; 404 NvU16 HBdeviceId; 405 NvU16 HBsubSysVendorId; 406 NvU16 HBsubSysDeviceId; 407 NvU32 sliBondId; 408 NvU8 vendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 409 NvU8 subSysVendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 410 NvU8 chipsetNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 411 NvU8 sliBondNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH]; 412 NvU32 flags; 413 } NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS; 414 415 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE 0:0 416 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO (0x00000000U) 417 #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES (0x00000001U) 418 419 420 421 /* 422 * NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES 423 * 424 * This command is used to retrieve the measured times spent holding and waiting for 425 * the main RM locks (API and GPU). 426 * 427 * waitApiLock 428 * Total time spent by RM API's waiting to acquire the API lock 429 * 430 * holdRoApiLock 431 * Total time spent by RM API's holding the API lock in RO mode. 432 * 433 * holdRwApiLock 434 * Total time spent by RM API's holding the API lock in RW mode. 435 * 436 * waitGpuLock 437 * Total time spent by RM API's waiting to acquire one or more GPU locks. 438 * 439 * holdGpuLock 440 * Total time spent by RM API's holding one or more GPU locks. 441 * 442 * 443 * Possible status values returned are: 444 * NV_OK 445 * NV_ERR_NOT_SUPPORTED 446 */ 447 448 #define NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES (0x109U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID" */ 449 450 #define NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID (0x9U) 451 452 typedef struct NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS { 453 NV_DECLARE_ALIGNED(NvU64 waitApiLock, 8); 454 NV_DECLARE_ALIGNED(NvU64 holdRoApiLock, 8); 455 NV_DECLARE_ALIGNED(NvU64 holdRwApiLock, 8); 456 NV_DECLARE_ALIGNED(NvU64 waitGpuLock, 8); 457 NV_DECLARE_ALIGNED(NvU64 holdGpuLock, 8); 458 } NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS; 459 460 /* 461 * NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST 462 * 463 * This command is used to retrieve the set of system-level classes 464 * supported by the platform. 465 * 466 * numClasses 467 * This parameter returns the number of valid entries in the returned 468 * classes[] list. This parameter will not exceed 469 * Nv0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE. 470 * classes 471 * This parameter returns the list of supported classes 472 * 473 * Possible status values returned are: 474 * NV_OK 475 * NV_ERR_INVALID_PARAM_STRUCT 476 */ 477 478 #define NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST (0x108U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID" */ 479 480 /* maximum number of classes returned in classes[] array */ 481 #define NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE (32U) 482 483 #define NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x8U) 484 485 typedef struct NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS { 486 NvU32 numClasses; 487 NvU32 classes[NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE]; 488 } NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS; 489 490 /* 491 * NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT 492 * 493 * This command is used to send triggered mobile related system events 494 * to the RM. 495 * 496 * eventType 497 * This parameter indicates the triggered event type. This parameter 498 * should specify a valid NV0000_CTRL_SYSTEM_EVENT_TYPE value. 499 * eventData 500 * This parameter specifies the type-dependent event data associated 501 * with EventType. This parameter should specify a valid 502 * NV0000_CTRL_SYSTEM_EVENT_DATA value. 503 * bEventDataForced 504 * This parameter specifies what we have to do, Whether trust current 505 * Lid/Dock state or not. This parameter should specify a valid 506 * NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED value. 507 508 * Possible status values returned are: 509 * NV_OK 510 * NV_ERR_INVALID_PARAM_STRUCT 511 * NV_ERR_INVALID_ARGUMENT 512 * 513 * Sync this up (#defines) with one in nvapi.spec! 514 * (NV_ACPI_EVENT_TYPE & NV_ACPI_EVENT_DATA) 515 */ 516 #define NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT (0x110U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID" */ 517 518 #define NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID (0x10U) 519 520 typedef struct NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS { 521 NvU32 eventType; 522 NvU32 eventData; 523 NvBool bEventDataForced; 524 } NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS; 525 526 /* valid eventType values */ 527 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE (0x00000000U) 528 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE (0x00000001U) 529 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE (0x00000002U) 530 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID (0x00000003U) 531 #define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK (0x00000004U) 532 533 /* valid eventData values */ 534 #define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN (0x00000000U) 535 #define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED (0x00000001U) 536 #define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY (0x00000000U) 537 #define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC (0x00000001U) 538 #define NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED (0x00000000U) 539 #define NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED (0x00000001U) 540 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM (0x00000000U) 541 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS (0x00000001U) 542 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF (0x00000002U) 543 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI (0x00000003U) 544 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL (0x00000004U) 545 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL + 1)" */ 546 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM (0x00000000U) 547 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS (0x00000001U) 548 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF (0x00000002U) 549 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI (0x00000003U) 550 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL (0x00000004U) 551 #define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL + 1)" */ 552 553 /* valid bEventDataForced values */ 554 #define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE (0x00000000U) 555 #define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE (0x00000001U) 556 557 /* 558 * NV000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE 559 * 560 * This command is used to query the platform type. 561 * 562 * systemType 563 * This parameter returns the type of the system. 564 * Legal values for this parameter include: 565 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP 566 * The system is a desktop platform. 567 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC 568 * The system is a mobile (non-Toshiba) platform. 569 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP 570 * The system is a mobile Toshiba platform. 571 * NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC 572 * The system is a system-on-a-chip (SOC) platform. 573 * 574 575 * Possible status values returned are: 576 * NV_OK 577 * NV_ERR_INVALID_PARAM_STRUCT 578 * NV_ERR_INVALID_ARGUMENT 579 */ 580 #define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE (0x111U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID" */ 581 582 #define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID (0x11U) 583 584 typedef struct NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS { 585 NvU32 systemType; 586 } NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS; 587 588 /* valid systemType values */ 589 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP (0x000000U) 590 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC (0x000001U) 591 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA (0x000002U) 592 #define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC (0x000003U) 593 594 595 596 597 /* 598 * NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL 599 * 600 * This command controls the current RmMsg filters. 601 * 602 * It is only supported if RmMsg is enabled (e.g. debug builds). 603 * 604 * cmd 605 * GET - Gets the current RmMsg filter string. 606 * SET - Sets the current RmMsg filter string. 607 * 608 * count 609 * The length of the RmMsg filter string. 610 * 611 * data 612 * The RmMsg filter string. 613 * 614 * Possible status values returned are: 615 * NV_OK 616 * NV_ERR_INVALID_ARGUMENT 617 * NV_ERR_NOT_SUPPORTED 618 */ 619 #define NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL (0x121U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID" */ 620 621 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE 512U 622 623 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET (0x00000000U) 624 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET (0x00000001U) 625 626 #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID (0x21U) 627 628 typedef struct NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS { 629 NvU32 cmd; 630 NvU32 count; 631 NvU8 data[NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE]; 632 } NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS; 633 634 /* 635 * NV0000_CTRL_SYSTEM_HWBC_INFO 636 * 637 * This structure contains information about the HWBC (BR04) specified by 638 * hwbcId. 639 * 640 * hwbcId 641 * This field specifies the HWBC ID. 642 * firmwareVersion 643 * This field returns the version of the firmware on the HWBC (BR04), if 644 * present. This is a packed binary number of the form 0x12345678, which 645 * corresponds to a firmware version of 12.34.56.78. 646 * subordinateBus 647 * This field returns the subordinate bus number of the HWBC (BR04). 648 * secondaryBus 649 * This field returns the secondary bus number of the HWBC (BR04). 650 * 651 * Possible status values returned are: 652 * NV_OK 653 * NV_ERR_INVALID_ARGUMENT 654 */ 655 656 typedef struct NV0000_CTRL_SYSTEM_HWBC_INFO { 657 NvU32 hwbcId; 658 NvU32 firmwareVersion; 659 NvU32 subordinateBus; 660 NvU32 secondaryBus; 661 } NV0000_CTRL_SYSTEM_HWBC_INFO; 662 663 #define NV0000_CTRL_SYSTEM_HWBC_INVALID_ID (0xFFFFFFFFU) 664 665 /* 666 * NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO 667 * 668 * This command returns information about all Hardware Broadcast (HWBC) 669 * devices present in the system that are BR04s. To get the complete 670 * list of HWBCs in the system, all GPUs present in the system must be 671 * initialized. See the description of NV0000_CTRL_CMD_GPU_ATTACH_IDS to 672 * accomplish this. 673 * 674 * hwbcInfo 675 * This field is an array of NV0000_CTRL_SYSTEM_HWBC_INFO structures into 676 * which HWBC information is placed. There is one entry for each HWBC 677 * present in the system. Valid entries are contiguous, invalid entries 678 * have the hwbcId equal to NV0000_CTRL_SYSTEM_HWBC_INVALID_ID. If no HWBC 679 * is present in the system, all the entries would be marked invalid, but 680 * the return value would still be SUCCESS. 681 * 682 * Possible status values returned are: 683 * NV_OK 684 * NV_ERR_INVALID_ARGUMENT 685 */ 686 #define NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO (0x124U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID" */ 687 688 #define NV0000_CTRL_SYSTEM_MAX_HWBCS (0x00000080U) 689 690 #define NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID (0x24U) 691 692 typedef struct NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS { 693 NV0000_CTRL_SYSTEM_HWBC_INFO hwbcInfo[NV0000_CTRL_SYSTEM_MAX_HWBCS]; 694 } NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS; 695 696 /* 697 * NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL 698 * 699 * This command is used to control GPS functionality. It allows control of 700 * GPU Performance Scaling (GPS), changing its operational parameters and read 701 * most GPS dynamic parameters. 702 * 703 * command 704 * This parameter specifies the command to execute. Invalid commands 705 * result in the return of an NV_ERR_INVALID_ARGUMENT status. 706 * locale 707 * This parameter indicates the specific locale to which the command 708 * 'command' is to be applied. 709 * Supported range of CPU/GPU {i = 0, ..., 255} 710 * data 711 * This parameter contains a command-specific data payload. It can 712 * be used to input data as well as output data. 713 * 714 * Possible status values returned are: 715 * NV_OK 716 * NV_ERR_INVALID_COMMAND 717 * NV_ERR_INVALID_STATE 718 * NV_ERR_INVALID_DATA 719 * NV_ERR_INVALID_REQUEST 720 * NV_ERR_NOT_SUPPORTED 721 */ 722 #define NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL (0x122U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID" */ 723 724 #define NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID (0x22U) 725 726 typedef struct NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS { 727 NvU16 command; 728 NvU16 locale; 729 NvU32 data; 730 } NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS; 731 732 /* 733 * Valid command values : 734 * 735 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT 736 * Is used to check if GPS was correctly initialized. 737 * Possible return (OUT) values are: 738 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO 739 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES 740 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC 741 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC 742 * Are used to stop/start GPS functionality and to get current status. 743 * Possible IN/OUT values are: 744 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP 745 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START 746 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS 747 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS 748 * Are used to control execution of GPS actions and to get current status. 749 * Possible IN/OUT values are: 750 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF 751 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON 752 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC 753 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC 754 * Are used to switch current GPS logic and to retrieve current logic. 755 * Possible IN/OUT values are: 756 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF 757 * Will cause that all GPS actions will be NULL. 758 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY 759 * Fuzzy logic will determine GPS actions based on current ruleset. 760 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC 761 * Deterministic logic will define GPS actions based on current ruleset. 762 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE 763 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE 764 * Are used to set/retrieve system control preference. 765 * Possible IN/OUT values are: 766 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU 767 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU 768 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH 769 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT 770 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT 771 * Are used to set/retrieve GPU2CPU pstate limits. 772 * IN/OUT values are four bytes packed into a 32-bit data field. 773 * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap 774 * index for the GPU pstate 3 is in the highest byte, etc. One 775 * special value is to disable the override to the GPU2CPU map: 776 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE 777 * Is used to stop/start GPS PMU functionality. 778 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE 779 * Is used to get the current status of PMU GPS. 780 * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE 781 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER 782 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER 783 * Are used to set/retrieve max power [mW] that system can provide. 784 * This is hardcoded GPS safety feature and logic/rules does not apply 785 * to this threshold. 786 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET 787 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET 788 * Are used to set/retrieve current system cooling budget [mW]. 789 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD 790 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD 791 * Are used to set/retrieve integration interval [sec]. 792 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET 793 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET 794 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT 795 * Are used to set/retrieve used ruleset [#]. Value is checked 796 * against MAX number of rules for currently used GPS logic. Also COUNT 797 * provides a way to find out how many rules exist for the current control 798 * system. 799 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST 800 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST 801 * Is used to set/get a delay relative to now during which to allow unbound 802 * CPU performance. Units are seconds. 803 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE 804 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE 805 * Is used to override/get the actual power supply mode (AC/Battery). 806 * Possible IN/OUT values are: 807 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL 808 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC 809 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT 810 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO 811 * Is used to get the Ventura system information for VCT tool 812 * Returned 32bit value should be treated as bitmask and decoded in 813 * following way: 814 * Encoding details are defined in objgps.h refer to 815 * NV_GPS_SYS_SUPPORT_INFO and corresponding bit defines. 816 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTION 817 * Is used to get the supported sub-functions defined in SBIOS. Returned 818 * value is a bitmask where each bit corresponds to different function: 819 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT 820 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS 821 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS 822 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC 823 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC 824 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB 825 * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS 826 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER 827 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA 828 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE 829 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG 830 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL 831 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN 832 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE 833 * Are used to retrieve appropriate power measurements and their derivatives 834 * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. 835 * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as 836 * index. 837 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS 838 * Is used to retrieve parameters when adjusting raw sensor power reading. 839 * The values may come from SBIOS, VBIOS, registry or driver default. 840 * Possible IN value is the index of interested parameter. 841 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP 842 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA 843 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE 844 * Are used to retrieve appropriate temperature measurements and their 845 * derivatives in [1/1000 Celsius]. 846 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE 847 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP 848 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN 849 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX 850 * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. 851 * Not applicable to _LOCALE_SYSTEM. 852 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION 853 * Is used to retrieve last GPS action for given domain. 854 * Not applicable to _LOCALE_SYSTEM. 855 * Possible return (OUT) values are: 856 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 857 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 858 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING 859 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT 860 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 861 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 862 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM 863 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM 864 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE 865 * Is used to set the power sensor simulator state. 866 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE 867 * Is used to get the power simulator sensor simulator state. 868 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA 869 * Is used to set power sensor simulator data 870 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA 871 * Is used to get power sensor simulator data 872 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK 873 * Is used to respond to the ACPI event triggered by SBIOS. RM will 874 * request value for budget and status, validate them, apply them 875 * and send ACK back to SBIOS. 876 * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT 877 * Is a test cmd that should notify SBIOS to send ACPI event requesting 878 * budget and status change. 879 */ 880 #define NV0000_CTRL_CMD_SYSTEM_GPS_INVALID (0xFFFFU) 881 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT (0x0000U) 882 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC (0x0001U) 883 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC (0x0002U) 884 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS (0x0003U) 885 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS (0x0004U) 886 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC (0x0005U) 887 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC (0x0006U) 888 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE (0x0007U) 889 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE (0x0008U) 890 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT (0x0009U) 891 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT (0x000AU) 892 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE (0x000BU) 893 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE (0x000CU) 894 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER (0x0100U) 895 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER (0x0101U) 896 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET (0x0102U) 897 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET (0x0103U) 898 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD (0x0104U) 899 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD (0x0105U) 900 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET (0x0106U) 901 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET (0x0107U) 902 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT (0x0108U) 903 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST (0x0109U) 904 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST (0x010AU) 905 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE (0x010BU) 906 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE (0x010CU) 907 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO (0x010DU) 908 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) 909 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER (0x0200U) 910 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA (0x0201U) 911 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE (0x0202U) 912 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG (0x0203U) 913 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL (0x0204U) 914 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN (0x0205U) 915 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE (0x0206U) 916 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS (0x0210U) 917 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP (0x0220U) 918 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA (0x0221U) 919 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE (0x0222U) 920 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE (0x0240U) 921 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP (0x0241U) 922 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN (0x0242U) 923 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX (0x0243U) 924 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION (0x0244U) 925 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) 926 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE (0x0250U) 927 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE (0x0251U) 928 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA (0x0252U) 929 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA (0x0253U) 930 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) 931 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT (0x0321U) 932 933 /* valid LOCALE values */ 934 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID (0xFFFFU) 935 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM (0x0000U) 936 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU(i) (0x0100+((i)%0x100)) 937 #define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU(i) (0x0200+((i)%0x100)) 938 939 /* valid data values for enums */ 940 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID (0x80000000U) 941 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO (0x00000000U) 942 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES (0x00000001U) 943 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP (0x00000000U) 944 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START (0x00000001U) 945 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF (0x00000000U) 946 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON (0x00000001U) 947 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF (0x00000000U) 948 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY (0x00000001U) 949 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) 950 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU (0x00000000U) 951 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU (0x00000001U) 952 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH (0x00000002U) 953 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) 954 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF (0x00000000U) 955 #define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON (0x00000001U) 956 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) 957 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) 958 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) 959 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT (0x00000001U) 960 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) 961 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS (0x00000004U) 962 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC (0x00000008U) 963 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC (0x00000010U) 964 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB (0x00000020U) 965 #define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) 966 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) 967 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) 968 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) 969 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) 970 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) 971 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) 972 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) 973 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) 974 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) 975 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) 976 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) 977 #define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) 978 979 /* 980 * NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL 981 * 982 * This command allows execution of multiple GpsControl commands within one 983 * RmControl call. For practical reasons # of commands is limited to 16. 984 * This command shares defines with NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL. 985 * 986 * cmdCount 987 * Number of commands that should be executed. 988 * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. 989 * 990 * succeeded 991 * Number of commands that were succesully executed. 992 * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. 993 * Failing commands return NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID 994 * in their data field. 995 * 996 * cmdData 997 * Array of commands with following structure: 998 * command 999 * This parameter specifies the command to execute. 1000 * Invalid commands result in the return of an 1001 * NV_ERR_INVALID_ARGUMENT status. 1002 * locale 1003 * This parameter indicates the specific locale to which 1004 * the command 'command' is to be applied. 1005 * Supported range of CPU/GPU {i = 0, ..., 255} 1006 * data 1007 * This parameter contains a command-specific data payload. 1008 * It is used both to input data as well as to output data. 1009 * 1010 * Possible status values returned are: 1011 * NV_OK 1012 * NV_ERR_INVALID_REQUEST 1013 * NV_ERR_NOT_SUPPORTED 1014 */ 1015 #define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL (0x123U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ 1016 1017 #define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX (16U) 1018 #define NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x23U) 1019 1020 typedef struct NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS { 1021 NvU32 cmdCount; 1022 NvU32 succeeded; 1023 1024 struct { 1025 NvU16 command; 1026 NvU16 locale; 1027 NvU32 data; 1028 } cmdData[NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX]; 1029 } NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS; 1030 1031 1032 /* 1033 * Deprecated. Please use NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 instead. 1034 */ 1035 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS (0x127U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ 1036 1037 /* 1038 * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED must remain equal to the square of 1039 * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS due to Check RM parsing issues. 1040 * NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS is the maximum size of GPU groups 1041 * allowed for batched P2P caps queries provided by the RM control 1042 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX. 1043 */ 1044 #define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS 32U 1045 #define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED 1024U 1046 #define NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS 8U 1047 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER 0xffffffffU 1048 1049 /* P2P capabilities status index values */ 1050 #define NV0000_CTRL_P2P_CAPS_INDEX_READ 0U 1051 #define NV0000_CTRL_P2P_CAPS_INDEX_WRITE 1U 1052 #define NV0000_CTRL_P2P_CAPS_INDEX_NVLINK 2U 1053 #define NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS 3U 1054 #define NV0000_CTRL_P2P_CAPS_INDEX_PROP 4U 1055 #define NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK 5U 1056 #define NV0000_CTRL_P2P_CAPS_INDEX_PCI 6U 1057 #define NV0000_CTRL_P2P_CAPS_INDEX_C2C 7U 1058 #define NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 8U 1059 1060 #define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE 9U 1061 1062 1063 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0x27U) 1064 1065 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS { 1066 NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1067 NvU32 gpuCount; 1068 NvU32 p2pCaps; 1069 NvU32 p2pOptimalReadCEs; 1070 NvU32 p2pOptimalWriteCEs; 1071 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 1072 NV_DECLARE_ALIGNED(NvP64 busPeerIds, 8); 1073 NV_DECLARE_ALIGNED(NvP64 busEgmPeerIds, 8); 1074 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS; 1075 1076 /* valid p2pCaps values */ 1077 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 0:0 1078 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE (0x00000000U) 1079 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE (0x00000001U) 1080 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1:1 1081 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE (0x00000000U) 1082 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE (0x00000001U) 1083 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 2:2 1084 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE (0x00000000U) 1085 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE (0x00000001U) 1086 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 3:3 1087 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE (0x00000000U) 1088 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE (0x00000001U) 1089 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 4:4 1090 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE (0x00000000U) 1091 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE (0x00000001U) 1092 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 5:5 1093 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE (0x00000000U) 1094 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE (0x00000001U) 1095 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 6:6 1096 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE (0x00000000U) 1097 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE (0x00000001U) 1098 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 7:7 1099 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE (0x00000000U) 1100 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE (0x00000001U) 1101 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 8:8 1102 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE (0x00000000U) 1103 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE (0x00000001U) 1104 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 9:9 1105 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE (0x00000000U) 1106 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE (0x00000001U) 1107 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 10:10 1108 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE (0x00000000U) 1109 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE (0x00000001U) 1110 1111 1112 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 12:12 1113 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE (0x00000000U) 1114 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE (0x00000001U) 1115 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED 13:13 1116 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE (0x00000000U) 1117 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE (0x00000001U) 1118 1119 /* P2P status codes */ 1120 #define NV0000_P2P_CAPS_STATUS_OK (0x00U) 1121 #define NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED (0x01U) 1122 #define NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED (0x02U) 1123 #define NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED (0x03U) 1124 #define NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY (0x04U) 1125 #define NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED (0x05U) 1126 1127 /* 1128 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 1129 * 1130 * This command returns peer to peer capabilities present between GPUs. 1131 * Valid requests must present a list of GPU Ids. 1132 * 1133 * [in] gpuIds 1134 * This member contains the array of GPU IDs for which we query the P2P 1135 * capabilities. Valid entries are contiguous, beginning with the first 1136 * entry in the list. 1137 * [in] gpuCount 1138 * This member contains the number of GPU IDs stored in the gpuIds[] array. 1139 * [out] p2pCaps 1140 * This member returns the peer to peer capabilities discovered between the 1141 * GPUs. Valid p2pCaps values include: 1142 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 1143 * When this bit is set, peer to peer writes between subdevices owned 1144 * by this device are supported. 1145 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1146 * When this bit is set, peer to peer reads between subdevices owned 1147 * by this device are supported. 1148 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 1149 * When this bit is set, peer to peer PROP between subdevices owned 1150 * by this device are supported. This is enabled by default 1151 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 1152 * When this bit is set, PCI is supported for all P2P between subdevices 1153 * owned by this device. 1154 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 1155 * When this bit is set, NVLINK is supported for all P2P between subdevices 1156 * owned by this device. 1157 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 1158 * When this bit is set, peer to peer atomics between subdevices owned 1159 * by this device are supported. 1160 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 1161 * When this bit is set, peer to peer loopback is supported for subdevices 1162 * owned by this device. 1163 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 1164 * When this bit is set, indirect peer to peer writes between subdevices 1165 * owned by this device are supported. 1166 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 1167 * When this bit is set, indirect peer to peer reads between subdevices 1168 * owned by this device are supported. 1169 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 1170 * When this bit is set, indirect peer to peer atomics between 1171 * subdevices owned by this device are supported. 1172 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 1173 * When this bit is set, indirect NVLINK is supported for subdevices 1174 * owned by this device. 1175 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 1176 * When this bit is set, C2C P2P is supported between the GPUs 1177 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_BAR1_SUPPORTED 1178 * When this bit is set, BAR1 P2P is supported between the GPUs 1179 * mentioned in @ref gpuIds 1180 * [out] p2pOptimalReadCEs 1181 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1182 * [out] p2pOptimalWriteCEs 1183 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1184 * [out] p2pCapsStatus 1185 * This member returns status of all supported p2p capabilities. Valid 1186 * status values include: 1187 * NV0000_P2P_CAPS_STATUS_OK 1188 * P2P capability is supported. 1189 * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED 1190 * Chipset doesn't support p2p capability. 1191 * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED 1192 * GPU doesn't support p2p capability. 1193 * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED 1194 * IOH topology isn't supported. For e.g. root ports are on different 1195 * IOH. 1196 * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY 1197 * P2P Capability is disabled by a regkey. 1198 * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED 1199 * P2P Capability is not supported. 1200 * NV0000_P2P_CAPS_STATUS_NVLINK_SETUP_FAILED 1201 * Indicates that NvLink P2P link setup failed. 1202 * [out] busPeerIds 1203 * Peer ID matrix. It is a one-dimentional array. 1204 * busPeerIds[X * gpuCount + Y] maps from index X to index Y in 1205 * the gpuIds[] table. For invalid or non-existent peer busPeerIds[] 1206 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 1207 * [out] busEgmPeerIds 1208 * EGM Peer ID matrix. It is a one-dimentional array. 1209 * busEgmPeerIds[X * gpuCount + Y] maps from index X to index Y in 1210 * the gpuIds[] table. For invalid or non-existent peer busEgmPeerIds[] 1211 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 1212 * 1213 * Possible status values returned are: 1214 * NV_OK 1215 * NV_ERR_INVALID_ARGUMENT 1216 * NV_ERR_INVALID_PARAM_STRUCT 1217 */ 1218 1219 1220 1221 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 (0x12bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID" */ 1222 1223 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID (0x2BU) 1224 1225 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS { 1226 NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1227 NvU32 gpuCount; 1228 NvU32 p2pCaps; 1229 NvU32 p2pOptimalReadCEs; 1230 NvU32 p2pOptimalWriteCEs; 1231 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 1232 NvU32 busPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED]; 1233 NvU32 busEgmPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED]; 1234 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS; 1235 1236 /* 1237 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX 1238 * 1239 * This command returns peer to peer capabilities present between all pairs of 1240 * GPU IDs {(a, b) : a in gpuIdGrpA and b in gpuIdGrpB}. This can be used to 1241 * collect all P2P capabilities in the system - see the SRT: 1242 * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX_TEST 1243 * for a demonstration. 1244 * 1245 * The call will query for all pairs between set A and set B, and returns 1246 * results in both link directions. The results are two-dimensional arrays where 1247 * the first dimension is the index within the set-A array of one GPU ID under 1248 * consideration, and the second dimension is the index within the set-B array 1249 * of the other GPU ID under consideration. 1250 * 1251 * That is, the result arrays are *ALWAYS* to be indexed first with the set-A 1252 * index, then with the set-B index. The B-to-A direction of results are put in 1253 * the b2aOptimal(Read|Write)CEs. This makes it unnecessary to call the query 1254 * twice, since the usual use case requires both directions. 1255 * 1256 * If a set is being compared against itself (by setting grpBCount to 0), then 1257 * the result matrices are symmetric - it doesn't matter which index is first. 1258 * However, the choice of indices is effectively a choice of which ID is "B" and 1259 * which is "A" for the "a2b" and "b2a" directional results. 1260 * 1261 * [in] grpACount 1262 * This member contains the number of GPU IDs stored in the gpuIdGrpA[] 1263 * array. Must be >= 0. 1264 * [in] grpBCount 1265 * This member contains the number of GPU IDs stored in the gpuIdGrpB[] 1266 * array. Can be == 0 to specify a check of group A against itself. 1267 * [in] gpuIdGrpA 1268 * This member contains the array of GPU IDs in "group A", each of which 1269 * will have its P2P capabilities returned with respect to each GPU ID in 1270 * "group B". Valid entries are contiguous, beginning with the first entry 1271 * in the list. 1272 * [in] gpuIdGrpB 1273 * This member contains the array of GPU IDs in "group B", each of which 1274 * will have its P2P capabilities returned with respect to each GPU ID in 1275 * "group A". Valid entries are contiguous, beginning with the first entry 1276 * in the list. May be equal to gpuIdGrpA, but best performance requires 1277 * that the caller specifies grpBCount = 0 in this case, and ignores this. 1278 * [out] p2pCaps 1279 * This member returns the peer to peer capabilities discovered between the 1280 * pairs of input GPUs between the groups, indexed by [A_index][B_index]. 1281 * Valid p2pCaps values include: 1282 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 1283 * When this bit is set, peer to peer writes between subdevices owned 1284 * by this device are supported. 1285 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1286 * When this bit is set, peer to peer reads between subdevices owned 1287 * by this device are supported. 1288 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 1289 * When this bit is set, peer to peer PROP between subdevices owned 1290 * by this device are supported. This is enabled by default 1291 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 1292 * When this bit is set, PCI is supported for all P2P between subdevices 1293 * owned by this device. 1294 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 1295 * When this bit is set, NVLINK is supported for all P2P between subdevices 1296 * owned by this device. 1297 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 1298 * When this bit is set, peer to peer atomics between subdevices owned 1299 * by this device are supported. 1300 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 1301 * When this bit is set, peer to peer loopback is supported for subdevices 1302 * owned by this device. 1303 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 1304 * When this bit is set, indirect peer to peer writes between subdevices 1305 * owned by this device are supported. 1306 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 1307 * When this bit is set, indirect peer to peer reads between subdevices 1308 * owned by this device are supported. 1309 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 1310 * When this bit is set, indirect peer to peer atomics between 1311 * subdevices owned by this device are supported. 1312 * NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 1313 * When this bit is set, indirect NVLINK is supported for subdevices 1314 * owned by this device. 1315 * [out] a2bOptimalReadCes 1316 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1317 * in the A-to-B direction. 1318 * [out] a2bOptimalWriteCes 1319 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1320 * in the A-to-B direction. 1321 * [out] b2aOptimalReadCes 1322 * For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink 1323 * in the B-to-A direction. 1324 * [out] b2aOptimalWriteCes 1325 * For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink 1326 * in the B-to-A direction. 1327 * 1328 * Possible status values returned are: 1329 * NV_OK 1330 * NV_ERR_INVALID_ARGUMENT 1331 * NV_ERR_INVALID_PARAM_STRUCT 1332 */ 1333 1334 1335 1336 #define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX (0x13aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID" */ 1337 1338 typedef NvU32 NV0000_CTRL_P2P_CAPS_MATRIX_ROW[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1339 #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID (0x3AU) 1340 1341 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS { 1342 NvU32 grpACount; 1343 NvU32 grpBCount; 1344 NvU32 gpuIdGrpA[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1345 NvU32 gpuIdGrpB[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1346 NV0000_CTRL_P2P_CAPS_MATRIX_ROW p2pCaps[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1347 NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1348 NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1349 NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1350 NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; 1351 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS; 1352 1353 /* 1354 * NV0000_CTRL_CMD_SYSTEM_GPS_CTRL 1355 * 1356 * This command is used to execute general GPS Functions, most dealing with 1357 * calling SBIOS, or retrieving cached sensor and GPS state data. 1358 * 1359 * version 1360 * This parameter specifies the version of the interface. Legal values 1361 * for this parameter are 1. 1362 * cmd 1363 * This parameter specifies the GPS API to be invoked. 1364 * Valid values for this parameter are: 1365 * NV0000_CTRL_GPS_CMD_GET_THERM_LIMIT 1366 * This command gets the temperature limit for thermal controller. When 1367 * this command is specified the input parameter contains ???. 1368 * NV0000_CTRL_GPS_CMD_SET_THERM_LIMIT 1369 * This command set the temperature limit for thermal controller. When 1370 * this command is specified the input parameter contains ???. 1371 * input 1372 * This parameter specifies the cmd-specific input value. 1373 * result 1374 * This parameter returns the cmd-specific output value. 1375 * 1376 * Possible status values returned are: 1377 * NV_OK 1378 * NV_ERR_INVALID_PARAM_STRUCT 1379 * NV_ERR_INVALID_ARGUMENT 1380 */ 1381 1382 #define NV0000_CTRL_CMD_SYSTEM_GPS_CTRL (0x12aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID" */ 1383 1384 #define NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID (0x2AU) 1385 1386 typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS { 1387 NvU32 cmd; 1388 NvS32 input[2]; 1389 NvS32 result[4]; 1390 } NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS; 1391 1392 /* valid version values */ 1393 #define NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) 1394 1395 /* valid cmd values */ 1396 #define NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) 1397 #define NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000U) 1398 #define NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT (0x00000000U) 1399 #define NV0000_CTRL_GPS_RESULT_MIN_LIMIT (0x00000001U) 1400 #define NV0000_CTRL_GPS_RESULT_MAX_LIMIT (0x00000002U) 1401 #define NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE (0x00000003U) 1402 1403 #define NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) 1404 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1405 #define NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT (0x00000001U) 1406 1407 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) 1408 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1409 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) 1410 1411 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) 1412 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1413 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) 1414 1415 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) 1416 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1417 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) 1418 1419 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) 1420 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1421 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) 1422 1423 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) 1424 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1425 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) 1426 1427 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) 1428 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1429 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) 1430 1431 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) 1432 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1433 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) 1434 1435 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) 1436 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1437 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) 1438 1439 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) 1440 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1441 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 1442 1443 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) 1444 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1445 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 1446 1447 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) 1448 #define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS (0x00000000U) 1449 1450 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) 1451 #define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS (0x00000000U) 1452 1453 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) 1454 #define NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) 1455 1456 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) 1457 #define NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) 1458 1459 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) 1460 // NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) 1461 #define NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL (0x00000001U) 1462 #define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE (0x00000000U) 1463 #define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) 1464 1465 #define NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI (0x0000001BU) 1466 #define NV0000_CTRL_GPS_INPUT_ACPI_CMD (0x00000000U) 1467 #define NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN (0x00000001U) 1468 #define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 (0x00000000U) 1469 #define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 (0x00000001U) 1470 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) 1471 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) 1472 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) 1473 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ (0x00000000U) 1474 #define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT (0x00000001U) 1475 1476 #define NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) 1477 #define NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO (0x00000000U) 1478 1479 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) 1480 #define NV0000_CTRL_GPS_INPUT_TEMP_PERIOD (0x00000000U) 1481 1482 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) 1483 #define NV0000_CTRL_GPS_RESULT_TEMP_PERIOD (0x00000000U) 1484 1485 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) 1486 #define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP (0x00000000U) 1487 #define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN (0x00000001U) 1488 1489 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) 1490 #define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP (0x00000000U) 1491 #define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN (0x00000001U) 1492 1493 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) 1494 #define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 1495 #define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 1496 1497 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) 1498 #define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 1499 #define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 1500 1501 #define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) 1502 #define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 1503 #define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 1504 1505 #define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) 1506 #define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 1507 #define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 1508 1509 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) 1510 #define NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE (0x00000000U) 1511 1512 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) 1513 #define NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE (0x00000000U) 1514 1515 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) 1516 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 1517 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) 1518 1519 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) 1520 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 1521 1522 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) 1523 #define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) 1524 1525 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) 1526 #define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) 1527 1528 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM (0x00000048U) 1529 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX (0000000000U) 1530 #define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) 1531 1532 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM (0x00000049U) 1533 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX (0000000000U) 1534 #define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX (2U) 1535 1536 #define NV0000_CTRL_GPS_PPM_INDEX 7:0 1537 #define NV0000_CTRL_GPS_PPM_INDEX_MAXPERF (0U) 1538 #define NV0000_CTRL_GPS_PPM_INDEX_BALANCED (1U) 1539 #define NV0000_CTRL_GPS_PPM_INDEX_QUIET (2U) 1540 #define NV0000_CTRL_GPS_PPM_INDEX_INVALID (0xFFU) 1541 #define NV0000_CTRL_GPS_PPM_MASK 15:8 1542 #define NV0000_CTRL_GPS_PPM_MASK_INVALID (0U) 1543 1544 /* valid PS_STATUS result values */ 1545 #define NV0000_CTRL_GPS_CMD_PS_STATUS_OFF (0U) 1546 #define NV0000_CTRL_GPS_CMD_PS_STATUS_ON (1U) 1547 1548 1549 /* 1550 * NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS 1551 * 1552 * This command allows privileged users to update the values of 1553 * security settings governing RM behavior. 1554 * 1555 * Possible status values returned are: 1556 * NV_OK 1557 * NV_ERR_INVALID_ARGUMENT, 1558 * NV_ERR_INVALID_OBJECT_HANDLE 1559 * NV_ERR_NOT_SUPPORTED 1560 * NV_ERR_INSUFFICIENT_PERMISSIONS 1561 * 1562 * Please note: as implied above, administrator privileges are 1563 * required to modify security settings. 1564 */ 1565 #define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID" */ 1566 1567 #define GPS_MAX_COUNTERS_PER_BLOCK 32U 1568 #define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID (0x29U) 1569 1570 typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { 1571 NvU32 objHndl; 1572 NvU32 blockId; 1573 NvU32 nextExpectedSampleTimems; 1574 NvU32 countersReq; 1575 NvU32 countersReturned; 1576 NvU32 counterBlock[GPS_MAX_COUNTERS_PER_BLOCK]; 1577 } NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS; 1578 1579 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 1580 1581 #define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2CU) 1582 1583 typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS; 1584 1585 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 1586 1587 #define NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x2EU) 1588 1589 typedef NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS; 1590 1591 /* 1592 * NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI 1593 * 1594 * This command allows users to call GPS ACPI commands for testing purposes. 1595 * 1596 * cmd 1597 * This parameter specifies the GPS ACPI command to execute. 1598 * 1599 * input 1600 * This parameter specified the cmd-dependent input value. 1601 * 1602 * resultSz 1603 * This parameter returns the size (in bytes) of the valid data 1604 * returned in the result parameter. 1605 * 1606 * result 1607 * This parameter returns the results of the specified cmd. 1608 * The maximum size (in bytes) of this returned data will 1609 * not exceed GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 1610 * 1611 * GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 1612 * The size of buffer (result) in unit of NvU32. 1613 * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. 1614 * Since the prior one is 24 bytes, and the later one is 48, 1615 * this value cannot be smaller than 288. 1616 * 1617 * Possible status values returned are: 1618 * NV_OK 1619 * NV_ERR_INVALID_ARGUMENT, 1620 * NV_ERR_INVALID_OBJECT_HANDLE 1621 * NV_ERR_NOT_SUPPORTED 1622 * NV_ERR_INSUFFICIENT_PERMISSIONS 1623 * 1624 */ 1625 #define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U 1626 #define NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID (0x2DU) 1627 1628 typedef struct NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS { 1629 NvU32 cmd; 1630 NvU32 input; 1631 NvU32 resultSz; 1632 NvU32 result[GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE]; 1633 } NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS; 1634 1635 #define NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI (0x12dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID" */ 1636 1637 /* 1638 * NV0000_CTRL_SYSTEM_PARAM_* 1639 * 1640 * The following is a list of system-level parameters (often sensors) that the 1641 * driver can be made aware of. They are primarily intended to be used by system 1642 * power-balancing algorithms that require system-wide visibility in order to 1643 * function. The names and values used here are established and specified in 1644 * several different NVIDIA documents that are made externally available. Thus, 1645 * updates to this list must be made with great caution. The only permissible 1646 * change is to append new parameters. Reordering is strictly prohibited. 1647 * 1648 * Brief Parameter Summary: 1649 * TGPU - GPU temperature (NvTemp) 1650 * PDTS - CPU package temperature (NvTemp) 1651 * SFAN - System fan speed (% of maximum fan speed) 1652 * SKNT - Skin temperature (NvTemp) 1653 * CPUE - CPU energy counter (NvU32) 1654 * TMP1 - Additional temperature sensor 1 (NvTemp) 1655 * TMP2 - Additional temperature sensor 2 (NvTemp) 1656 * CTGP - Mode 2 power limit offset (NvU32) 1657 * PPMD - Power mode data (NvU32) 1658 */ 1659 #define NV0000_CTRL_SYSTEM_PARAM_TGPU (0x00000000U) 1660 #define NV0000_CTRL_SYSTEM_PARAM_PDTS (0x00000001U) 1661 #define NV0000_CTRL_SYSTEM_PARAM_SFAN (0x00000002U) 1662 #define NV0000_CTRL_SYSTEM_PARAM_SKNT (0x00000003U) 1663 #define NV0000_CTRL_SYSTEM_PARAM_CPUE (0x00000004U) 1664 #define NV0000_CTRL_SYSTEM_PARAM_TMP1 (0x00000005U) 1665 #define NV0000_CTRL_SYSTEM_PARAM_TMP2 (0x00000006U) 1666 #define NV0000_CTRL_SYSTEM_PARAM_CTGP (0x00000007U) 1667 #define NV0000_CTRL_SYSTEM_PARAM_PPMD (0x00000008U) 1668 #define NV0000_CTRL_SYSTEM_PARAM_COUNT (0x00000009U) 1669 1670 /* 1671 * NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD 1672 * 1673 * This command is used to execute general ACPI methods. 1674 * 1675 * method 1676 * This parameter identifies the MXM ACPI API to be invoked. 1677 * Valid values for this parameter are: 1678 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS 1679 * This value specifies that the DSM NVOP subfunction OPTIMUSCAPS 1680 * API is to be invoked. 1681 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG 1682 * This value specifies that the DSM NVOP subfunction OPTIMUSFLAG 1683 * API is to be invoked. This API will set a Flag in sbios to Indicate 1684 * that HD Audio Controller is disable/Enabled from GPU Config space. 1685 * This flag will be used by sbios to restore Audio state after resuming 1686 * from s3/s4. 1687 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS 1688 * This value specifies that the DSM JT subfunction FUNC_CAPS is to 1689 * to be invoked to get the SBIOS capabilities 1690 * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY 1691 * This value specifies that the DSM JT subfunction FUNC_PLATPOLICY is 1692 * to be invoked to set and get the various platform policies for JT. 1693 * Refer to the JT spec in more detail on various policies. 1694 * inData 1695 * This parameter specifies the method-specific input buffer. Data is 1696 * passed to the specified API using this buffer. 1697 * inDataSize 1698 * This parameter specifies the size of the inData buffer in bytes. 1699 * outStatus 1700 * This parameter returns the status code from the associated ACPI call. 1701 * outData 1702 * This parameter specifies the method-specific output buffer. Data 1703 * is returned by the specified API using this buffer. 1704 * outDataSize 1705 * This parameter specifies the size of the outData buffer in bytes. 1706 * 1707 * Possible status values returned are: 1708 * NV_OK 1709 * NV_ERR_INVALID_PARAM_STRUCT 1710 * NV_ERR_INVALID_ARGUMENT 1711 */ 1712 1713 #define NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x130U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */ 1714 1715 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x30U) 1716 1717 typedef struct NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { 1718 NvU32 method; 1719 NV_DECLARE_ALIGNED(NvP64 inData, 8); 1720 NvU16 inDataSize; 1721 NvU32 outStatus; 1722 NV_DECLARE_ALIGNED(NvP64 outData, 8); 1723 NvU16 outDataSize; 1724 } NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS; 1725 1726 /* valid method parameter values */ 1727 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000000U) 1728 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000001U) 1729 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS (0x00000002U) 1730 #define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY (0x00000003U) 1731 /* 1732 * NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS 1733 * 1734 * This command can be used to instruct the RM to enable/disable specific module 1735 * of ETW events. 1736 * 1737 * moduleMask 1738 * This parameter specifies the module of events we would like to 1739 * enable/disable. 1740 * 1741 * Possible status values returned are: 1742 * NV_OK 1743 */ 1744 #define NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS (0x131U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID" */ 1745 1746 #define NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID (0x31U) 1747 1748 typedef struct NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS { 1749 NvU32 moduleMask; 1750 } NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS; 1751 1752 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL (0x00000001U) 1753 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ (0x00000002U) 1754 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH (0x00000004U) 1755 1756 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF (0x00000010U) 1757 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG (0x00000020U) 1758 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS (0x00000040U) 1759 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER (0x00000080U) 1760 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP (0x00000100U) 1761 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI (0x00000200U) 1762 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR (0x00000400U) 1763 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK (0x00000800U) 1764 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL (0x00001000U) 1765 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC (0x00002000U) 1766 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM (0x00004000U) 1767 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS (0x00008000U) 1768 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE (0x00010000U) 1769 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY (0x00020000U) 1770 1771 /* 1772 * NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA 1773 * 1774 * This command is used to read FRL data based on need. 1775 * 1776 * nextSampleNumber 1777 * This parameter returns the counter of next sample which is being filled. 1778 * samples 1779 * This parameter returns the frame time, render time, target time, client ID 1780 * with one reserve bit for future use. 1781 * 1782 * Possible status values returned are: 1783 * NV_OK 1784 * NV_ERR_NOT_SUPPORTED 1785 */ 1786 1787 #define NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA (0x12fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ 1788 1789 #define NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE 64U 1790 1791 typedef struct NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE { 1792 NvU16 frameTime; 1793 NvU16 renderTime; 1794 NvU16 targetTime; 1795 NvU8 sleepTime; 1796 NvU8 sampleNumber; 1797 } NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE; 1798 1799 #define NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x2FU) 1800 1801 typedef struct NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS { 1802 NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE]; 1803 NvU8 nextSampleNumber; 1804 } NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS; 1805 1806 /* 1807 * NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA 1808 * 1809 * This command is used to write FRM data based on need. 1810 * 1811 * frameTime 1812 * This parameter contains the frame time of current frame. 1813 * renderTime 1814 * This parameter contains the render time of current frame. 1815 * targetTime 1816 * This parameter contains the target time of current frame. 1817 * sleepTime 1818 * This parameter contains the sleep duration inserted by FRL for the latest frame. 1819 * 1820 * Possible status values returned are: 1821 * NV_OK 1822 * NV_ERR_NOT_SUPPORTED 1823 */ 1824 1825 #define NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA (0x132U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ 1826 1827 #define NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x32U) 1828 1829 typedef struct NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS { 1830 NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE sampleData; 1831 } NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS; 1832 1833 /* 1834 * NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO 1835 * 1836 * This command returns the current host driver, host OS and 1837 * plugin information. It is only valid when VGX is setup. 1838 * szHostDriverVersionBuffer 1839 * This field returns the host driver version (NV_VERSION_STRING). 1840 * szHostVersionBuffer 1841 * This field returns the host driver version (NV_BUILD_BRANCH_VERSION). 1842 * szHostTitleBuffer 1843 * This field returns the host driver title (NV_DISPLAY_DRIVER_TITLE). 1844 * szPluginTitleBuffer 1845 * This field returns the plugin build title (NV_DISPLAY_DRIVER_TITLE). 1846 * szHostUnameBuffer 1847 * This field returns the call of 'uname' on the host OS. 1848 * iHostChangelistNumber 1849 * This field returns the changelist value of the host driver (NV_BUILD_CHANGELIST_NUM). 1850 * iPluginChangelistNumber 1851 * This field returns the changelist value of the plugin (NV_BUILD_CHANGELIST_NUM). 1852 * 1853 * Possible status values returned are: 1854 * NV_OK 1855 * NV_ERR_INVALID_PARAM_STRUCT 1856 */ 1857 1858 #define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE 256U 1859 #define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO (0x133U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID" */ 1860 1861 #define NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID (0x33U) 1862 1863 typedef struct NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS { 1864 char szHostDriverVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1865 char szHostVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1866 char szHostTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1867 char szPluginTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1868 char szHostUnameBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; 1869 NvU32 iHostChangelistNumber; 1870 NvU32 iPluginChangelistNumber; 1871 } NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS; 1872 1873 /* 1874 * NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS 1875 * 1876 * This command returns the power status of the GPUs in the system, successfully attached or not because of 1877 * insufficient power. It is supported on Kepler and up only. 1878 * gpuCount 1879 * This field returns the count into the following arrays. 1880 * busNumber 1881 * This field returns the busNumber of a GPU. 1882 * gpuExternalPowerStatus 1883 * This field returns the corresponding external power status: 1884 * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 1885 * NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1886 * 1887 * Possible status values returned are: 1888 * NV_OK 1889 * NV_ERR_INVALID_PARAM_STRUCT 1890 * NV_ERR_NOT_SUPPORTED 1891 */ 1892 1893 #define NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS (0x134U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID" */ 1894 1895 #define NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID (0x34U) 1896 1897 typedef struct NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS { 1898 NvU8 gpuCount; 1899 NvU8 gpuBus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1900 NvU8 gpuExternalPowerStatus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 1901 } NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS; 1902 1903 /* Valid gpuExternalPowerStatus values */ 1904 #define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 0U 1905 #define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1U 1906 1907 /* 1908 * NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS 1909 * 1910 * This command returns the caller's API access privileges using 1911 * this client handle. 1912 * 1913 * privStatus 1914 * This parameter returns a mask of possible access privileges: 1915 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_USER_FLAG 1916 * The caller is running with elevated privileges 1917 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_ROOT_HANDLE_FLAG 1918 * Client is of NV01_ROOT class. 1919 * NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG 1920 * Client has PRIV bit set. 1921 * 1922 * Possible status values returned are: 1923 * NV_OK 1924 * NV_ERR_INVALID_PARAM_STRUCT 1925 */ 1926 1927 1928 #define NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS (0x135U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID" */ 1929 1930 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID (0x35U) 1931 1932 typedef struct NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS { 1933 NvU8 privStatusFlags; 1934 } NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS; 1935 1936 1937 /* Valid privStatus values */ 1938 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG (0x00000001U) 1939 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG (0x00000002U) 1940 #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG (0x00000004U) 1941 1942 /* 1943 * NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS 1944 * 1945 * The fabric manager (FM) notifies RM that fabric (system) is ready for peer to 1946 * peer (P2P) use or still initializing the fabric. This command allows clients 1947 * to query fabric status to allow P2P operations. 1948 * 1949 * Note, on systems where FM isn't used, RM just returns _SKIP. 1950 * 1951 * fabricStatus 1952 * This parameter returns current fabric status: 1953 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP 1954 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED 1955 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS 1956 * NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED 1957 * 1958 * Possible status values returned are: 1959 * NV_OK 1960 * NV_ERR_INVALID_ARGUMENT 1961 * NV_ERR_INVALID_OBJECT_HANDLE 1962 * NV_ERR_NOT_SUPPORTED 1963 * NV_ERR_INSUFFICIENT_PERMISSIONS 1964 * NV_ERR_INVALID_PARAM_STRUCT 1965 */ 1966 1967 typedef enum NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS { 1968 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = 1, 1969 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = 2, 1970 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = 3, 1971 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = 4, 1972 } NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS; 1973 1974 #define NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS (0x136U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID" */ 1975 1976 #define NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID (0x36U) 1977 1978 typedef struct NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS { 1979 NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS fabricStatus; 1980 } NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS; 1981 1982 /* 1983 * NV0000_CTRL_VGPU_GET_VGPU_VERSION_INFO 1984 * 1985 * This command is used to query the range of VGX version supported. 1986 * 1987 * host_min_supported_version 1988 * The minimum vGPU version supported by host driver 1989 * host_max_supported_version 1990 * The maximum vGPU version supported by host driver 1991 * user_min_supported_version 1992 * The minimum vGPU version set by user for vGPU support 1993 * user_max_supported_version 1994 * The maximum vGPU version set by user for vGPU support 1995 * 1996 * Possible status values returned are: 1997 * NV_OK 1998 * NV_ERR_INVALID_REQUEST 1999 */ 2000 #define NV0000_CTRL_VGPU_GET_VGPU_VERSION (0x137U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ 2001 2002 /* 2003 * NV0000_CTRL_VGPU_GET_VGPU_VERSION 2004 */ 2005 #define NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x37U) 2006 2007 typedef struct NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS { 2008 NvU32 host_min_supported_version; 2009 NvU32 host_max_supported_version; 2010 NvU32 user_min_supported_version; 2011 NvU32 user_max_supported_version; 2012 } NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS; 2013 2014 /* 2015 * NV0000_CTRL_VGPU_SET_VGPU_VERSION 2016 * 2017 * This command is used to query whether pGPU is live migration capable or not. 2018 * 2019 * min_version 2020 * The minimum vGPU version to be supported being set 2021 * max_version 2022 * The maximum vGPU version to be supported being set 2023 * 2024 * Possible status values returned are: 2025 * NV_OK 2026 * NV_ERR_INVALID_REQUEST 2027 */ 2028 #define NV0000_CTRL_VGPU_SET_VGPU_VERSION (0x138U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ 2029 2030 /* 2031 * NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS 2032 */ 2033 #define NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x38U) 2034 2035 typedef struct NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS { 2036 NvU32 min_version; 2037 NvU32 max_version; 2038 } NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS; 2039 2040 /* 2041 * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID 2042 * 2043 * This command is used to get a unique identifier for the instance of RM. 2044 * The returned value will only change when the driver is reloaded. A previous 2045 * value will never be reused on a given machine. 2046 * 2047 * rm_instance_id; 2048 * The instance ID of the current RM instance 2049 * 2050 * Possible status values returned are: 2051 * NV_OK 2052 */ 2053 #define NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID (0x139U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID" */ 2054 2055 /* 2056 * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS 2057 */ 2058 #define NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID (0x39U) 2059 2060 typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS { 2061 NV_DECLARE_ALIGNED(NvU64 rm_instance_id, 8); 2062 } NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS; 2063 2064 /* 2065 * NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO 2066 * 2067 * This API is used to get the TPP(total processing power) and 2068 * the rated TGP(total GPU power) from SBIOS. 2069 * 2070 * NVPCF is an acronym for Nvidia Platform Controllers and Framework 2071 * which implements platform level policies. NVPCF is implemented in 2072 * a kernel driver on windows. It is implemented in a user mode app 2073 * called nvidia-powerd on Linux. 2074 * 2075 * Valid subFunc ids for NVPCF 1x include : 2076 * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED 2077 * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS 2078 * 2079 * Valid subFunc ids for NVPCF 2x include : 2080 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED 2081 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS 2082 * NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES 2083 * 2084 * Possible status values returned are: 2085 * NV_OK 2086 * NV_ERR_INVALID_REQUEST 2087 * NV_ERR_NOT_SUPPORTED 2088 */ 2089 #define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */ 2090 2091 #define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU) 2092 2093 typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS { 2094 /* GPU ID */ 2095 NvU32 gpuId; 2096 2097 /* Total processing power including CPU and GPU */ 2098 NvU32 tpp; 2099 2100 /* Rated total GPU Power */ 2101 NvU32 ratedTgp; 2102 2103 /* NVPCF subfunction id */ 2104 NvU32 subFunc; 2105 2106 /* Configurable TGP offset, in mW */ 2107 NvS32 ctgpOffsetmW; 2108 2109 /* TPP, as offset in mW */ 2110 NvS32 targetTppOffsetmW; 2111 2112 /* Maximum allowed output, as offset in mW */ 2113 NvS32 maxOutputOffsetmW; 2114 2115 /* Minimum allowed output, as offset in mW */ 2116 NvS32 minOutputOffsetmW; 2117 2118 /* The System Controller Table Version */ 2119 NvU8 version; 2120 2121 /* Base sampling period */ 2122 NvU16 samplingPeriodmS; 2123 2124 /* Sampling Multiplier */ 2125 NvU16 samplingMulti; 2126 2127 /* Fitler function type */ 2128 NvU8 filterType; 2129 2130 union { 2131 2132 /* weight */ 2133 NvU8 weight; 2134 2135 /* windowSize */ 2136 NvU8 windowSize; 2137 } filterParam; 2138 2139 /* Reserved */ 2140 NvU16 filterReserved; 2141 2142 /* Controller Type Dynamic Boost Controller */ 2143 NvBool bIsBoostController; 2144 2145 /* Increase power limit ratio */ 2146 NvU16 incRatio; 2147 2148 /* Decrease power limit ratio */ 2149 NvU16 decRatio; 2150 2151 /* Dynamic Boost Controller DC Support */ 2152 NvBool bSupportBatt; 2153 2154 /* CPU type(Intel/AMD) */ 2155 NvU8 cpuType; 2156 2157 /* GPU type(Nvidia) */ 2158 NvU8 gpuType; 2159 } NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS; 2160 2161 /* Define the filter types */ 2162 #define CONTROLLER_FILTER_TYPE_EMWA 0U 2163 #define CONTROLLER_FILTER_TYPE_MOVING_MAX 1U 2164 2165 /* Valid NVPCF subfunction case */ 2166 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE 2U 2167 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE 3U 2168 2169 /* NVPCF subfunction to get the static data tables */ 2170 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE 4U 2171 2172 /* Valid NVPCF subfunction ids */ 2173 #define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED (0x00000000) 2174 #define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) 2175 2176 /* 2177 * Defines for get supported sub functions bit fields 2178 */ 2179 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0 2180 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1 2181 #define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0 2182 2183 /*! 2184 * Config DSM 2x version specific defines 2185 */ 2186 #define NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION (0x00000200) 2187 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED (0x00000000) 2188 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES (0x00000001) 2189 #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) 2190 2191 /*! 2192 * Defines the max buffer size for config 2193 */ 2194 #define NVPCF0100_CTRL_CONFIG_2X_BUFF_SIZE_MAX (255) 2195 2196 /* 2197 * NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT 2198 * 2199 * This API is used to sync the external fabric management status with 2200 * GSP-RM 2201 * 2202 * bExternalFabricMgmt 2203 * Whether fabric is externally managed 2204 * 2205 * Possible status values returned are: 2206 * NV_OK 2207 */ 2208 #define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT (0x13cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID" */ 2209 2210 #define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID (0x3CU) 2211 2212 typedef struct NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS { 2213 NvBool bExternalFabricMgmt; 2214 } NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS; 2215 2216 /* 2217 * NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO 2218 * 2219 * This API is used to get information about the RM client 2220 * database. 2221 * 2222 * clientCount [OUT] 2223 * This field indicates the number of clients currently allocated. 2224 * 2225 * resourceCount [OUT] 2226 * This field indicates the number of resources currently allocated 2227 * across all clients. 2228 * 2229 */ 2230 #define NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO (0x13dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID" */ 2231 2232 #define NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID (0x3DU) 2233 2234 typedef struct NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS { 2235 NvU32 clientCount; 2236 NV_DECLARE_ALIGNED(NvU64 resourceCount, 8); 2237 } NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS; 2238 2239 /* 2240 * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 2241 * 2242 * This command returns the current driver information in 2243 * statically sized character arrays. 2244 * 2245 * driverVersionBuffer 2246 * This field returns the version (NV_VERSION_STRING). 2247 * versionBuffer 2248 * This field returns the version (NV_BUILD_BRANCH_VERSION). 2249 * titleBuffer 2250 * This field returns the title (NV_DISPLAY_DRIVER_TITLE). 2251 * changelistNumber 2252 * This field returns the changelist value (NV_BUILD_CHANGELIST_NUM). 2253 * officialChangelistNumber 2254 * This field returns the last official changelist value 2255 * (NV_LAST_OFFICIAL_CHANGELIST_NUM). 2256 * 2257 * Possible status values returned are: 2258 * NV_OK 2259 */ 2260 2261 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE 256U 2262 #define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 (0x13eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID" */ 2263 2264 #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID (0x3EU) 2265 2266 typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS { 2267 char driverVersionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2268 char versionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2269 char titleBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE]; 2270 NvU32 changelistNumber; 2271 NvU32 officialChangelistNumber; 2272 } NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS; 2273 2274 /* 2275 * NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL 2276 * 2277 * This API is used to get/set RMCTRL cache mode 2278 * 2279 * cmd [IN] 2280 * GET - Gets RMCTRL cache mode 2281 * SET - Sets RMCTRL cache mode 2282 * 2283 * mode [IN/OUT] 2284 * On GET, this field is the output of current RMCTRL cache mode 2285 * On SET, this field indicates the mode to set RMCTRL cache to 2286 * Valid values for this parameter are: 2287 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE 2288 * No get/set action to cache. 2289 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE 2290 * Try to get from cache at the beginning of the control. 2291 * Set cache after control finished if the control has not been cached. 2292 * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY 2293 * Do not get from cache. Set cache when control call finished. 2294 * When setting the cache, verify the value in the cache is the same 2295 * with the current control value if the control is already cached. 2296 * 2297 * Possible status values returned are: 2298 * NV_OK 2299 * NV_ERR_INVALID_ARGUMENT 2300 */ 2301 #define NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL (0x13fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID" */ 2302 2303 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID (0x3FU) 2304 2305 typedef struct NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS { 2306 NvU32 cmd; 2307 NvU32 mode; 2308 } NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS; 2309 2310 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET (0x00000000U) 2311 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET (0x00000001U) 2312 2313 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE (0x00000000U) 2314 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE (0x00000001U) 2315 #define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY (0x00000002U) 2316 2317 /* 2318 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL 2319 * 2320 * This command is used to control PFM_REQ_HNDLR functionality. It allows control of 2321 * GPU Performance Scaling (PFM_REQ_HNDLR), changing its operational parameters and read 2322 * most PFM_REQ_HNDLR dynamic parameters. 2323 * 2324 * command 2325 * This parameter specifies the command to execute. Invalid commands 2326 * result in the return of an NV_ERR_INVALID_ARGUMENT status. 2327 * locale 2328 * This parameter indicates the specific locale to which the command 2329 * 'command' is to be applied. 2330 * Supported range of CPU/GPU {i = 0, ..., 255} 2331 * data 2332 * This parameter contains a command-specific data payload. It can 2333 * be used to input data as well as output data. 2334 * 2335 * Possible status values returned are: 2336 * NV_OK 2337 * NV_ERR_INVALID_COMMAND 2338 * NV_ERR_INVALID_STATE 2339 * NV_ERR_INVALID_DATA 2340 * NV_ERR_INVALID_REQUEST 2341 * NV_ERR_NOT_SUPPORTED 2342 */ 2343 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL (0x140U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID" */ 2344 2345 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID (0x40U) 2346 2347 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS { 2348 NvU16 command; 2349 NvU16 locale; 2350 NvU32 data; 2351 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS; 2352 2353 /* 2354 * Valid command values : 2355 * 2356 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT 2357 * Is used to check if PFM_REQ_HNDLR was correctly initialized. 2358 * Possible return (OUT) values are: 2359 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO 2360 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES 2361 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC 2362 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC 2363 * Are used to stop/start PFM_REQ_HNDLR functionality and to get current status. 2364 * Possible IN/OUT values are: 2365 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP 2366 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START 2367 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS 2368 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS 2369 * Are used to control execution of PFM_REQ_HNDLR actions and to get current status. 2370 * Possible IN/OUT values are: 2371 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF 2372 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON 2373 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC 2374 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC 2375 * Are used to switch current PFM_REQ_HNDLR logic and to retrieve current logic. 2376 * Possible IN/OUT values are: 2377 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF 2378 * Will cause that all PFM_REQ_HNDLR actions will be NULL. 2379 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY 2380 * Fuzzy logic will determine PFM_REQ_HNDLR actions based on current ruleset. 2381 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC 2382 * Deterministic logic will define PFM_REQ_HNDLR actions based on current ruleset. 2383 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE 2384 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE 2385 * Are used to set/retrieve system control preference. 2386 * Possible IN/OUT values are: 2387 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU 2388 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU 2389 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH 2390 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT 2391 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT 2392 * Are used to set/retrieve GPU2CPU pstate limits. 2393 * IN/OUT values are four bytes packed into a 32-bit data field. 2394 * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap 2395 * index for the GPU pstate 3 is in the highest byte, etc. One 2396 * special value is to disable the override to the GPU2CPU map: 2397 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE 2398 * Is used to stop/start PFM_REQ_HNDLR PMU functionality. 2399 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE 2400 * Is used to get the current status of PMU PFM_REQ_HNDLR. 2401 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE 2402 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER 2403 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER 2404 * Are used to set/retrieve max power [mW] that system can provide. 2405 * This is hardcoded PFM_REQ_HNDLR safety feature and logic/rules does not apply 2406 * to this threshold. 2407 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET 2408 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET 2409 * Are used to set/retrieve current system cooling budget [mW]. 2410 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD 2411 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD 2412 * Are used to set/retrieve integration interval [sec]. 2413 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET 2414 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET 2415 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT 2416 * Are used to set/retrieve used ruleset [#]. Value is checked 2417 * against MAX number of rules for currently used PFM_REQ_HNDLR logic. Also COUNT 2418 * provides a way to find out how many rules exist for the current control 2419 * system. 2420 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST 2421 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST 2422 * Is used to set/get a delay relative to now during which to allow unbound 2423 * CPU performance. Units are seconds. 2424 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE 2425 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE 2426 * Is used to override/get the actual power supply mode (AC/Battery). 2427 * Possible IN/OUT values are: 2428 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL 2429 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC 2430 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT 2431 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO 2432 * Is used to get the Ventura system information for VCT tool 2433 * Returned 32bit value should be treated as bitmask and decoded in 2434 * following way: 2435 * Encoding details are defined in objPFM_REQ_HNDLR.h refer to 2436 * NV_PFM_REQ_HNDLR_SYS_SUPPORT_INFO and corresponding bit defines. 2437 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTION 2438 * Is used to get the supported sub-functions defined in SBIOS. Returned 2439 * value is a bitmask where each bit corresponds to different function: 2440 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT 2441 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS 2442 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS 2443 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC 2444 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC 2445 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB 2446 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS 2447 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER 2448 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA 2449 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE 2450 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG 2451 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL 2452 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN 2453 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE 2454 * Are used to retrieve appropriate power measurements and their derivatives 2455 * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. 2456 * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as 2457 * index. 2458 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS 2459 * Is used to retrieve parameters when adjusting raw sensor power reading. 2460 * The values may come from SBIOS, VBIOS, registry or driver default. 2461 * Possible IN value is the index of interested parameter. 2462 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP 2463 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA 2464 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE 2465 * Are used to retrieve appropriate temperature measurements and their 2466 * derivatives in [1/1000 Celsius]. 2467 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE 2468 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP 2469 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN 2470 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX 2471 * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. 2472 * Not applicable to _LOCALE_SYSTEM. 2473 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION 2474 * Is used to retrieve last PFM_REQ_HNDLR action for given domain. 2475 * Not applicable to _LOCALE_SYSTEM. 2476 * Possible return (OUT) values are: 2477 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 2478 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 2479 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING 2480 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT 2481 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 2482 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 2483 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM 2484 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM 2485 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE 2486 * Is used to set the power sensor simulator state. 2487 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE 2488 * Is used to get the power simulator sensor simulator state. 2489 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA 2490 * Is used to set power sensor simulator data 2491 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA 2492 * Is used to get power sensor simulator data 2493 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK 2494 * Is used to respond to the ACPI event triggered by SBIOS. RM will 2495 * request value for budget and status, validate them, apply them 2496 * and send ACK back to SBIOS. 2497 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT 2498 * Is a test cmd that should notify SBIOS to send ACPI event requesting 2499 * budget and status change. 2500 */ 2501 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID (0xFFFFU) 2502 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT (0x0000U) 2503 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC (0x0001U) 2504 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC (0x0002U) 2505 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS (0x0003U) 2506 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS (0x0004U) 2507 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC (0x0005U) 2508 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC (0x0006U) 2509 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE (0x0007U) 2510 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE (0x0008U) 2511 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT (0x0009U) 2512 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT (0x000AU) 2513 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE (0x000BU) 2514 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE (0x000CU) 2515 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER (0x0100U) 2516 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER (0x0101U) 2517 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET (0x0102U) 2518 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET (0x0103U) 2519 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD (0x0104U) 2520 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD (0x0105U) 2521 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET (0x0106U) 2522 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET (0x0107U) 2523 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT (0x0108U) 2524 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST (0x0109U) 2525 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST (0x010AU) 2526 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE (0x010BU) 2527 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE (0x010CU) 2528 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO (0x010DU) 2529 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) 2530 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER (0x0200U) 2531 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA (0x0201U) 2532 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE (0x0202U) 2533 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG (0x0203U) 2534 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL (0x0204U) 2535 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN (0x0205U) 2536 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE (0x0206U) 2537 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS (0x0210U) 2538 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP (0x0220U) 2539 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA (0x0221U) 2540 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE (0x0222U) 2541 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE (0x0240U) 2542 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP (0x0241U) 2543 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN (0x0242U) 2544 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX (0x0243U) 2545 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION (0x0244U) 2546 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) 2547 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE (0x0250U) 2548 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE (0x0251U) 2549 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA (0x0252U) 2550 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA (0x0253U) 2551 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) 2552 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT (0x0321U) 2553 2554 /* valid LOCALE values */ 2555 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID (0xFFFFU) 2556 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM (0x0000U) 2557 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU(i) (0x0100+((i)%0x100)) 2558 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU(i) (0x0200+((i)%0x100)) 2559 2560 /* valid data values for enums */ 2561 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID (0x80000000U) 2562 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO (0x00000000U) 2563 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES (0x00000001U) 2564 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP (0x00000000U) 2565 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START (0x00000001U) 2566 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF (0x00000000U) 2567 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON (0x00000001U) 2568 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF (0x00000000U) 2569 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY (0x00000001U) 2570 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) 2571 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU (0x00000000U) 2572 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU (0x00000001U) 2573 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH (0x00000002U) 2574 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) 2575 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF (0x00000000U) 2576 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON (0x00000001U) 2577 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) 2578 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) 2579 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) 2580 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT (0x00000001U) 2581 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) 2582 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS (0x00000004U) 2583 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC (0x00000008U) 2584 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC (0x00000010U) 2585 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB (0x00000020U) 2586 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) 2587 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) 2588 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) 2589 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) 2590 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) 2591 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) 2592 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) 2593 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) 2594 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) 2595 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) 2596 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) 2597 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) 2598 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) 2599 2600 /* 2601 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL 2602 * 2603 * This command allows execution of multiple PFM_REQ_HNDLRControl commands within one 2604 * RmControl call. For practical reasons # of commands is limited to 16. 2605 * This command shares defines with NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL. 2606 * 2607 * cmdCount 2608 * Number of commands that should be executed. 2609 * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. 2610 * 2611 * succeeded 2612 * Number of commands that were succesully executed. 2613 * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. 2614 * Failing commands return NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID 2615 * in their data field. 2616 * 2617 * cmdData 2618 * Array of commands with following structure: 2619 * command 2620 * This parameter specifies the command to execute. 2621 * Invalid commands result in the return of an 2622 * NV_ERR_INVALID_ARGUMENT status. 2623 * locale 2624 * This parameter indicates the specific locale to which 2625 * the command 'command' is to be applied. 2626 * Supported range of CPU/GPU {i = 0, ..., 255} 2627 * data 2628 * This parameter contains a command-specific data payload. 2629 * It is used both to input data as well as to output data. 2630 * 2631 * Possible status values returned are: 2632 * NV_OK 2633 * NV_ERR_INVALID_REQUEST 2634 * NV_ERR_NOT_SUPPORTED 2635 */ 2636 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL (0x141U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ 2637 2638 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX (16U) 2639 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x41U) 2640 2641 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS { 2642 NvU32 cmdCount; 2643 NvU32 succeeded; 2644 2645 struct { 2646 NvU16 command; 2647 NvU16 locale; 2648 NvU32 data; 2649 } cmdData[NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX]; 2650 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS; 2651 2652 /* 2653 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL 2654 * 2655 * This command is used to execute general PFM_REQ_HNDLR Functions, most dealing with 2656 * calling SBIOS, or retrieving cached sensor and PFM_REQ_HNDLR state data. 2657 * 2658 * version 2659 * This parameter specifies the version of the interface. Legal values 2660 * for this parameter are 1. 2661 * cmd 2662 * This parameter specifies the PFM_REQ_HNDLR API to be invoked. 2663 * Valid values for this parameter are: 2664 * NV0000_CTRL_PFM_REQ_HNDLR_CMD_GET_THERM_LIMIT 2665 * This command gets the temperature limit for thermal controller. When 2666 * this command is specified the input parameter contains ???. 2667 * NV0000_CTRL_PFM_REQ_HNDLR_CMD_SET_THERM_LIMIT 2668 * This command set the temperature limit for thermal controller. When 2669 * this command is specified the input parameter contains ???. 2670 * input 2671 * This parameter specifies the cmd-specific input value. 2672 * result 2673 * This parameter returns the cmd-specific output value. 2674 * 2675 * Possible status values returned are: 2676 * NV_OK 2677 * NV_ERR_INVALID_PARAM_STRUCT 2678 * NV_ERR_INVALID_ARGUMENT 2679 */ 2680 2681 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL (0x142U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID" */ 2682 2683 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID (0x42U) 2684 2685 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS { 2686 NvU32 cmd; 2687 NvS32 input[2]; 2688 NvS32 result[4]; 2689 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS; 2690 2691 /* valid version values */ 2692 #define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) 2693 2694 /* valid cmd values */ 2695 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) 2696 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000U) 2697 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT (0x00000000U) 2698 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT (0x00000001U) 2699 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT (0x00000002U) 2700 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE (0x00000003U) 2701 2702 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) 2703 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2704 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT (0x00000001U) 2705 2706 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) 2707 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2708 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) 2709 2710 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) 2711 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2712 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) 2713 2714 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) 2715 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2716 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) 2717 2718 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) 2719 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2720 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) 2721 2722 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) 2723 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2724 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) 2725 2726 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) 2727 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2728 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) 2729 2730 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) 2731 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2732 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) 2733 2734 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) 2735 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2736 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) 2737 2738 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) 2739 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2740 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 2741 2742 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) 2743 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2744 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) 2745 2746 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) 2747 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS (0x00000000U) 2748 2749 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) 2750 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS (0x00000000U) 2751 2752 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) 2753 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) 2754 2755 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) 2756 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) 2757 2758 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) 2759 // NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) 2760 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL (0x00000001U) 2761 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE (0x00000000U) 2762 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) 2763 2764 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI (0x0000001BU) 2765 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD (0x00000000U) 2766 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN (0x00000001U) 2767 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 (0x00000000U) 2768 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 (0x00000001U) 2769 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) 2770 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) 2771 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) 2772 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ (0x00000000U) 2773 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT (0x00000001U) 2774 2775 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) 2776 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO (0x00000000U) 2777 2778 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) 2779 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD (0x00000000U) 2780 2781 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) 2782 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD (0x00000000U) 2783 2784 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) 2785 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP (0x00000000U) 2786 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN (0x00000001U) 2787 2788 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) 2789 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP (0x00000000U) 2790 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN (0x00000001U) 2791 2792 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) 2793 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 2794 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 2795 2796 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) 2797 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) 2798 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) 2799 2800 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) 2801 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 2802 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 2803 2804 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) 2805 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) 2806 #define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) 2807 2808 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) 2809 #define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE (0x00000000U) 2810 2811 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) 2812 #define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE (0x00000000U) 2813 2814 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) 2815 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 2816 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) 2817 2818 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) 2819 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) 2820 2821 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) 2822 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) 2823 2824 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) 2825 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) 2826 2827 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM (0x00000048U) 2828 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX (0000000000U) 2829 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) 2830 2831 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM (0x00000049U) 2832 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX (0000000000U) 2833 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX (2U) 2834 2835 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX 7:0 2836 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF (0U) 2837 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED (1U) 2838 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET (2U) 2839 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID (0xFFU) 2840 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK 15:8 2841 #define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID (0U) 2842 2843 /* valid PS_STATUS result values */ 2844 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF (0U) 2845 #define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON (1U) 2846 2847 #define PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK 32U 2848 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS { 2849 NvU32 objHndl; 2850 NvU32 blockId; 2851 NvU32 nextExpectedSampleTimems; 2852 NvU32 countersReq; 2853 NvU32 countersReturned; 2854 NvU32 counterBlock[PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK]; 2855 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS; 2856 2857 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 2858 2859 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID (0x46U) 2860 2861 typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS; 2862 2863 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID" */ 2864 2865 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID (0x47U) 2866 2867 typedef NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS; 2868 2869 /* 2870 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI 2871 * 2872 * This command allows users to call PFM_REQ_HNDLR ACPI commands for testing purposes. 2873 * 2874 * cmd 2875 * This parameter specifies the PFM_REQ_HNDLR ACPI command to execute. 2876 * 2877 * input 2878 * This parameter specified the cmd-dependent input value. 2879 * 2880 * resultSz 2881 * This parameter returns the size (in bytes) of the valid data 2882 * returned in the result parameter. 2883 * 2884 * result 2885 * This parameter returns the results of the specified cmd. 2886 * The maximum size (in bytes) of this returned data will 2887 * not exceed PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 2888 * 2889 * PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 2890 * The size of buffer (result) in unit of NvU32. 2891 * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. 2892 * Since the prior one is 24 bytes, and the later one is 48, 2893 * this value cannot be smaller than 288. 2894 * 2895 * Possible status values returned are: 2896 * NV_OK 2897 * NV_ERR_INVALID_ARGUMENT, 2898 * NV_ERR_INVALID_OBJECT_HANDLE 2899 * NV_ERR_NOT_SUPPORTED 2900 * NV_ERR_INSUFFICIENT_PERMISSIONS 2901 * 2902 */ 2903 #define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U 2904 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID (0x43U) 2905 2906 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS { 2907 NvU32 cmd; 2908 NvU32 input; 2909 NvU32 resultSz; 2910 NvU32 result[PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE]; 2911 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS; 2912 2913 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI (0x143U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID" */ 2914 2915 #define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR (0x00008000U) 2916 2917 /* 2918 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA 2919 * 2920 * This command is used to read FRL data based on need. 2921 * 2922 * nextSampleNumber 2923 * This parameter returns the counter of next sample which is being filled. 2924 * samples 2925 * This parameter returns the frame time, render time, target time, client ID 2926 * with one reserve bit for future use. 2927 * 2928 * Possible status values returned are: 2929 * NV_OK 2930 * NV_ERR_NOT_SUPPORTED 2931 */ 2932 2933 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA (0x144U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ 2934 2935 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE 64U 2936 2937 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE { 2938 NvU16 frameTime; 2939 NvU16 renderTime; 2940 NvU16 targetTime; 2941 NvU8 sleepTime; 2942 NvU8 sampleNumber; 2943 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE; 2944 2945 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x44U) 2946 2947 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS { 2948 NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE]; 2949 NvU8 nextSampleNumber; 2950 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS; 2951 2952 /* 2953 * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA 2954 * 2955 * This command is used to write FRM data based on need. 2956 * 2957 * frameTime 2958 * This parameter contains the frame time of current frame. 2959 * renderTime 2960 * This parameter contains the render time of current frame. 2961 * targetTime 2962 * This parameter contains the target time of current frame. 2963 * sleepTime 2964 * This parameter contains the sleep duration inserted by FRL for the latest frame. 2965 * 2966 * Possible status values returned are: 2967 * NV_OK 2968 * NV_ERR_NOT_SUPPORTED 2969 */ 2970 2971 #define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA (0x145U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ 2972 2973 #define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x45U) 2974 2975 typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS { 2976 NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE sampleData; 2977 } NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS; 2978 2979 /* _ctrl0000system_h_ */ 2980