1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrl0073/ctrl0073dfp.finn 31 // 32 33 #include "ctrl/ctrl0073/ctrl0073base.h" 34 #include "ctrl/ctrl0073/ctrl0073common.h" 35 36 #include "nvcfg_sdk.h" 37 38 /* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */ 39 40 /* 41 * NV0073_CTRL_CMD_DFP_GET_INFO 42 * 43 * This command can be used to determine the associated display type for 44 * the specified displayId. 45 * 46 * subDeviceInstance 47 * This parameter specifies the subdevice instance within the 48 * NV04_DISPLAY_COMMON parent device to which the operation should be 49 * directed. This parameter must specify a value between zero and the 50 * total number of subdevices within the parent device. This parameter 51 * should be set to zero for default behavior. 52 * displayId 53 * This parameter specifies the ID of the display for which the dfp 54 * caps should be returned. The display ID must be a dfp display 55 * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. 56 * If more than one displayId bit is set or the displayId is not a dfp, 57 * this call will return NV_ERR_INVALID_ARGUMENT. 58 * flags 59 * This parameter returns the information specific to this dfp. Here are 60 * the possible fields: 61 * NV0073_CTRL_DFP_FLAGS_SIGNAL 62 * This specifies the type of signal used for this dfp. 63 * NV0073_CTRL_DFP_FLAGS_LANES 64 * This specifies whether the board supports 1, 2, or 4 lanes 65 * for DISPLAYPORT signals. 66 * NV0073_CTRL_DFP_FLAGS_LIMIT 67 * Some GPUs were not qualified to run internal TMDS except at 60 HZ 68 * refresh rates. So, if LIMIT_60HZ_RR is set, then the client must 69 * make sure to only allow 60 HZ refresh rate modes to the OS/User. 70 * NV0073_CTRL_DFP_FLAGS_SLI_SCALER 71 * While running in SLI, if SLI_SCALER_DISABLE is set, the GPU cannot 72 * scale any resolutions. So, the output timing must match the 73 * memory footprint. 74 * NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 75 * This specifies whether the DFP displayId is capable of 76 * transmitting HDMI. 77 * NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 78 * This specifies whether the displayId is capable of sending a 79 * limited color range out from the board. 80 * NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 81 * This specifies whether the displayId is capable of auto-configuring 82 * the color range. 83 * NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 84 * This specifies whether the displayId is capable of sending the 85 * YCBCR422 color format out from the board. 86 * NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 87 * This specifies whether the displayId is capable of sending 88 * YCBCR444 color format out from the board. 89 * NV0073_CTRL_DFP_FLAGS_DP_LINK_BANDWIDTH 90 * This specifies max link rate supported by the displayId, if the DFP is 91 * display port. 92 * NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 93 * This specifies whether the DFP displayId is allowed to transmit HDMI 94 * based on the VBIOS settings. 95 * NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 96 * This specifies whether the DFP displayId is actually an embedded display 97 * port based on VBIOS connector information AND ASSR cap. 98 * NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 99 * This specifies whether the DFP displayId must be trained to RBR mode 100 * (if it is using DP protocol) whenever possible. 101 * NV0073_CTRL_DFP_FLAGS_LINK 102 * This specifies whether the board supports single or dual links 103 * for TMDS, LVDS, and SDI signals. 104 * NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 105 * This specifies if PostCursor2 is disabled in the VBIOS 106 * NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 107 * This indicates whether this SOR uses DSI-A, DSI-B or both (ganged mode). 108 * NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 109 * This indicates whether this DFP supports Dynamic MUX 110 * UHBRSupportedByDfp 111 * Bitmask to specify the UHBR link rates supported by this dfp. 112 * 113 * Possible status values returned are: 114 * NV_OK 115 * NV_ERR_INVALID_PARAM_STRUCT 116 * NV_ERR_INVALID_ARGUMENT 117 */ 118 #define NV0073_CTRL_CMD_DFP_GET_INFO (0x731140U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID" */ 119 120 #define NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID (0x40U) 121 122 typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS { 123 NvU32 subDeviceInstance; 124 NvU32 displayId; 125 NvU32 flags; 126 NvU32 UHBRSupportedByDfp; 127 } NV0073_CTRL_DFP_GET_INFO_PARAMS; 128 129 /* valid display types */ 130 #define NV0073_CTRL_DFP_FLAGS_SIGNAL 2:0 131 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U) 132 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U) 133 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U) 134 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U) 135 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U) 136 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U) 137 #define NV0073_CTRL_DFP_FLAGS_LANE 5:3 138 #define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U) 139 #define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U) 140 #define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U) 141 #define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U) 142 #define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U) 143 #define NV0073_CTRL_DFP_FLAGS_LIMIT 6:6 144 #define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U) 145 #define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U) 146 #define NV0073_CTRL_DFP_FLAGS_SLI_SCALER 7:7 147 #define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U) 148 #define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U) 149 #define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 8:8 150 #define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U) 151 #define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U) 152 #define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 9:9 153 #define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U) 154 #define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U) 155 #define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 10:10 156 #define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U) 157 #define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U) 158 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 11:11 159 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U) 160 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U) 161 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12 162 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U) 163 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U) 164 #define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14 165 #define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U) 166 #define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U) 167 #define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 15:15 168 #define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U) 169 #define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U) 170 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 16:16 171 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U) 172 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U) 173 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW 19:17 174 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U) 175 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U) 176 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U) 177 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U) 178 #define NV0073_CTRL_DFP_FLAGS_LINK 21:20 179 #define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U) 180 #define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U) 181 #define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U) 182 #define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID 22:22 183 #define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U) 184 #define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U) 185 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 24:23 186 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U) 187 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U) 188 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U) 189 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U) 190 #define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 25:25 191 #define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U) 192 #define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U) 193 #define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT 29:26 194 #define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30 195 #define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U) 196 #define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U) 197 198 199 200 /* 201 * NV0073_CTRL_CMD_DFP_GET_DP2TMDS_DONGLE_INFO 202 * 203 * This command can be used to determine information about dongles attached 204 * to a displayport connection. 205 * 206 * subDeviceInstance 207 * This parameter specifies the subdevice instance within the 208 * NV04_DISPLAY_COMMON parent device to which the operation should be 209 * directed. This parameter must specify a value between zero and the 210 * total number of subdevices within the parent device. This parameter 211 * should be set to zero for default behavior. 212 * displayId 213 * This parameter specifies the ID of the dfp display which owns the 214 * panel power to adjust. The display ID must be a dfp display 215 * as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command. 216 * If more than one displayId bit is set or the displayId is not a dfp, 217 * this call will return NV_ERR_INVALID_ARGUMENT. 218 * flags 219 * This parameter provide state information about the dongle attachments. 220 * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_CAPABLE 221 * Specifies if the connection is capable of a dongle. This field 222 * returns false in all cases of signal types except for those capable 223 * of outputting TMDS. Even then the if a gpio is not defined, the 224 * the a statement of false will also be returned. 225 * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_ATTACHED 226 * When attached, this value specifies that a dongle is detected and 227 * attached. The client should read the _TYPE field to determine 228 * if it is a dp2hdmi or dp2dvi dongle. 229 * NV0073_CTRL_DFP_GET_DP2TMDS_DONGLE_INFO_FLAGS_TYPE 230 * _DP2DVI: no response to i2cAddr 0x80 per DP interop guidelines. 231 * clients MUST avoid outputting HDMI even if capable. 232 * _DP2HDMI: dongle responds to i2cAddr 0x80 per DP interop guidelines. 233 * client is allowed to output HDMI when possible. 234 * _LFH_DVI: DMS59-DVI breakout dongle is in use. 235 * _LFH_VGA: DMS59-VGA breakout dongle is in use. 236 * NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE 237 * _1: Max TMDS Clock rate is 165 MHz for both DVI and HDMI. 238 * _2: Max TMDS Clock rate will be specified in the dongle 239 * address space at device address 0x80. 240 * DVI is up to 165 MHz 241 * HDMI is up to 300 MHz 242 * There are type 2 devices that support beyond 600 MHz 243 * though not defined in the spec. 244 * maxTmdsClkRateHz 245 * This defines the max TMDS clock rate for dual mode adaptor in Hz. 246 */ 247 #define NV0073_CTRL_CMD_DFP_GET_DISPLAYPORT_DONGLE_INFO (0x731142U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS_MESSAGE_ID" */ 248 249 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS_MESSAGE_ID (0x42U) 250 251 typedef struct NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS { 252 NvU32 subDeviceInstance; 253 NvU32 displayId; 254 NvU32 flags; 255 NvU32 maxTmdsClkRateHz; 256 } NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS; 257 258 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE 0:0 259 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE_FALSE (0x00000000U) 260 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_CAPABLE_TRUE (0x00000001U) 261 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED 1:1 262 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED_FALSE (0x00000000U) 263 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_ATTACHED_TRUE (0x00000001U) 264 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE 7:4 265 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_DP2DVI (0x00000000U) 266 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_DP2HDMI (0x00000001U) 267 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_LFH_DVI (0x00000002U) 268 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_TYPE_LFH_VGA (0x00000003U) 269 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE 8:8 270 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE_1 (0x00000000U) 271 #define NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_FLAGS_DP2TMDS_DONGLE_TYPE_2 (0x00000001U) 272 273 274 275 /* 276 * NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS 277 * 278 * This command is used to inform hardware the receiver's audio capabilities 279 * using the new EDID Like Data (ELD) memory structure. The ELD memory 280 * structure is read by the audio driver by issuing the ELD Data command verb. 281 * This mechanism is used for passing sink device' audio EDID information 282 * from graphics software to audio software. ELD contents will contain a 283 * subset of the sink device's EDID information. 284 * The client should inform hardware at initial boot, a modeset, and whenever 285 * a hotplug event occurs. 286 * 287 * displayId 288 * This parameter indicates the digital display device's 289 * mask. This comes as input to this command. 290 * subDeviceInstance 291 * This parameter specifies the subdevice instance within the 292 * NV04_DISPLAY_COMMON parent device to which the operation should be directed. 293 * This parameter must specify a value between zero and the total number 294 * of subdevices within the parent device. This parameter should be set 295 * to zero for default behavior. 296 * numELDSize 297 * This parameter specifies how many bytes of data RM should write to the 298 * ELD buffer. Section 7.3.3.36 of the ECN specifies that the ELD buffer 299 * size of zero based. HDAudio driver will then use this information to 300 * determine how many bytes of the ELD buffer the HDAudio should read. 301 * The maximum size of the buffer is 96 bytes. 302 * bufferELD 303 * This buffer contains data as defined in the ECR HDMI ELD memory structure. 304 * Refer to the ELD Memory Structure Specification for more details. 305 * The format should be: 306 * - Header block is fixed at 4 bytes 307 * The header block contains the ELD version and baseline ELD len as 308 * well as some reserved fields. 309 * - Baseline block for audio descriptors is 76 bytes 310 * (15 SAD; each SAD=3 bytes requiring 45 bytes with 31 bytes to spare) 311 * As well as some other bits used to denote the CEA version, 312 * the speaker allocation data, monitor name, connector type, and 313 * hdcp capabilities. 314 * - Vendor specific block of 16 bytes 315 * maxFreqSupported 316 * Supply the maximum frequency supported for the overall audio caps. 317 * This value should match CEA861-X defines for sample freq. 318 * ctrl: 319 * NV0073_CTRL_DFP_SET_ELD_AUDIO_CAPS_CTRL_PD: 320 * Specifies the presence detect of the receiver. On a hotplug 321 * or modeset client should set this bit to TRUE. 322 * NV0073_CTRL_DFP_SET_ELD_AUDIO_CAPS_CTRL_ELDV: 323 * Specifies whether the ELD buffer contents are valid. 324 * An intrinsic unsolicited response (UR) is generated whenever 325 * the ELDV bit changes in value and the PD=1. When _PD=1(hotplug), 326 * RM will set the ELDV bit after ELD buffer contents are written. 327 * If _ELDV bit is set to false such as during a unplug, then the 328 * contents of the ELD buffer will be cleared. 329 * deviceEntry: 330 * The deviceEntry number from which the SF should accept packets. 331 * _NONE if disabling audio. 332 * Possible status values returned are: 333 * NV_OK 334 * NV_ERR_INVALID_PARAM_STRUCT 335 * NV_ERR_INVALID_ARGUMENT 336 */ 337 #define NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS (0x731144U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID" */ 338 339 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER 96U 340 341 #define NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID (0x44U) 342 343 typedef struct NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS { 344 NvU32 subDeviceInstance; 345 NvU32 displayId; 346 NvU32 numELDSize; 347 NvU8 bufferELD[NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER]; 348 NvU32 maxFreqSupported; 349 NvU32 ctrl; 350 NvU32 deviceEntry; 351 } NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS; 352 353 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0320KHZ (0x00000001U) 354 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0441KHZ (0x00000002U) 355 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0480KHZ (0x00000003U) 356 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0882KHZ (0x00000004U) 357 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_0960KHZ (0x00000005U) 358 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_1764KHZ (0x00000006U) 359 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_MAX_FREQ_SUPPORTED_1920KHZ (0x00000007U) 360 361 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD 0:0 362 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_FALSE (0x00000000U) 363 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_TRUE (0x00000001U) 364 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV 1:1 365 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_FALSE (0x00000000U) 366 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_TRUE (0x00000001U) 367 368 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_0 (0x00000000U) 369 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_1 (0x00000001U) 370 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_2 (0x00000002U) 371 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_3 (0x00000003U) 372 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_NONE (0x00000007U) 373 374 375 376 /* 377 * NV0073_CTRL_CMD_DFP_GET_SPREAD_SPECTRUM_STATUS 378 * 379 * This command is used to get spread spectrum status for a display device. 380 * 381 * displayId 382 * Display ID for which the spread spectrum status is needed. 383 * checkRMSsState 384 * Default is to check in Vbios. This flag lets this control call to check in register. 385 * status 386 * Return status value. 387 */ 388 389 #define NV0073_CTRL_CMD_DFP_GET_SPREAD_SPECTRUM (0x73114cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS_MESSAGE_ID" */ 390 391 #define NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS_MESSAGE_ID (0x4CU) 392 393 typedef struct NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS { 394 NvU32 displayId; 395 NvBool enabled; 396 } NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS; 397 398 /* 399 * NV0073_CTRL_CMD_DFP_UPDATE_DYNAMIC_DFP_CACHE 400 * 401 * Update the Dynamic DFP with Bcaps read from remote display. 402 * Also updates hdcpFlags, gpu hdcp capable flags in DFP. 403 * If bResetDfp is true, all the flags are reset before making changes. 404 * 405 * Possible status values returned are: 406 * NV_OK 407 * NV_ERR_INVALID_ARGUMENT 408 * NV_ERR_NOT_SUPPORTED 409 */ 410 411 #define NV0073_CTRL_CMD_DFP_UPDATE_DYNAMIC_DFP_CACHE (0x73114eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS_MESSAGE_ID" */ 412 413 #define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS_MESSAGE_ID (0x4EU) 414 415 typedef struct NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS { 416 NvU32 subDeviceInstance; 417 NvU32 headIndex; 418 NvU8 bcaps; 419 NvU8 bksv[5]; 420 NvU32 hdcpFlags; 421 NvBool bHdcpCapable; 422 NvBool bResetDfp; 423 NvU8 updateMask; 424 } NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS; 425 426 #define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_BCAPS 0x01U 427 #define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_BKSV 0x02U 428 #define NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_MASK_FLAGS 0x03U 429 430 /* 431 * NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE 432 * 433 * This command sets the audio enable state of the DFP. When disabled, 434 * no audio stream packets or audio timestamp packets will be sent. 435 * 436 * subDeviceInstance 437 * This parameter specifies the subdevice instance within the 438 * NV04_DISPLAY_COMMON parent device to which the operation should be 439 * directed. This parameter must specify a value between zero and the 440 * total number of subdevices within the parent device. This parameter 441 * should be set to zero for default behavior. 442 * displayId 443 * This parameter specifies the ID of the display for which the dfp 444 * audio should be enabled or disabled. The display ID must be a dfp display. 445 * If the displayId is not a dfp, this call will return 446 * NV_ERR_INVALID_ARGUMENT. 447 * enable 448 * This parameter specifies whether to enable (NV_TRUE) or disable (NV_FALSE) 449 * audio to the display. 450 * 451 * Possible status values returned are: 452 * NV_OK 453 * NV_ERR_INVALID_PARAM_STRUCT 454 * NV_ERR_INVALID_ARGUMENT 455 * 456 * 457 */ 458 #define NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE (0x731150U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID" */ 459 460 #define NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID (0x50U) 461 462 typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS { 463 NvU32 subDeviceInstance; 464 NvU32 displayId; 465 NvBool enable; 466 } NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS; 467 468 469 470 /* 471 * NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG 472 * 473 * This variable specifies default/primary/secondary sor sublinks to be configured. 474 * These access modes are: 475 * 476 * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE 477 * Default link config 478 * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK 479 * Primary sor sublink to be configured 480 * NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK 481 * Secondary sor sublink to be configured 482 */ 483 typedef NvU32 NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG; 484 485 #define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_NONE (0x0U) 486 #define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_PRIMARY_SOR_LINK (0x1U) 487 #define NV0073_CTRL_DFP_ASSIGN_SOR_FORCE_SECONDARY_SOR_LINK (0x2U) 488 489 /* 490 * NV0073_CTRL_DFP_ASSIGN_SOR_INFO 491 * 492 * This structure describes info about assigned SOR 493 * 494 * displayMask 495 * The displayMask for the SOR corresponding to its HW routings 496 * sorType 497 * This parameter specifies the SOR type 498 * Here are the current defined fields: 499 * NV0073_CTRL_DFP_SOR_TYPE_NONE 500 * Unallocated SOR 501 * NV0073_CTRL_DFP_SOR_TYPE_2H1OR_PRIMARY 502 * Primary SOR for 2H1OR stream 503 * NV0073_CTRL_DFP_SOR_TYPE_2H1OR_SECONDARY 504 * Secondary SOR for 2H1OR stream 505 * NV0073_CTRL_DFP_SOR_TYPE_SINGLE 506 * Default Single SOR 507 * Note - sorType should only be referred to identify 2H1OR Primary and Secondary SOR 508 * 509 */ 510 511 typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_INFO { 512 NvU32 displayMask; 513 NvU32 sorType; 514 } NV0073_CTRL_DFP_ASSIGN_SOR_INFO; 515 516 #define NV0073_CTRL_DFP_SOR_TYPE_NONE (0x00000000U) 517 #define NV0073_CTRL_DFP_SOR_TYPE_SINGLE (0x00000001U) 518 #define NV0073_CTRL_DFP_SOR_TYPE_2H1OR_PRIMARY (0x00000002U) 519 #define NV0073_CTRL_DFP_SOR_TYPE_2H1OR_SECONDARY (0x00000003U) 520 521 /* 522 * NV0073_CTRL_CMD_DFP_ASSIGN_SOR 523 * 524 * This command is used by the clients to assign SOR to DFP for CROSS-BAR 525 * when the default SOR-DFP routing that comes from vbios is not considered. 526 * SOR shall be assigned to a DFP at the runtime. This call should be called 527 * before a modeset is done on any dfp display and also before LinkTraining for DP displays. 528 * 529 * subDeviceInstance 530 * This parameter specifies the subdevice instance within the 531 * NV04_DISPLAY_COMMON parent device to which the operation should be 532 * directed. This parameter must specify a value between zero and the 533 * total number of subdevices within the parent device. This parameter 534 * should be set to zero for default behavior. 535 * displayId 536 * DisplayId of the primary display for which SOR is to be assigned. However, if 537 * displayId is 0 then RM shall return the XBAR config it has stored in it's structures. 538 * sorExcludeMask 539 * sorMask of the SORs which should not be used for assignment. If this is 0, 540 * then SW is free to allocate any available SOR. 541 * slaveDisplayId 542 * displayId of the slave device in case of dualSST mode. This ctrl call will 543 * allocate SORs to both slave and the master if slaveDisplayId is set. 544 * forceSublinkConfig 545 * forces RM to configure primary or secondary sor sublink on the given diaplayId. 546 * If not set, then RM will do the default configurations. 547 * bIs2Head1Or 548 * Specifies that SOR allocation is required for 2 head 1 OR. This will allocate 549 * 2 SOR for same displayId - one Master and one Slave. Slave SOR would be disconnected 550 * from any padlink and get feedback clock from Master SOR's padlink. 551 * sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS] 552 * returns the displayMask for all SORs corresponding to their HW routings. 553 * sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS] 554 * returns the displayMask for all SORs corresponding to their HW routings along with 555 * SOR type to identify 2H1OR Primary and Secondary SORs. SOR type would be identified by 556 * NV0073_CTRL_DFP_SOR_TYPE. sorAssignList would look as below - 557 * sorAssignListWithTag[] = { DisplayMask, SOR Type 558 * {0x100, SECONDARY_SOR} 559 * {0x200, SINGLE_SOR} 560 * {0x100, PRIMARY_SOR} 561 * {0, NONE}} 562 * } 563 * Here, for display id = 0x100, SOR2 is Primary and SOR0 is Secondary. 564 * Note - sorAssignList parameter would be removed after Bug 200749158 is resolved 565 * reservedSorMask 566 * returns the sorMask reserved for the internal panels. 567 * flags 568 * Other detail settings. 569 * _AUDIO_OPTIMAL: Client requests trying to get audio SOR if possible. 570 * If there's no audio capable SOR and OD is HDMI/DP, 571 * RM will fail the control call. 572 * _AUDIO_DEFAULT: RM does not check audio-capability of SOR. 573 * 574 * _ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES : RM returns Active SOR which is not Audio capable. 575 * _ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO : RM is not returning 'Active non-audio capable SOR'. 576 * 577 * Possible status values returned are: 578 * NV_OK 579 * NV_ERR_INVALID_ARGUMENT 580 * NV_ERR_NOT_SUPPORTED 581 */ 582 583 584 #define NV0073_CTRL_CMD_DFP_ASSIGN_SOR (0x731152U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID" */ 585 586 #define NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS 4U 587 588 #define NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID (0x52U) 589 590 typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS { 591 NvU32 subDeviceInstance; 592 NvU32 displayId; 593 NvU8 sorExcludeMask; 594 NvU32 slaveDisplayId; 595 NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG forceSublinkConfig; 596 NvBool bIs2Head1Or; 597 NvU32 sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]; 598 NV0073_CTRL_DFP_ASSIGN_SOR_INFO sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]; 599 NvU8 reservedSorMask; 600 NvU32 flags; 601 } NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS; 602 603 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO 0:0 604 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_OPTIMAL (0x00000001U) 605 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_DEFAULT (0x00000000U) 606 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE 1:1 607 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO (0x00000000U) 608 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES (0x00000001U) 609 610 /* 611 * NV0073_CTRL_CMD_DFP_GET_PADLINK_MASK 612 * 613 * This command will only be used by chipTB tests to get the padlinks corresponding 614 * to the given displayId. RM gets this information from vbios. This control call is 615 * only for verif purpose. 616 * 617 * subDeviceInstance 618 * This parameter specifies the subdevice instance within the 619 * NV04_DISPLAY_COMMON parent device to which the operation should be 620 * directed. This parameter must specify a value between zero and the 621 * total number of subdevices within the parent device. This parameter 622 * should be set to zero for default behavior. 623 * displayId 624 * DisplayId of the display for which the client needs analog link Mask 625 * padlinkMask 626 * analogLinkMask for the given displayId. This value returned is 0xffffffff if 627 * the given displayId is invalid else RM returns the corresponding padlinkMask. 628 * NV_OK 629 * NV_ERR_INVALID_ARGUMENT 630 * NV_ERR_NOT_SUPPORTED 631 */ 632 633 634 #define NV0073_CTRL_CMD_DFP_GET_PADLINK_MASK (0x731153U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS_MESSAGE_ID" */ 635 636 #define NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS_MESSAGE_ID (0x53U) 637 638 typedef struct NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS { 639 NvU32 subDeviceInstance; 640 NvU32 displayId; 641 NvU32 padlinkMask; 642 } NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS; 643 644 /* 645 * NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE 646 * This enum defines the functions that are supported for which a 647 * corresponding GPIO pin number could be retrieved 648 * Values copied from objgpio.h GPIO_FUNC_TYPE_LCD_*. Please keep the 649 * values in sync between the 2 files 650 */ 651 652 typedef enum NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE { 653 // GPIO types of LCD GPIO functions common to all internal panels 654 NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_BACKLIGHT = 268435456, 655 NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_POWER = 285212672, 656 NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_POWER_OK = 301989888, 657 NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_SELF_TEST = 318767104, 658 NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_LAMP_STATUS = 335544320, 659 NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE_LCD_BRIGHTNESS = 352321536, 660 } NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE; 661 662 /* 663 * NV0073_CTRL_CMD_DFP_GET_LCD_GPIO_PIN_NUM 664 * 665 * This command can be used to get the GPIO pin number that corresponds to one 666 * of the LCD functions 667 * 668 * subDeviceInstance 669 * This parameter specifies the subdevice instance within the 670 * NV04_DISPLAY_COMMON parent device to which the operation should be 671 * directed. This parameter must specify a value between zero and the 672 * total number of subdevices within the parent device. This parameter 673 * should be set to zero for default behavior. 674 * displayId 675 * This parameter specifies the ID of the dfp display. 676 * If more than one displayId bit is set or the displayId is not a dfp, 677 * this call will return NVOS_STATUS_ERROR_INVALID_ARGUMENT. 678 * funcType 679 * The LDC function for which the GPIO pin number is needed 680 * lcdGpioPinNum 681 * The GPIO pin number that corresponds to the LCD function. 682 * 683 */ 684 #define NV0073_CTRL_CMD_DFP_GET_LCD_GPIO_PIN_NUM (0x731154U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS_MESSAGE_ID" */ 685 686 #define NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS_MESSAGE_ID (0x54U) 687 688 typedef struct NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS { 689 NvU32 subDeviceInstance; 690 NvU32 displayId; 691 NV0073_CTRL_CMD_DFP_LCD_GPIO_FUNC_TYPE funcType; 692 NvU32 lcdGpioPinNum; 693 } NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS; 694 695 696 697 /* 698 * NV0073_CTRL_CMD_DFP_CONFIG_TWO_HEAD_ONE_OR 699 * 700 * This command is used for configuration of 2 head 1 OR. 701 * 702 * subDeviceInstance 703 * This parameter specifies the subdevice instance within the 704 * NV04_DISPLAY_COMMON parent device to which the operation should be 705 * directed. This parameter must specify a value between zero and the 706 * total number of subdevices within the parent device. This parameter 707 * should be set to zero for default behavior. 708 * displayId 709 * Display Id of the panel for which Two Head One OR is going to be used 710 * bEnable 711 * Enable/Disable 2 Head 1 OR 712 * masterSorIdx 713 * Master SOR Index which will send pixels to panel 714 * slaveSorIdx 715 * Slave SOR Index which will take feedback clock from Master SOR's 716 * padlink 717 * Possible status values returned are: 718 * NVOS_STATUS_SUCCESS 719 * NVOS_STATUS_ERROR_INVALID_ARGUMENT 720 * NVOS_STATUS_ERROR_NOT_SUPPORTED 721 */ 722 723 724 #define NV0073_CTRL_CMD_DFP_CONFIG_TWO_HEAD_ONE_OR (0x731156U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS_MESSAGE_ID" */ 725 726 #define NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS_MESSAGE_ID (0x56U) 727 728 typedef struct NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS { 729 NvU32 subDeviceInstance; 730 NvU32 displayId; 731 NvBool bEnable; 732 NvU32 masterSorIdx; 733 NvU32 slaveSorIdx; 734 } NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS; 735 736 /* 737 * NV0073_CTRL_CMD_DFP_DSC_CRC_CONTROL 738 * 739 * This command is used to enable/disable CRC on the GPU or query the registers 740 * related to it 741 * 742 * subDeviceInstance 743 * This parameter specifies the subdevice instance within the 744 * NV04_DISPLAY_COMMON parent device to which the operation should be 745 * directed. This parameter must specify a value between zero and the 746 * total number of subdevices within the parent device. This parameter 747 * should be set to zero for default behavior. 748 * headIndex 749 * index of the head 750 * cmd 751 * specifying if setup or querying is done 752 * bEnable 753 * enable or disable CRC on the GPU 754 * gpuCrc0 755 * 0-indexed CRC register of the GPU 756 * gpuCrc1 757 * 1-indexed CRC register of the GPU 758 * gpuCrc0 759 * 2-indexed CRC register of the GPU 760 * Possible status values returned are: 761 * NVOS_STATUS_SUCCESS 762 * NVOS_STATUS_ERROR_NOT_SUPPORTED 763 */ 764 765 766 #define NV0073_CTRL_CMD_DFP_DSC_CRC_CONTROL (0x731157U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS_MESSAGE_ID" */ 767 768 #define NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS_MESSAGE_ID (0x57U) 769 770 typedef struct NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS { 771 NvU32 subDeviceInstance; 772 NvU32 headIndex; 773 NvU32 cmd; 774 NvBool bEnable; 775 NvU16 gpuCrc0; 776 NvU16 gpuCrc1; 777 NvU16 gpuCrc2; 778 } NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS; 779 780 #define NV0073_CTRL_DP_CRC_CONTROL_CMD 0:0 781 #define NV0073_CTRL_DP_CRC_CONTROL_CMD_SETUP (0x00000000U) 782 #define NV0073_CTRL_DP_CRC_CONTROL_CMD_QUERY (0x00000001U) 783 784 /* 785 * NV0073_CTRL_CMD_DFP_INIT_MUX_DATA 786 * 787 * This control call is used to configure the display MUX related data 788 * for the given display device. Clients to RM are expected to call this 789 * control call to initialize the data related to MUX before any MUX related 790 * operations such mux switch or PSR entry/ exit are performed. 791 * 792 * subDeviceInstance (in) 793 * This parameter specifies the subdevice instance within the 794 * NV04_DISPLAY_COMMON parent device to which the operation should be 795 * directed. 796 * displayId (in) 797 * ID of the display device for which the mux state has to be initialized 798 * manfId (in) 799 * Specifies the manufacturer ID of panel obtained from the EDID. This 800 * parameter is expected to be non-zero only in case of internal panel. 801 * productId (in) 802 * Specifies the product ID of panel obtained from the EDID. This 803 * parameter is expected to be non-zero only in case of internal panel. 804 * 805 * Possible status values returned are: 806 * NV_OK 807 * NV_ERR_INVALID_PARAM_STRUCT 808 * NV_ERR_INVALID_ARGUMENT 809 * NV_ERR_NOT_SUPPORTED 810 */ 811 812 #define NV0073_CTRL_CMD_DFP_INIT_MUX_DATA (0x731158U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS_MESSAGE_ID" */ 813 814 #define NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS_MESSAGE_ID (0x58U) 815 816 typedef struct NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS { 817 NvU32 subDeviceInstance; 818 NvU32 displayId; 819 NvU16 manfId; 820 NvU16 productId; 821 } NV0073_CTRL_CMD_DFP_INIT_MUX_DATA_PARAMS; 822 823 824 825 /* 826 * NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX 827 * 828 * This command is used to switch the dynamic display mux between 829 * integrated GPU and discrete GPU. 830 * 831 * subDeviceInstance (in) 832 * This parameter specifies the subdevice instance within the 833 * NV04_DISPLAY_COMMON parent device to which the operation should be 834 * directed. 835 * displayId (in) 836 * ID of the display device for which the display MUX has to be switched 837 * flags (in) 838 * Flags indicating the action to be performed. Here are the possible 839 * valid values- 840 * NV0073_CTRL_DFP_DISP_MUX_SWITCH_IGPU_TO_DGPU 841 * When set mux is switched from integrated to discrete GPU. 842 * NV0073_CTRL_DFP_DISP_MUX_SWITCH_DGPU_TO_IGPU 843 * When set mux is switched from discrete to integrated GPU. 844 * NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS 845 * Set to true for PSR panels as we skip sideband access. 846 * auxSettleDelay (in) 847 * Time, in milliseconds, necessary for AUX channel to settle and become 848 * accessible after a mux switch. Set to zero to use the default delay. 849 * muxSwitchLatencyMs (out) 850 * mux switch latency stats in milli-seconds 851 * 852 * Possible status values returned are: 853 * NV_OK 854 * NV_ERR_INVALID_PARAM_STRUCT 855 * NV_ERR_INVALID_ARGUMENT 856 * NV_ERR_NOT_SUPPORTED 857 */ 858 859 #define NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX (0x731160U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID" */ 860 861 #define NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID (0x60U) 862 863 typedef struct NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS { 864 NvU32 subDeviceInstance; 865 NvU32 displayId; 866 NvU32 flags; 867 NvU32 auxSettleDelay; 868 NvU32 muxSwitchLatencyMs; 869 } NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS; 870 871 /* valid flags*/ 872 #define NV0073_CTRL_DFP_DISP_MUX_SWITCH 0:0 873 #define NV0073_CTRL_DFP_DISP_MUX_SWITCH_IGPU_TO_DGPU 0x00000000 874 #define NV0073_CTRL_DFP_DISP_MUX_SWITCH_DGPU_TO_IGPU 0x00000001 875 #define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS 1:1 876 #define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS_YES 0x00000001 877 #define NV0073_CTRL_DFP_DISP_MUX_SWITCH_SKIP_SIDEBAND_ACCESS_NO 0x00000000 878 879 /* 880 * NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS 881 * 882 * This command is used to perform all the operations that need to be 883 * performed before a mux switch is started. 884 * 885 * subDeviceInstance (in) 886 * This parameter specifies the subdevice instance within the 887 * NV04_DISPLAY_COMMON parent device to which the operation should be 888 * directed. 889 * displayId (in) 890 * ID of the display device for which the pre mux switch operations have 891 * to be performed. 892 * flags (in) 893 * Flags indicating the action to be performed. Here are the possible 894 * valid values - 895 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU 896 * Indicates a switch from i to d is initiated 897 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU 898 * Indicates a switch from d to i is initiated 899 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_NO 900 * When set RM will execute the PSR enter sequence. By default RM will 901 * not skip SR enter sequence 902 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_YES 903 * When set RM will skip the PSR enter sequence 904 * iGpuBrightness (in) 905 * iGPU brightness value (scale 0~100) before switching mux from I2D. 906 * This is used to match brightness after switching mux to dGPU 907 * preOpsLatencyMs (out) 908 * premux switch operations latency stats in milli-seconds. This includes - 909 * - disabling SOR sequencer and enable BL GPIO control 910 * - toggling LCD VDD, BL EN and PWM MUX GPIOs 911 * - PSR entry, if not skipped 912 * psrEntryLatencyMs (out) 913 * psr entry latency stats in milli-seconds 914 * 915 * Possible status values returned are: 916 * NV_OK 917 * NV_ERR_INVALID_PARAM_STRUCT 918 * NV_ERR_INVALID_ARGUMENT 919 * NV_ERR_NOT_SUPPORTED 920 */ 921 922 #define NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS (0x731161U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID" */ 923 924 #define NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID (0x61U) 925 926 typedef struct NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS { 927 NvU32 subDeviceInstance; 928 NvU32 displayId; 929 NvU32 flags; 930 NvU32 iGpuBrightness; 931 NvU32 preOpsLatencyMs; 932 NvU32 psrEntryLatencyMs; 933 } NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS; 934 935 /* valid flags*/ 936 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE 0:0 937 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU 0x00000000U 938 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU 0x00000001U 939 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP 1:1 940 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_NO 0x00000000U 941 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_ENTER_SKIP_YES 0x00000001U 942 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING 2:2 943 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_KNOWN 0x00000000 944 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_UNKNOWN 0x00000001 945 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE 3:3 946 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE_NO 0x00000000U 947 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE_YES 0x00000001U 948 949 #define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MIN 0U 950 #define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MAX 100U 951 952 /* 953 * NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS 954 * 955 * This command is used to perform all the operations that need to be 956 * performed after a successful mux switch is completed. 957 * 958 * subDeviceInstance (in) 959 * This parameter specifies the subdevice instance within the 960 * NV04_DISPLAY_COMMON parent device to which the operation should be 961 * directed. 962 * displayId (in) 963 * ID of the display device for which the post mux switch operations have 964 * to be performed. 965 * flags (in) 966 * Flags indicating the action to be performed. Here are the possible 967 * valid values - 968 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_IGPU_TO_DGPU 969 * Indicates a switch from i to d is initiated 970 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE_DGPU_TO_IGPU 971 * Indicates a switch from d to i is initiated 972 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_NO 973 * When set RM will execute the PSR exit sequence. By default RM will 974 * not skip SR exit sequence 975 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_YES 976 * When set RM will skip the PSR exit sequence 977 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_KNOWN 978 * Indicates mux switches where we know when igpu powers up 979 * NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_UNKNOWN 980 * Indicates mux switches where we don't know when igpu powers up 981 * postOpsLatencyMs (out) 982 * postmux switch operations latency stats in milli-seconds. This includes - 983 * - restoring SOR sequencer and BL GPIO control 984 * - toggling LCD VDD, BL EN and PWM MUX GPIOs 985 * - PSR exit, if not skipped 986 * psrExitLatencyMs (out) 987 * psr exit latency stats in milli-seconds 988 * psrExitTransitionToInactiveLatencyMs (out) 989 * psr exit latency stats in milli-seconds, from state 2 (SR active) to state 4 (transition to inactive) 990 * 991 * Possible status values returned are: 992 * NV_OK 993 * NV_ERR_INVALID_PARAM_STRUCT 994 * NV_ERR_INVALID_ARGUMENT 995 * NV_ERR_NOT_SUPPORTED 996 * NV_ERR_TIMEOUT in case of SR exit failure 997 */ 998 999 #define NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS (0x731162U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID" */ 1000 1001 #define NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS_MESSAGE_ID (0x62U) 1002 1003 typedef struct NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS { 1004 NvU32 subDeviceInstance; 1005 NvU32 displayId; 1006 NvU32 flags; 1007 NvU32 postOpsLatencyMs; 1008 NvU32 psrExitLatencyMs; 1009 NvU32 psrExitTransitionToInactiveLatencyMs; 1010 } NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS; 1011 1012 /* valid flags*/ 1013 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SWITCH_TYPE 0:0 1014 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP 1:1 1015 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_NO 0x00000000U 1016 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SR_EXIT_SKIP_YES 0x00000001U 1017 1018 /* 1019 * NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS 1020 * 1021 * This command is used to query the display mux status for the given 1022 * display device 1023 * 1024 * subDeviceInstance (in) 1025 * This parameter specifies the subdevice instance within the 1026 * NV04_DISPLAY_COMMON parent device to which the operation should be 1027 * directed. 1028 * displayId (in) 1029 * ID of the display device for which the post mux switch operations have 1030 * to be performed. 1031 * muxStatus (out) 1032 * status indicating the current state of the mux. 1033 * valid values - 1034 * NV0073_CTRL_DFP_DISP_MUX_STATE_INTEGRATED_GPU 1035 * Indicates that the MUX is currently switched to integrated GPU. 1036 * NV0073_CTRL_DFP_DISP_MUX_STATE_DISCRETE_GPU 1037 * Indicates that the MUX is currently switched to discrete GPU. 1038 * NV0073_CTRL_DFP_DISP_MUX_MODE_DISCRETE_ONLY 1039 * Indicates that the MUX mode is set to discrete mode, where all displays 1040 * are driven by discrete GPU. 1041 * NV0073_CTRL_DFP_DISP_MUX_MODE_INTEGRATED_ONLY 1042 * Indicates that the MUX mode is set to integrated mode, where all 1043 * displays are driven by Integrated GPU. 1044 * NV0073_CTRL_DFP_DISP_MUX_MODE_HYBRID 1045 * Indicates that the MUX mode is set to hybrid, where internal panel is 1046 * driven by integrated GPU, while external displays might be driven by 1047 * discrete GPU. 1048 * NV0073_CTRL_DFP_DISP_MUX_MODE_DYNAMIC 1049 * Indicates that the MUX mode is dynamic. It is only in this mode, the 1050 * display MUX can be toggled between discrete and hybrid dynamically. 1051 * 1052 * Possible status values returned are: 1053 * NV_OK 1054 * NV_ERR_INVALID_PARAM_STRUCT 1055 * NV_ERR_INVALID_ARGUMENT 1056 * NV_ERR_NOT_SUPPORTED 1057 */ 1058 1059 #define NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS (0x731163U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID" */ 1060 1061 #define NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID (0x63U) 1062 1063 typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS { 1064 NvU32 subDeviceInstance; 1065 NvU32 displayId; 1066 NvU32 muxStatus; 1067 } NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS; 1068 1069 /* valid flags */ 1070 #define NV0073_CTRL_DFP_DISP_MUX_STATE 1:0 1071 #define NV0073_CTRL_DFP_DISP_MUX_STATE_INVALID 0x00000000U 1072 #define NV0073_CTRL_DFP_DISP_MUX_STATE_INTEGRATED_GPU 0x00000001U 1073 #define NV0073_CTRL_DFP_DISP_MUX_STATE_DISCRETE_GPU 0x00000002U 1074 #define NV0073_CTRL_DFP_DISP_MUX_MODE 4:2 1075 #define NV0073_CTRL_DFP_DISP_MUX_MODE_INVALID 0x00000000U 1076 #define NV0073_CTRL_DFP_DISP_MUX_MODE_INTEGRATED_ONLY 0x00000001U 1077 #define NV0073_CTRL_DFP_DISP_MUX_MODE_DISCRETE_ONLY 0x00000002U 1078 #define NV0073_CTRL_DFP_DISP_MUX_MODE_HYBRID 0x00000003U 1079 #define NV0073_CTRL_DFP_DISP_MUX_MODE_DYNAMIC 0x00000004U 1080 1081 1082 1083 /* 1084 * NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING 1085 * 1086 * This command can be used to get DSI mode timing parameters. 1087 * 1088 * subDeviceInstance 1089 * This parameter specifies the subdevice instance within the 1090 * NV04_DISPLAY_COMMON parent device to which the operation should be 1091 * directed. This parameter must specify a value between zero and the 1092 * total number of subdevices within the parent device. This parameter 1093 * should be set to zero for default behavior. 1094 * displayId 1095 * This parameter specifies the ID of the display on which the DSI 1096 * info will be set. The display ID must be a DSI-capable display. 1097 * hActive 1098 * This parameter specifies the horizontal length of the active pixel 1099 * data in the raster. 1100 * vActive 1101 * This parameter specifies the vertical lines of the active pixel 1102 * data in the raster. 1103 * hFrontPorch 1104 * This parameter specifies the number of horizontal front porch 1105 * blanking pixels in the raster. 1106 * vFrontPorch 1107 * This parameter specifies the numer of lines of the vertical front 1108 * porch in the raster. 1109 * hBackPorch 1110 * This parameter specifies the number of horizontal back porch 1111 * blanking pixels in the raster. 1112 * vBackPorch 1113 * This parameter specifies the numer of lines of the vertical back 1114 * porch in the raster. 1115 * hSyncWidth 1116 * This parameter specifies the number of horizontal sync pixels in 1117 * the raster. 1118 * vSyncWidth 1119 * This parameter specifies the numer of lines of the vertical sync 1120 * in the raster. 1121 * bpp 1122 * This parameter specifies the depth (Bits per Pixel) of the output 1123 * display stream. 1124 * refresh 1125 * This parameter specifies the refresh rate of the panel (in Hz). 1126 * pclkHz 1127 * This parameter specifies the pixel clock rate in Hz. 1128 * numLanes 1129 * Number of DSI data lanes. 1130 * dscEnable 1131 * Flag to indicate if DSC an be enabled, which in turn indicates if 1132 * panel supports DSC. 1133 * dscBpp 1134 * DSC Bits per pixel 1135 * dscNumSlices 1136 * Number of slices for DSC. 1137 * dscDuaDsc 1138 * Flag to indicate if panel supports DSC streams from two DSI 1139 * controllers. 1140 * dscSliceHeight 1141 * Height of DSC slices. 1142 * dscBlockPrediction 1143 * Flag to indicate if DSC Block Prediction needs to be enabled. 1144 * dscDecoderVersionMajor 1145 * Major version number of DSC decoder on Panel. 1146 * dscDecoderVersionMinor 1147 * Minor version number of DSC decoder on Panel. 1148 * dscUseCustomPPS 1149 * Flag to indicate if Panel uses custom PPS values which deviate from standard values. 1150 * dscCustomPPSData 1151 * 32 bytes of custom PPS data required by Panel. 1152 * dscEncoderCaps 1153 * Capabilities of DSC encoder in SoC. 1154 * 1155 * Possible status values returned are: 1156 * NV_OK 1157 * NV_ERR_INVALID_ARGUMENT 1158 * NV_ERR_NOT_SUPPORTED 1159 */ 1160 1161 #define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING (0x731166U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID" */ 1162 1163 #define NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT 32U 1164 1165 #define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID (0x66U) 1166 1167 typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS { 1168 NvU32 subDeviceInstance; 1169 NvU32 displayId; 1170 NvU32 hActive; 1171 NvU32 vActive; 1172 NvU32 hFrontPorch; 1173 NvU32 vFrontPorch; 1174 NvU32 hBackPorch; 1175 NvU32 vBackPorch; 1176 NvU32 hSyncWidth; 1177 NvU32 vSyncWidth; 1178 NvU32 bpp; 1179 NvU32 refresh; 1180 NvU32 pclkHz; 1181 NvU32 numLanes; 1182 NvU32 dscEnable; 1183 NvU32 dscBpp; 1184 NvU32 dscNumSlices; 1185 NvU32 dscDualDsc; 1186 NvU32 dscSliceHeight; 1187 NvU32 dscBlockPrediction; 1188 NvU32 dscDecoderVersionMajor; 1189 NvU32 dscDecoderVersionMinor; 1190 NvBool dscUseCustomPPS; 1191 NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT]; 1192 NV0073_CTRL_CMD_DSC_CAP_PARAMS dscEncoderCaps; 1193 } NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS; 1194 1195 1196 1197 /* 1198 * NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING 1199 * 1200 * This control call is used to retrieve the display mode timing info that's 1201 * specified for a given DFP from an offline configuration blob (e.g., Device Tree). 1202 * This display timing info is intended to replace the timings exposed in a 1203 * sink's EDID. 1204 * 1205 * subDeviceInstance (in) 1206 * This parameter specifies the subdevice instance within the 1207 * NV04_DISPLAY_COMMON parent device to which the operation should be 1208 * directed. 1209 * displayId (in) 1210 * ID of the display device for which the timings should be retrieved. 1211 * stream (in) 1212 * For MST connectors with static topologies (e.g., DP serializers), 1213 * this parameter further identifies the video stream for which the 1214 * timings should be retrieved. 1215 * valid (out) 1216 * Indicates whether a valid display timing was found for this DFP. 1217 * hActive (out) 1218 * Horizontal active width in pixels 1219 * hFrontPorch (out) 1220 * Horizontal front porch 1221 * hSyncWidth (out) 1222 * Horizontal sync width 1223 * hBackPorch (out) 1224 * Horizontal back porch 1225 * vActive (out) 1226 * Vertical active height in lines 1227 * vFrontPorch (out) 1228 * Vertical front porch 1229 * vSyncWidth (out) 1230 * Vertical sync width 1231 * vBackPorch (out) 1232 * Vertical back porch 1233 * pclkKHz (out) 1234 * Pixel clock frequency in KHz 1235 * rrx1k (out) 1236 * Refresh rate in units of 0.001Hz 1237 * x (out) 1238 * x offset inside superframe at which this view starts 1239 * y (out) 1240 * y offset inside superframe at which this view starts 1241 * width (out) 1242 * Horizontal active width in pixels for this view 1243 * height (out) 1244 * Vertical active height in lines for this view 1245 * 1246 * Possible status values returned are: 1247 * NV_OK 1248 * NV_ERR_INVALID_ARGUMENT 1249 * NV_ERR_NOT_SUPPORTED 1250 */ 1251 #define NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING (0x731172) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8 | NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID)" */ 1252 1253 #define NV0073_CTRL_DFP_FIXED_MODE_TIMING_MAX_SUPERFRAME_VIEWS 4U 1254 1255 #define NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID (0x72U) 1256 1257 typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS { 1258 NvU32 subDeviceInstance; 1259 NvU32 displayId; 1260 NvU8 stream; 1261 1262 NvBool valid; 1263 1264 NvU16 hActive; 1265 NvU16 hFrontPorch; 1266 NvU16 hSyncWidth; 1267 NvU16 hBackPorch; 1268 1269 NvU16 vActive; 1270 NvU16 vFrontPorch; 1271 NvU16 vSyncWidth; 1272 NvU16 vBackPorch; 1273 1274 NvU32 pclkKHz; 1275 NvU32 rrx1k; 1276 1277 struct { 1278 NvU8 numViews; 1279 struct { 1280 NvU16 x; 1281 NvU16 y; 1282 NvU16 width; 1283 NvU16 height; 1284 } view[NV0073_CTRL_DFP_FIXED_MODE_TIMING_MAX_SUPERFRAME_VIEWS]; 1285 } superframeInfo; 1286 } NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS; 1287 1288 1289 1290 /* 1291 * NV0073_CTRL_CMD_DFP_EDP_DRIVER_UNLOAD 1292 * 1293 * This command is called when we want to inform RM of driver 1294 * unload. 1295 * 1296 * subDeviceInstance (in) 1297 * This parameter specifies the subdevice instance within the 1298 * NV04_DISPLAY_COMMON parent device to which the operation 1299 * should be directed. 1300 * displayId (in) 1301 * This parameter inputs the displayId of the active display. A value 1302 * of zero indicates no display is active. 1303 * 1304 * Possible status values returned are: 1305 * NV_OK 1306 * NV_ERR_INVALID_PARAM_STRUCT 1307 * NV_ERR_INVALID_ARGUMENT 1308 * NV_ERR_NOT_SUPPORTED 1309 */ 1310 #define NV0073_CTRL_CMD_DFP_EDP_DRIVER_UNLOAD (0x731174U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS_MESSAGE_ID" */ 1311 1312 #define NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS_MESSAGE_ID (0x74U) 1313 1314 typedef struct NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS { 1315 NvU32 subDeviceInstance; 1316 NvU32 displayId; 1317 } NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS; 1318 1319 /* _ctrl0073dfp_h_ */ 1320