1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrl2080/ctrl2080bus.finn 31 // 32 33 #include "nvcfg_sdk.h" 34 #include "ctrl/ctrl2080/ctrl2080base.h" 35 36 /* NV20_SUBDEVICE_XX bus control commands and parameters */ 37 38 /** 39 * NV2080_CTRL_CMD_BUS_GET_PCI_INFO 40 * 41 * This command returns PCI bus identifier information for the specified GPU. 42 * 43 * pciDeviceId 44 * This parameter specifies the internal PCI device and vendor 45 * identifiers for the GPU. 46 * pciSubSystemId 47 * This parameter specifies the internal PCI subsystem identifier for 48 * the GPU. 49 * pciRevisionId 50 * This parameter specifies the internal PCI device-specific revision 51 * identifier for the GPU. 52 * pciExtDeviceId 53 * This parameter specifies the external PCI device identifier for 54 * the GPU. It contains only the 16-bit device identifier. This 55 * value is identical to the device identifier portion of 56 * pciDeviceId since non-transparent bridges are no longer supported. 57 * 58 * Possible status values returned are: 59 * NV_OK 60 * NV_ERR_INVALID_PARAM_STRUCT 61 * NV_ERR_INVALID_ARGUMENT 62 */ 63 #define NV2080_CTRL_CMD_BUS_GET_PCI_INFO (0x20801801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID" */ 64 65 #define NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1U) 66 67 typedef struct NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS { 68 NvU32 pciDeviceId; 69 NvU32 pciSubSystemId; 70 NvU32 pciRevisionId; 71 NvU32 pciExtDeviceId; 72 } NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS; 73 74 /* 75 * NV2080_CTRL_BUS_INFO 76 * 77 * This structure represents a single 32bit bus engine value. Clients 78 * request a particular bus engine value by specifying a unique bus 79 * information index. 80 * 81 * Legal bus information index values are: 82 * NV2080_CTRL_BUS_INFO_INDEX_TYPE 83 * This index is used to request the bus type of the GPU. 84 * Legal return values for this index are: 85 * NV2080_CTRL_BUS_INFO_TYPE_PCI 86 * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS 87 * NV2080_CTRL_BUS_INFO_TYPE_FPCI 88 * NV2080_CTRL_BUS_INFO_INDEX_INTLINE 89 * This index is used to request the interrupt line (or irq) assignment 90 * for the GPU. The return value is system-dependent. 91 * NV2080_CTRL_BUS_INFO_INDEX_CAPS 92 * This index is used to request the bus engine capabilities for the GPU. 93 * The return value is specified as a mask of capabilities. 94 * Legal return values for this index are: 95 * NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH 96 * NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED 97 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS 98 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS 99 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS 100 * These indices are used to request PCI Express link-specific 101 * capabilities values. A value of zero is returned for non-PCIE GPUs. 102 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS 103 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS 104 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS 105 * These indices are used to request PCI Express link-specific 106 * control status values. A value of zero is returned for non-PCIE GPUs. 107 * NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS 108 * This index is used to request coherent dma transfer flags. 109 * Valid coherent dma transfer flags include: 110 * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA 111 * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART 112 * NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS 113 * This index is used to request noncoherent dma transfer flags. 114 * Valid noncoherent dma transfer flags include: 115 * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA 116 * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART 117 * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE 118 * NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE 119 * This index is used to request the size of the GPU GART in MBytes. 120 * NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS 121 * This index is used to request GPU GART flags. 122 * Valid gart flags include: 123 * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH 124 * This flag indicates that GPU GART clients need to do an explicit 125 * flush via an appropriate SetContextDma method. 126 * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED 127 * This flag indicates that the GART address range includes both 128 * system and video memory. 129 * NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER 130 * This index is used to request the PCI-based bus number of the GPU. 131 * Support for this index is platform-dependent. 132 * NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER 133 * This index is used to request the PCI-based device number of the GPU. 134 * Support for this index is platform-dependent. 135 * NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER 136 * This index is used to request the PCI-based domain number of the GPU. 137 * Support for this index is platform-dependent. 138 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS 139 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS 140 * These indices are used to request PCI Express error status. 141 * The current status is cleared as part of these requests. 142 * Valid PCI Express error status values include: 143 * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR 144 * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR 145 * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR 146 * NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST 147 * NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE 148 * This index is used to request the bus interface type of the GPU. 149 * Legal return values for this index are: 150 * NV2080_CTRL_BUS_INFO_TYPE_PCI 151 * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS 152 * NV2080_CTRL_BUS_INFO_TYPE_FPCI 153 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO // DEPRECATED 154 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO // REPLACES "GEN2" variant 155 * This index is used to retrieve PCI Express Gen configuration support 156 * This index is used to retrieve PCI Express Gen2 configuration support 157 * for the GPU. 158 * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1 159 * The GPU is PCI Express Gen1 capable. 160 * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2 161 * The GPU is PCI Express Gen2 capable. 162 * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 163 * The GPU is PCI Express Gen3 capable. 164 * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 165 * The GPU is PCI Express Gen4 capable. 166 * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 167 * The GPU is PCI Express Gen5 capable. 168 * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 169 * The GPU is configured in PCI Express Gen1 mode. 170 * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 171 * The GPU is configured in PCI Express Gen2 mode. 172 * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 173 * The GPU is configured in PCI Express Gen3 mode. 174 * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 175 * The GPU is configured in PCI Express Gen4 mode. 176 * NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 177 * The GPU is configured in PCI Express Gen5 mode. 178 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER 179 * This index retrieves PCI Express Advanced Error Reporting (AER) errors 180 * for the GPU. 181 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS 182 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS 183 * This index retrieves the PCI Express link capabilities for the 184 * board. For example, a Quadro FX4700X2 has two GPUs and PCIe 185 * switch. With this board, this index returns the link 186 * capabilities of the PCIe switch. In a single GPU board, this 187 * index returns the link capabilities of the GPU. A value of 188 * zero is returned for non-PCIE GPUs. 189 * UPSTREAM_LINK_CAPS is kept for backwards compatibility. 190 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS 191 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS 192 * This index retrieves the PCI Express link status for the board. 193 * For example, a Quadro FX4700X2 has two GPUs and PCIe switch. 194 * With this board, this index returns the link capabilities of 195 * the PCIe switch. In a single GPU board, this index returns the 196 * link status of the GPU. A value of zero is returned for 197 * non-PCIE GPUs. 198 * UPSTREAM_LINK_CTRL_STATUS is kept for backwards compatibility. 199 * NV2080_CTRL_BUS_INFO_INDEX_ASLM_STATUS 200 * This index is used to request the PCI Express ASLM settings. 201 * This index is only valid when NV2080_CTRL_BUS_INFO_TYPE indicates PCIE. 202 * A value of zero is returned for non-PCI Express bus type. 203 * _ASLM_STATUS_PCIE is always _PRESENT if PCI Express bus type. 204 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT 205 * This index is used to get the ASLM switching error count. 206 * A value of zero will be returned if no errors occurs while 207 * ASLM switching 208 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_SWITCH_ERROR_COUNT 209 * This index is used to get the Gen1<-->Gen2 switching error count 210 * A value of zero will be returned in case speed change from Gen1 to 211 * Gen2 is clean or if chipset is not gen2 capable or if gen1<-->gen2 212 * switching is disabled. 213 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM 214 * This index is used to get the ASPM CYA L0s\L1 enable\disable status. 215 * Legal return value is specified as a mask of valid and data field 216 * possible return values are: 217 * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO 218 * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES 219 * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED 220 * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S 221 * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1 222 * NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1 223 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS 224 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS 225 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED 226 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS 227 * These indices are used to request detailed PCI Express error counters. 228 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR 229 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR 230 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR 231 * NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR 232 * These indices are used to clear detailed PCI Express error counters. 233 * NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE 234 * This index is used to request the internal interface type of the GPU. 235 * Legal return values for this index are: 236 * NV2080_CTRL_BUS_INFO_TYPE_PCI 237 * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS 238 * NV2080_CTRL_BUS_INFO_TYPE_FPCI 239 * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE 240 * This index queries the type of sysmem connection to CPU 241 * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE 242 * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK 243 * NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C 244 * 245 */ 246 247 typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_BUS_INFO; 248 249 /* valid bus info index values */ 250 251 /** 252 * This index is used to request the bus type of the GPU. 253 * Legal return values for this index are: 254 * NV2080_CTRL_BUS_INFO_TYPE_PCI 255 * NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS 256 * NV2080_CTRL_BUS_INFO_TYPE_FPCI 257 */ 258 #define NV2080_CTRL_BUS_INFO_INDEX_TYPE (0x00000000) 259 #define NV2080_CTRL_BUS_INFO_INDEX_INTLINE (0x00000001) 260 #define NV2080_CTRL_BUS_INFO_INDEX_CAPS (0x00000002) 261 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS (0x00000003) 262 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS (0x00000004) 263 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS (0x00000005) 264 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS (0x00000006) 265 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS (0x00000007) 266 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS (0x00000008) 267 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS (0x00000009) 268 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS (0x0000000A) 269 /** 270 * This index is used to request coherent dma transfer flags. 271 * Valid coherent dma transfer flags include: 272 * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA 273 * NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART 274 */ 275 #define NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS (0x0000000B) 276 /** 277 * This index is used to request noncoherent dma transfer flags. 278 * Valid noncoherent dma transfer flags include: 279 * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA 280 * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART 281 * NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE 282 */ 283 #define NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS (0x0000000C) 284 /** 285 * This index is used to request the size of the GPU GART in MBytes. 286 */ 287 #define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE (0x0000000D) 288 /** 289 * This index is used to request GPU GART flags. 290 * Valid gart flags include: 291 * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH 292 * This flag indicates that GPU GART clients need to do an explicit 293 * flush via an appropriate SetContextDma method. 294 * NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED 295 * This flag indicates that the GART address range includes both 296 * system and video memory. 297 */ 298 #define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS (0x0000000E) 299 #define NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER (0x0000000F) 300 #define NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER (0x00000010) 301 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS (0x00000011) 302 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS (0x00000012) 303 #define NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE (0x00000013) 304 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO (0x00000014) 305 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER (0x00000015) 306 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS (0x00000016) 307 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS (0x00000017) 308 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_ASLM_STATUS (0x00000018) 309 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT (0x00000019) 310 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_SPEED_SWITCH_ERROR_COUNT (0x0000001A) 311 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM (0x0000001B) 312 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS (0x0000001C) 313 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS (0x0000001D) 314 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED (0x0000001E) 315 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS (0x0000001F) 316 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR (0x00000020) 317 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR (0x00000021) 318 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR (0x00000022) 319 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR (0x00000023) 320 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS (0x00000024) 321 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS (0x00000025) 322 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS (0x00000026) 323 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS (0x00000027) 324 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS_CLEAR (0x00000028) 325 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS_CLEAR (0x00000029) 326 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS_CLEAR (0x0000002A) 327 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS_CLEAR (0x0000002B) 328 #define NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER (0x0000002C) 329 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO (0x0000002D) 330 #define NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE (0x0000002E) 331 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_GEN_INFO (0x0000002F) 332 #define NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_GEN_INFO (0x00000030) 333 #define NV2080_CTRL_BUS_INFO_INDEX_MSI_INFO (0x00000031) 334 /** 335 * This index is used to request the top 32 bits of the size of the GPU 336 * GART in MBytes. 337 */ 338 #define NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI (0x00000032) 339 #define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE (0x00000033) 340 #define NV2080_CTRL_BUS_INFO_INDEX_MAX NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE 341 #define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE (0x00000034) 342 343 /* valid bus info type return values */ 344 #define NV2080_CTRL_BUS_INFO_TYPE_PCI (0x00000001) 345 #define NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS (0x00000003) 346 #define NV2080_CTRL_BUS_INFO_TYPE_FPCI (0x00000004) 347 #define NV2080_CTRL_BUS_INFO_TYPE_AXI (0x00000008) 348 349 /* valid bus capability flags */ 350 #define NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH (0x00000001) 351 #define NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED (0x00000002) 352 353 /* 354 * Format of PCIE link caps return values 355 * Note that Link Capabilities register format is followed only for bits 11:0 356 */ 357 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED 3:0 358 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_2500MBPS (0x00000001) 359 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_5000MBPS (0x00000002) 360 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS (0x00000003) 361 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS (0x00000004) 362 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS (0x00000005) 363 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS (0x00000006) 364 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_WIDTH 9:4 365 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM 11:10 366 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE (0x00000000) 367 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S (0x00000001) 368 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S_L1 (0x00000003) 369 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN 15:12 370 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1 (0x00000000) 371 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2 (0x00000001) 372 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 (0x00000002) 373 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 (0x00000003) 374 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 (0x00000004) 375 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6 (0x00000005) 376 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL 19:16 377 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 (0x00000000) 378 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 (0x00000001) 379 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 (0x00000002) 380 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 (0x00000003) 381 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 (0x00000004) 382 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6 (0x00000005) 383 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN 23:20 384 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1 (0x00000000) 385 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2 (0x00000001) 386 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3 (0x00000002) 387 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4 (0x00000003) 388 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5 (0x00000004) 389 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6 (0x00000005) 390 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES 24:24 391 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED (0x00000000) 392 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED (0x00000001) 393 394 /* format of PCIE control status return values */ 395 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM 1:0 396 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_DISABLED (0x00000000) 397 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S (0x00000001) 398 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L1 (0x00000002) 399 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S_L1 (0x00000003) 400 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED 19:16 401 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_2500MBPS (0x00000001) 402 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_5000MBPS (0x00000002) 403 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS (0x00000003) 404 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS (0x00000004) 405 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS (0x00000005) 406 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS (0x00000006) 407 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH 25:20 408 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED (0x00000000) 409 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1 (0x00000001) 410 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X2 (0x00000002) 411 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X4 (0x00000004) 412 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X8 (0x00000008) 413 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X12 (0x0000000C) 414 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X16 (0x00000010) 415 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X32 (0x00000020) 416 417 /* coherent dma transfer flags */ 418 #define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA 0:0 419 #define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_FALSE (0x00000000) 420 #define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_TRUE (0x00000001) 421 #define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART 2:2 422 #define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_FALSE (0x00000000) 423 #define NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_TRUE (0x00000001) 424 425 /* noncoherent dma transfer flags */ 426 #define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA 0:0 427 #define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_FALSE (0x00000000) 428 #define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_TRUE (0x00000001) 429 #define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART 2:2 430 #define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_FALSE (0x00000000) 431 #define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_TRUE (0x00000001) 432 #define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE 3:3 433 #define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_FALSE (0x00000000) 434 #define NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_TRUE (0x00000001) 435 436 /* GPU GART flags */ 437 #define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH 0:0 438 #define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_FALSE (0x00000000) 439 #define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_TRUE (0x00000001) 440 #define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED 1:1 441 #define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_FALSE (0x00000000) 442 #define NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_TRUE (0x00000001) 443 444 /* format of PCIE errors return values */ 445 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR (0x00000001) 446 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR (0x00000002) 447 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR (0x00000004) 448 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST (0x00000008) 449 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY (0x00000010) 450 451 /* PCIE Gen2 capability and current level */ 452 #define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP 0:0 453 #define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_FALSE (0x00000000) 454 #define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_TRUE (0x00000001) 455 #define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL 1:1 456 #define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN1 (0x00000000) 457 #define NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN2 (0x00000001) 458 459 /* format of PCIE AER return values */ 460 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_TRAINING_ERR (0x00000001) 461 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR (0x00000002) 462 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP (0x00000004) 463 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_FC_PROTO_ERR (0x00000008) 464 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT (0x00000010) 465 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_ABORT (0x00000020) 466 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL (0x00000040) 467 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_RCVR_OVERFLOW (0x00000080) 468 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP (0x00000100) 469 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_ECRC_ERROR (0x00000200) 470 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ (0x00000400) 471 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR (0x00010000) 472 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP (0x00020000) 473 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP (0x00040000) 474 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER (0x00080000) 475 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT (0x00100000) 476 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL (0x00200000) 477 478 /* format of PCIE ASLM status return value */ 479 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE 0:0 480 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_ERROR (0x00000000) 481 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_PRESENT (0x00000001) 482 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED 1:1 483 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_NO (0x00000000) 484 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_YES (0x00000001) 485 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE 2:2 486 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_NO (0x00000000) 487 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_YES (0x00000001) 488 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED 3:3 489 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_NO (0x00000000) 490 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_YES (0x00000001) 491 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04 4:4 492 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_MISSING (0x00000000) 493 #define NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_PRESENT (0x00000001) 494 495 /* format of GPU CYA CAPS return value */ 496 #define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID 0:0 497 #define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO (0x00000000) 498 #define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES (0x00000001) 499 #define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM 2:1 500 #define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED (0x00000000) 501 #define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S (0x00000001) 502 #define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1 (0x00000002) 503 #define NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1 (0x00000003) 504 505 /* format of MSI INFO return value */ 506 #define NV2080_CTRL_BUS_INFO_MSI_STATUS 0:0 507 #define NV2080_CTRL_BUS_INFO_MSI_STATUS_DISABLED (0x00000000) 508 #define NV2080_CTRL_BUS_INFO_MSI_STATUS_ENABLED (0x00000001) 509 510 /*format of L1PM Substates capabilities information */ 511 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED 0:0 512 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_YES (0x00000001) 513 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_NO (0x00000000) 514 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED 1:1 515 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_YES (0x00000001) 516 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_NO (0x00000000) 517 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED 2:2 518 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_YES (0x00000001) 519 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_NO (0x00000000) 520 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED 3:3 521 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_YES (0x00000001) 522 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_NO (0x00000000) 523 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED 4:4 524 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_YES (0x00000001) 525 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_NO (0x00000000) 526 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_RESERVED 7:5 527 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PORT_RESTORE_TIME 15:8 528 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_SCALE 17:16 529 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_VALUE 23:19 530 531 /*format of L1 PM Substates Control 1 Register */ 532 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED 0:0 533 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_YES (0x00000001) 534 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_NO (0x00000000) 535 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED 1:1 536 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_YES (0x00000001) 537 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_NO (0x00000000) 538 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED 2:2 539 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_YES (0x00000001) 540 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_NO (0x00000000) 541 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED 3:3 542 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_YES (0x00000001) 543 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_NO (0x00000000) 544 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_COMMON_MODE_RESTORE_TIME 15:8 545 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_VALUE 25:16 546 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_SCALE 31:29 547 548 /*format of L1 PM Substates Control 2 Register */ 549 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_SCALE 1:0 550 #define NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_VALUE 7:3 551 552 /* valid sysmem connection type values */ 553 #define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE (0x00000000) 554 #define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK (0x00000001) 555 #define NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C (0x00000002) 556 557 /** 558 * NV2080_CTRL_CMD_BUS_GET_INFO 559 * 560 * This command returns bus engine information for the associated GPU. 561 * Requests to retrieve bus information use a list of one or more 562 * NV2080_CTRL_BUS_INFO structures. 563 * 564 * busInfoListSize 565 * This field specifies the number of entries on the caller's 566 * busInfoList. 567 * busInfoList 568 * This field specifies a pointer in the caller's address space 569 * to the buffer into which the bus information is to be returned. 570 * This buffer must be at least as big as busInfoListSize multiplied 571 * by the size of the NV2080_CTRL_BUS_INFO structure. 572 * 573 * Possible status values returned are: 574 * NV_OK 575 * NV_ERR_INVALID_PARAM_STRUCT 576 * NV_ERR_INVALID_ARGUMENT 577 * NV_ERR_OPERATING_SYSTEM 578 */ 579 #define NV2080_CTRL_CMD_BUS_GET_INFO (0x20801802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID" */ 580 581 #define NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID (0x2U) 582 583 typedef struct NV2080_CTRL_BUS_GET_INFO_PARAMS { 584 NvU32 busInfoListSize; 585 NV_DECLARE_ALIGNED(NvP64 busInfoList, 8); 586 } NV2080_CTRL_BUS_GET_INFO_PARAMS; 587 588 #define NV2080_CTRL_CMD_BUS_GET_INFO_V2 (0x20801823) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID" */ 589 590 #define NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID (0x23U) 591 592 typedef struct NV2080_CTRL_BUS_GET_INFO_V2_PARAMS { 593 NvU32 busInfoListSize; 594 NV2080_CTRL_BUS_INFO busInfoList[NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE]; 595 } NV2080_CTRL_BUS_GET_INFO_V2_PARAMS; 596 597 /* 598 * NV2080_CTRL_BUS_PCI_BAR_INFO 599 * 600 * This structure describes PCI bus BAR information. 601 * 602 * flags 603 * This field contains any flags for the associated BAR. 604 * barSize 605 * This field contains the size in megabytes of the associated BAR. 606 * DEPRECATED, please use barSizeBytes. 607 * barSizeBytes 608 * This field contains the size in bytes of the associated BAR. 609 * barOffset 610 * This field contains the PCI bus offset in bytes of the associated BAR. 611 */ 612 typedef struct NV2080_CTRL_BUS_PCI_BAR_INFO { 613 NvU32 flags; 614 NvU32 barSize; 615 NV_DECLARE_ALIGNED(NvU64 barSizeBytes, 8); 616 NV_DECLARE_ALIGNED(NvU64 barOffset, 8); 617 } NV2080_CTRL_BUS_PCI_BAR_INFO; 618 619 /* 620 * NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO 621 * 622 * This command returns PCI bus BAR information. 623 * 624 * barCount 625 * This field returns the number of BARs for the associated subdevice. 626 * Legal values for this parameter will be between one to 627 * NV2080_CTRL_BUS_MAX_BARS. 628 * barInfo 629 * This field returns per-BAR information in the form of an array of 630 * NV2080_CTRL_BUS_PCI_BAR_INFO structures. Information for as many as 631 * NV2080_CTRL_BUS_MAX_PCI_BARS will be returned. Any unused entries will 632 * be initialized to zero. 633 * 634 * Possible status values returned are: 635 * NV_OK 636 * NV_ERR_INVALID_PARAM_STRUCT 637 */ 638 #define NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO (0x20801803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID" */ 639 640 /* maximum number of BARs per subdevice */ 641 #define NV2080_CTRL_BUS_MAX_PCI_BARS (8) 642 643 #define NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID (0x3U) 644 645 typedef struct NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS { 646 NvU32 pciBarCount; 647 NV_DECLARE_ALIGNED(NV2080_CTRL_BUS_PCI_BAR_INFO pciBarInfo[NV2080_CTRL_BUS_MAX_PCI_BARS], 8); 648 } NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS; 649 650 /* 651 * NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH 652 * 653 * This command sets PCI-E link width to the specified new value. 654 * 655 * pcieLinkWidth 656 * This field specifies the new PCI-E link width. 657 * 658 * failingReason 659 * This field specifies the reason why the change of link width fails. 660 * It is valid only when this routine returns NV_ERR_GENERIC. 661 * 662 * Possible status values returned are: 663 * NV_OK 664 * NV_ERR_INVALID_PARAM_STRUCT 665 * NV_ERR_INVALID_ARGUMENT 666 * NV_ERR_NOT_SUPPORTED 667 * NV_ERR_GENERIC 668 */ 669 #define NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH (0x20801804) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID" */ 670 671 #define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID (0x4U) 672 673 typedef struct NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS { 674 NvU32 pcieLinkWidth; 675 NvU32 failingReason; 676 } NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS; 677 678 #define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PSTATE (0x00000001) 679 #define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PCIE_CFG_ACCESS (0x00000002) 680 #define NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_TRAINING (0x00000004) 681 682 /* 683 * NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED 684 * 685 * This command Initiates a change in PCIE Bus Speed 686 * 687 * busSpeed 688 * This field is the target speed to train to. 689 * Legal values for this parameter are: 690 * NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS 691 * NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS 692 * NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS 693 * NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS 694 * NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS 695 * 696 * Possible status values returned are: 697 * NV_OK 698 * NV_ERR_INVALID_ARGUMENT 699 */ 700 #define NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED (0x20801805) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID" */ 701 702 #define NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID (0x5U) 703 704 typedef struct NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS { 705 NvU32 busSpeed; 706 } NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS; 707 708 #define NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS (0x00000001) 709 #define NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS (0x00000002) 710 #define NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS (0x00000003) 711 #define NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS (0x00000004) 712 #define NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS (0x00000005) 713 #define NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS (0x00000006) 714 715 /* 716 * NV2080_CTRL_CMD_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED 717 * 718 * This command Initiates a change in PCIE Bus Speed for a HWBC device's upstream 719 * link. 720 * 721 * busSpeed 722 * This field specifies the target speed to which to train. 723 * Legal values for this parameter are: 724 * NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS 725 * NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS 726 * primaryBus 727 * This field is the PCI Express Primary Bus number that uniquely identifies 728 * a HWBC device's upstream port, i.e. the BR04 Upstream Port. 729 * 730 * Possible status values returned are: 731 * NV_OK 732 * NV_ERR_INVALID_ARGUMENT 733 */ 734 #define NV2080_CTRL_CMD_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED (0x20801806) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID" */ 735 736 #define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID (0x6U) 737 738 typedef struct NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS { 739 NvU32 busSpeed; 740 NvU8 primaryBus; 741 } NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS; 742 743 #define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_2500MBPS (0x00000001) 744 #define NV2080_CTRL_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED_5000MBPS (0x00000002) 745 746 /* 747 * NV2080_CTRL_CMD_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED 748 * 749 * This command gets the current PCIE Bus Speed for a HWBC device's upstream 750 * link. 751 * 752 * primaryBus 753 * This field is the PCI Express Primary Bus number that uniquely identifies 754 * a HWBC device's upstream port, i.e. the BR04 Upstream Port. 755 * busSpeed 756 * This field specifies a pointer in the caller's address space 757 * to the NvU32 variable into which the bus speed is to be returned. 758 * On success, this parameter will contain one of the following values: 759 * NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS 760 * NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS 761 * 762 * Possible status values returned are: 763 * NV_OK 764 * NV_ERR_INVALID_ARGUMENT 765 */ 766 #define NV2080_CTRL_CMD_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED (0x20801807) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID" */ 767 768 #define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS_MESSAGE_ID (0x7U) 769 770 typedef struct NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS { 771 NvU32 busSpeed; 772 NvU8 primaryBus; 773 } NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_PARAMS; 774 775 #define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_2500MBPS (0x00000001) 776 #define NV2080_CTRL_BUS_GET_HWBC_UPSTREAM_PCIE_SPEED_5000MBPS (0x00000002) 777 778 /* 779 * NV2080_CTRL_CMD_BUS_MAP_BAR2 780 * 781 * This command sets up BAR2 page tables for passed-in memory handle. 782 * This command MUST be executed before NV2080_CTRL_CMD_BUS_UNMAP_BAR2 783 * or NV2080_CTRL_CMD_BUS_VERIFY_BAR2. Not supported on SLI. 784 * 785 * hMemory 786 * This field is a handle to physical memory. 787 * 788 * Possible status values returned are 789 * NV_OK 790 * NV_ERR_INVALID_ARGUMENT 791 * NV_ERR_NOT_SUPPORTED 792 * 793 */ 794 #define NV2080_CTRL_CMD_BUS_MAP_BAR2 (0x20801809) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID" */ 795 796 #define NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID (0x9U) 797 798 typedef struct NV2080_CTRL_BUS_MAP_BAR2_PARAMS { 799 NvHandle hMemory; 800 } NV2080_CTRL_BUS_MAP_BAR2_PARAMS; 801 802 /* 803 * NV2080_CTRL_CMD_BUS_UNMAP_BAR2 804 * 805 * This command unmaps any pending BAR2 page tables created with 806 * NV2080_CTRL_CMD_BUS_MAP_BAR2 command. The handle passed in must 807 * match the handle used to map the page tables. Not supported on SLI. 808 * 809 * hMemory 810 * This field is a handle to physical memory. 811 * 812 * Possible status values returned are 813 * NV_OK 814 * NV_ERR_INVALID_ARGUMENT 815 * NV_ERR_NOT_SUPPORTED 816 * 817 */ 818 #define NV2080_CTRL_CMD_BUS_UNMAP_BAR2 (0x2080180a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID" */ 819 820 #define NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID (0xAU) 821 822 typedef struct NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS { 823 NvHandle hMemory; 824 } NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS; 825 826 /* 827 * NV2080_CTRL_CMD_BUS_VERIFY_BAR2 828 * 829 * This command tests BAR2 against BAR0 if there are BAR2 page tables 830 * set up with NV2080_CTRL_CMD_BUS_MAP_BAR2 command. The handle passed 831 * in must match the handle used to map the page tables. Not supported on SLI. 832 * 833 * hMemory 834 * This field is a handle to physical memory. 835 * offset 836 * Base offset of the surface where the test will make its first dword write. 837 * size 838 * Test will write '(size/4)*4' bytes starting at surface offset `offset'. 839 * 840 * Possible status values returned are 841 * NV_OK 842 * NV_ERR_INVALID_ARGUMENT 843 * NV_ERR_NOT_SUPPORTED 844 * 845 */ 846 #define NV2080_CTRL_CMD_BUS_VERIFY_BAR2 (0x2080180b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID" */ 847 848 #define NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID (0xBU) 849 850 typedef struct NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS { 851 NvHandle hMemory; 852 NvU32 offset; 853 NvU32 size; 854 } NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS; 855 856 /* 857 * NV2080_CTRL_CMD_BUS_HWBC_GET_UPSTREAM_BAR0 858 * 859 * This command gets the BAR0 for a HWBC device's upstream port. 860 * 861 * primaryBus 862 * This field is the PCI Express Primary Bus number that uniquely identifies 863 * a HWBC device's upstream port, i.e. the BR04 Upstream Port. 864 * physBAR0 865 * This field returns the BAR0 physical address of the HWBC device's 866 * upstream port. 867 * 868 * Possible status values returned are: 869 * NV_OK 870 * NV_ERR_INVALID_ARGUMENT 871 */ 872 #define NV2080_CTRL_CMD_BUS_HWBC_GET_UPSTREAM_BAR0 (0x2080180e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS_MESSAGE_ID" */ 873 874 #define NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS_MESSAGE_ID (0xEU) 875 876 typedef struct NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS { 877 NV_DECLARE_ALIGNED(NvU64 physBAR0, 8); 878 NvU8 primaryBus; 879 } NV2080_CTRL_BUS_HWBC_GET_UPSTREAM_BAR0_PARAMS; 880 881 /* 882 * NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE 883 * This command would reports the current Audio device power state or Sets new power state. 884 * 885 * command 886 * This parametrer specifies the target GPU multifunction state. 887 * NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE Enables the multi function state 888 * NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE Disables the multi function state. 889 * NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE Get the Current device power state. 890 * 891 * Possible status values returned are: 892 * NV_OK 893 * NV_ERR_GENERIC 894 */ 895 896 #define NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE (0x20801812) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID" */ 897 898 #define NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID (0x12U) 899 900 typedef struct NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS { 901 NvU8 command; 902 NvU32 deviceState; 903 } NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS; 904 905 #define NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE (0x00000000) 906 #define NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE (0x00000001) 907 #define NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE (0x00000002) 908 909 /* 910 * NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS 911 * This command gets the counts for different counter types. 912 * 913 * pexCounterMask 914 * This parameter specifies the input mask for desired counter types. 915 * 916 * pexTotalCorrectableErrors 917 * This parameter gives the total correctable errors which includes 918 * NV_XVE_ERROR_COUNTER1 plus LCRC Errors, 8B10B Errors, NAKS and Failed L0s 919 * 920 * pexCorrectableErrors 921 * This parameter only includes NV_XVE_ERROR_COUNTER1 value. 922 * 923 * pexTotalNonFatalErrors 924 * This parameter returns total Non-Fatal Errors which may or may not 925 * include Correctable Errors. 926 * 927 * pexTotalFatalErrors 928 * This parameter returns Total Fatal Errors 929 * 930 * pexTotalUnsupportedReqs 931 * This parameter returns Total Unsupported Requests 932 * 933 * pexErrors 934 * This array contains the error counts for each error type as requested from 935 * the pexCounterMask. The array indexes correspond to the mask bits one-to-one. 936 */ 937 938 #define NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS (0x20801813) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID" */ 939 940 #define NV2080_CTRL_PEX_MAX_COUNTER_TYPES 31 941 #define NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x13U) 942 943 typedef struct NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS { 944 NvU32 pexCounterMask; 945 NvU32 pexTotalCorrectableErrors; 946 NvU16 pexCorrectableErrors; 947 NvU8 pexTotalNonFatalErrors; 948 NvU8 pexTotalFatalErrors; 949 NvU8 pexTotalUnsupportedReqs; 950 NvU16 pexCounters[NV2080_CTRL_PEX_MAX_COUNTER_TYPES]; 951 } NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS; 952 953 /* 954 * Note that MAX_COUNTER_TYPES will need to be updated each time 955 * a new counter type gets added to the list below. The value 956 * depends on the bits set for the last valid define. Look 957 * at pexCounters[] comments above for details. 958 * 959 */ 960 #define NV2080_CTRL_BUS_PEX_COUNTER_TYPE 0x00000000 961 #define NV2080_CTRL_BUS_PEX_COUNTER_RECEIVER_ERRORS 0x00000001 962 #define NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_COUNT 0x00000002 963 #define NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_ROLLOVER_COUNT 0x00000004 964 #define NV2080_CTRL_BUS_PEX_COUNTER_BAD_DLLP_COUNT 0x00000008 965 #define NV2080_CTRL_BUS_PEX_COUNTER_BAD_TLP_COUNT 0x00000010 966 #define NV2080_CTRL_BUS_PEX_COUNTER_8B10B_ERRORS_COUNT 0x00000020 967 #define NV2080_CTRL_BUS_PEX_COUNTER_SYNC_HEADER_ERRORS_COUNT 0x00000040 968 #define NV2080_CTRL_BUS_PEX_COUNTER_LCRC_ERRORS_COUNT 0x00000080 969 #define NV2080_CTRL_BUS_PEX_COUNTER_FAILED_L0S_EXITS_COUNT 0x00000100 970 #define NV2080_CTRL_BUS_PEX_COUNTER_NAKS_SENT_COUNT 0x00000200 971 #define NV2080_CTRL_BUS_PEX_COUNTER_NAKS_RCVD_COUNT 0x00000400 972 #define NV2080_CTRL_BUS_PEX_COUNTER_LANE_ERRORS 0x00000800 973 #define NV2080_CTRL_BUS_PEX_COUNTER_L1_TO_RECOVERY_COUNT 0x00001000 974 #define NV2080_CTRL_BUS_PEX_COUNTER_L0_TO_RECOVERY_COUNT 0x00002000 975 #define NV2080_CTRL_BUS_PEX_COUNTER_RECOVERY_COUNT 0x00004000 976 #define NV2080_CTRL_BUS_PEX_COUNTER_CHIPSET_XMIT_L0S_ENTRY_COUNT 0x00008000 977 #define NV2080_CTRL_BUS_PEX_COUNTER_GPU_XMIT_L0S_ENTRY_COUNT 0x00010000 978 #define NV2080_CTRL_BUS_PEX_COUNTER_L1_ENTRY_COUNT 0x00020000 979 #define NV2080_CTRL_BUS_PEX_COUNTER_L1P_ENTRY_COUNT 0x00040000 980 #define NV2080_CTRL_BUS_PEX_COUNTER_DEEP_L1_ENTRY_COUNT 0x00080000 981 #define NV2080_CTRL_BUS_PEX_COUNTER_ASLM_COUNT 0x00100000 982 #define NV2080_CTRL_BUS_PEX_COUNTER_TOTAL_CORR_ERROR_COUNT 0x00200000 983 #define NV2080_CTRL_BUS_PEX_COUNTER_CORR_ERROR_COUNT 0x00400000 984 #define NV2080_CTRL_BUS_PEX_COUNTER_NON_FATAL_ERROR_COUNT 0x00800000 985 #define NV2080_CTRL_BUS_PEX_COUNTER_FATAL_ERROR_COUNT 0x01000000 986 #define NV2080_CTRL_BUS_PEX_COUNTER_UNSUPP_REQ_COUNT 0x02000000 987 #define NV2080_CTRL_BUS_PEX_COUNTER_L1_1_ENTRY_COUNT 0x04000000 988 #define NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ENTRY_COUNT 0x08000000 989 #define NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ABORT_COUNT 0x10000000 990 #define NV2080_CTRL_BUS_PEX_COUNTER_L1SS_TO_DEEP_L1_TIMEOUT_COUNT 0x20000000 991 #define NV2080_CTRL_BUS_PEX_COUNTER_L1_SHORT_DURATION_COUNT 0x40000000 992 993 /* 994 * NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTER_COUNTERS 995 * This command gets the counts for different counter types. 996 * 997 * pexCounterMask 998 * This parameter specifies the input mask for desired counters to be 999 * cleared. Note that all counters cannot be cleared. 1000 */ 1001 1002 #define NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTERS (0x20801814) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID" */ 1003 1004 #define NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x14U) 1005 1006 typedef struct NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS { 1007 NvU32 pexCounterMask; 1008 } NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS; 1009 1010 /* 1011 * NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS 1012 * This command gets the counts for different counter types. 1013 * 1014 * pexCounterMask 1015 * This parameter specifies the input mask for desired counters to be 1016 * freezed. Note that all counters cannot be frozen. 1017 * 1018 * bFreezeRmCounter 1019 * This parameter decides whether API will freeze it or unfreeze it. 1020 * NV_TRUE for freeze and NV_FALSE for unfreeze. 1021 */ 1022 1023 #define NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS (0x20801815) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID" */ 1024 1025 #define NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID (0x15U) 1026 1027 typedef struct NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS { 1028 NvU32 pexCounterMask; 1029 NvBool bFreezeRmCounter; 1030 } NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS; 1031 1032 /* 1033 * NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS 1034 * This command gets the per Lane Counters and the type of errors. 1035 * 1036 * pexLaneErrorStatus 1037 * This mask specifies the type of error detected on any of the Lanes. 1038 * 1039 * pexLaneCounter 1040 * This array gives the counters per Lane. Each index corresponds to Lane 1041 * index + 1 1042 */ 1043 1044 #define NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS (0x20801816) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID" */ 1045 1046 #define NV2080_CTRL_PEX_MAX_LANES 16 1047 #define NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID (0x16U) 1048 1049 typedef struct NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS { 1050 NvU16 pexLaneErrorStatus; 1051 NvU8 pexLaneCounter[NV2080_CTRL_PEX_MAX_LANES]; 1052 } NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS; 1053 1054 #define NV2080_CTRL_BUS_PEX_COUNTER_LANE_TYPE 0x00000000 1055 #define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_CODING_ERR 0x00000001 1056 #define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_ORDER_ERR 0x00000002 1057 #define NV2080_CTRL_BUS_PEX_COUNTER_LANE_OS_DATA_SEQ_ERR 0x00000004 1058 #define NV2080_CTRL_BUS_PEX_COUNTER_LANE_TSX_DATA_SEQ_ERR 0x00000008 1059 #define NV2080_CTRL_BUS_PEX_COUNTER_LANE_SKPOS_LFSR_ERR 0x00000010 1060 #define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RX_CLK_FIFO_OVERFLOW 0x00000020 1061 #define NV2080_CTRL_BUS_PEX_COUNTER_LANE_ELASTIC_FIFO_OVERFLOW 0x00000040 1062 #define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LINK_NUM_ERR 0x00000080 1063 #define NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LANE_NUM_ERR 0x00000100 1064 1065 #define NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY (0x20801817) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID" */ 1066 1067 #define NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID (0x17U) 1068 1069 typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS { 1070 NvBool bPexLtrRegkeyOverride; 1071 NvBool bPexRootPortLtrSupported; 1072 NvBool bPexGpuLtrSupported; 1073 NvU16 pexLtrSnoopLatencyValue; 1074 NvU8 pexLtrSnoopLatencyScale; 1075 NvU16 pexLtrNoSnoopLatencyValue; 1076 NvU8 pexLtrNoSnoopLatencyScale; 1077 } NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS; 1078 1079 #define NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY (0x20801818) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID" */ 1080 1081 #define NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID (0x18U) 1082 1083 typedef struct NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS { 1084 NvU16 pexLtrSnoopLatencyValue; 1085 NvU8 pexLtrSnoopLatencyScale; 1086 NvU16 pexLtrNoSnoopLatencyValue; 1087 NvU8 pexLtrNoSnoopLatencyScale; 1088 } NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS; 1089 1090 /* 1091 * NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS 1092 * This command gets the counts for different counter types. 1093 * 1094 * pexCounterMask 1095 * This parameter specifies the input mask for desired counter types. 1096 * 1097 */ 1098 #define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_BYTES 0x00000001 1099 #define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_BYTES 0x00000002 1100 #define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0 0x00000004 1101 #define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0 0x00000008 1102 #define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0S 0x00000010 1103 #define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0S 0x00000020 1104 #define NV2080_CTRL_BUS_PEX_UTIL_COUNTER_NON_L0_L0S 0x00000040 1105 #define NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES 7 1106 1107 #define NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS (0x20801819) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID" */ 1108 1109 #define NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID (0x19U) 1110 1111 typedef struct NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS { 1112 NvU32 pexCounterMask; 1113 NvU32 pexCounters[NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES]; 1114 } NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS; 1115 1116 /* 1117 * NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTER_COUNTERS 1118 * This command gets the counts for different counter types. 1119 * 1120 * pexCounterMask 1121 * This parameter specifies the input mask for desired counters to be 1122 * cleared. Note that all counters cannot be cleared. 1123 * 1124 * NOTE: EX_UTIL_COUNTER_UPSTREAM & NV2080_CTRL_BUS_PEX_UTIL_COUNTER_DOWNSTREAM 1125 * belongs to PMU. The ctrl function will not reset nor disable/enable them. 1126 */ 1127 #define NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTERS (0x20801820) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID" */ 1128 1129 #define NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID (0x20U) 1130 1131 typedef struct NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS { 1132 NvU32 pexCounterMask; 1133 } NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS; 1134 1135 #define NV2080_CTRL_CMD_BUS_GET_BFD (0x20801821) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID" */ 1136 1137 typedef struct NV2080_CTRL_BUS_GET_BFD_PARAMS { 1138 NvBool valid; 1139 NvU16 deviceID; 1140 NvU16 vendorID; 1141 NvU32 domain; 1142 NvU16 bus; 1143 NvU16 device; 1144 NvU8 function; 1145 } NV2080_CTRL_BUS_GET_BFD_PARAMS; 1146 1147 #define NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID (0x21U) 1148 1149 typedef struct NV2080_CTRL_BUS_GET_BFD_PARAMSARR { 1150 NV2080_CTRL_BUS_GET_BFD_PARAMS params[32]; 1151 } NV2080_CTRL_BUS_GET_BFD_PARAMSARR; 1152 1153 /* 1154 * NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS 1155 * This command gets the following mentioned PDB Properties 1156 * 1157 * aspmDisableFlags[] 1158 * NvBool array stores each of the properties' state. the array size can 1159 * be increased as per requirement. 1160 * 1161 * NOTE: When adding more properties, increment NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS. 1162 */ 1163 1164 #define NV2080_CTRL_ASPM_DISABLE_FLAGS_L1_MASK_REGKEY_OVERRIDE 0x00000000 1165 #define NV2080_CTRL_ASPM_DISABLE_FLAGS_OS_RM_MAKES_POLICY_DECISIONS 0x00000001 1166 #define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_BEHIND_BRIDGE 0x00000002 1167 #define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_UNSUPPORTED 0x00000003 1168 #define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED 0x00000004 1169 #define NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY 0x00000005 1170 #define NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_DISABLED 0x00000006 1171 #define NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY 0x00000007 1172 #define NV2080_CTRL_ASPM_DISABLE_FLAGS_BIF_ENABLE_ASPM_DT_L1 0x00000008 1173 //append properties here 1174 1175 #define NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS 9 1176 1177 #define NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS (0x20801822) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID" */ 1178 1179 #define NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID (0x22U) 1180 1181 typedef struct NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS { 1182 NvBool aspmDisableFlags[NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS]; 1183 } NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS; 1184 1185 #define NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS (0x20801824) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID" */ 1186 1187 #define NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID (0x24U) 1188 1189 typedef struct NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS { 1190 NvBool bEnable; 1191 } NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS; 1192 1193 /* 1194 * NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK 1195 * 1196 * This command returns cached(SW only) NVLINK peer id mask. Currently, this control 1197 * call is only needed inside a SR-IOV enabled guest where page table management is 1198 * being done by the guest. Guest needs this mask to derive the peer id corresponding 1199 * to the peer GPU. This peer id will then be programmed inside the PTEs by guest RM. 1200 * 1201 * nvlinkPeerIdMask[OUT] 1202 * - The peer id mask is returned in this array. 1203 * 1204 * Possible status values returned are: 1205 * NV_OK 1206 * NV_ERR_NOT_SUPPORTED 1207 */ 1208 #define NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK (0x20801825) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID" */ 1209 1210 #define NV2080_CTRL_BUS_MAX_NUM_GPUS 32 1211 1212 #define NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID (0x25U) 1213 1214 typedef struct NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS { 1215 NvU32 nvlinkPeerIdMask[NV2080_CTRL_BUS_MAX_NUM_GPUS]; 1216 } NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS; 1217 1218 /* 1219 * NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS 1220 * This command takes parameters eomMode, eomNblks and eomNerrs from the client 1221 * and then sends it out to PMU. 1222 */ 1223 #define NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS (0x20801826) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID" */ 1224 1225 #define NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID (0x26U) 1226 1227 typedef struct NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS { 1228 NvU8 eomMode; 1229 NvU8 eomNblks; 1230 NvU8 eomNerrs; 1231 } NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS; 1232 1233 /* 1234 * NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE 1235 * This command takes parameters UPHY register's address and lane from the client 1236 * and then sends it out to PMU. 1237 */ 1238 #define NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE (0x20801827) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID" */ 1239 1240 #define NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID (0x27U) 1241 1242 typedef struct NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS { 1243 NvU32 regAddress; 1244 NvU32 laneSelectMask; 1245 NvU16 regValue; 1246 } NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS; 1247 1248 /* 1249 * NV2080_CTRL_CMD_BUS_GET_EOM_STATUS 1250 * 1251 */ 1252 #define NV2080_CTRL_CMD_BUS_GET_EOM_STATUS (0x20801828) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID" */ 1253 1254 #define NV2080_CTRL_BUS_MAX_NUM_LANES 32 1255 1256 #define NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID (0x28U) 1257 1258 typedef struct NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS { 1259 NvU8 eomMode; 1260 NvU8 eomNblks; 1261 NvU8 eomNerrs; 1262 NvU8 eomBerEyeSel; 1263 NvU8 eomPamEyeSel; 1264 NvU32 laneMask; 1265 NvU16 eomStatus[NV2080_CTRL_BUS_MAX_NUM_LANES]; 1266 } NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS; 1267 1268 /* 1269 * NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS 1270 * 1271 * This command returns the PCIe requester atomics operation capabilities 1272 * from GPU to coherent SYSMEM. 1273 * 1274 * atomicsCaps[OUT] 1275 * Mask of supported PCIe atomic operations in the form of 1276 * NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_* 1277 * 1278 * Possible status values returned are: 1279 * NV_OK 1280 * NV_ERR_NOT_SUPPORTED 1281 */ 1282 1283 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS (0x20801829) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID" */ 1284 1285 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID (0x29U) 1286 1287 typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS { 1288 NvU32 atomicsCaps; 1289 } NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS; 1290 1291 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32 0:0 1292 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES (0x00000001) 1293 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO (0x00000000) 1294 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64 1:1 1295 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES (0x00000001) 1296 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO (0x00000000) 1297 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32 2:2 1298 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES (0x00000001) 1299 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO (0x00000000) 1300 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64 3:3 1301 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES (0x00000001) 1302 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO (0x00000000) 1303 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32 4:4 1304 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES (0x00000001) 1305 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO (0x00000000) 1306 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64 5:5 1307 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES (0x00000001) 1308 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO (0x00000000) 1309 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128 6:6 1310 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES (0x00000001) 1311 #define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO (0x00000000) 1312 1313 /* 1314 * NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS 1315 * 1316 * This command returns the supported GPU atomic operations 1317 * that map to the capable PCIe atomic operations from GPU to 1318 * coherent SYSMEM. 1319 * 1320 * atomicOp[OUT] 1321 * Array of structure that contains the atomic operation 1322 * supported status and its attributes. The array can be 1323 * indexed using one of NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_* 1324 * 1325 * bSupported[OUT] 1326 * Is the GPU atomic operation natively supported by the PCIe? 1327 * 1328 * attributes[OUT] 1329 * Provides the attributes mask of the GPU atomic operation when supported 1330 * in the form of 1331 * NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_* 1332 * 1333 */ 1334 #define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS (0x2080182a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID" */ 1335 1336 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD 0 1337 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN 1 1338 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX 2 1339 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC 3 1340 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC 4 1341 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND 5 1342 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR 6 1343 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR 7 1344 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH 8 1345 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS 9 1346 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD 10 1347 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN 11 1348 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX 12 1349 1350 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT 13 1351 1352 #define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID (0x2AU) 1353 1354 typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS { 1355 struct { 1356 NvBool bSupported; 1357 NvU32 attributes; 1358 } atomicOp[NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT]; 1359 } NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS; 1360 1361 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR 0:0 1362 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES 1 1363 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO 0 1364 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR 1:1 1365 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES 1 1366 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO 0 1367 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION 2:2 1368 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES 1 1369 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO 0 1370 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32 3:3 1371 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES 1 1372 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO 0 1373 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64 4:4 1374 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES 1 1375 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO 0 1376 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128 5:5 1377 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES 1 1378 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO 0 1379 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED 6:6 1380 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES 1 1381 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO 0 1382 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED 7:7 1383 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES 1 1384 #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO 0 1385 1386 /* 1387 * NV2080_CTRL_CMD_BUS_GET_C2C_INFO 1388 * 1389 * This command returns the C2C links information. 1390 * 1391 * bIsLinkUp[OUT] 1392 * NV_TRUE if the C2C links are present and the links are up. 1393 * The below remaining fields are valid only if return value is 1394 * NV_OK and bIsLinkUp is NV_TRUE. 1395 * nrLinks[OUT] 1396 * Total number of C2C links that are up. 1397 * maxNrLinks[OUT] 1398 * Maximum number of C2C links that are supported. 1399 * linkMask[OUT] 1400 * Bitmask of the C2C links present and up. 1401 * perLinkBwMBps[OUT] 1402 * Theoretical per link bandwidth in MBps. 1403 * perLinkLaneWidth[OUT] 1404 * Lane width per link. 1405 * remoteType[OUT] 1406 * Type of the device connected to the remote end of the C2C link. 1407 * Valid values are : 1408 * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU 1409 * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU - connected to another GPU 1410 * 1411 * Possible status values returned are: 1412 * NV_OK 1413 * NV_ERR_INVALID_STATE 1414 * 1415 * Please also review the information below for additional information on 1416 * select fields: 1417 * 1418 * remoteType[OUT] 1419 * NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU 1420 */ 1421 1422 /* 1423 * in either self-hosted mode or 1424 * externally-hostedmode. 1425 */ 1426 1427 1428 1429 #define NV2080_CTRL_CMD_BUS_GET_C2C_INFO (0x2080182b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID" */ 1430 1431 #define NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID (0x2BU) 1432 1433 typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS { 1434 NvBool bIsLinkUp; 1435 NvU32 nrLinks; 1436 NvU32 maxNrLinks; 1437 NvU32 linkMask; 1438 NvU32 perLinkBwMBps; 1439 NvU32 perLinkLaneWidth; 1440 NvU32 remoteType; 1441 } NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS; 1442 1443 #define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU 1 1444 #define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU 2 1445 1446 /* 1447 * NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS 1448 * 1449 * This command disables the GPU system memory access after quiescing the GPU, 1450 * or re-enables sysmem access. 1451 * 1452 * bDisable 1453 * If NV_TRUE the GPU is quiesced and system memory access is disabled . 1454 * If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed. 1455 * 1456 * Possible status values returned are: 1457 * NV_OK 1458 * NV_ERR_INVALID_PARAM_STRUCT 1459 * NV_ERR_INVALID_ARGUMENT 1460 */ 1461 1462 #define NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS (0x2080182c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID" */ 1463 1464 #define NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID (0x2CU) 1465 1466 typedef struct NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS { 1467 NvBool bDisable; 1468 } NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS; 1469 1470 1471 1472 /* 1473 * NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING 1474 * 1475 * This command sets P2P mapping. 1476 * 1477 * connectionType[IN] 1478 * Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION 1479 * peerId[IN] 1480 * peerId of remote GPU from local GPU on which call is made. 1481 * bSpaAccessOnly[IN] 1482 * SPA access only. SPA addressing mode is supported when we support ATS. 1483 * bUseUuid [in] 1484 * Option only available for Guest RPCs and is not avaliable for external clients. 1485 * Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU. 1486 * remoteGpuId[IN] 1487 * GPU ID of remote GPU. 1488 * remoteGpuUuid [in] 1489 * Alternative to gpuId; used to identify target GPU for which caps are being queried. 1490 * Option only available for Guest RPCs. 1491 * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. 1492 * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. 1493 * 1494 * Possible status values returned are: 1495 * NV_OK 1496 * NV_ERR_INVALID_ARGUMENT 1497 * NV_ERR_NOT_SUPPORTED 1498 */ 1499 1500 #define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING (0x2080182e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID" */ 1501 1502 #define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID 0 1503 #define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK 1 1504 #define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE 2 1505 #define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1 3 1506 #define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C 4 1507 1508 #define NV2080_SET_P2P_MAPPING_UUID_LEN 16U 1509 1510 #define NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2EU) 1511 1512 typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS { 1513 NvU32 connectionType; 1514 NvU32 peerId; 1515 NvBool bEgmPeer; 1516 NvBool bSpaAccessOnly; 1517 NvBool bUseUuid; 1518 NvU32 remoteGpuId; 1519 NvU8 remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN]; 1520 } NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS; 1521 1522 /* 1523 * NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING 1524 * 1525 * This command unsets P2P mapping. 1526 * 1527 * connectionType[IN] 1528 * Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION 1529 * peerId[IN] 1530 * peerId of remote GPU from local GPU on which call is mad. 1531 * bUseUuid [in] 1532 * Option only available for Guest RPCs and is not avaliable for external clients. 1533 * Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU. 1534 * remoteGpuId[IN] 1535 * GPU ID of remote GPU. 1536 * remoteGpuUuid [in] 1537 * Alternative to gpuId; used to identify target GPU for which caps are being queried. 1538 * Option only available for Guest RPCs. 1539 * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. 1540 * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. 1541 * 1542 * Possible status values returned are: 1543 * NV_OK 1544 * NV_ERR_INVALID_ARGUMENT 1545 * NV_ERR_NOT_SUPPORTED 1546 */ 1547 1548 #define NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING (0x2080182f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID" */ 1549 1550 #define NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2FU) 1551 1552 typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS { 1553 NvU32 connectionType; 1554 NvU32 peerId; 1555 NvBool bUseUuid; 1556 NvU32 remoteGpuId; 1557 NvU8 remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN]; 1558 } NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS; 1559 1560