1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrl2080/ctrl2080ce.finn 31 // 32 33 34 35 #include "nvcfg_sdk.h" 36 37 38 /* NV20_SUBDEVICE_XX ce control commands and parameters */ 39 40 /* 41 * NV2080_CTRL_CMD_CE_GET_CAPS 42 * 43 * This command returns the set of CE capabilities for the device 44 * in the form of an array of unsigned bytes. 45 * 46 * ceEngineType 47 * This parameter specifies the copy engine type 48 * capsTblSize 49 * This parameter specifies the size in bytes of the caps table per CE. 50 * This value should be set to NV2080_CTRL_CE_CAPS_TBL_SIZE. 51 * capsTbl 52 * This parameter specifies a pointer to the client's caps table buffer 53 * into which the CE caps bits will be transferred by the RM. 54 * The caps table is an array of unsigned bytes. 55 * 56 * Possible status values returned are: 57 * NV_OK 58 * NV_ERR_INVALID_PARAM_STRUCT 59 * NV_ERR_INVALID_ARGUMENT 60 */ 61 62 #define NV2080_CTRL_CMD_CE_GET_CAPS (0x20802a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID" */ 63 64 /* 65 * Size in bytes of CE caps table. This value should be one greater 66 * than the largest byte_index value below. 67 */ 68 #define NV2080_CTRL_CE_CAPS_TBL_SIZE 2 69 70 #define NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID (0x1U) 71 72 typedef struct NV2080_CTRL_CE_GET_CAPS_PARAMS { 73 NvU32 ceEngineType; 74 NvU32 capsTblSize; 75 NV_DECLARE_ALIGNED(NvP64 capsTbl, 8); 76 } NV2080_CTRL_CE_GET_CAPS_PARAMS; 77 78 #define NV2080_CTRL_CMD_CE_GET_CAPS_V2 (0x20802a03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ 79 80 #define NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x3U) 81 82 typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS { 83 NvU32 ceEngineType; 84 NvU8 capsTbl[NV2080_CTRL_CE_CAPS_TBL_SIZE]; 85 } NV2080_CTRL_CE_GET_CAPS_V2_PARAMS; 86 87 /* extract cap bit setting from tbl */ 88 #define NV2080_CTRL_CE_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c)) 89 90 /* caps format is byte_index:bit_mask */ 91 #define NV2080_CTRL_CE_CAPS_CE_GRCE 0:0x01 92 #define NV2080_CTRL_CE_CAPS_CE_SHARED 0:0x02 93 #define NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ 0:0x04 94 #define NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE 0:0x08 95 #define NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P 0:0x10 96 #define NV2080_CTRL_CE_CAPS_CE_SYSMEM 0:0x20 97 #define NV2080_CTRL_CE_CAPS_CE_P2P 0:0x40 98 #define NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED 0:0x80 99 #define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL 1:0x01 100 #define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL 1:0x02 101 #define NV2080_CTRL_CE_CAPS_CE_CC_SECURE 1:0x04 102 103 /* 104 * NV2080_CTRL_CE_CAPS_CE_GRCE 105 * Set if the CE is synchronous with GR 106 * 107 * NV2080_CTRL_CE_CAPS_CE_SHARED 108 * Set if the CE shares physical CEs with any other CE 109 * 110 * NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ 111 * Set if the CE can give enhanced performance for SYSMEM reads over other CEs 112 * 113 * NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE 114 * Set if the CE can give enhanced performance for SYSMEM writes over other CEs 115 * 116 * NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P 117 * Set if the CE can be used for P2P transactions using NVLINK 118 * Once a CE is exposed for P2P over NVLINK, it will remain available for the life of RM 119 * PCE2LCE mapping may change based on the number of GPUs registered in RM however 120 * 121 * NV2080_CTRL_CE_CAPS_CE_SYSMEM 122 * Set if the CE can be used for SYSMEM transactions 123 * 124 * NV2080_CTRL_CE_CAPS_CE_P2P 125 * Set if the CE can be used for P2P transactions 126 * 127 * NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED 128 * Set if the CE supports BL copy size greater than 64K 129 * 130 * NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL 131 * Set if the CE supports non-pipelined Block linear 132 * 133 * NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL 134 * Set if the CE supports pipelined Block Linear 135 * 136 * NV2080_CTRL_CE_CAPS_CE_CC_SECURE 137 * Set if the CE is capable of encryption/decryption 138 */ 139 140 /* 141 * NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK 142 * 143 * This command returns the mapping of PCE's for the given LCE. 144 * 145 * ceEngineType 146 * This parameter specifies the copy engine type 147 * pceMask 148 * This parameter specifies a mask of PCEs that correspond 149 * to the LCE specified in ceEngineType 150 * 151 * Possible status values returned are: 152 * NV_OK 153 * NV_ERR_INVALID_PARAM_STRUCT 154 * NV_ERR_INVALID_ARGUMENT 155 */ 156 157 158 159 #define NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK (0x20802a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID" */ 160 161 #define NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID (0x2U) 162 163 typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS { 164 NvU32 ceEngineType; 165 NvU32 pceMask; 166 } NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS; 167 168 /* 169 * NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG 170 * 171 * This command sets the PCE2LCE configuration 172 * 173 * pceLceConfig[NV2080_CTRL_MAX_PCES] 174 * This parameter specifies the PCE-LCE mapping requested 175 * grceLceConfig[NV2080_CTRL_MAX_GRCES] 176 * This parameter specifies which LCE is the GRCE sharing with 177 * 0xF -> Does not share with any LCE 178 * 0-MAX_LCE -> Shares with the given LCE 179 * 180 * Possible status values returned are: 181 * NV_OK 182 * NV_ERR_INVALID_PARAM_STRUCT 183 * NV_ERR_INVALID_ARGUMENT 184 */ 185 186 #define NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG (0x20802a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID" */ 187 188 #define NV2080_CTRL_MAX_PCES 32 189 #define NV2080_CTRL_MAX_GRCES 4 190 191 #define NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID (0x4U) 192 193 typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS { 194 NvU32 ceEngineType; 195 NvU32 pceLceMap[NV2080_CTRL_MAX_PCES]; 196 NvU32 grceSharedLceMap[NV2080_CTRL_MAX_GRCES]; 197 } NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS; 198 199 /* 200 * NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS 201 * 202 * This command updates the PCE-LCE mappings 203 * 204 * pceLceMap [IN] 205 * This parameter contains the array of PCE to LCE mappings. 206 * The array is indexed by the PCE index, and contains the 207 * LCE index that the PCE is assigned to. A unused PCE is 208 * tagged with NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE. 209 * 210 * grceConfig [IN] 211 * This parameter contains the array of GRCE configs. 212 * 0xF -> GRCE does not share with any LCE 213 * 0-MAX_LCE -> GRCE shares with the given LCE 214 * 215 * exposeCeMask [IN] 216 * This parameter specifies the mask of LCEs to export to the 217 * clients after the update. 218 * 219 * bUpdateNvlinkPceLce [IN] 220 * Whether PCE-LCE mappings need to be updated for nvlink topology. 221 * If this is NV_FALSE, RM would ignore the above values. However, 222 * PCE-LCE mappings will still be updated if there were any regkey 223 * overrides. 224 * 225 * Possible status values returned are: 226 * NV_OK 227 * NV_ERR_INVALID_ARGUMENT 228 * NV_ERR_GENERIC 229 */ 230 231 232 233 #define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */ 234 235 #define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID (0x5U) 236 237 typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS { 238 NvU32 pceLceMap[NV2080_CTRL_MAX_PCES]; 239 NvU32 grceConfig[NV2080_CTRL_MAX_GRCES]; 240 NvU32 exposeCeMask; 241 NvBool bUpdateNvlinkPceLce; 242 } NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS; 243 244 #define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE 0xf 245 246 /* 247 * NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB 248 * 249 * This function triggers an update of the exported CE classes. CEs with 250 * no physical resources will not be exported. A record of these 251 * will be return in in the stubbedCeMask. 252 * 253 * An example if NV2080_ENGINE_TYPE_COPY4 is stubbed (1<<4) will be 254 * set in stubbedCeMask. 255 */ 256 257 258 #define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */ 259 260 #define NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID (0x6U) 261 262 typedef struct NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS { 263 NvU32 stubbedCeMask; 264 } NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS; 265 266 /* 267 * NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS 268 * 269 * Query _CE_GRCE, _CE_SHARED, _CE_SUPPORTS_PIPELINED_BL, _CE_SUPPORTS_NONPIPELINED_BL bits of CE 270 * capabilities. 271 * 272 */ 273 274 #define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */ 275 276 #define NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID (0x7U) 277 278 typedef NV2080_CTRL_CE_GET_CAPS_V2_PARAMS NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS; 279 280 #define NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x8U) 281 282 typedef struct NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS { 283 NvU32 size; 284 } NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS; 285 286 #define NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE (0x20802a08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ 287 288 /* 289 * NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASKS 290 * 291 * Get HSHUB and FBHUB PCE masks. 292 * 293 * [out] hshubPceMasks 294 * PCE mask for each HSHUB 295 * [out] fbhubPceMask 296 * FBHUB PCE mask 297 */ 298 299 #define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK (0x20802a09) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID" */ 300 301 #define NV2080_CTRL_CE_MAX_HSHUBS 32 302 303 #define NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID (0x9U) 304 305 typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS { 306 NvU32 hshubPceMasks[NV2080_CTRL_CE_MAX_HSHUBS]; 307 NvU32 fbhubPceMask; 308 } NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS; 309 310 /* 311 * NV2080_CTRL_CMD_CE_GET_ALL_CAPS 312 * 313 * Query caps of all CEs. 314 * 315 * [out] capsTbl 316 * Array of CE caps in the order of CEs. The caps bits interpretation is the same as in 317 * NV2080_CTRL_CMD_CE_GET_CAPS. 318 * [out] present 319 * Bit mask indicating which CEs are usable by the client and have their caps indicated in capsTbl. 320 * If a CE is not marked present, its caps bits should be ignored. 321 * If client is subscribed to a MIG instance, only the CEs present in the instance are tagged as such. 322 */ 323 324 #define NV2080_CTRL_CMD_CE_GET_ALL_CAPS (0x20802a0a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID" */ 325 326 #define NV2080_CTRL_MAX_CES 64 327 328 #define NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID (0xaU) 329 330 typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS { 331 NvU8 capsTbl[NV2080_CTRL_MAX_CES][NV2080_CTRL_CE_CAPS_TBL_SIZE]; 332 NV_DECLARE_ALIGNED(NvU64 present, 8); 333 } NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS; 334 335 #define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */ 336 337 #define NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID (0xbU) 338 339 typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS; 340 341 342 343 /* _ctrl2080ce_h_ */ 344