1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrl2080/ctrl2080internal.finn 31 // 32 33 #include "nvimpshared.h" 34 #include "cc_drv.h" 35 #include "ctrl/ctrl2080/ctrl2080base.h" 36 37 #include "ctrl/ctrl2080/ctrl2080gpu.h" 38 #include "ctrl/ctrl2080/ctrl2080gr.h" /* Some controls derivative of 2080gr */ 39 #include "ctrl/ctrl0080/ctrl0080msenc.h" /* NV0080_CTRL_MSENC_CAPS_TBL_SIZE */ 40 #include "ctrl/ctrl0080/ctrl0080bsp.h" /* NV0080_CTRL_BSP_CAPS_TBL_SIZE */ 41 #include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */ 42 #include "ctrl/ctrl0073/ctrl0073system.h" /* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS */ 43 #include "ctrl/ctrl0000/ctrl0000system.h" 44 #include "ctrl/ctrl90f1.h" 45 #include "ctrl/ctrl30f1.h" 46 #include "nvcfg_sdk.h" 47 48 /*! 49 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO 50 * 51 * This command obtains information from physical RM for use by CPU-RM. 52 * 53 * feHwSysCap 54 * Display IP v03_00 and later. 55 * Contents of capability register. 56 * 57 * windowPresentMask 58 * Display IP v03_00 and later. 59 * Mask for the present WINDOWs actually on the current chip. 60 * bFbRemapperEnabled 61 * Display IP v02_01 and later. 62 * Indicates that the display remapper HW exists and is enabled. 63 * numHeads 64 * Display IP v02_01 and later. 65 * Provides the number of heads HW support. 66 */ 67 68 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 69 70 #define NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x1U) 71 72 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS { 73 NvU32 feHwSysCap; 74 NvU32 windowPresentMask; 75 NvBool bFbRemapperEnabled; 76 NvU32 numHeads; 77 NvBool bPrimaryVga; 78 NvU32 i2cPort; 79 NvU32 internalDispActiveMask; 80 NvU32 embeddedDisplayPortMask; 81 NvBool bExternalMuxSupported; 82 NvBool bInternalMuxSupported; 83 } NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS; 84 85 86 87 // 88 // MemorySystem settings that are static after GPU state init/load is finished. 89 // 90 // Fields are shared between the VGPU guest/GSP Client as well as the VGPU 91 // host/GSP-RM. 92 // 93 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID (0x1CU) 94 95 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS { 96 /*! Determines if RM should use 1 to 1 Comptagline allocation policy */ 97 NvBool bOneToOneComptagLineAllocation; 98 99 /*! Determines if RM should use 1 to 4 Comptagline allocation policy */ 100 NvBool bUseOneToFourComptagLineAllocation; 101 102 /*! Determines if RM should use raw Comptagline allocation policy */ 103 NvBool bUseRawModeComptaglineAllocation; 104 105 /*! Has COMPBIT_BACKING_SIZE been overridden to zero (i.e. disabled)? */ 106 NvBool bDisableCompbitBacking; 107 108 /*! Determine if we need to disable post L2 compression */ 109 NvBool bDisablePostL2Compression; 110 111 /*! Is ECC DRAM feature supported? */ 112 NvBool bEnabledEccFBPA; 113 114 NvBool bL2PreFill; 115 116 /*! L2 cache size */ 117 NV_DECLARE_ALIGNED(NvU64 l2CacheSize, 8); 118 119 /*! Indicate whether fpba is present or not */ 120 NvBool bFbpaPresent; 121 122 /*! Size covered by one comptag */ 123 NvU32 comprPageSize; 124 125 /*! log32(comprPageSize) */ 126 NvU32 comprPageShift; 127 128 /*! RAM type */ 129 NvU32 ramType; 130 131 /*! LTC count */ 132 NvU32 ltcCount; 133 134 /*! LTS per LTC count */ 135 NvU32 ltsPerLtcCount; 136 } NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS; 137 138 /*! 139 * Retrieve Memory System Static data. 140 */ 141 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG (0x20800a1c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID" */ 142 143 /* 144 * NV2080_CTRL_CMD_INTERNAL_REGISTER_UVM_ACCESS_CNTR_BUFFER 145 * 146 * This command sends access counter buffer pages allocated by CPU-RM 147 * to be setup and enabled in physical RM. 148 * 149 * accessCounterIndex 150 * Index of access counter buffer to register. 151 * 152 * bufferSize 153 * Size of the access counter buffer to register. 154 * 155 * bufferPteArray 156 * Pages of access counter buffer. 157 * 158 * Possible status values returned are: 159 * NV_OK 160 */ 161 #define NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER (0x20800a1d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */ 162 163 #define NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES 64 164 #define NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1DU) 165 166 typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS { 167 NvU32 accessCounterIndex; 168 NvU32 bufferSize; 169 NV_DECLARE_ALIGNED(NvU64 bufferPteArray[NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES], 8); 170 } NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS; 171 172 /* 173 * NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER 174 * 175 * This command requests physical RM to disable the access counter buffer. 176 * 177 * accessCounterIndex 178 * Index of access counter buffer to unregister. 179 * 180 * Possible status values returned are: 181 * NV_OK 182 */ 183 #define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */ 184 185 #define NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1EU) 186 187 typedef struct NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS { 188 NvU32 accessCounterIndex; 189 } NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS; 190 191 #define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8 192 193 /*! 194 * @ref NV2080_CTRL_CMD_GR_GET_CAPS_V2 195 */ 196 197 198 199 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CAPS { 200 NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE]; 201 } NV2080_CTRL_INTERNAL_STATIC_GR_CAPS; 202 203 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x20U) 204 205 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS { 206 NV2080_CTRL_INTERNAL_STATIC_GR_CAPS engineCaps[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 207 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS; 208 209 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID" */ 210 211 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID (0x1FU) 212 213 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS; 214 215 /* 216 * NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS 217 * 218 * Set flags for use by the video event buffer 219 * 220 * flags 221 * VIDEO_TRACE_FLAG__* 222 * 223 */ 224 #define NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS_MESSAGE_ID" */ 225 226 #define NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS_MESSAGE_ID (0x21U) 227 228 typedef struct NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS { 229 NvU32 flags; 230 } NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS; 231 232 /*! 233 * @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER 234 * @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS 235 */ 236 237 238 239 #define NV2080_CTRL_INTERNAL_GR_MAX_SM 240 240 241 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER { 242 struct { 243 NvU16 gpcId; 244 NvU16 localTpcId; 245 NvU16 localSmId; 246 NvU16 globalTpcId; 247 NvU16 virtualGpcId; 248 NvU16 migratableTpcId; 249 } globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM]; 250 251 NvU16 numSm; 252 NvU16 numTpc; 253 } NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER; 254 255 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x23U) 256 257 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS { 258 NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 259 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS; 260 261 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */ 262 263 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x22U) 264 265 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS; 266 267 /*! 268 * Retrieve BSP Static data. 269 */ 270 #define NV2080_CTRL_CMD_INTERNAL_BSP_GET_CAPS (0x20800a24) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS_MESSAGE_ID" */ 271 272 #define NV2080_CTRL_CMD_INTERNAL_MAX_BSPS 8 273 274 typedef struct NV2080_CTRL_INTERNAL_BSP_CAPS { 275 NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE]; 276 } NV2080_CTRL_INTERNAL_BSP_CAPS; 277 278 #define NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS_MESSAGE_ID (0x24U) 279 280 typedef struct NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS { 281 NV2080_CTRL_INTERNAL_BSP_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; 282 NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; 283 } NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS; 284 285 /*! 286 * Retrieve MSENC Static data. 287 */ 288 #define NV2080_CTRL_CMD_INTERNAL_MSENC_GET_CAPS (0x20800a25) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */ 289 290 #define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS 8 291 292 typedef struct NV2080_CTRL_INTERNAL_MSENC_CAPS { 293 NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE]; 294 } NV2080_CTRL_INTERNAL_MSENC_CAPS; 295 296 #define NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID (0x25U) 297 298 typedef struct NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS { 299 NV2080_CTRL_INTERNAL_MSENC_CAPS caps[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS]; 300 NvBool valid[NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS]; 301 } NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS; 302 303 304 #define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12 305 #define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10 306 307 /*! 308 * @ref NV2080_CTRL_CMD_GR_GET_GPC_MASK 309 * @ref NV2080_CTRL_CMD_GR_GET_TPC_MASK 310 * @ref NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK 311 */ 312 313 314 315 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS { 316 NvU32 gpcMask; 317 318 /*! 319 * tpcMask is indexed by logical GPC ID for MIG case 320 * and indexed by physical GPC ID for non-MIG case 321 */ 322 NvU32 tpcMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 323 324 /*! 325 * tpcCount is always indexed by logical GPC ID 326 */ 327 NvU32 tpcCount[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 328 NvU32 physGpcMask; 329 NvU32 mmuPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 330 331 NvU32 tpcToPesMap[NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT]; 332 NvU32 numPesPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 333 334 /*! 335 * zcullMask is always indexed by physical GPC ID 336 */ 337 NvU32 zcullMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 338 339 NvU32 physGfxGpcMask; 340 NvU32 numGfxTpc; 341 } NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS; 342 343 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x27U) 344 345 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS { 346 /*! 347 * floorsweeping masks which are indexed via local GR index 348 */ 349 NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 350 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS; 351 352 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID" */ 353 354 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x26U) 355 356 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS; 357 358 /* 359 * NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES 360 * 361 * This command returns physical addresses of specified context buffer. 362 * To obtain addresses of whole buffer firstPage has to be advanced on 363 * subsequent invocations of the control until whole buffer is probed. 364 * If the buffer is contiguous, only single address will be returned by 365 * this control. 366 * 367 * bufferType[IN] 368 * Buffer type as returned by GET_CTX_BUFFER_INFO. 369 * 370 * firstPage[IN] 371 * Index of the first page to return in 'physAddrs' array. 372 * 373 * numPages[OUT] 374 * Number of entries filled in 'physAddrs' array. This will be 0 375 * if firstPage is greater or equal to number of pages managed by 'hBuffer'. 376 * 377 * physAddrs[OUT] 378 * Physical addresses of pages comprising specified buffer. 379 * 380 * bNoMorePages[OUT] 381 * End of buffer reached. Either 'physAddrs' contains last page of the 382 * buffer or 'firstPage' specifies index past the buffer. 383 */ 384 #define NV2080_CTRL_KGR_MAX_BUFFER_PTES 128 385 #define NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES (0x20800a28) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID" */ 386 387 #define NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID (0x28U) 388 389 typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS { 390 NvHandle hUserClient; 391 NvHandle hChannel; 392 NvU32 bufferType; 393 NvU32 firstPage; 394 NvU32 numPages; 395 NV_DECLARE_ALIGNED(NvU64 physAddrs[NV2080_CTRL_KGR_MAX_BUFFER_PTES], 8); 396 NvBool bNoMorePages; 397 } NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS; 398 399 /*! 400 * NV2080_CTRL_INTERNAL_MEMDESC_INFO 401 * 402 * A generic container structure representing a memory region to be used as a 403 * component of other control call parameters. 404 * 405 */ 406 typedef struct NV2080_CTRL_INTERNAL_MEMDESC_INFO { 407 NV_DECLARE_ALIGNED(NvU64 base, 8); 408 NV_DECLARE_ALIGNED(NvU64 size, 8); 409 NV_DECLARE_ALIGNED(NvU64 alignment, 8); 410 NvU32 addressSpace; 411 NvU32 cpuCacheAttrib; 412 } NV2080_CTRL_INTERNAL_MEMDESC_INFO; 413 414 /* 415 * NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY 416 * 417 * Set memory for use by the video event buffer 418 * 419 * memDescInfo 420 * Information to set up memory descriptor on GSP 421 * 422 * engDesc 423 * Video engdesc to find correct engine 424 * 425 * bEngineFound 426 * Bool for whether or not the engine is actually assigned to a video object 427 */ 428 #define NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY (0x20800a29) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS_MESSAGE_ID" */ 429 430 #define NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS_MESSAGE_ID (0x29U) 431 432 typedef struct NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS { 433 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO memDescInfo, 8); 434 NvU32 engDesc; 435 NvBool bEngineFound; 436 } NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS; 437 438 /*! 439 * @ref NV0080_CTRL_CMD_GR_GET_INFO 440 * @ref NV0080_CTRL_CMD_GR_GET_INFO_V2 441 * @ref NV2080_CTRL_CMD_GR_GET_INFO 442 * @ref NV2080_CTRL_CMD_GR_GET_INFO_V2 443 */ 444 445 446 447 /*! 448 * @ref NV2080_CTRL_GR_INFO 449 */ 450 typedef struct NV2080_CTRL_INTERNAL_GR_INFO { 451 NvU32 index; 452 NvU32 data; 453 } NV2080_CTRL_INTERNAL_GR_INFO; 454 455 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO { 456 NV2080_CTRL_INTERNAL_GR_INFO infoList[NV0080_CTRL_GR_INFO_MAX_SIZE]; 457 } NV2080_CTRL_INTERNAL_STATIC_GR_INFO; 458 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID (0x2BU) 459 460 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS { 461 NV2080_CTRL_INTERNAL_STATIC_GR_INFO engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 462 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS; 463 464 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID" */ 465 466 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID (0x2AU) 467 468 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS; 469 470 /*! 471 * @ref NV2080_CTRL_CMD_GR_GET_ZCULL_INFO 472 */ 473 474 475 476 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO { 477 NvU32 widthAlignPixels; 478 NvU32 heightAlignPixels; 479 NvU32 pixelSquaresByAliquots; 480 NvU32 aliquotTotal; 481 NvU32 zcullRegionByteMultiplier; 482 NvU32 zcullRegionHeaderSize; 483 NvU32 zcullSubregionHeaderSize; 484 NvU32 subregionCount; 485 NvU32 subregionWidthAlignPixels; 486 NvU32 subregionHeightAlignPixels; 487 } NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO; 488 489 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2DU) 490 491 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS { 492 NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 493 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS; 494 495 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */ 496 497 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2CU) 498 499 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS; 500 501 /*! 502 * @ref NV2080_CTRL_CMD_GR_GET_ROP_INFO 503 */ 504 505 506 507 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO { 508 NvU32 ropUnitCount; 509 NvU32 ropOperationsFactor; 510 NvU32 ropOperationsCount; 511 } NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO; 512 513 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2FU) 514 515 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS { 516 NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 517 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS; 518 519 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */ 520 521 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2EU) 522 523 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS; 524 525 /*! 526 * @ref NV2080_CTRL_CMD_GR_GET_PPC_MASK 527 */ 528 529 530 531 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS { 532 NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC]; 533 } NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS; 534 535 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x31U) 536 537 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS { 538 NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 539 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS; 540 541 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID" */ 542 543 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x30U) 544 545 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS; 546 547 /*! 548 * @ref NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES 549 * @ref NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE 550 */ 551 552 553 554 #define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x1a 555 556 typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO { 557 NvU32 size; 558 NvU32 alignment; 559 } NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO; 560 561 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO { 562 NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT]; 563 } NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO; 564 565 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x33U) 566 567 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS { 568 NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 569 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS; 570 571 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */ 572 573 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x32U) 574 575 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS; 576 577 /*! 578 * @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER 579 */ 580 581 582 583 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER { 584 NvU8 imla0; 585 NvU8 fmla16; 586 NvU8 dp; 587 NvU8 fmla32; 588 NvU8 ffma; 589 NvU8 imla1; 590 NvU8 imla2; 591 NvU8 imla3; 592 NvU8 imla4; 593 } NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER; 594 595 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x35U) 596 597 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS { 598 NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 599 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; 600 601 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */ 602 603 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x34U) 604 605 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; 606 607 /* 608 * NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS 609 * 610 * This command obtains information from physical RM for use by CPU-RM. 611 */ 612 613 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO (0x20800a36) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID" */ 614 615 /* 616 * Maximum number of register bases to return. 617 * These are indexed by NV_REG_BASE_* constants from gpu.h, and this value needs 618 * to be updated if NV_REG_BASE_LAST ever goes over it. See the ct_assert() in gpu.h 619 */ 620 #define NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX 16 621 #define NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID (0x36U) 622 623 typedef struct NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS { 624 NvU8 chipSubRev; 625 NvU32 emulationRev1; 626 NvBool isCmpSku; 627 NvU32 pciDeviceId; 628 NvU32 pciSubDeviceId; 629 NvU32 pciRevisionId; 630 NvU32 regBases[NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX]; 631 } NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS; 632 633 /** 634 * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE 635 * 636 * Set whether or not context switch logging is enabled 637 * 638 * bEnable 639 * Enable/Disable status for context switch logging 640 */ 641 #define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE (0x20800a37) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */ 642 643 /** 644 * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE 645 * 646 * Retrieve whether or not context switch logging is enabled 647 * 648 * bEnable 649 * Enable/Disable status for context switch logging 650 */ 651 #define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE (0x20800a38) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID" */ 652 653 typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS { 654 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 655 NvBool bEnable; 656 } NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS; 657 658 #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x37U) 659 660 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS; 661 662 #define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x38U) 663 664 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS; 665 666 /** 667 * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET 668 * 669 * Set read offset into FECS context switch trace record 670 * 671 * offset 672 * Value indicating number of records by which to offset 673 */ 674 #define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET (0x20800a39) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */ 675 676 /** 677 * NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET 678 * 679 * Set write offset into FECS context switch trace record 680 * 681 * offset 682 * Value indicating number of records by which to offset 683 */ 684 #define NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET (0x20800a3a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID" */ 685 686 /** 687 * NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET 688 * 689 * Get read offset into FECS context switch trace record 690 * 691 * offset 692 * Value indicating number of records by which to offset 693 */ 694 695 #define NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET (0x20800a3b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID" */ 696 697 typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS { 698 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 699 NvU32 offset; 700 } NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS; 701 702 #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x39U) 703 704 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS; 705 706 #define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID (0x3AU) 707 708 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS; 709 710 #define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x3BU) 711 712 typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS; 713 714 /** 715 * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE 716 * 717 * Get size of FECS record 718 * 719 * fecsRecordSize 720 * Size of FECS record 721 */ 722 723 724 725 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE (0x20800a3d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID" */ 726 727 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE { 728 NvU32 fecsRecordSize; 729 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE; 730 731 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3CU) 732 733 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS { 734 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 735 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS; 736 737 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3DU) 738 739 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS; 740 741 /** 742 * NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES 743 * 744 * Get HW defines used to extract information from FECS records 745 * 746 * fecsRecordSize 747 * Size of FECS record 748 * 749 * timestampHiTagMask 750 * Mask for high bits of raw timestamp to extract tag 751 * 752 * timestampHiTagShift 753 * Shift for high bits of raw timestamp to extract tag 754 * 755 * timestampVMask 756 * Mask to extract timestamp from raw timestamp 757 * 758 * numLowerBitsZeroShift 759 * Number of bits timestamp is shifted by 760 */ 761 762 763 764 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES { 765 NvU32 fecsRecordSize; 766 NvU32 timestampHiTagMask; 767 NvU8 timestampHiTagShift; 768 NV_DECLARE_ALIGNED(NvU64 timestampVMask, 8); 769 NvU8 numLowerBitsZeroShift; 770 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES; 771 772 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3EU) 773 774 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS { 775 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES], 8); 776 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS; 777 778 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID" */ 779 780 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3FU) 781 782 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS; 783 784 /** 785 * NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE 786 * 787 * Parse the DEVICE_INFO2_TABLE on the physical side and return it to kernel. 788 */ 789 typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO { 790 NvU32 faultId; 791 NvU32 instanceId; 792 NvU32 typeEnum; 793 NvU32 resetId; 794 NvU32 devicePriBase; 795 NvU32 isEngine; 796 NvU32 rlEngId; 797 NvU32 runlistPriBase; 798 NvU32 groupId; 799 } NV2080_CTRL_INTERNAL_DEVICE_INFO; 800 #define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 256 801 802 #define NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE (0x20800a40) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */ 803 804 #define NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID (0x40U) 805 806 typedef struct NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS { 807 NvU32 numEntries; 808 NV2080_CTRL_INTERNAL_DEVICE_INFO deviceInfoTable[NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES]; 809 } NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS; 810 811 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP (0x20800a41) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID" */ 812 813 #define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE 4096 814 #define NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES 4096 815 816 #define NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID (0x41U) 817 818 typedef struct NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS { 819 NvU32 userRegisterAccessMapSize; 820 NvU32 compressedSize; 821 NvU8 compressedData[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE]; 822 NvU32 profilingRangesSize; 823 NvU8 profilingRanges[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES]; 824 } NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS; 825 826 /** 827 * Get GR PDB properties synchronized between Kernel and Physical 828 * 829 * bPerSubCtxheaderSupported 830 * @ref PDB_PROP_GR_SUPPORTS_PER_SUBCONTEXT_CONTEXT_HEADER 831 */ 832 833 834 835 typedef struct NV2080_CTRL_INTERNAL_NV_RANGE { 836 NV_DECLARE_ALIGNED(NvU64 lo, 8); 837 NV_DECLARE_ALIGNED(NvU64 hi, 8); 838 } NV2080_CTRL_INTERNAL_NV_RANGE; 839 840 /*! 841 * NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS 842 * 843 * This structure specifies a target swizz-id and mem_range to update 844 * 845 * swizzId[IN] 846 * - Targeted swizz-id for which the memRange is being set 847 * 848 * memAddrRange[IN] 849 * - Memory Range for given GPU instance 850 */ 851 #define NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x43U) 852 853 typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS { 854 NvU32 swizzId; 855 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE memAddrRange, 8); 856 } NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS; 857 858 #define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a44) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */ 859 860 #define NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x44U) 861 862 typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS; 863 864 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */ 865 866 867 868 #define NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x45U) 869 870 typedef struct NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS { 871 NvBool bTeardown; 872 } NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS; 873 874 #define NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x20800a46) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */ 875 #define NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x46U) 876 877 typedef NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS; 878 879 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES { 880 NvBool bPerSubCtxheaderSupported; 881 } NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES; 882 883 #define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x47U) 884 885 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS { 886 NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES]; 887 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS; 888 889 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID" */ 890 891 #define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x48U) 892 893 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS; 894 895 /*! 896 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM 897 * 898 * This command writes instance memory information in the display hardware registers. 899 * 900 * instMemPhysAddr 901 * GPU physical address or IOVA address of the display instance memory. 902 * 903 * instMemSize 904 * Size of the display instance memory. 905 * 906 * instMemAddrSpace 907 * Address space of the display instance memory. 908 * 909 * instMemCpuCacheAttr 910 * Cache attribute of the display instance memory. 911 */ 912 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */ 913 914 #define NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID (0x49U) 915 916 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS { 917 NV_DECLARE_ALIGNED(NvU64 instMemPhysAddr, 8); 918 NV_DECLARE_ALIGNED(NvU64 instMemSize, 8); 919 NvU32 instMemAddrSpace; 920 NvU32 instMemCpuCacheAttr; 921 } NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS; 922 923 /* 924 * NV2080_CTRL_INTERNAL_GPU_RECOVER_ALL_COMPUTE_CONTEXTS 925 * 926 * This command issues RC recovery for all compute contexts running on the given GPU. 927 */ 928 #define NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS (0x20800a4a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x4A" */ 929 930 /*! 931 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION 932 * 933 * This command obtains IP version of display engine for use by Kernel RM. 934 * 935 * ipVersion 936 * IP Version of display engine. 937 * 938 * Possible status values returned are: 939 * NV_OK 940 * NV_ERR_NOT_SUPPORTED - DISP has been disabled 941 */ 942 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION (0x20800a4b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID" */ 943 944 #define NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4BU) 945 946 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS { 947 NvU32 ipVersion; 948 } NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS; 949 950 /*! 951 * NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE 952 * 953 * This command determines the current status of MIG MODE from Physical RM. 954 * 955 * smcMode [OUT] 956 * Current MIG MODE of the GPU. Values range NV2080_CTRL_GPU_INFO_GPU_SMC_MODE* 957 */ 958 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE (0x20800a4c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID" */ 959 960 #define NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID (0x4CU) 961 962 typedef struct NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS { 963 NvU32 smcMode; 964 } NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS; 965 966 /*! 967 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR 968 * 969 * head 970 * This parameter specifies the head for which the callback is to be registered/unregistered. This value must be 971 * less than the maximum number of heads supported by the GPU subdevice. 972 * 973 * rgLineNum 974 * This indicates the RG scanout line number on which the callback will be executed. 975 * 976 * intrLine 977 * Enable: [out] Which interrupt line was allocated for this head. 978 * Disable: [in] Which interrupt line to deallocate. 979 * 980 * bEnable 981 * Should we allocate or deallocate an interrupt line? 982 * 983 * Possible status values returned are: 984 * NV_OK 985 * NV_ERR_GENERIC - There was no available interrupt to allocate. 986 * NV_ERR_INVALID_ARGUMENT 987 */ 988 989 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR (0x20800a4d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID" */ 990 991 #define NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID (0x4DU) 992 993 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS { 994 NvU32 head; 995 NvU32 rgLineNum; 996 NvU32 intrLine; 997 NvBool bEnable; 998 } NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS; 999 1000 /*! 1001 * NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO 1002 * 1003 * Description of a supported GPU instance. 1004 * 1005 * partitionFlag [OUT] 1006 * Allocation flag to be used to allocate a partition with this profile. 1007 * 1008 * grCount [OUT] 1009 * # GR engines, including the GFX capable ones. 1010 * 1011 * gfxGrCount [OUT] 1012 * # GR engines capable of Gfx, which is a subset of the GR engines included in grCount 1013 * 1014 * gpcCount [OUT] 1015 * # total gpcs, including the GFX capable ones. 1016 * 1017 * virtualGpcCount [OUT] 1018 * # virtualized gpcs, including the GFX capable ones. 1019 * 1020 * gfxGpcCount [OUT] 1021 * # total gpcs capable of Gfx. This is a subset of the GPCs included in gpcCount. 1022 * 1023 * veidCount [OUT] 1024 * # total veids 1025 * 1026 * smCount [OUT] 1027 * # total SMs 1028 * 1029 * ceCount [OUT] 1030 * # CE engines 1031 * 1032 * nvEncCount [OUT] 1033 * # NVENC engines 1034 * 1035 * nvDecCount [OUT] 1036 * # NVDEC engines 1037 * 1038 * nvJpgCount [OUT] 1039 * # NVJPG engines 1040 * 1041 * nvOfaCount [OUT] 1042 * # NVOFA engines 1043 * 1044 * validCTSIdMask [OUT] 1045 * # mask of CTS IDs which can be assigned under this profile 1046 * 1047 * validGfxCTSIdMask [OUT] 1048 * # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile 1049 */ 1050 #define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 60 1051 1052 1053 1054 typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO { 1055 NvU32 partitionFlag; 1056 NvU32 grCount; 1057 NvU32 gfxGrCount; 1058 NvU32 gpcCount; 1059 NvU32 virtualGpcCount; 1060 NvU32 gfxGpcCount; 1061 NvU32 veidCount; 1062 NvU32 smCount; 1063 NvU32 ceCount; 1064 NvU32 nvEncCount; 1065 NvU32 nvDecCount; 1066 NvU32 nvJpgCount; 1067 NvU32 nvOfaCount; 1068 NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); 1069 NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8); 1070 } NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO; 1071 1072 /*! 1073 * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS 1074 * 1075 * Returns the list of supported GPU instance profiles. 1076 * 1077 * count [OUT] 1078 * Number of supported profiles. 1079 * 1080 * table [OUT] 1081 * Supported profiles. 1082 */ 1083 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x4FU) 1084 1085 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS { 1086 NvU32 count; 1087 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8); 1088 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS; 1089 1090 /*! 1091 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM 1092 * 1093 * This command instructs the physical MemorySystem to set up memory partitioning 1094 * exterior boundaries in hardware. 1095 * 1096 * partitionableMemSize [input] 1097 * Size of the partitionable memory in bytes 1098 * 1099 * bottomRsvdSize [input] 1100 * Size of the reserved region below partitionable memory in bytes 1101 * 1102 * topRsvdSize [input] 1103 * Size of the reserved region above partitionable memory in bytes 1104 * 1105 * partitionableStartAddr [output] 1106 * Start address of the partitionable memory, aligned to HW constraints 1107 * 1108 * partitionableEndAddr [output] 1109 * End address of the partitionable memory, aligned to HW constraints 1110 */ 1111 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM (0x20800a51) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID" */ 1112 1113 #define NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID (0x51U) 1114 1115 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS { 1116 NV_DECLARE_ALIGNED(NvU64 partitionableMemSize, 8); 1117 NV_DECLARE_ALIGNED(NvU64 bottomRsvdSize, 8); 1118 NV_DECLARE_ALIGNED(NvU64 topRsvdSize, 8); 1119 NV_DECLARE_ALIGNED(NvU64 partitionableStartAddr, 8); 1120 NV_DECLARE_ALIGNED(NvU64 partitionableEndAddr, 8); 1121 } NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS; 1122 1123 1124 1125 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE 4 1126 1127 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x52U) 1128 1129 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS { 1130 NV_DECLARE_ALIGNED(NvU64 engineMask[NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE], 8); 1131 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; 1132 1133 #define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS 2 1134 #define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID 64 1135 /*! 1136 * NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS 1137 * 1138 * Promote a single partition's runlist buffers allocated by kernel Client RM to Physical RM 1139 * 1140 * rlBuffers [IN] 1141 * 2D array of runlist buffers for a single partition 1142 * 1143 * runlistIdMask [IN] 1144 * Mask of runlists belonging to partition 1145 * 1146 */ 1147 #define NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS (0x20800a53) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID" */ 1148 1149 #define NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID (0x53U) 1150 1151 typedef struct NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS { 1152 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MEMDESC_INFO rlBuffers[NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID][NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS], 8); 1153 NV_DECLARE_ALIGNED(NvU64 runlistIdMask, 8); 1154 NvU32 swizzId; 1155 } NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS; 1156 1157 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO (0x20800a54) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID" */ 1158 1159 #define NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID (0x54U) 1160 1161 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS { 1162 TEGRA_IMP_IMPORT_DATA tegraImpImportData; 1163 } NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS; 1164 1165 #define NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO (0x20800a55) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID" */ 1166 1167 #define NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID (0x55U) 1168 1169 typedef struct NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS { 1170 NvU16 pciDeviceId; 1171 NvU16 pciSubDeviceId; 1172 NvBool iseGPUBridge; 1173 NvU8 approvedBusType; 1174 } NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS; 1175 1176 #define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE (0x00000000) 1177 #define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM (0x00000001) 1178 #define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2 (0x00000002) 1179 #define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3 (0x00000003) 1180 1181 1182 /*! 1183 * NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR 1184 * 1185 * This command triggers a sysmembar to flush VIDMEM writes. 1186 * This command accepts no parameters. 1187 * 1188 */ 1189 #define NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR (0x20800a70) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x70" */ 1190 1191 /* 1192 * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL 1193 * 1194 * Setup local PCIE P2P Mailbox 1195 * 1196 * local2Remote[IN] 1197 * Local peer ID of remote gpu on local gpu 1198 * 1199 * remote2Local[IN] 1200 * Remote peer ID of local gpu on remote gpu 1201 * 1202 * localP2PDomainRemoteAddr[IN] 1203 * P2P domain remote address on local gpu 1204 * 1205 * remoteP2PDomainLocalAddr[IN] 1206 * P2P domain local address on remote gpu 1207 * 1208 * remoteWMBoxLocalAddr[IN] 1209 * Local mailbox address on remote gpu 1210 * 1211 * p2pWmbTag[OUT] 1212 * Tag for mailbox to transport from local to remote GPU 1213 * 1214 * bNeedWarBug999673[IN] 1215 * Set to true if WAR for bug 999673 is required 1216 * 1217 * Possible status values returned are: 1218 * NV_OK 1219 * NV_ERR_NOT_SUPPORTED 1220 */ 1221 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL (0x20800a71) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID" */ 1222 1223 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID (0x71U) 1224 1225 typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS { 1226 NvU32 local2Remote; 1227 NvU32 remote2Local; 1228 NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8); 1229 NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8); 1230 NV_DECLARE_ALIGNED(NvU64 remoteWMBoxLocalAddr, 8); 1231 NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8); 1232 NvBool bNeedWarBug999673; 1233 } NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS; 1234 1235 /* 1236 * NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE 1237 * 1238 * Setup remote PCIE P2P Mailbox 1239 * 1240 * local2Remote[IN] 1241 * Local peer ID of remote gpu on local gpu 1242 * 1243 * remote2Local[IN] 1244 * Remote peer ID of local gpu on remote gpu 1245 * 1246 * localP2PDomainRemoteAddr[IN] 1247 * P2P domain remote address on local gpu 1248 * 1249 * remoteP2PDomainLocalAddr[IN] 1250 * P2P domain local address on remote gpu 1251 * 1252 * remoteWMBoxAddrU64[IN] 1253 * Mailbox address on remote gpu 1254 * 1255 * p2pWmbTag[IN] 1256 * Tag for mailbox to transport from local to remote GPU 1257 * 1258 * Possible status values returned are: 1259 * NV_OK 1260 * NV_ERR_NOT_SUPPORTED 1261 */ 1262 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE (0x20800a72) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID" */ 1263 1264 #define NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID (0x72U) 1265 1266 typedef struct NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS { 1267 NvU32 local2Remote; 1268 NvU32 remote2Local; 1269 NV_DECLARE_ALIGNED(NvU64 localP2PDomainRemoteAddr, 8); 1270 NV_DECLARE_ALIGNED(NvU64 remoteP2PDomainLocalAddr, 8); 1271 NV_DECLARE_ALIGNED(NvU64 remoteWMBoxAddrU64, 8); 1272 NV_DECLARE_ALIGNED(NvU64 p2pWmbTag, 8); 1273 } NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS; 1274 1275 /* 1276 * NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX 1277 * 1278 * Destroy PCIE P2P Mailbox 1279 * 1280 * peerIdx[IN] 1281 * Peer ID of the P2P destination GPU 1282 * 1283 * bNeedWarBug999673[IN] 1284 * Set to true if WAR for bug 999673 is required 1285 * 1286 * Possible status values returned are: 1287 * NV_OK 1288 * NV_ERR_NOT_SUPPORTED 1289 */ 1290 #define NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX (0x20800a73) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID" */ 1291 1292 #define NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID (0x73U) 1293 1294 typedef struct NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS { 1295 NvU32 peerIdx; 1296 NvBool bNeedWarBug999673; 1297 } NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS; 1298 1299 /* 1300 * NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING 1301 * 1302 * Create C2C mapping to a given peer GPU 1303 * 1304 * peerId[IN] 1305 * Peer ID for local to remote GPU 1306 * 1307 * Possible status values returned are: 1308 * NV_OK 1309 * NV_ERR_NOT_SUPPORTED 1310 */ 1311 #define NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING (0x20800a74) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */ 1312 1313 #define NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x74U) 1314 1315 typedef struct NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS { 1316 NvU32 peerId; 1317 } NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS; 1318 1319 /* 1320 * NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING 1321 * 1322 * Remove C2C mapping to a given peer GPU 1323 * 1324 * peerId[IN] 1325 * Peer ID for local to remote GPU 1326 * 1327 * Possible status values returned are: 1328 * NV_OK 1329 * NV_ERR_NOT_SUPPORTED 1330 */ 1331 #define NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING (0x20800a75) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID" */ 1332 1333 #define NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID (0x75U) 1334 1335 typedef struct NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS { 1336 NvU32 peerId; 1337 } NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS; 1338 1339 /*! 1340 * NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES 1341 * 1342 * Retrieves the corresponding SPAs (per the given GFID's VMMU mappings) 1343 * for the given array of GPAs. 1344 * 1345 * gfid [IN] 1346 * GFID to translate GPAs for 1347 * 1348 * numEntries [IN] 1349 * Number of entries (<= NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES) 1350 * to translate (i.e. number of elements in gpaEntries) 1351 * 1352 * gpaEntries [IN] 1353 * Array of GPAs to translate 1354 * 1355 * spaEntries [OUT] 1356 * Resulting array of SPAs 1357 */ 1358 #define NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES (0x20800a57) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID" */ 1359 1360 #define NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES 128 1361 1362 #define NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID (0x57U) 1363 1364 typedef struct NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS { 1365 NvU32 gfid; 1366 NvU32 numEntries; 1367 NV_DECLARE_ALIGNED(NvU64 gpaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8); 1368 NV_DECLARE_ALIGNED(NvU64 spaEntries[NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES], 8); 1369 } NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS; 1370 1371 /*! 1372 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER 1373 * 1374 * Pass required pushbuffer parameters from kernel RM to Physical RM 1375 * 1376 * addressSpace [IN] 1377 * Address space of pushbuffer whtether it is ADDR_SYSMEM or ADDR_FBMEM 1378 * 1379 * physicalAddr [IN] 1380 * Physical address of pushbuffer 1381 * 1382 * addressSpace [IN] 1383 * Limit of the pushbuffer address, it should be less than 4K 1384 * 1385 * cacheSnoop [IN] 1386 * Cachesnoop supported or not 1387 * 1388 * channelInstance [IN] 1389 * Channel instance pass by the client to get corresponding dispchannel 1390 * 1391 * hclass [IN] 1392 * External class ID pass by the client to get the channel class 1393 * 1394 * valid [IN] 1395 * This bit indicates whether pushbuffer parameters are valid or not 1396 * 1397 * pbTargetAperture [IN] 1398 * Indicates the PushBuffer Target Aperture type (IOVA, PCI, PCI_COHERENT or NVM) 1399 * 1400 */ 1401 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */ 1402 1403 #define NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID (0x58U) 1404 1405 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS { 1406 NvU32 addressSpace; 1407 NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8); 1408 NV_DECLARE_ALIGNED(NvU64 limit, 8); 1409 NvU32 cacheSnoop; 1410 NvU32 hclass; 1411 NvU32 channelInstance; 1412 NvBool valid; 1413 NvU32 pbTargetAperture; 1414 } NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS; 1415 1416 /*! 1417 * NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO 1418 * 1419 * This command obtains information from physical RM for use by CPU-RM. 1420 * 1421 * replayableFaultBufferSize 1422 * Default size of replayable fault buffer 1423 * 1424 * nonReplayableFaultBufferSize 1425 * Default size of non-replayable fault buffer 1426 * 1427 */ 1428 1429 #define NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO (0x20800a59) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 1430 1431 #define NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0x59U) 1432 1433 typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS { 1434 NvU32 replayableFaultBufferSize; 1435 NvU32 replayableShadowFaultBufferMetadataSize; 1436 NvU32 nonReplayableFaultBufferSize; 1437 NvU32 nonReplayableShadowFaultBufferMetadataSize; 1438 } NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS; 1439 1440 /*! 1441 * @ref NV2080_CTRL_CMD_GR_GET_CTXSW_MODES 1442 */ 1443 #define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */ 1444 1445 #define NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x5AU) 1446 1447 typedef NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS; 1448 1449 /*! 1450 * NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE 1451 * 1452 * Get heap reservation size needed by different module 1453 */ 1454 #define NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE (0x20800a5b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID" */ 1455 1456 #define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID (0x5BU) 1457 1458 typedef struct NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS { 1459 NvU32 moduleIndex; 1460 NvU32 size; 1461 } NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS; 1462 1463 /*! 1464 * NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE 1465 * 1466 * tableLen [OUT] 1467 * Number of valid records in table field. 1468 * 1469 * table [OUT] 1470 * Interrupt table for Kernel RM. 1471 * 1472 * subtreeMap [OUT] 1473 * Subtree range for each NV2080_INTR_CATEGORY. 1474 */ 1475 #define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */ 1476 1477 #define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE 128 1478 1479 /*! 1480 * Categories of interrupts. 1481 * 1482 * Each of these categories get a separate range of interrupt subtrees (top 1483 * level bits). 1484 */ 1485 typedef enum NV2080_INTR_CATEGORY { 1486 NV2080_INTR_CATEGORY_DEFAULT = 0, 1487 NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1, 1488 NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2, 1489 NV2080_INTR_CATEGORY_RUNLIST = 3, 1490 NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4, 1491 NV2080_INTR_CATEGORY_UVM_OWNED = 5, 1492 NV2080_INTR_CATEGORY_UVM_SHARED = 6, 1493 NV2080_INTR_CATEGORY_ENUM_COUNT = 7, 1494 } NV2080_INTR_CATEGORY; 1495 1496 #define NV2080_INTR_INVALID_SUBTREE NV_U8_MAX 1497 1498 typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP { 1499 NvU8 subtreeStart; 1500 NvU8 subtreeEnd; 1501 } NV2080_INTR_CATEGORY_SUBTREE_MAP; 1502 1503 typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY { 1504 NvU16 engineIdx; 1505 NvU32 pmcIntrMask; 1506 NvU32 vectorStall; 1507 NvU32 vectorNonStall; 1508 } NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY; 1509 1510 #define NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID (0x5CU) 1511 1512 typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS { 1513 NvU32 tableLen; 1514 NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE]; 1515 NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT]; 1516 } NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS; 1517 1518 /* Index to retrieve the needed heap space for specific module */ 1519 #define NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR (0x00000000) 1520 1521 /* 1522 * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK 1523 * 1524 * Checking if the reservation / release of the PERFMON HW is possible 1525 * 1526 * bReservation [IN] 1527 * NV_TRUE -> request for reservation, NV_FALSE -> request for release 1528 * 1529 */ 1530 #define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK (0x20800a98) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID" */ 1531 1532 1533 #define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID (0x98U) 1534 1535 typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS { 1536 NvBool bReservation; 1537 } NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS; 1538 1539 /*! 1540 * NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET 1541 * 1542 * Reserving / Releasing PERFMON HW 1543 * 1544 * bReservation [IN] 1545 * NV_TRUE -> request for reservation, NV_FALSE -> request for release 1546 * 1547 * bClientHandlesGrGating [IN] 1548 * DM-TODO: Add comment for this 1549 * 1550 * bRmHandlesIdleSlow [IN] 1551 * If the IDLE slowdown is required 1552 * 1553 */ 1554 #define NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET (0x20800a99) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID" */ 1555 1556 #define NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID (0x99U) 1557 1558 typedef struct NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS { 1559 NvBool bReservation; 1560 NvBool bClientHandlesGrGating; 1561 NvBool bRmHandlesIdleSlow; 1562 } NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS; 1563 1564 /*! 1565 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES 1566 * 1567 * Get active display devices 1568 * 1569 * displayMask [OUT] 1570 * Get the mask of the active display devices in VBIOS 1571 * 1572 * numHeads [OUT] 1573 * Number of heads display supported. 1574 * 1575 */ 1576 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES (0x20800a5d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID" */ 1577 1578 #define NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID (0x5DU) 1579 1580 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS { 1581 1582 NvU32 displayMask; 1583 NvU32 numHeads; 1584 } NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS; 1585 1586 1587 1588 /* 1589 * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES 1590 * 1591 * Get FB Mem page ranges for all possible swizzIds 1592 * 1593 * fbMemPageRanges [OUT] 1594 * Mem page ranges for each swizzId in the form of {lo, hi} 1595 */ 1596 #define NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a60) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */ 1597 1598 #define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15 1599 1600 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U) 1601 1602 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS { 1603 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE fbMemPageRanges[NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID], 8); 1604 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS; 1605 1606 /*! 1607 * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS 1608 * 1609 * This command is an internal command sent from Kernel RM to Physical RM 1610 * to get number of channels for a given runlist ID 1611 * 1612 * runlistId [IN] 1613 * numChannels [OUT] 1614 */ 1615 #define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS (0x20800a61) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID" */ 1616 1617 #define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID (0x61U) 1618 1619 typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS { 1620 NvU32 runlistId; 1621 NvU32 numChannels; 1622 } NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS; 1623 1624 /*! 1625 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES 1626 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES 1627 */ 1628 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID" */ 1629 1630 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x63U) 1631 1632 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS; 1633 1634 /*! 1635 * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES 1636 * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES 1637 */ 1638 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID" */ 1639 1640 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x65U) 1641 1642 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; 1643 1644 /*! 1645 * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES 1646 * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES 1647 */ 1648 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */ 1649 1650 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x66U) 1651 1652 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS; 1653 1654 /*! 1655 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG 1656 * NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG 1657 * 1658 * This command retrieves memory config from HW 1659 * 1660 * memBoundaryCfgA [OUT] 1661 * Memory boundary config A (4KB aligned) 1662 * 1663 * memBoundaryCfgB [OUT] 1664 * Memory boundary config B (4KB aligned) 1665 * 1666 * memBoundaryCfgC [OUT] 1667 * Memory boundary config C (64KB aligned) 1668 * 1669 * memBoundaryCfg [OUT] 1670 * Memory boundary config (64KB aligned) 1671 * 1672 * memBoundaryCfgValInit [OUT] 1673 * Memory boundary config initial value (64KB aligned) 1674 */ 1675 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */ 1676 1677 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x68U) 1678 1679 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS { 1680 NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgA, 8); 1681 NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgB, 8); 1682 NvU32 memBoundaryCfgC; 1683 NvU32 memBoundaryCfg; 1684 NvU32 memBoundaryCfgValInit; 1685 } NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; 1686 1687 #define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */ 1688 1689 #define NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x67U) 1690 1691 typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS; 1692 1693 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE (0x20800a6b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID" */ 1694 1695 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE 8 1696 1697 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID (0x6BU) 1698 1699 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS { 1700 NvU32 data[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE]; 1701 } NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS; 1702 1703 /*! 1704 * NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT 1705 * 1706 * Invoke RC recovery after watchdog timeout is hit. 1707 */ 1708 #define NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT (0x20800a6a) /* finn: Evaluated from "((FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6a)" */ 1709 1710 /* ! 1711 * This command disables cuda limit activation at teardown of the client. 1712 */ 1713 #define NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */ 1714 1715 /* 1716 * This command is cleaning up OPTP when a client is found to have 1717 * been terminated unexpectedly. 1718 */ 1719 #define NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR (0x20800a7c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7C" */ 1720 1721 /* ! 1722 * This command is used to get the current AUX power state of the sub-device. 1723 */ 1724 #define NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE (0x20800a81) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */ 1725 1726 #define NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x81U) 1727 1728 typedef struct NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS { 1729 NvU32 powerState; 1730 } NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS; 1731 1732 /*! 1733 * This command can be used to boost P-State up one level or to the highest for a limited 1734 * duration for the associated subdevice. Boosts from different clients are being tracked 1735 * independently. Note that there are other factors that can limit P-States so the resulting 1736 * P-State may differ from expectation. 1737 * 1738 * flags 1739 * This parameter specifies the actual command. _CLEAR is to clear existing boost. 1740 * _BOOST_1LEVEL is to boost P-State one level higher. _BOOST_TO_MAX is to boost 1741 * to the highest P-State. 1742 * duration 1743 * This parameter specifies the duration of the boost in seconds. This has to be less 1744 * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. 1745 * 1746 * Possible status values returned are: 1747 * NV_OK 1748 * NV_ERR_INVALID_PARAM_STRUCT 1749 * NV_ERR_INVALID_ARGUMENT 1750 */ 1751 #define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X (0x20800a9a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID" */ 1752 1753 #define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID (0x9AU) 1754 1755 typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X { 1756 1757 NvBool flags; 1758 NvU32 duration; 1759 } NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X; 1760 1761 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE 0U 1762 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK 1U 1763 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK 1764 #define NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM (0x2U) /* finn: Evaluated from "NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST + 1" */ 1765 1766 /*! 1767 * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL 1768 * 1769 * Activate/Deactivate GPU Boost Sync algorithm 1770 * 1771 * bActivate [IN] 1772 * GPU Boost Sync algorithm: 1773 * NV_TRUE -> activate 1774 * NV_FALSE -> deactivate 1775 * 1776 */ 1777 #define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL (0x20800a7e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID" */ 1778 1779 #define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7EU) 1780 1781 typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS { 1782 NvBool bActivate; 1783 } NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS; 1784 1785 /*! 1786 * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS 1787 * 1788 * Apply given limits to a specific subdevice 1789 * 1790 * flags [IN] 1791 * DM-TODO: write description here 1792 * 1793 * bBridgeless [IN] 1794 * Bridgeless information, for now supporting only MIO bridges 1795 * 1796 * currLimits 1797 * Array of limits that will be applied 1798 * 1799 */ 1800 #define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS (0x20800a7f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID" */ 1801 1802 #define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID (0x7FU) 1803 1804 typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS { 1805 NvU32 flags; 1806 NvBool bBridgeless; 1807 NvU32 currLimits[NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM]; 1808 } NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS; 1809 1810 /*! 1811 * NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO 1812 * 1813 * Data for GPU Boost Sync structure initialization 1814 * 1815 * hysteresisus [OUT] 1816 * Hysteresis value for GPU Boost synchronization hysteresis algorithm. 1817 * 1818 * bHystersisEnable [OUT] 1819 * hysteresis algorithm for SLI GPU Boost synchronization: 1820 * NV_TRUE -> enabled, 1821 * NV_FALSE -> disabled 1822 * 1823 * bSliGpuBoostSyncEnable [OUT] 1824 * SLI GPU Boost feature is: 1825 * NV_TRUE -> enabled, 1826 * NV_FALSE -> disabled 1827 * 1828 */ 1829 #define NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO (0x20800a80) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID" */ 1830 1831 #define NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID (0x80U) 1832 1833 typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS { 1834 NV_DECLARE_ALIGNED(NvU64 hysteresisus, 8); 1835 NvBool bHystersisEnable; 1836 NvBool bSliGpuBoostSyncEnable; 1837 } NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS; 1838 1839 /* 1840 * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER 1841 * 1842 * This command sends replayable fault buffer pages allocated by CPU-RM 1843 * to be setup and enabled in physical RM. 1844 * 1845 * hClient 1846 * Client handle. 1847 * 1848 * hObject 1849 * Object handle. 1850 * 1851 * faultBufferSize 1852 * Size of the replayable fault buffer to register. 1853 * 1854 * faultBufferPteArray 1855 * Pages of replayable fault buffer. 1856 * 1857 * Possible status values returned are: 1858 * NV_OK 1859 */ 1860 #define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER (0x20800a9b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ 1861 1862 #define NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES 256 1863 #define NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9BU) 1864 1865 typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS { 1866 NvHandle hClient; 1867 NvHandle hObject; 1868 NvU32 faultBufferSize; 1869 NV_DECLARE_ALIGNED(NvU64 faultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES], 8); 1870 } NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS; 1871 1872 /* 1873 * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER 1874 * 1875 * This command requests physical RM to disable the replayable fault buffer. 1876 * 1877 * Possible status values returned are: 1878 * NV_OK 1879 */ 1880 #define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER (0x20800a9c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9C" */ 1881 1882 // Valid fault buffer types 1883 #define NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000) 1884 #define NV2080_CTRL_FAULT_BUFFER_REPLAYABLE (0x00000001) 1885 1886 /* 1887 * NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER 1888 * 1889 * This command sends client shadow fault buffer pages allocated by CPU-RM 1890 * to be setup and enabled in physical RM. 1891 * 1892 * shadowFaultBufferQueuePhysAddr 1893 * Physical address of shadow fault buffer queue. 1894 * 1895 * faultBufferSize 1896 * Size of the client shadow fault buffer to register. 1897 * 1898 * shadowFaultBufferPteArray 1899 * Pages of client shadow fault buffer. 1900 * 1901 * shadowFaultBufferType 1902 * Replayable or non-replayable fault buffer 1903 * 1904 * faultBufferSharedMemoryPhysAddr 1905 * Fault buffer shared memory address. Used only by the Replayable fault buffer. 1906 * 1907 * Possible status values returned are: 1908 * NV_OK 1909 */ 1910 #define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ 1911 1912 #define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 3000 1913 #define NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9DU) 1914 1915 typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { 1916 NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8); 1917 NvU32 shadowFaultBufferSize; 1918 NvU32 shadowFaultBufferMetadataSize; 1919 NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8); 1920 NvU32 shadowFaultBufferType; 1921 NV_DECLARE_ALIGNED(NvU64 faultBufferSharedMemoryPhysAddr, 8); 1922 } NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; 1923 1924 /* 1925 * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER 1926 * 1927 * This command requests physical RM to disable the client shadow fault buffer. 1928 * 1929 * shadowFaultBufferType 1930 * Replayable or non-replayable fault buffer 1931 * 1932 * Possible status values returned are: 1933 * NV_OK 1934 */ 1935 #define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */ 1936 1937 #define NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9EU) 1938 1939 typedef struct NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS { 1940 NvU32 shadowFaultBufferType; 1941 } NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; 1942 1943 /* 1944 * NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER 1945 * 1946 * Pin PDEs for Global VA range on the server RM and then mirror the client's page 1947 * directory/tables in the server. 1948 * 1949 * Possible status values returned are: 1950 * NV_OK 1951 */ 1952 #define NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER (0x20800a9f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID" */ 1953 1954 #define NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID (0x9FU) 1955 1956 typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS { 1957 NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8); 1958 } NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS; 1959 1960 /*! 1961 * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X 1962 * 1963 * This command can be used to boost P-State the highest for a limited 1964 * duration for the associated subdevice. Boosts from different clients are being tracked 1965 * independently. Note that there are other factors that can limit P-States so the resulting 1966 * P-State may differ from expectation. 1967 * 1968 * flags [IN] 1969 * This parameter specifies the actual command. _CLEAR is to clear existing boost. 1970 * and _BOOST_TO_MAX is to boost to the highest P-State. 1971 * 1972 * boostDuration [IN] 1973 * This parameter specifies the duration of the boost in seconds. This has to be less 1974 * than NV2080_CTRL_PERF_BOOST_DURATION_MAX. 1975 * 1976 * gfId [IN] 1977 * This specifies Id of the Kernel RM that is requesting the Boost 1978 * 1979 * bOverrideInfinite[IN] 1980 * This parameter specifies if we want to override already registered infinite boost for the specific Kernel RM. 1981 * This should be NV_TRUE only in case when we are removing the current infinite boost for a specific Kernel RM 1982 * and setting the boost duration to a next maximum duration registered for the Kernel RM in question. 1983 * 1984 * Possible status values returned are: 1985 * NV_OK 1986 * NV_ERR_INVALID_PARAM_STRUCT 1987 * NV_ERR_INVALID_ARGUMENT 1988 */ 1989 #define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */ 1990 1991 #define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U) 1992 1993 typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X { 1994 NvU32 flags; 1995 NvU32 boostDuration; 1996 NvU32 gfId; 1997 NvBool bOverrideInfinite; 1998 } NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X; 1999 2000 /*! 2001 * NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X 2002 * 2003 * Clear the boost for specific Kernel RM 2004 * 2005 * bIsCudaClient [IN] 2006 * Specifies if the request is for clearing the CUDA boost or regular boost 2007 * NV_TRUE -> CUDA boost, NV_FALSE otherwise 2008 * 2009 * gfId [IN] 2010 * Specifies Id of the Kernel RM that is requesting Boost clear 2011 * 2012 */ 2013 #define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X (0x20800aa1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID" */ 2014 2015 #define NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID (0xA1U) 2016 2017 typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X { 2018 2019 NvBool bIsCudaClient; 2020 NvU32 gfId; 2021 } NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X; 2022 2023 /* 2024 * NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO 2025 * 2026 * Retrieves skyline information about the GPU. Params are sized to currently known max 2027 * values, but will need to be modified in the future should that change. 2028 */ 2029 #define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO (0x20800aa2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */ 2030 2031 #define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES 8 2032 #define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 12 2033 /*! 2034 * NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO 2035 * skylineVgpcSize[OUT] 2036 * - TPC count of non-singleton VGPCs 2037 * singletonVgpcMask[OUT] 2038 * - Mask of active Singletons 2039 * maxInstances[OUT] 2040 * - Max allowed instances of this skyline concurrently on a GPU 2041 * computeSizeFlag 2042 * - One of NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* flags which is associated with this skyline 2043 * numNonSingletonVgpcs 2044 * - Number of VGPCs with non-zero TPC counts which are not singletons 2045 */ 2046 typedef struct NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO { 2047 NvU8 skylineVgpcSize[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS]; 2048 NvU32 singletonVgpcMask; 2049 NvU32 maxInstances; 2050 NvU32 computeSizeFlag; 2051 NvU32 numNonSingletonVgpcs; 2052 } NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO; 2053 2054 /*! 2055 * NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS 2056 * skylineTable[OUT] 2057 * - TPC count of non-singleton VGPCs 2058 * - Mask of singleton vGPC IDs active 2059 * - Max Instances of this skyline possible concurrently 2060 * - Associated compute size with the indexed skyline 2061 * - Number of VGPCs with non-zero TPC counts which are not singletons 2062 * validEntries[OUT] 2063 * - Number of entries which contain valid info in skylineInfo 2064 */ 2065 #define NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID (0xA2U) 2066 2067 typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS { 2068 NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO skylineTable[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES]; 2069 NvU32 validEntries; 2070 } NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS; 2071 2072 /*! 2073 * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE 2074 */ 2075 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */ 2076 2077 #define NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0xA3U) 2078 2079 typedef NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS; 2080 2081 /*! 2082 * @ref NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION 2083 */ 2084 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2085 2086 #define NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA4U) 2087 2088 typedef NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS; 2089 2090 /*! 2091 * @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONS 2092 */ 2093 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */ 2094 2095 #define NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA5U) 2096 2097 typedef NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS; 2098 2099 /*! 2100 * @ref NV2080_CTRL_CMD_GPU_GET_PARTITIONS 2101 */ 2102 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */ 2103 2104 #define NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA6U) 2105 2106 typedef NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS; 2107 2108 /*! 2109 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED 2110 * 2111 * Tell Physical RM whether any ZBC-kind surfaces are allocated. 2112 * If PF and all VFs report false, ZBC table can be flushed by Physical RM. 2113 * 2114 * bZbcReferenced [IN] 2115 * NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM 2116 * 2117 */ 2118 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */ 2119 2120 #define NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x69U) 2121 2122 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS { 2123 NvBool bZbcSurfacesExist; 2124 } NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS; 2125 2126 /*! 2127 * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE 2128 * 2129 * Export the resource and placement information about a gpu instance such that a 2130 * similar gpu instance can be recreated from scratch in the same position on the 2131 * same or similar GPU. Note that different GPUs may have different physical 2132 * resources due to floorsweeping, and an imported gpu instance is not guaranteed 2133 * to get the exact same resources as the exported gpu instance, but the imported 2134 * gpu instance should behave identically with respect to fragmentation and 2135 * placement / span positioning. 2136 */ 2137 #define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2138 2139 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2140 2141 /*! 2142 * NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE 2143 * 2144 * Create a gpu instance resembling the exported instance info. Note that 2145 * different GPUs may have different physical resources due to floorsweeping, 2146 * and an imported gpu instance is not guaranteed to get the exact same resources 2147 * as the exported gpu instance, but the imported gpu instance should behave 2148 * identically with respect to fragmentation and placement / span positioning. 2149 */ 2150 #define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2151 2152 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */ 2153 2154 #define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE 4 2155 typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO { 2156 NV_DECLARE_ALIGNED(NvU64 enginesMask[NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE], 8); 2157 NvU32 partitionFlags; 2158 NvU32 gpcMask; 2159 NvU32 virtualGpcCount; 2160 NvU32 veidOffset; 2161 NvU32 veidCount; 2162 } NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO; 2163 2164 typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS { 2165 NvU32 swizzId; 2166 NvU8 uuid[NV_GI_UUID_LEN]; 2167 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8); 2168 } NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS; 2169 2170 #define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA7U) 2171 2172 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS; 2173 2174 #define NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA8U) 2175 2176 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS; 2177 2178 #define NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA9U) 2179 2180 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS; 2181 2182 #define NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xAAU) 2183 2184 typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS; 2185 2186 /*! 2187 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT 2188 * 2189 * Invalidate and/or evict the L2 cache 2190 * 2191 * flags [IN] 2192 * flags that specify required actions 2193 * 2194 */ 2195 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT (0x20800a6c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID" */ 2196 2197 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID (0x6cU) 2198 2199 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS { 2200 NvU32 flags; 2201 } NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS; 2202 2203 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL (0x00000001) 2204 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST (0x00000002) 2205 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST (0x00000004) 2206 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL (0x00000008) 2207 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN (0x00000010) 2208 #define NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL (0x00000020) 2209 2210 /*! 2211 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES 2212 * 2213 * Flush all L2 Rams and Caches using the ELPG flush 2214 * 2215 */ 2216 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES (0x20800a6d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6D" */ 2217 2218 /*! 2219 * NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO 2220 * 2221 * This command obtains information from physical RM for use by CPU-RM 2222 * 2223 * Data fields -> 2224 * bPcieGen4Capable - tells whether PCIe is Gen4 capable 2225 */ 2226 #define NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO (0x20800aac) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 2227 2228 #define NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xacU) 2229 2230 typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS { 2231 NvBool bPcieGen4Capable; 2232 NvBool bIsC2CLinkUp; 2233 NvBool bIsDeviceMultiFunction; 2234 NvBool bGcxPmuCfgSpaceRestore; 2235 NV_DECLARE_ALIGNED(NvU64 dmaWindowStartAddress, 8); 2236 } NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS; 2237 2238 /*! 2239 * NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG 2240 * 2241 * Program HSHUB Peer Conn Config space. 2242 * 2243 * programPeerMask[IN] 2244 * If nonzero, the peer mask for programming peers based on hshub connectivity. 2245 * 2246 * invalidatePeerMask[IN] 2247 * If nonzero, the peer mask for invalidating peers. 2248 * 2249 * programPciePeerMask[IN] 2250 * If nonzero, the peer mask for programming peers in pcie case. 2251 * 2252 * Possible status values returned are: 2253 * NV_OK 2254 * NV_WARN_NOTHING_TO_DO 2255 * If all peer masks are zero. 2256 */ 2257 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG (0x20800a88) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID" */ 2258 2259 #define NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID (0x88U) 2260 2261 typedef struct NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS { 2262 NvU32 programPeerMask; 2263 NvU32 invalidatePeerMask; 2264 NvU32 programPciePeerMask; 2265 } NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS; 2266 2267 /*! 2268 * NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID 2269 * 2270 * Given a mask of link ids, find the first with a valid peerId. 2271 * 2272 * linkMask[IN] 2273 * Mask of linkIds to check. 2274 * 2275 * peerId[OUT] 2276 * The peerId for the lowest-index link with a valid peerId, if any. 2277 * If none found, NV2080_CTRLINTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER (return value will still be NV_OK). 2278 * 2279 * Possible status values returned are: 2280 * NV_OK 2281 * 2282 */ 2283 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID (0x20800a89) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID" */ 2284 2285 #define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER 0xffffffff 2286 2287 #define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID (0x89U) 2288 2289 typedef struct NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS { 2290 NvU32 linkMask; 2291 NvU32 peerId; 2292 } NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS; 2293 2294 /*! 2295 * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS 2296 * 2297 * Get the Hshub Ids connected to the other end of links. 2298 * 2299 * linkMask[IN] 2300 * A mask of link ids to query. 2301 * 2302 * hshubIds[OUT] 2303 * For each set bit in the link mask, the peer Hshub Id. 2304 * 2305 * Possible status values returned are: 2306 * NV_OK 2307 * NV_WARN_NOTHING_TO_DO 2308 * If the mask is zero. 2309 */ 2310 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS (0x20800a8a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID" */ 2311 #define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE 32 2312 2313 #define NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID (0x8aU) 2314 2315 typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS { 2316 NvU32 linkMask; 2317 NvU8 hshubIds[NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE]; 2318 } NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS; 2319 2320 /*! 2321 * NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS 2322 * 2323 * Return the number of HSHUB units. 2324 * 2325 * numHshubs[OUT] 2326 * 2327 * Possible status values returned are: 2328 * NV_OK 2329 */ 2330 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS (0x20800a8b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID" */ 2331 2332 #define NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID (0x8bU) 2333 2334 typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS { 2335 NvU32 numHshubs; 2336 } NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS; 2337 2338 /*! 2339 * NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID 2340 * 2341 * Return the next hshubId after the given hshubId. 2342 * 2343 * hshubId[IN/OUT] 2344 * 2345 * Possible status values returned are: 2346 * NV_OK 2347 */ 2348 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID (0x20800a8c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID" */ 2349 2350 #define NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID (0x8cU) 2351 2352 typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS { 2353 NvU8 hshubId; 2354 } NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS; 2355 2356 /*! 2357 * NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG 2358 * 2359 * Program HSHUB for EGM peer id. 2360 * 2361 * egmPeerId[IN] 2362 * EGM peer id to program in the HSHUB registers. 2363 * 2364 * Possible status values returned are: 2365 * NV_OK 2366 */ 2367 #define NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG (0x20800a8d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID" */ 2368 2369 #define NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID (0x8dU) 2370 2371 typedef struct NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS { 2372 NvU32 egmPeerId; 2373 } NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS; 2374 2375 2376 2377 /* 2378 * NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR 2379 * 2380 * Enable compute peer addressing mode 2381 * This command accepts no parameters. 2382 */ 2383 2384 #define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR (0x20800aad) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xad" */ 2385 2386 /* 2387 * NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR 2388 * 2389 * Get/Set NVSwitch fabric address for FLA 2390 * 2391 * [In] bGet 2392 * Whether to get or set the NVSwitch fabric address 2393 * [In/Out] addr 2394 * Address that is to be set or retrieved. 2395 */ 2396 #define NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID (0xaeU) 2397 2398 typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS { 2399 NvBool bGet; 2400 NV_DECLARE_ALIGNED(NvU64 addr, 8); 2401 } NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS; 2402 2403 #define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR (0x20800aae) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID" */ 2404 2405 /*! 2406 * NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS 2407 * 2408 * This command obtains information from physical RM for use by CPU-RM 2409 * 2410 * Data fields -> 2411 * bCyaMaskL1 2412 * bEnableAspmDtL1 2413 */ 2414 #define NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS (0x20800ab0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID" */ 2415 2416 #define NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID (0xb0U) 2417 2418 typedef struct NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS { 2419 NvBool bCyaMaskL1; 2420 NvBool bEnableAspmDtL1; 2421 } NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS; 2422 2423 /*! 2424 * NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT 2425 * 2426 * Sets number of VM slots that are active in VGPU's scheduler 2427 * 2428 * maxActiveVGpuVMCount [IN] 2429 * Number of VM slots that are active in vGPU's scheduler. 2430 * 2431 * Possible status values returned are: 2432 * NV_OK 2433 * NV_ERR_OUT_OF_RANGE - Passed value is out of range 2434 * NV_ERR_NO_MEMORY - Out of memory 2435 */ 2436 #define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT (0x20800ab1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID" */ 2437 2438 /*! 2439 * Maximum value of VM slots that are active in vGPU's scheduler. 2440 */ 2441 #define NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE 32 2442 2443 #define NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID (0xB1U) 2444 2445 typedef struct NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS { 2446 NvU8 maxActiveVGpuVMCount; 2447 } NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS; 2448 2449 /*! 2450 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS 2451 * 2452 * Disable all NVLINK FB peers 2453 * 2454 */ 2455 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS (0x20800a6e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6E" */ 2456 2457 /*! 2458 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE 2459 * 2460 * Program GPU in raw / legacy compression mode 2461 * 2462 */ 2463 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE (0x20800a6f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID" */ 2464 2465 #define NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID (0x6fU) 2466 2467 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS { 2468 NvBool bRawMode; 2469 } NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS; 2470 2471 /* 2472 * NV2080_CTRL_CMD_INTERNAL_CCU_MAP 2473 * 2474 * This command gets the shared buffer memory descriptor from the CPU-RM and maps to it 2475 * in physical-RM. 2476 * 2477 * Possible status values returned are: 2478 * NV_OK 2479 * NV_ERR_INVALID_ARGUMENT 2480 * NV_ERR_INVALID_ADDRESS 2481 */ 2482 #define NV2080_CTRL_CMD_INTERNAL_CCU_MAP (0x20800ab3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID" */ 2483 2484 #define NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX 1 2485 #define NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID (0xB3U) 2486 2487 typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS { 2488 NV_DECLARE_ALIGNED(NvU64 phyAddr[NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE + NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX], 8); 2489 } NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS; 2490 /* 2491 * NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP 2492 * 2493 * This command unmaps the shared buffer memory mapping in physical-RM 2494 * 2495 * Possible status values returned are: 2496 * NV_OK 2497 */ 2498 #define NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP (0x20800ab4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID" */ 2499 2500 #define NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID (0xB4U) 2501 2502 typedef struct NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS { 2503 NvBool bDevShrBuf; 2504 NvBool bMigShrBuf; 2505 } NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS; 2506 2507 /*! 2508 * NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO 2509 * 2510 * [in] gpuId 2511 * GPU ID. 2512 * [in] gpuInstance 2513 * GPU instance. 2514 * [in] p2pCaps 2515 * Peer to peer capabilities discovered between the GPUs. 2516 * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. 2517 * [in] p2pOptimalReadCEs 2518 * Mask of CEs to use for p2p reads over Nvlink. 2519 * [in] p2pOptimalWriteCEs 2520 * Mask of CEs to use for p2p writes over Nvlink. 2521 * [in] p2pCapsStatus 2522 * Status of all supported p2p capabilities. 2523 * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. 2524 * [in] busPeerId 2525 * Bus peer ID. For an invalid or a non-existent peer this field 2526 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 2527 */ 2528 typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO { 2529 NvU32 gpuId; 2530 NvU32 gpuInstance; 2531 NvU32 p2pCaps; 2532 NvU32 p2pOptimalReadCEs; 2533 NvU32 p2pOptimalWriteCEs; 2534 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 2535 NvU32 busPeerId; 2536 } NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO; 2537 2538 /*! 2539 * NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS 2540 * 2541 * An internal call to propagate the peer to peer capabilities of peer GPUs 2542 * to the Physical RM. These capabilities are to be consumed by the vGPU GSP plugin. 2543 * This control is used to both add and and update the peer to peer capabilities. 2544 * The existing GPU entries will be updated and those which don't exist will be added. 2545 * Use NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS to remove the added entries. 2546 * 2547 * [in] peerGpuCount 2548 * The number of the peerGpuInfos entries. 2549 * [in] peerGpuInfos 2550 * The array of NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS entries, describing 2551 * the peer to peer capabilities of the specified GPUs. 2552 * 2553 * Possible status values returned are: 2554 * NV_OK 2555 * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount 2556 * NV_ERR_INSUFFICIENT_RESOURCES - Total GPU count exceeds the maximum value 2557 */ 2558 #define NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS (0x20800ab5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID" */ 2559 2560 #define NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID (0xB5U) 2561 2562 typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS { 2563 NvU32 peerGpuCount; 2564 NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO peerGpuInfos[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 2565 } NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS; 2566 2567 /*! 2568 * NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS 2569 * 2570 * An internal call to remove the cached peer to peer capabilities of peer GPUs 2571 * from the Physical RM. 2572 * 2573 * [in] peerGpuIdCount 2574 * The number of the peerGpuIds entries. 2575 * [in] peerGpuIds 2576 * The array of GPU IDs, specifying the GPU for which the entries need to be removed. 2577 * 2578 * Possible status values returned are: 2579 * NV_OK 2580 * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuIdCount 2581 * NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuIds[] entry 2582 */ 2583 #define NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS (0x20800ab6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID" */ 2584 2585 #define NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB6U) 2586 2587 typedef struct NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS { 2588 NvU32 peerGpuIdCount; 2589 NvU32 peerGpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 2590 } NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS; 2591 2592 2593 2594 /*! 2595 * NV2080_CTRL_CMD_INTERNAL_BUS_GET_PCIE_P2P_CAPS 2596 * 2597 * This command returns the GPU's PCIE P2P caps 2598 * 2599 * [in] bCommonPciSwitchFound 2600 * All GPUs are under the same PCI switch 2601 * [out] p2pReadCapsStatus 2602 * [out] p2pWriteCapsStatus 2603 * These members returns status of all supported p2p capabilities. Valid 2604 * status values include: 2605 * NV0000_P2P_CAPS_STATUS_OK 2606 * P2P capability is supported. 2607 * NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED 2608 * Chipset doesn't support p2p capability. 2609 * NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED 2610 * GPU doesn't support p2p capability. 2611 * NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED 2612 * IOH topology isn't supported. For e.g. root ports are on different 2613 * IOH. 2614 * NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY 2615 * P2P Capability is disabled by a regkey. 2616 * NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED 2617 * P2P Capability is not supported. 2618 * 2619 * Possible status values returned are: 2620 * NV_OK 2621 * NV_ERR_INVALID_ARGUMENT 2622 * NV_ERR_INVALID_PARAM_STRUCT 2623 */ 2624 #define NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS (0x20800ab8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID" */ 2625 2626 #define NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB8U) 2627 2628 typedef struct NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS { 2629 NvBool bCommonPciSwitchFound; 2630 NvU8 p2pReadCapsStatus; 2631 NvU8 p2pWriteCapsStatus; 2632 } NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS; 2633 2634 /*! 2635 * NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO 2636 * 2637 * Enable/disable PCIe Relaxed Ordering. 2638 * 2639 */ 2640 #define NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO (0x20800ab9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID" */ 2641 2642 #define NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID (0xB9U) 2643 2644 typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS { 2645 // Enable/disable PCIe relaxed ordering 2646 NvBool enableRo; 2647 } NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS; 2648 2649 /* 2650 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE 2651 * 2652 * An internal call to invoke the sequence VGA register reads & writes to 2653 * perform save and restore of VGA 2654 * 2655 * [in] bSave 2656 * To indicate whether save or restore needs to be performed. 2657 * [in] bUseVbios 2658 * Primary VGA indication from OS. 2659 * 2660 * Possible status values returned are: 2661 * NV_OK 2662 * NV_ERR_INVALID_OPERATION 2663 * NV_ERR_NOT_SUPPORTED 2664 */ 2665 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ 2666 2667 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U) 2668 2669 typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS { 2670 NvBool bSave; 2671 NvBool bUseVbios; 2672 } NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS; 2673 2674 /*! 2675 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE 2676 * 2677 * To perform save or restore operation from/to saved fonts. 2678 * 2679 * [in] bSave 2680 * To indicate whether save or restore needs to be performed. 2681 * [in] bUseVbios 2682 * Primary VGA indication from OS. 2683 * [in] bVbiosCallSuccessful 2684 * Indicates if vbios invocation was successful or not. 2685 * 2686 * Possible status values returned are: 2687 * NV_OK 2688 * NV_ERR_NOT_SUPPORTED 2689 */ 2690 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ 2691 2692 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x77U) 2693 2694 typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS { 2695 NvBool bSave; 2696 NvBool bUseVbios; 2697 NvBool bVbiosCallSuccessful; 2698 } NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS; 2699 2700 /*! 2701 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES 2702 * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES 2703 */ 2704 2705 /*! 2706 * NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE 2707 * 2708 * This structure specifies resources in an execution partition 2709 * 2710 * computeSize[OUT] 2711 * - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile 2712 * 2713 * gfxGpcCount[OUT] 2714 * - Total Number of GFX Supporting GPCs in this partition 2715 * 2716 * gpcCount[OUT] 2717 * - Total Number of GPCs in this partition (including GFX Supported GPCs) 2718 * 2719 * veidCount[OUT] 2720 * - Number of VEIDs allocated to this profile 2721 * 2722 * smCount[OUT] 2723 * - Number of SMs usable in this profile 2724 */ 2725 typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE { 2726 NvU8 computeSize; 2727 NvU32 gfxGpcCount; 2728 NvU32 gpcCount; 2729 NvU32 veidCount; 2730 NvU32 smCount; 2731 NvU32 physicalSlots; 2732 } NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE; 2733 2734 /*! 2735 * NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS 2736 * 2737 * This structure specifies resources in an execution partition 2738 * 2739 * profileCount[OUT] 2740 * - Total Number of profiles filled 2741 * 2742 * profiles[OUT] 2743 * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles 2744 */ 2745 #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU) 2746 2747 typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS { 2748 NvU32 profileCount; 2749 NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; 2750 } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS; 2751 2752 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ 2753 2754 #define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBAU) 2755 2756 typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS; 2757 2758 2759 2760 /* 2761 * NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE 2762 * 2763 * This command sets the ccu stream to enable/disable state. 2764 * 2765 * Possible status values returned are: 2766 * NV_OK 2767 * NV_ERR_INVALID_ARGUMENT 2768 * NV_ERR_NOT_SUPPORTED 2769 */ 2770 2771 #define NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE (0x20800abd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID" */ 2772 2773 #define NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID (0xBDU) 2774 2775 typedef struct NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS { 2776 NvBool bStreamState; 2777 } NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS; 2778 2779 /*! 2780 * NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT 2781 * 2782 * Attach GPU to the external device. 2783 * 2784 * [in] bExtDevFound 2785 * To enable GPIO interrupts. 2786 * 2787 * Possible status values returned are: 2788 * NV_OK 2789 * NV_ERR_GENERIC 2790 * NV_ERR_NOT_SUPPORTED 2791 */ 2792 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT (0x20800abe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID" */ 2793 2794 #define NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID (0xBEU) 2795 2796 typedef struct NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS { 2797 NvBool bExtDevFound; 2798 } NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS; 2799 2800 /*! 2801 * NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS 2802 * 2803 * Optimize the Gsync timing parameters 2804 * 2805 * [in] timingParameters 2806 * Timing parameters passed by client. 2807 * 2808 * Possible status values returned are: 2809 * NV_OK 2810 * NV_ERR_GENERIC 2811 * NV_ERR_NOT_SUPPORTED 2812 */ 2813 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS (0x20800abf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID" */ 2814 2815 #define NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID (0xBFU) 2816 2817 typedef struct NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS { 2818 NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS timingParameters; 2819 } NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS; 2820 2821 /*! 2822 * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS 2823 * 2824 * Get displayIDs supported by the display. 2825 * 2826 * [out] displayIds 2827 * Associated display ID with head. 2828 * 2829 * Possible status values returned are: 2830 * NV_OK 2831 * NV_ERR_GENERIC 2832 * NV_ERR_NOT_SUPPORTED 2833 */ 2834 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS (0x20800ac0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID" */ 2835 2836 #define NV2080_MAX_NUM_HEADS 4 2837 2838 #define NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID (0xC0U) 2839 2840 typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS { 2841 NvU32 displayIds[NV2080_MAX_NUM_HEADS]; 2842 } NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS; 2843 2844 /*! 2845 * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC 2846 * 2847 * Set the Stereo sync for Gsync 2848 * 2849 * [in] slave 2850 * Slave GPU head status. 2851 * [in] localSlave 2852 * Slave GPU head status but are not coupled. 2853 * [in] master 2854 * Master GPU head status. 2855 * [in] regstatus 2856 * Register status of status1 register. 2857 * 2858 * Possible status values returned are: 2859 * NV_OK 2860 * NV_ERR_GENERIC 2861 * NV_ERR_NOT_SUPPORTED 2862 */ 2863 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC (0x20800ac1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID" */ 2864 2865 #define NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID (0xC1U) 2866 2867 typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS { 2868 NvU32 slave[NV2080_MAX_NUM_HEADS]; 2869 NvU32 localSlave[NV2080_MAX_NUM_HEADS]; 2870 NvU32 master[NV2080_MAX_NUM_HEADS]; 2871 NvU32 regStatus; 2872 } NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS; 2873 2874 /*! 2875 * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES 2876 * 2877 * Get vertical active lines for given head. 2878 * 2879 * [in] head 2880 * For the headIdx which we need active. 2881 * [out] vActiveLines 2882 * Vertical active lines. 2883 * 2884 * Possible status values returned are: 2885 * NV_OK 2886 * NV_ERR_GENERIC 2887 * NV_ERR_NOT_SUPPORTED 2888 */ 2889 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES (0x20800ac4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID" */ 2890 2891 #define NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID (0xC4U) 2892 2893 typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS { 2894 NvU32 headIdx; 2895 NvU32 vActiveLines; 2896 } NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS; 2897 2898 /*! 2899 * NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID 2900 * 2901 * Verifies if this displayId is valid. 2902 * 2903 * [in] displays 2904 * Displays given by the client 2905 * 2906 * [out] displayId 2907 * DisplayId for the given display 2908 * 2909 * Possible status values returned are: 2910 * NV_OK 2911 * NV_ERR_GENERIC 2912 * NV_ERR_NOT_SUPPORTED 2913 */ 2914 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID (0x20800ac9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID" */ 2915 2916 #define NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID (0xC9U) 2917 2918 typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS { 2919 NvU32 displays; 2920 NvU32 displayId; 2921 } NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS; 2922 2923 /*! 2924 * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC 2925 * 2926 * Disable the raster sync gpio on the other P2060 GPU 2927 * that's connected to master over Video bridge. 2928 * 2929 * [in] bEnableMaster 2930 * If it is master gpu. 2931 * 2932 * [out] bRasterSyncGpioSaved 2933 * If raster sync GPIO direction is saved or not. 2934 * 2935 * [in/out] bRasterSyncGpioDirection 2936 * During save it gets the direction. 2937 * In restores it sets the direction. 2938 * 2939 * Possible status values returned are: 2940 * NV_OK 2941 * NV_ERR_NOT_SUPPORTED 2942 */ 2943 #define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC (0x20800aca) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID" */ 2944 2945 #define NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID (0xCAU) 2946 2947 typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS { 2948 NvBool bEnableMaster; 2949 NvBool bRasterSyncGpioSaved; 2950 NvU32 bRasterSyncGpioDirection; 2951 } NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS; 2952 2953 /*! 2954 * NV2080_CTRL_CMD_INTERNAL_FBSR_INIT 2955 * 2956 * Initialize FBSR on GSP to prepare for suspend-resume 2957 * 2958 * [in] fbsrType 2959 * Fbsr object type 2960 * [in] numRegions 2961 * Number of regions that GSP should allocate records for 2962 * [in] hClient 2963 * Handle to client of SYSMEM memlist object 2964 * [in] hSysMem 2965 * Handle to SYSMEM memlist object 2966 * [in] gspFbAllocsSysOffset 2967 * Offset in SYSMEM for GSP's FB Allocations 2968 * [in] bEnteringGcoffState 2969 * Value of PDB_PROP_GPU_GCOFF_STATE_ENTERING 2970 * 2971 * Possible status values returned are: 2972 * NV_OK 2973 * NV_ERR_GENERIC 2974 * NV_ERR_NOT_SUPPORTED 2975 */ 2976 2977 #define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */ 2978 2979 #define NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID (0xC2U) 2980 2981 typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS { 2982 NvU32 fbsrType; 2983 NvU32 numRegions; 2984 NvHandle hClient; 2985 NvHandle hSysMem; 2986 NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8); 2987 NvBool bEnteringGcoffState; 2988 } NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS; 2989 2990 /*! 2991 * NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO 2992 * 2993 * Send info of FB region that will be saved/restored by GSP on suspend-resume 2994 * 2995 * [in] fbsrType 2996 * Fbsr object type 2997 * [in] hClient 2998 * Handle to client of FBMEM memlist object 2999 * [in] hVidMem 3000 * Handle to FBMEM memlist object 3001 * [in] vidOffset 3002 * Offset in FBMEM region to save/restore 3003 * [in] sysOffset 3004 * Offset in SYSMEM region to save to/restore from 3005 * [in] size 3006 * Size of region being saved/restored 3007 */ 3008 #define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */ 3009 3010 #define NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID (0xC3U) 3011 3012 typedef struct NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS { 3013 NvU32 fbsrType; 3014 NvHandle hClient; 3015 NvHandle hVidMem; 3016 NV_DECLARE_ALIGNED(NvU64 vidOffset, 8); 3017 NV_DECLARE_ALIGNED(NvU64 sysOffset, 8); 3018 NV_DECLARE_ALIGNED(NvU64 size, 8); 3019 } NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS; 3020 3021 /* 3022 * NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB 3023 * 3024 * This command is used to get the amount of host reserved FB 3025 * 3026 * hostReservedFb [OUT] 3027 * Amount of FB reserved for the host 3028 * vgpuTypeId [IN] 3029 * The Type ID for VGPU profile 3030 * 3031 * Possible status values returned are: 3032 * NV_OK 3033 * NV_ERR_INVALID_ARGUMENT 3034 */ 3035 #define NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB (0x20800ac5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID" */ 3036 3037 #define NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID (0xC5U) 3038 3039 typedef struct NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS { 3040 NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8); 3041 NvU32 vgpuTypeId; 3042 } NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS; 3043 3044 /*! 3045 * NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD 3046 * 3047 * This command initiates brightc module state load. 3048 * 3049 * Possible status values returned are: 3050 * NV_OK 3051 * NV_ERR_INVALID_ARGUMENT 3052 * NV_ERR_NOT_SUPPORTED 3053 */ 3054 3055 #define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */ 3056 3057 #define NV2080_CTRL_ACPI_DSM_READ_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ 3058 3059 #define NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID (0xC6U) 3060 3061 typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS { 3062 NvU32 status; 3063 NvU16 backLightDataSize; 3064 NvU8 backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE]; 3065 } NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS; 3066 3067 /* 3068 * NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL 3069 * 3070 * Returns number of active links allowed per IOCTRL 3071 * 3072 * [Out] numActiveLinksPerIoctrl 3073 */ 3074 #define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC7U) 3075 3076 typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS { 3077 NvU32 numActiveLinksPerIoctrl; 3078 } NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS; 3079 #define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL (0x20800ac7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ 3080 /* 3081 * NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL 3082 * 3083 * Returns number of links per IOCTRL 3084 * 3085 * [Out] numLinksPerIoctrl 3086 */ 3087 #define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC8U) 3088 3089 typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS { 3090 NvU32 numLinksPerIoctrl; 3091 } NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS; 3092 #define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL (0x20800ac8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ 3093 3094 /*! 3095 * NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE 3096 * 3097 * Update the system control capability 3098 * 3099 * bIsSysCtrlSupported [IN] 3100 If the system control is supported 3101 * bIsPlatformLegacy [OUT] 3102 If the platform is legacy 3103 * 3104 * Possible status values returned are: 3105 * NV_OK 3106 * NV_ERR_NOT_SUPPORTED 3107 */ 3108 3109 #define NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE (0x20800acb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID" */ 3110 3111 #define NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID (0xCBU) 3112 3113 typedef struct NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS { 3114 NvBool bIsSysCtrlSupported; 3115 NvBool bIsPlatformLegacy; 3116 } NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS; 3117 3118 /*! 3119 * Macros for PFM_REQ_HNDLR_STATE_SYNC data types. 3120 */ 3121 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR 0x00U 3122 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM 0x01U 3123 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI 0x02U 3124 3125 /*! 3126 * Structure representing static data for a PFM_REQ_HNDLR_STATE_SYNC_SMBPBI. 3127 */ 3128 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI { 3129 /*! 3130 * PFM sensor ID 3131 */ 3132 NvU32 sensorId; 3133 3134 /*! 3135 * PFM sensor limit value if required 3136 */ 3137 NvU32 limit; 3138 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI; 3139 3140 /*! 3141 * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC data types. 3142 */ 3143 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA { 3144 /*! 3145 * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_<xyz> 3146 */ 3147 NvU8 type; 3148 3149 /*! 3150 * Type-specific information. 3151 */ 3152 union { 3153 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI smbpbi; 3154 } data; 3155 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA; 3156 3157 /*! 3158 * Macros for PFM_REQ_HNDLR_STATE_SYNC flags for specific operation. 3159 */ 3160 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD 0x00U 3161 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT 0x01U 3162 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR 0x02U 3163 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET 0x03U 3164 3165 /*! 3166 * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC params. 3167 */ 3168 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS { 3169 /*! 3170 * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_<xyz> 3171 */ 3172 NvU8 flags; 3173 3174 /*! 3175 * Type-specific information. 3176 */ 3177 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA syncData; 3178 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS; 3179 3180 /*! 3181 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC 3182 * 3183 * State sync with platform req handler and SMBPBI 3184 * 3185 * flags [IN] 3186 * Flags that needs sync operation between physical and kernel 3187 * 3188 * syncData [IN] 3189 * Sync payload data 3190 * 3191 */ 3192 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID" */ 3193 3194 #define NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID (0xCCU) 3195 3196 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS; 3197 3198 /*! 3199 * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC 3200 * 3201 * State sync with platform req handler and SMBPBI 3202 * 3203 * flags [IN] 3204 * Flags that needs sync operation between physical and kernel 3205 * 3206 * syncData [IN] 3207 * Sync payload data 3208 * 3209 */ 3210 #define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID" */ 3211 3212 #define NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID (0xCDU) 3213 3214 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS; 3215 3216 /*! 3217 * NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE 3218 * 3219 * Query Coherent FB Aperture Size. 3220 * 3221 */ 3222 #define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */ 3223 3224 #define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU) 3225 3226 typedef struct NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS { 3227 // Get Coherent Fb Aperture Size 3228 NV_DECLARE_ALIGNED(NvU64 coherentFbApertureSize, 8); 3229 } NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS; 3230 3231 3232 /*! 3233 * Macros for NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE flag 3234 */ 3235 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS 0x00U 3236 #define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS 0x01U 3237 3238 /*! 3239 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE 3240 * 3241 * Queries PM1 Forced off / PM1 Available status 3242 * 3243 * flag [IN] 3244 * Fetch PM1 Forced off / PM1 Available status based on value. 3245 * bStatus [OUT] 3246 * PM1 Forced off / PM1 Available is true or false. 3247 * 3248 * Possible status values returned are: 3249 * NV_OK 3250 * NV_ERR_NOT_SUPPORTED 3251 * NV_ERR_INVALID_ARGUMETS 3252 */ 3253 3254 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE (0x20800ace) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID" */ 3255 3256 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID (0xCEU) 3257 3258 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS { 3259 /*! 3260 * Fetch PM1 Forced off / PM1 Available status based on value. 3261 */ 3262 NvU8 flag; 3263 3264 /*! 3265 * PM1 Forced off / PM1 Available status 3266 */ 3267 NvBool bStatus; 3268 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS; 3269 3270 /*! 3271 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE 3272 * 3273 * Set PM1 state to enabled / disabled (boost clocks). 3274 * 3275 * bEnable [IN] 3276 * NV_TRUE means enable PM1, NV_FALSE means disable. 3277 * 3278 * Possible status values returned are: 3279 * NV_OK 3280 * NV_ERR_NOT_SUPPORTED 3281 */ 3282 3283 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE (0x20800acf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID" */ 3284 3285 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID (0xCFU) 3286 3287 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS { 3288 3289 /*! 3290 * NV_TRUE means enable PM1, NV_FALSE means disable. 3291 */ 3292 NvBool bEnable; 3293 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS; 3294 3295 /*! 3296 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT 3297 * 3298 * Updates EDPpeak Limit of GPU 3299 * 3300 * bEnable [IN] 3301 * Enable or Reset the settings 3302 * clientLimit [IN] 3303 * Client requested limit 3304 * 3305 * Possible status values returned are: 3306 * NV_OK 3307 * NV_ERR_GENERIC 3308 * NV_ERR_NOT_SUPPORTED 3309 * NV_ERR_NOT_READY 3310 */ 3311 3312 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT (0x20800ad0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID" */ 3313 3314 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID (0xD0U) 3315 3316 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS { 3317 NvBool bEnable; 3318 NvU32 clientLimit; 3319 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS; 3320 3321 /*! 3322 * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT 3323 * 3324 * Updates Target Temperature of GPU 3325 * 3326 * targetTemp [IN] 3327 * Target Temperature Set from SBIOS 3328 * 3329 * Possible status values returned are: 3330 * NV_OK 3331 * NV_ERR_NOT_SUPPORTED 3332 */ 3333 3334 #define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT (0x20800ad1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID" */ 3335 3336 #define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID (0xD1U) 3337 3338 typedef struct NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS { 3339 NvS32 targetTemp; 3340 } NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS; 3341 3342 /*! 3343 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE 3344 * 3345 * Enable / disable CTGP MODE 3346 * 3347 * bEnable [IN] 3348 * Enable or Reset the settings 3349 * 3350 * Possible status values returned are: 3351 * NV_OK 3352 * NV_ERR_NOT_SUPPORTED 3353 */ 3354 3355 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE (0x20800ad2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID" */ 3356 3357 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID (0xD2U) 3358 3359 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS { 3360 NvBool bEnable; 3361 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS; 3362 3363 /*! 3364 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 3365 * 3366 * Configuration of the turbo v2 parameters for NVPCF-Turbo arb control 3367 * 3368 * ctgpOffsetmW [IN] 3369 * TGP MODE Offset in mW 3370 * 3371 * Possible status values returned are: 3372 * NV_OK 3373 * NV_ERR_NOT_SUPPORTED 3374 */ 3375 3376 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 (0x20800ad3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID" */ 3377 3378 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID (0xD3U) 3379 3380 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS { 3381 NvU32 ctgpOffsetmW; 3382 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS; 3383 3384 /*! 3385 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO 3386 * 3387 * Query VPstatese info. Get VPS PS2.0 support / get highest VP State Idx and requested VP State Idx 3388 * 3389 * bVpsPs20Supported [OUT] 3390 * Reflects Vpstates PS20 support 3391 * vPstateIdxHighest [OUT} 3392 * Reflects Highest VPstate Idx 3393 * 3394 * Possible status values returned are: 3395 * NV_OK 3396 * NV_ERR_NOT_SUPPORTED 3397 */ 3398 3399 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO (0x20800ad4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID" */ 3400 3401 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID (0xD4U) 3402 3403 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS { 3404 /*! 3405 * Reflects Vpstates PS20 support 3406 */ 3407 NvBool bVpsPs20Supported; 3408 3409 /*! 3410 * Get highest VPState Idx from VBIOS 3411 */ 3412 NvU32 vPstateIdxHighest; 3413 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS; 3414 3415 /*! 3416 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING 3417 * 3418 * Get vPstate mapping for requested pStateIdx 3419 * 3420 * pStateIdx [IN] 3421 * Requested PState Idx 3422 * vPstateIdx [OUT} 3423 * Mapped VPstate Idx 3424 * 3425 * Possible status values returned are: 3426 * NV_OK 3427 * NV_ERR_NOT_SUPPORTED 3428 */ 3429 3430 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING (0x20800ad5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID" */ 3431 3432 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID (0xD5U) 3433 3434 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS { 3435 /*! 3436 * Requested PState Idx 3437 */ 3438 NvU32 pStateIdx; 3439 3440 /*! 3441 * Mapped VPstate Idx 3442 */ 3443 NvU32 vPstateIdxMapping; 3444 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS; 3445 3446 /*! 3447 * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE 3448 * 3449 * Set requested VPstate 3450 * 3451 * vPstateIdx [IN] 3452 * VPstate Idx to be set 3453 * 3454 * Possible status values returned are: 3455 * NV_OK 3456 * NV_ERR_NOT_SUPPORTED 3457 */ 3458 3459 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE (0x20800ad6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID" */ 3460 3461 #define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID (0xD6U) 3462 3463 typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS { 3464 3465 /*! 3466 * NV_TRUE means enable PM1, NV_FALSE means disable. 3467 */ 3468 NvU32 vPstateIdx; 3469 } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS; 3470 3471 /* 3472 * NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE 3473 * 3474 * This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3 3475 * 3476 * Possible status return values are: 3477 * NV_OK Success 3478 */ 3479 #define NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */ 3480 3481 #define NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U) 3482 3483 typedef struct NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS { 3484 NvBool bIsGC6Satisfied; 3485 NvBool bIsGCOFFSatisfied; 3486 } NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS; 3487 3488 /* 3489 * This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly. 3490 */ 3491 #define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */ 3492 3493 /*! 3494 * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS 3495 * 3496 * This command is an internal command sent from Kernel RM to Physical RM 3497 * to get number of secure channels supported on SEC2 and CE 3498 * 3499 * maxSec2SecureChannels [OUT] 3500 * maxCeSecureChannels [OUT] 3501 */ 3502 #define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS (0x20800ad8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID" */ 3503 3504 #define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xD8U) 3505 3506 typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS { 3507 NvU32 maxSec2SecureChannels; 3508 NvU32 maxCeSecureChannels; 3509 } NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS; 3510 3511 /* 3512 * NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS 3513 * 3514 * This command is an internal command sent from Kernel RM to Physical RM 3515 * to disable the GPU system memory access after quiescing the GPU or 3516 * re-enable sysmem access. 3517 * 3518 * bDisable [IN] 3519 * If NV_TRUE the GPU is quiesced and system memory access is disabled . 3520 * If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed. 3521 * 3522 * Possible status values returned are: 3523 * NV_OK 3524 * NV_ERR_INVALID_PARAM_STRUCT 3525 * NV_ERR_INVALID_ARGUMENT 3526 * NV_ERR_NOT_SUPPORTED 3527 */ 3528 #define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */ 3529 3530 #define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU) 3531 3532 typedef struct NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS { 3533 NvBool bDisable; 3534 } NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS; 3535 3536 #define NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS (0x20800adc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID" */ 3537 3538 #define NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID (0xDCU) 3539 3540 typedef struct NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS { 3541 NvU32 pinSetIn; // in 3542 NvU32 pinSetOut; // in 3543 NvBool bMasterScanLock; // out 3544 NvU32 masterScanLockPin; // out 3545 NvBool bSlaveScanLock; // out 3546 NvU32 slaveScanLockPin; // out 3547 } NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS; 3548 3549 #define NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE (0x20800add) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xDD" */ 3550 3551 #define NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL (0x20800ade) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID" */ 3552 3553 #define NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID (0xDEU) 3554 3555 typedef struct NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS { 3556 NvU32 pinSet; // in 3557 NvU32 gpioFunction; // out 3558 NvU32 gpioPin; // out 3559 NvBool gpioDirection; // out 3560 } NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS; 3561 3562 /* NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA 3563 * 3564 * This command sets up ACPI DDC Edid data. 3565 * 3566 * Possible status values returned are: 3567 * NV_OK 3568 * NV_ERR_INVALID_ARGUMENT 3569 * NV_ERR_NOT_SUPPORTED 3570 */ 3571 #define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA (0x20800adf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID" */ 3572 3573 /* From ACPI6.5 spec., the max size of EDID data from SBIOS(_DDC) is 512B */ 3574 #define MAX_EDID_SIZE_FROM_SBIOS 512U 3575 3576 typedef struct NV2080_CTRL_INTERNAL_EDID_DATA { 3577 NvU32 status; 3578 NvU32 acpiId; 3579 NvU32 bufferSize; 3580 NvU8 edidBuffer[MAX_EDID_SIZE_FROM_SBIOS]; 3581 } NV2080_CTRL_INTERNAL_EDID_DATA; 3582 3583 #define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID (0xDFU) 3584 3585 typedef struct NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS { 3586 NvU32 tableLen; 3587 NV2080_CTRL_INTERNAL_EDID_DATA edidTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; 3588 } NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS; 3589 3590 /*! 3591 * NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED 3592 * 3593 * This command intializes display ACPI child devices. 3594 * This command accepts no parameters. 3595 * 3596 */ 3597 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED (0x20800af0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF0" */ 3598 3599 /* NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET */ 3600 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET (0x20800af1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF1" */ 3601 3602 /* NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET */ 3603 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET (0x20800af2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF2" */ 3604 3605 /*! 3606 * NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS 3607 * 3608 * This structure provides the params for getting GPU Fabric Probe Internal 3609 * Info from GSP to CPU RM 3610 * 3611 * numProbes[OUT] 3612 * - Number of probe requests sent 3613 */ 3614 #define NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF4U) 3615 3616 typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS { 3617 NV_DECLARE_ALIGNED(NvU64 numProbes, 8); 3618 } NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS; 3619 3620 /*! 3621 * NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO 3622 * 3623 * This command is used to get NV2080_CTRL_CMD_INTERNAL_GPU_FABRIC_PROBE_INFO_PARAMS 3624 * from GSP to CPU RM. 3625 * This command accepts NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS 3626 * 3627 */ 3628 #define NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO (0x208001f4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ 3629 3630 /*! 3631 * NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS 3632 * 3633 * This structure provides the params for starting GPU Fabric Probe 3634 * 3635 * bwMode[IN] 3636 * - Nvlink Bandwidth mode 3637 * 3638 * bLocalEgmEnabled[IN] 3639 * - EGM Enablement Status that needs to be set in GSP-RM 3640 */ 3641 #define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U) 3642 3643 typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS { 3644 NvU8 bwMode; 3645 NvBool bLocalEgmEnabled; 3646 } NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS; 3647 3648 /*! 3649 * NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE 3650 * 3651 * This command is used to trigger start of GPU FABRIC PROBE PROCESS on GSP. 3652 * This command accepts NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS 3653 * 3654 */ 3655 #define NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE (0x208001f5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ 3656 3657 /*! 3658 * NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE 3659 * 3660 * This command is used to trigger stop of GPU FABRIC PROBE PROCESS on GSP. 3661 * This command accepts no parameters 3662 * 3663 */ 3664 #define NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE (0x208001f6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF6" */ 3665 3666 /*! 3667 * NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE 3668 * 3669 * This command is used to trigger suspend of GPU FABRIC PROBE PROCESS on GSP. 3670 * This command accepts no parameters 3671 * 3672 */ 3673 #define NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE (0x208001f7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF7" */ 3674 3675 3676 /*! 3677 * NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS 3678 * 3679 * This structure provides the params for resuming GPU Fabric Probe 3680 * 3681 * bwMode[IN] 3682 * - Nvlink Bandwidth mode 3683 */ 3684 #define NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF8U) 3685 3686 typedef struct NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS { 3687 NvU8 bwMode; 3688 } NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS; 3689 3690 /*! 3691 * NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE 3692 * 3693 * This command is used to trigger resume of GPU FABRIC PROBE PROCESS on GSP. 3694 * This command accepts NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS 3695 * 3696 */ 3697 #define NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE (0x208001f8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ 3698 3699 /*! 3700 * NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE 3701 * 3702 * This command is used to invalidate/reset GPU_FABRIC_PROBE_INFO on GSP. 3703 * This command accepts no parameters 3704 * 3705 */ 3706 #define NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE (0x208001f9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF9" */ 3707 3708 /*! 3709 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO 3710 * 3711 * This command is an internal command sent from Kernel RM to Physical RM 3712 * to get static conf compute info 3713 * 3714 * bIsBar1Trusted: [OUT] 3715 * Is BAR1 trusted to access CPR 3716 * bIsPcieTrusted: [OUT] 3717 * Is PCIE trusted to access CPR 3718 */ 3719 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO (0x20800af3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 3720 3721 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xF3U) 3722 3723 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS { 3724 NvBool bIsBar1Trusted; 3725 NvBool bIsPcieTrusted; 3726 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS; 3727 3728 /*! 3729 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS 3730 * 3731 * This command is an internal command sent from Kernel RM to Physical RM 3732 * to derive SWL keys and IV masks for a given engine 3733 * 3734 * engineId: [IN] 3735 * NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived 3736 * ivMaskSet: [OUT] 3737 * Set of IV masks for given engine 3738 */ 3739 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS (0x20800ae1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID" */ 3740 3741 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE 3U 3742 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL 0U 3743 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER 1U 3744 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER 2U 3745 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 3U 3746 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT 6U 3747 3748 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK { 3749 NvU32 ivMask[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE]; 3750 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK; 3751 3752 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID (0xE1U) 3753 3754 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS { 3755 NvU32 engineId; 3756 NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT]; 3757 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS; 3758 3759 /*! 3760 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS 3761 * 3762 * This command is an internal command sent from Kernel RM to Physical RM 3763 * to derive LCE keys and IV masks for a given engine 3764 * 3765 * engineId: [IN] 3766 * NV2080_ENGINE_TYPE_* for engine for which keys and IV mask should be derived 3767 * ivMaskSet: [OUT] 3768 * Set of IV masks for given engine 3769 */ 3770 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS (0x20800ae2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID" */ 3771 3772 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID (0xE2U) 3773 3774 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS { 3775 NvU32 engineId; 3776 NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT]; 3777 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS; 3778 3779 /*! 3780 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS 3781 * 3782 * This command handles key rotation for a given H2D key (and corresponding D2H key) 3783 * by deriving new key on GSP and updating the key on relevant SEC2 or LCE. 3784 * It also updates IVs for all channels using the key and conditionally re-enables them 3785 * and notifies clients of key rotation status at the end. 3786 * 3787 * globalH2DKey : [IN] 3788 * global h2d key to be rotated 3789 * updatedEncryptIVMask: [OUT] 3790 * Encrypt IV mask post IV key rotation for a given engine's kernel channel 3791 * updatedDecryptIVMask: [OUT] 3792 * Decrypt IV mask post IV key rotation for a given engine's kernel channel 3793 */ 3794 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS (0x20800ae5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID" */ 3795 3796 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID (0xE5U) 3797 3798 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS { 3799 NvU32 globalH2DKey; 3800 NvU32 updatedEncryptIVMask[CC_AES_256_GCM_IV_SIZE_DWORD]; 3801 NvU32 updatedDecryptIVMask[CC_AES_256_GCM_IV_SIZE_DWORD]; 3802 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS; 3803 3804 /*! 3805 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION 3806 * 3807 * This command RCs all channels that use the given key and have not reported 3808 * idle via NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION yet. 3809 * RM needs to RC such channels before going ahead with key rotation. 3810 * 3811 * globalH2DKey : [IN] 3812 * global h2d key whose channels will be RCed 3813 */ 3814 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION (0x20800ae6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID" */ 3815 3816 #define NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID (0xE6U) 3817 3818 typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS { 3819 NvU32 exceptionType; 3820 NvU32 globalH2DKey; 3821 } NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS; 3822 3823 /*! 3824 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE 3825 * 3826 * This control call can be used to set gpu state on GSP to accept client requests 3827 * or to block client requests. 3828 * This is a internal command sent from Kernel RM to Physical RM. 3829 * 3830 * bAcceptClientRequest:[IN] 3831 * NV_TRUE : set gpu state to accept client work requests 3832 * NV_FALSE: set gpu state to block client work requests 3833 * 3834 */ 3835 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE (0x20800ae7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID" */ 3836 3837 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID (0xE7U) 3838 3839 typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS { 3840 NvBool bAcceptClientRequest; 3841 } NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS; 3842 3843 /*! 3844 * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY 3845 * 3846 * This control call can be used to set CC security policy on GSP. 3847 * This is a internal command sent from Kernel RM to Physical RM. 3848 * 3849 * attackerAdvantage [IN] 3850 * The minimum and maximum values for attackerAdvantage. 3851 * The probability of an attacker successfully guessing the contents of 3852 * an encrypted packet go up ("attacker advantage"). 3853 * 3854 * Possible status values returned are: 3855 * NV_OK 3856 * NV_ERR_INVALID_OBJECT_HANDLE 3857 * NV_ERR_INVALID_STATE 3858 * NV_ERR_INVALID_ARGUMENT 3859 * NV_ERR_NOT_SUPPORTED 3860 */ 3861 3862 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY (0x20800ae8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID" */ 3863 3864 #define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID (0xE8U) 3865 3866 typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS { 3867 NV_DECLARE_ALIGNED(NvU64 attackerAdvantage, 8); 3868 } NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS; 3869 3870 3871 3872 /* 3873 * NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP 3874 * 3875 * This command is used by CPU-RM to perform memory operations using GSP 3876 * 3877 * 3878 * Possible status values returned are: 3879 * NV_OK 3880 * NVOS_STATUS_TIMEOUT_RETRY 3881 * NV_ERR_NOT_SUPPORTED 3882 */ 3883 3884 #define NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP (0x20800afa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID" */ 3885 3886 typedef enum NV2080_CTRL_MEMMGR_MEMORY_OP { 3887 NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY = 0, 3888 NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET = 1, 3889 } NV2080_CTRL_MEMMGR_MEMORY_OP; 3890 3891 typedef struct NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO { 3892 /*! 3893 * Base physical address of the surface 3894 */ 3895 NV_DECLARE_ALIGNED(NvU64 baseAddr, 8); 3896 3897 /*! 3898 * Size of the surface in bytes 3899 */ 3900 NV_DECLARE_ALIGNED(NvU64 size, 8); 3901 3902 /*! 3903 * Offset in bytes into the surface where read/write must happen 3904 */ 3905 NV_DECLARE_ALIGNED(NvU64 offset, 8); 3906 3907 /*! 3908 * Aperture where the surface is allocated 3909 */ 3910 NvU32 aperture; 3911 3912 /*! 3913 * CPU caching attribute of the surface 3914 */ 3915 NvU32 cpuCacheAttrib; 3916 } NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO; 3917 3918 #define CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES (0x10U) /* finn: Evaluated from "(128 / 8)" */ 3919 3920 #define NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID (0xFAU) 3921 3922 typedef struct NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS { 3923 3924 /*! 3925 * Source surface info 3926 */ 3927 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO src, 8); 3928 3929 /*! 3930 * Authentication tag if data is encrypted 3931 */ 3932 NvU8 authTag[CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES]; 3933 3934 /*! 3935 * Destination surface info 3936 */ 3937 NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO dst, 8); 3938 3939 /*! 3940 * Size of the data to be transferred 3941 */ 3942 NV_DECLARE_ALIGNED(NvU64 transferSize, 8); 3943 3944 /*! 3945 * To be set in case of memset 3946 */ 3947 NvU32 value; 3948 3949 /*! 3950 * Memory op to be performed 3951 */ 3952 NV2080_CTRL_MEMMGR_MEMORY_OP memop; 3953 } NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS; 3954 3955 /*! 3956 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG 3957 * 3958 * This command is an internal command sent from Kernel RM to Physical RM 3959 * to get local GPU's ATS config 3960 * 3961 * addrSysPhys : [OUT] 3962 * System Physical Address 3963 * addrWidth : [OUT] 3964 * Address width value 3965 * mask : [OUT] 3966 * Mask value 3967 * maskWidth : [OUT] 3968 * Mask width value 3969 */ 3970 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG (0x20800afb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID" */ 3971 3972 #define NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFBU) 3973 3974 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS { 3975 NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8); 3976 NvU32 addrWidth; 3977 NvU32 mask; 3978 NvU32 maskWidth; 3979 } NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS; 3980 3981 /*! 3982 * NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG 3983 * 3984 * This command is an internal command sent from Kernel RM to Physical RM 3985 * to set peer ATS config using the parameters passed in. 3986 * 3987 * peerId : [IN] 3988 * Peer Id of the peer for which ATS config is to be programmed 3989 * addrSysPhys : [IN] 3990 * System Physical Address 3991 * addrWidth : [IN] 3992 * Address width value 3993 * mask : [IN] 3994 * Mask value 3995 * maskWidth : [IN] 3996 * Mask width value 3997 */ 3998 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG (0x20800afc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID" */ 3999 4000 #define NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFCU) 4001 4002 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS { 4003 NvU32 peerId; 4004 NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8); 4005 NvU32 addrWidth; 4006 NvU32 mask; 4007 NvU32 maskWidth; 4008 } NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS; 4009 4010 /*! 4011 * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO 4012 * 4013 * Get GPU EDPpeak Limit information 4014 * 4015 * limitMin [OUT] 4016 * Minimum allowed limit value on EDPp policy on both AC and DC 4017 * limitRated [OUT] 4018 * Rated/default allowed limit value on EDPp policy on AC 4019 * limitMax [OUT] 4020 * Maximum allowed limit value on EDPp policy on AC 4021 * limitCurr [OUT] 4022 * Current resultant limit effective on EDPp policy on AC and DC 4023 * limitBattRated [OUT] 4024 * Default/rated allowed limit on EDPp policy on DC 4025 * limitBattMax [OUT] 4026 * Maximum allowed limit on EDPp policy on DC 4027 * 4028 * Possible status values returned are: 4029 * NV_OK 4030 * NV_ERR_GENERIC 4031 */ 4032 4033 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO (0x20800afd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID" */ 4034 4035 #define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID (0xFDU) 4036 4037 typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS { 4038 NvU32 limitMin; 4039 NvU32 limitRated; 4040 NvU32 limitMax; 4041 NvU32 limitCurr; 4042 NvU32 limitBattRated; 4043 NvU32 limitBattMax; 4044 } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS; 4045 4046 /* 4047 * NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA 4048 * 4049 * @brief Initialize RM User Shared Data memory mapping on physical RM 4050 * 4051 * @param[in] physAddr Physical address of memdesc to link physical to kernel 4052 * 0 to de-initialize 4053 * 4054 * @return NV_OK on success 4055 * @return NV_ERR_ otherwise 4056 */ 4057 #define NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID (0xFEU) 4058 4059 typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS { 4060 NV_DECLARE_ALIGNED(NvU64 physAddr, 8); 4061 } NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS; 4062 #define NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA (0x20800afe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID" */ 4063 4064 /* 4065 * NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL 4066 * 4067 * @brief Set mask of data to be polled on physical for RUSD 4068 * 4069 * @param[in] polledDataMask Bitmask of data requested, defined in cl00de 4070 * 4071 * @return NV_OK on success 4072 * @return NV_ERR_ otherwise 4073 */ 4074 #define NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID (0xFFU) 4075 4076 typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS { 4077 NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8); 4078 } NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS; 4079 #define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */ 4080 4081 /*! 4082 * NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS 4083 * 4084 * This structure provides the params for starting GPU Fabric Probe 4085 * 4086 * tracepointMask[IN] 4087 * - tracepoint selection filter 4088 * bufferSize[IN] 4089 * - size of gsp side logging buffer 4090 * bufferWatermark[IN] 4091 * - entry threshold for GSP to issue RPC of logged entries to kernel RM 4092 * bStart[IN] 4093 * - if true, start tracing. if false, stop tracing. 4094 */ 4095 #define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID (0xE3U) 4096 4097 typedef struct NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS { 4098 NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8); 4099 NvU32 bufferSize; 4100 NvU32 bufferWatermark; 4101 NvBool bStart; 4102 } NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS; 4103 4104 /* 4105 * NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE 4106 * 4107 * This command is used to start GSP-RM trace tool. 4108 * This command accepts NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS 4109 * 4110 */ 4111 #define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE (0x208001e3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID" */ 4112 4113 /* 4114 * NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES 4115 * 4116 * @brief get state (enabled/disabled) of SEC2 classes 4117 * 4118 * 4119 * @return NV_OK on success 4120 * @return NV_ERR_ otherwise 4121 */ 4122 #define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID (0xAFU) 4123 4124 typedef struct NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS { 4125 NvBool bMaxwellSec2Enabled; 4126 NvBool bNv95A1TsecEnabled; 4127 NvBool bHopperSec2WorkLaunchAEnabled; 4128 } NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS; 4129 #define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES (0x20800aaf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID" */ 4130 4131 4132 /*! 4133 * @ref NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND 4134 */ 4135 #define NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND (0x20800ae4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID" */ 4136 4137 #define NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID (0xE4U) 4138 4139 typedef NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS; 4140 4141 /* ctrl2080internal_h */ 4142