1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 #pragma once 24 25 #include <nvtypes.h> 26 27 // 28 // This file was generated with FINN, an NVIDIA coding tool. 29 // Source file: ctrl/ctrl2080/ctrl2080gpu.finn 30 // 31 32 #include "ctrl/ctrl2080/ctrl2080base.h" 33 #include "ctrl/ctrl2080/ctrl2080gr.h" 34 #include "ctrl/ctrl0000/ctrl0000system.h" 35 #include "nvcfg_sdk.h" 36 #include "nvstatus.h" 37 38 #define NV_GRID_LICENSE_INFO_MAX_LENGTH (128) 39 40 /* License info strings for vGPU products */ 41 #define NV_GRID_LICENSE_FEATURE_VPC_EDITION "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" 42 #define NV_GRID_LICENSE_FEATURE_VAPPS_EDITION "GRID-Virtual-Apps,3.0" 43 #define NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" 44 #define NV_GRID_LICENSE_FEATURE_GAMING_EDITION "GRID-vGaming,8.0" 45 #define NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION "NVIDIA-vComputeServer,9.0;Quadro-Virtual-DWS,5.0" 46 47 #define NV_GRID_LICENSED_PRODUCT_VWS "NVIDIA RTX Virtual Workstation" 48 #define NV_GRID_LICENSED_PRODUCT_GAMING "NVIDIA Cloud Gaming" 49 #define NV_GRID_LICENSED_PRODUCT_VPC "NVIDIA Virtual PC" 50 #define NV_GRID_LICENSED_PRODUCT_VAPPS "NVIDIA Virtual Applications" 51 #define NV_GRID_LICENSED_PRODUCT_COMPUTE "NVIDIA Virtual Compute Server" 52 53 54 55 /* NV20_SUBDEVICE_XX gpu control commands and parameters */ 56 57 58 59 typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO; 60 61 /* valid gpu info index values */ 62 63 #define NV2080_CTRL_GPU_INFO_INDEX_INDEX 23:0 64 65 66 67 #define NV2080_CTRL_GPU_INFO_INDEX_ECID_LO32 (0x00000001U) 68 #define NV2080_CTRL_GPU_INFO_INDEX_ECID_HI32 (0x00000002U) 69 #define NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT (0x00000004U) 70 71 72 #define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0 (0x00000012U) 73 #define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1 (0x00000013U) 74 75 76 #define NV2080_CTRL_GPU_INFO_INDEX_ECID_EXTENDED (0x0000001bU) 77 #define NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS (0x0000001fU) 78 79 80 #define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD (0x00000022U) 81 82 83 #define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE (0x00000025U) 84 #define NV2080_CTRL_GPU_INFO_INDEX_IBMNPU_RELAXED_ORDERING (0x00000026U) 85 #define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED (0x00000027U) 86 #define NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED (0x00000028U) 87 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT (0x00000029U) 88 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE (0x0000002aU) 89 #define NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM (0x0000002bU) 90 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION (0x0000002cU) 91 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY (0x0000002dU) 92 93 94 #define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM (0x0000002fU) 95 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY (0x00000030U) 96 #define NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE (0x00000031U) 97 98 99 #define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED (0x00000033U) 100 #define NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED (0x00000034U) 101 #define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED (0x00000035U) 102 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY (0x00000036U) 103 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY (0x00000037U) 104 105 106 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY (0x0000003aU) 107 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY (0x0000003bU) 108 #define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003cU) 109 #define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003dU) 110 111 112 #define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED (0x0000003fU) 113 114 115 116 #define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000041U) 117 118 #define NV2080_CTRL_GPU_INFO_INDEX_GROUP_ID 30:24 119 120 121 #define NV2080_CTRL_GPU_INFO_INDEX_RESERVED 31:31 122 123 /* valid minor revision extended values */ 124 #define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U) 125 #define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P (0x00000001U) 126 #define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V (0x00000002U) 127 #define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV (0x00000003U) 128 129 130 131 /* valid system memory access capability values */ 132 #define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO (0x00000000U) 133 #define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES (0x00000001U) 134 135 136 137 /* valid gemini board values */ 138 #define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO (0x00000000U) 139 #define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES (0x00000001U) 140 141 /* valid surprise removal values */ 142 #define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO (0x00000000U) 143 #define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES (0x00000001U) 144 145 /* valid relaxed ordering values */ 146 #define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_DISABLED (0x00000000U) 147 #define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_ENABLED (0x00000001U) 148 #define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_UNSUPPORTED (0xFFFFFFFFU) 149 150 /* valid poison fuse capability values */ 151 #define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO (0x00000000U) 152 #define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES (0x00000001U) 153 154 /* valid nvswitch proxy detected values */ 155 #define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO (0x00000000U) 156 #define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES (0x00000001U) 157 158 /* valid NVSR GPU support info values */ 159 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO (0x00000000U) 160 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES (0x00000001U) 161 162 /* valid SMC mode values */ 163 #define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED (0x00000000U) 164 #define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED (0x00000001U) 165 #define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED (0x00000002U) 166 #define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING (0x00000003U) 167 #define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING (0x00000004U) 168 169 /* valid split VAS mode values */ 170 #define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO (0x00000000U) 171 #define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES (0x00000001U) 172 173 /* valid grid capability values */ 174 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO (0x00000000U) 175 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES (0x00000001U) 176 177 /* valid per runlist channel ram capability values */ 178 #define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED (0x00000000U) 179 #define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED (0x00000001U) 180 181 /* valid ATS capability values */ 182 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO (0x00000000U) 183 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES (0x00000001U) 184 185 /* valid Nvenc Session Stats reporting state values */ 186 #define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED (0x00000000U) 187 #define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED (0x00000001U) 188 #define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED (0x00000002U) 189 190 /* valid 4K PAGE isolation requirement values */ 191 #define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_NO (0x00000000U) 192 #define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES (0x00000001U) 193 194 /* valid display enabled values */ 195 #define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO (0x00000000U) 196 #define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES (0x00000001U) 197 198 /* valid mobile config enabled values */ 199 #define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO (0x00000000U) 200 #define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES (0x00000001U) 201 202 203 /* valid profiling capability values */ 204 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED (0x00000000U) 205 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED (0x00000001U) 206 207 /* valid debugging capability values */ 208 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED (0x00000000U) 209 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED (0x00000001U) 210 211 212 213 /* valid local EGM supported values */ 214 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO (0x00000000U) 215 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES (0x00000001U) 216 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_PEERID 31:1 217 218 /* valid self hosted values */ 219 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO (0x00000000U) 220 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES (0x00000001U) 221 222 /* valid CMP (Crypto Mining Processor) SKU values */ 223 #define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO (0x00000000U) 224 #define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES (0x00000001U) 225 226 227 /* valid dma-buf suport values */ 228 #define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO (0x00000000U) 229 #define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES (0x00000001U) 230 231 /* valid resetless MIG device supported values */ 232 #define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO (0x00000000U) 233 #define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES (0x00000001U) 234 235 /* 236 * NV2080_CTRL_CMD_GPU_GET_INFO 237 * 238 * This command returns gpu information for the associated GPU. Requests 239 * to retrieve gpu information use a list of one or more NV2080_CTRL_GPU_INFO 240 * structures. 241 * 242 * gpuInfoListSize 243 * This field specifies the number of entries on the caller's 244 * gpuInfoList. 245 * gpuInfoList 246 * This field specifies a pointer in the caller's address space 247 * to the buffer into which the gpu information is to be returned. 248 * This buffer must be at least as big as gpuInfoListSize multiplied 249 * by the size of the NV2080_CTRL_GPU_INFO structure. 250 * 251 * Possible status values returned are: 252 * NV_OK 253 * NV_ERR_INVALID_PARAM_STRUCT 254 * NV_ERR_INVALID_ARGUMENT 255 * NV_ERR_NOT_SUPPORTED 256 * NV_ERR_OPERATING_SYSTEM 257 */ 258 #define NV2080_CTRL_CMD_GPU_GET_INFO (0x20800101U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID" */ 259 260 #define NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID (0x1U) 261 262 typedef struct NV2080_CTRL_GPU_GET_INFO_PARAMS { 263 NvU32 gpuInfoListSize; 264 NV_DECLARE_ALIGNED(NvP64 gpuInfoList, 8); 265 } NV2080_CTRL_GPU_GET_INFO_PARAMS; 266 267 #define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID" */ 268 269 #define NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID (0x2U) 270 271 typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS { 272 NvU32 gpuInfoListSize; 273 NV2080_CTRL_GPU_INFO gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE]; 274 } NV2080_CTRL_GPU_GET_INFO_V2_PARAMS; 275 276 /* 277 * NV2080_CTRL_CMD_GPU_GET_NAME_STRING 278 * 279 * This command returns the name of the GPU in string form in either ASCII 280 * or UNICODE format. 281 * 282 * gpuNameStringFlags 283 * This field specifies flags to use while creating the GPU name string. 284 * Valid flags values: 285 * NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII 286 * The returned name string should be in standard ASCII format. 287 * NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE 288 * The returned name string should be in unicode format. 289 * gpuNameString 290 * This field contains the buffer into which the name string should be 291 * returned. The length of the returned string will be no more than 292 * NV2080_CTRL_GPU_MAX_NAME_STRING_LENGTH bytes in size. 293 * 294 * Possible status values returned are: 295 * NV_OK 296 * NV_ERR_INVALID_PARAM_STRUCT 297 * NV_ERR_INVALID_ARGUMENT 298 * NV_ERR_OPERATING_SYSTEM 299 */ 300 #define NV2080_CTRL_CMD_GPU_GET_NAME_STRING (0x20800110U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID" */ 301 302 #define NV2080_GPU_MAX_NAME_STRING_LENGTH (0x0000040U) 303 304 // This field is deprecated - 'gpuNameStringFlags' is now a simple scalar. 305 // Field maintained (and extended from 0:0) for compile-time compatibility. 306 #define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE 31:0 307 308 /* valid gpu name string flags */ 309 #define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII (0x00000000U) 310 #define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE (0x00000001U) 311 312 #define NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID (0x10U) 313 314 typedef struct NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS { 315 NvU32 gpuNameStringFlags; 316 union { 317 NvU8 ascii[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 318 NvU16 unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 319 } gpuNameString; 320 } NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS; 321 322 /* 323 * NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING 324 * 325 * This command returns the short name of the GPU in ASCII string form. 326 * 327 * gpuShortNameString 328 * This field contains the buffer into which the short name string should 329 * be returned. The length of the returned string will be no more than 330 * NV2080_MAX_NAME_STRING_LENGTH bytes in size. 331 * 332 * Possible status values returned are: 333 * NV_OK 334 * NV_ERR_INVALID_PARAM_STRUCT 335 * NV_ERR_INVALID_ARGUMENT 336 * NV_ERR_OPERATING_SYSTEM 337 */ 338 #define NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING (0x20800111U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID" */ 339 340 #define NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID (0x11U) 341 342 typedef struct NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS { 343 NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 344 } NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS; 345 346 /* 347 * NV2080_CTRL_CMD_GPU_SET_POWER 348 * 349 * This command sets the power state for the GPU as a whole, various engines, 350 * or clocks. 351 * 352 * target 353 * One of NV2080_CTRL_GPU_SET_POWER_TARGET_* 354 * 355 * newLevel 356 * One of NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_* 357 * NV2080_CTRL_GPU_SET_POWER_STATE_ENGINE_LEVEL_* 358 * NV2080_CTRL_GPU_SET_POWER_STATE_CLOCK_LEVEL_* 359 * depending on the target above. 360 * 361 * oldLevel 362 * Previous level as appropriate. 363 * 364 * Possible status values returned are: 365 * NV_OK 366 * NV_ERR_INVALID_ARGUMENT 367 */ 368 #define NV2080_CTRL_CMD_GPU_SET_POWER (0x20800112U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID" */ 369 370 #define NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID (0x12U) 371 372 typedef struct NV2080_CTRL_GPU_SET_POWER_PARAMS { 373 NvU32 target; 374 NvU32 newLevel; 375 NvU32 oldLevel; 376 } NV2080_CTRL_GPU_SET_POWER_PARAMS; 377 378 379 380 #define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0 (0x00000000U) 381 #define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1 (0x00000001U) 382 #define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2 (0x00000002U) 383 #define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 (0x00000003U) 384 #define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4 (0x00000004U) 385 #define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7 (0x00000007U) 386 387 /* 388 * NV2080_CTRL_CMD_GPU_GET_SDM 389 * 390 * This command returns the subdevice mask value for the associated subdevice. 391 * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction 392 * provided by the NV36_CHANNEL_DMA and newer channel dma classes. 393 * 394 * subdeviceMask [out] 395 * This field return the subdevice mask value. 396 * 397 * Possible status values returned are: 398 * NV_OK 399 * NV_ERR_INVALID_PARAM_STRUCT 400 */ 401 #define NV2080_CTRL_CMD_GPU_GET_SDM (0x20800118U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID" */ 402 403 #define NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID (0x18U) 404 405 typedef struct NV2080_CTRL_GPU_GET_SDM_PARAMS { 406 NvU32 subdeviceMask; 407 } NV2080_CTRL_GPU_GET_SDM_PARAMS; 408 409 /* 410 * NV2080_CTRL_CMD_GPU_SET_SDM 411 * 412 * This command sets the subdevice instance and mask value for the associated subdevice. 413 * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction 414 * provided by the NV36_CHANNEL_DMA and newer channel dma classes. 415 * It must be called before the GPU HW is initialized otherwise 416 * NV_ERR_INVALID_STATE is being returned. 417 * 418 * subdeviceMask [in] 419 * This field configures the subdevice mask value for the GPU/Subdevice 420 * 421 * Possible status values returned are: 422 * NV_OK 423 * NV_ERR_INVALID_STATE 424 * NV_ERR_INVALID_DATA 425 * NV_ERR_INVALID_PARAM_STRUCT 426 */ 427 #define NV2080_CTRL_CMD_GPU_SET_SDM (0x20800120U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID" */ 428 429 #define NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID (0x20U) 430 431 typedef struct NV2080_CTRL_GPU_SET_SDM_PARAMS { 432 NvU32 subdeviceMask; 433 } NV2080_CTRL_GPU_SET_SDM_PARAMS; 434 435 /* 436 * NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO 437 * 438 * This command returns the associated subdevices' simulation information. 439 * 440 * type 441 * This field returns the simulation type. 442 * One of NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_* 443 * 444 * Possible status values returned are: 445 * NV_OK 446 * NV_ERR_NOT_SUPPORTED 447 */ 448 #define NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO (0x20800119U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID" */ 449 450 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID (0x19U) 451 452 typedef struct NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS { 453 NvU32 type; 454 } NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS; 455 456 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE (0x00000000U) 457 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL (0x00000001U) 458 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL (0x00000002U) 459 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL (0x00000003U) 460 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL (0x00000004U) 461 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU (0x00000005U) 462 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER (0x00000006U) 463 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA (0x00000007U) 464 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL (0x00000008U) 465 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL (0x00000009U) 466 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN (0xFFFFFFFFU) 467 468 /* 469 * NV2080_CTRL_GPU_REG_OP 470 * 471 * This structure describes register operation information for use with 472 * the NV2080_CTRL_CMD_GPU_EXEC_REG_OPS command. The structure describes 473 * a single register operation. The operation can be a read or write and 474 * can involve either 32bits or 64bits of data. 475 * 476 * For 32bit read operations, the operation takes the following form: 477 * 478 * regValueLo = read(bar0 + regOffset) 479 * regValueHi = 0 480 * 481 * For 64bit read operations, the operation takes the following form: 482 * 483 * regValueLo = read(bar0 + regOffset) 484 * regValueHi = read(bar0 + regOffset + 4) 485 * 486 * For 32bit write operations, the operation takes the following form: 487 * 488 * new = ((read(bar0 + regOffset) & ~regAndNMaskLo) | regValueLo) 489 * write(bar0 + regOffset, new) 490 * 491 * For 64bit write operations, the operation takes the following form: 492 * 493 * new_lo = ((read(bar0 + regOffset) & ~regAndNMaskLo) | regValueLo) 494 * new_hi = ((read(bar0 + regOffset + 4) & ~regAndNMaskHi) | regValueHi) 495 * write(bar0 + regOffset, new_lo) 496 * write(bar0 + regOffset + 4, new_hi) 497 * 498 * Details on the parameters follow: 499 * 500 * regOp 501 * This field specifies the operation to be applied to the register 502 * specified by the regOffset parameter. Valid values for this 503 * parameter are: 504 * NV2080_CTRL_GPU_REG_OP_READ_08 505 * The register operation should be a 8bit global privileged register read. 506 * NV2080_CTRL_GPU_REG_OP_WRITE_08 507 * The register operation should be a 8bit global privileged register write. 508 * NV2080_CTRL_GPU_REG_OP_READ_32 509 * The register operation should be a 32bit register read. 510 * NV2080_CTRL_GPU_REG_OP_WRITE_32 511 * The register operation should be a 32bit register write. 512 * NV2080_CTRL_GPU_REG_OP_READ_64 513 * The register operation should be a 64bit register read. 514 * NV2080_CTRL_GPU_REG_OP_WRITE_64 515 * The register operation should be a 64bit register write. 516 * regType 517 * This field specifies the type of the register specified by the 518 * regOffset parameter. Valid values for this parameter are: 519 * NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL 520 * The register is a global privileged register. Read operations 521 * return the current value from the associated global register. 522 * Write operations for registers of this type take effect immediately. 523 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX 524 * The register is a graphics context register. Read operations 525 * return the current value from the associated global register. 526 * Write operations are applied to all existing graphics engine 527 * contexts. Any newly created graphics engine contexts will also 528 * be modified. 529 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC 530 * This is a graphics context TPC register group. Write operations are 531 * applied to TPC group(s) specified by regGroupMask. 532 * This field is ignored for read operations. 533 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM 534 * This is a graphics context SM register group that is inside TPC 535 * group. Write operations are applied to SM group(s) specified by 536 * regGroupMask (TPC) and regSubGroupMask (SM). This field is ignored 537 * for read operations. 538 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP 539 * This is a graphics context CROP register group. Write operations 540 * are applied to registers specified by regGroupMask. This field is 541 * ignored for read operations. 542 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP 543 * This is a graphics context ZROP register group. Write operations 544 * are applied to registers specified by regGroupMask. This field is 545 * ignored for read operations. 546 * NV2080_CTRL_GPU_REG_OP_TYPE_FB 547 * This is a fb register group. Write operations are applied to 548 * registers specified by regGroupMask. This field is 549 * ignored for read operations. 550 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD 551 * This is a graphics context QUAD register group. Operations 552 * are applied to registers specified by regQuad value. 553 * regQuad 554 * This field specifies the quad to be accessed for register regOffsetwhen 555 * the regType specified is NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD. 556 * regGroupMask 557 * This field specifies which registers inside an array should be updated. 558 * This field is used when regType is one of below: 559 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC 560 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM 561 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP 562 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP 563 * NV2080_CTRL_GPU_REG_OP_TYPE_FB 564 * When regGroupMask is used, the regOffset MUST be the first register in 565 * an array. 566 * regSubGroupMask 567 * This field specifies which registers inside a group should be updated. 568 * This field is used for updating SM registers when regType is: 569 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC 570 * When regSubGroupMask is used, regOffset MUST be the first register in an 571 * array AND also the first one in sub array. regGroupMask specifies 572 * TPC(X) and regSubGroupMask specifies SM_CTX_N(Y) 573 * regStatus 574 * This field returns the completion status for the associated register 575 * operation in the form of a bitmask. Possible status values for this 576 * field are: 577 * NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS 578 * This value indicates the operation completed successfully. 579 * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP 580 * This bit value indicates that the regOp value is not valid. 581 * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE 582 * This bit value indicates that the regType value is not valid. 583 * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET 584 * This bit value indicates that the regOffset value is invalid. 585 * The regOffset value must be within the legal BAR0 range for the 586 * associated GPU and must target a supported register with a 587 * supported operation. 588 * NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OFFSET 589 * This bit value indicates that the operation to the register 590 * specified by the regOffset value is not supported for the 591 * associated GPU. 592 * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK 593 * This bit value indicates that the regTpcMask value is invalid. 594 * The regTpcMask must be a subset of TPCs that are enabled on the 595 * associated GPU. 596 * NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS 597 * The caller does not have access to the register at given offset 598 * regOffset 599 * This field specifies the register offset to access. The specified 600 * offset must be a valid BAR0 offset for the associated GPU. 601 * regValueLo 602 * This field contains the low 32bits of the register value. 603 * For read operations, this value returns the current value of the 604 * register specified by regOffset. For write operations, this field 605 * specifies the logical OR value applied to the current value 606 * contained in the register specified by regOffset. 607 * regValueHi 608 * This field contains the high 32bits of the register value. 609 * For read operations, this value returns the current value of the 610 * register specified by regOffset + 4. For write operations, this field 611 * specifies the logical OR value applied to the current value 612 * contained in the register specified by regOffset + 4. 613 * regAndNMaskLo 614 * This field contains the mask used to clear a desired field from 615 * the current value contained in the register specified by regOffsetLo. 616 * This field is negated and ANDed to this current register value. 617 * This field is only used for write operations. This field is ignored 618 * for read operations. 619 * regAndNMaskHi 620 * This field contains the mask used to clear a desired field from 621 * the current value contained in the register specified by regOffsetHi. 622 * This field is negated and ANDed to this current register value. 623 * This field is only used for write operations. This field is ignored 624 * for read operations. 625 */ 626 typedef struct NV2080_CTRL_GPU_REG_OP { 627 NvU8 regOp; 628 NvU8 regType; 629 NvU8 regStatus; 630 NvU8 regQuad; 631 NvU32 regGroupMask; 632 NvU32 regSubGroupMask; 633 NvU32 regOffset; 634 NvU32 regValueHi; 635 NvU32 regValueLo; 636 NvU32 regAndNMaskHi; 637 NvU32 regAndNMaskLo; 638 } NV2080_CTRL_GPU_REG_OP; 639 640 /* valid regOp values */ 641 #define NV2080_CTRL_GPU_REG_OP_READ_32 (0x00000000U) 642 #define NV2080_CTRL_GPU_REG_OP_WRITE_32 (0x00000001U) 643 #define NV2080_CTRL_GPU_REG_OP_READ_64 (0x00000002U) 644 #define NV2080_CTRL_GPU_REG_OP_WRITE_64 (0x00000003U) 645 #define NV2080_CTRL_GPU_REG_OP_READ_08 (0x00000004U) 646 #define NV2080_CTRL_GPU_REG_OP_WRITE_08 (0x00000005U) 647 648 /* valid regType values */ 649 #define NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL (0x00000000U) 650 #define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX (0x00000001U) 651 #define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC (0x00000002U) 652 #define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM (0x00000004U) 653 #define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP (0x00000008U) 654 #define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP (0x00000010U) 655 #define NV2080_CTRL_GPU_REG_OP_TYPE_FB (0x00000020U) 656 #define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD (0x00000040U) 657 #define NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE (0x00000080U) 658 659 /* valid regStatus values (note: NvU8 ie, 1 byte) */ 660 #define NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS (0x00U) 661 #define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP (0x01U) 662 #define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE (0x02U) 663 #define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET (0x04U) 664 #define NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP (0x08U) 665 #define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK (0x10U) 666 #define NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS (0x20U) 667 668 /* 669 * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS 670 * 671 * This command is used to submit a buffer containing one or more 672 * NV2080_CTRL_GPU_REG_OP structures for processing. Each entry in the 673 * buffer specifies a single read or write operation. Each entry is checked 674 * for validity in an initial pass over the buffer with the results for 675 * each operation stored in the corresponding regStatus field. Unless 676 * bNonTransactional flag is set to true, if any invalid entries are found 677 * during this initial pass then none of the operations are executed. Entries 678 * are processed in order within each regType with NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL 679 * entries processed first followed by NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX entries. 680 * 681 * hClientTarget 682 * This parameter specifies the handle of the client that owns the channel 683 * specified by hChannelTarget. If this parameter is set to 0 then the set 684 * of channel-specific register operations are applied to all current and 685 * future channels. 686 * hChannelTarget 687 * This parameter specifies the handle of the target channel (or channel 688 * group) object instance to which channel-specific register operations are 689 * to be directed. If hClientTarget is set to 0 then this parameter must 690 * also be set to 0. 691 * bNonTransactional 692 * This field specifies if command is non-transactional i.e. if set to 693 * true, all the valid operations will be executed. 694 * reserved00 695 * This parameter is reserved for future use. It should be initialized to 696 * zero for correct operation. 697 * regOpCount 698 * This field specifies the number of entries on the caller's regOps 699 * list. 700 * regOps 701 * This field specifies a pointer in the caller's address space 702 * to the buffer from which the desired register information is to be 703 * retrieved. This buffer must be at least as big as regInfoCount 704 * multiplied by the size of the NV2080_CTRL_GPU_REG_OP structure. 705 * grRouteInfo 706 * This parameter specifies the routing information used to 707 * disambiguate the target GR engine. When SMC is enabled, this 708 * is a mandatory parameter. 709 * 710 * Possible status values returned are: 711 * NV_OK 712 * NV_ERR_INVALID_ARGUMENT 713 * NV_ERR_INVALID_PARAM_STRUCT 714 */ 715 #define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */ 716 717 #define NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0x22U) 718 719 typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS { 720 NvHandle hClientTarget; 721 NvHandle hChannelTarget; 722 NvU32 bNonTransactional; 723 NvU32 reserved00[2]; 724 NvU32 regOpCount; 725 NV_DECLARE_ALIGNED(NvP64 regOps, 8); 726 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 727 } NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS; 728 729 /* 730 * NV2080_CTRL_CMD_GPU_GET_ENGINES 731 * 732 * Returns a list of supported engine types along with the number of instances 733 * of each type. Querying with engineList NULL returns engineCount. 734 * 735 * engineCount 736 * This field specifies the number of entries on the caller's engineList 737 * field. 738 * engineList 739 * This field is a pointer to a buffer of NvU32 values representing the 740 * set of engines supported by the associated subdevice. Refer to cl2080.h 741 * for the complete set of supported engine types. 742 * 743 * Possible status values returned are: 744 * NV_OK 745 */ 746 #define NV2080_CTRL_CMD_GPU_GET_ENGINES (0x20800123U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID" */ 747 748 #define NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID (0x23U) 749 750 typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS { 751 NvU32 engineCount; 752 NV_DECLARE_ALIGNED(NvP64 engineList, 8); 753 } NV2080_CTRL_GPU_GET_ENGINES_PARAMS; 754 755 #define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */ 756 757 /* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */ 758 #define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x54U 759 760 #define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U) 761 762 typedef struct NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS { 763 NvU32 engineCount; 764 NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; 765 } NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS; 766 767 /* 768 * NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST 769 * 770 * Returns a list of classes supported by a given engine type. 771 * 772 * engineType 773 * This field specifies the engine type being queried. 774 * NV2080_CTRL_ENGINE_TYPE_ALLENGINES will return classes 775 * supported by all engines. 776 * 777 * numClasses 778 * This field specifies the number of classes supported by 779 * engineType. 780 * 781 * classList 782 * This field is an array containing the list of supported 783 * classes. Is of type (NvU32*) 784 * 785 * Possible status values returned are: 786 * NV_OK 787 * NV_ERR_INVALID_ARGUMENT 788 * NV_ERR_INVALID_PARAM_STRUCT 789 */ 790 #define NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST (0x20800124U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID" */ 791 792 #define NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID (0x24U) 793 794 typedef struct NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS { 795 NvU32 engineType; 796 NvU32 numClasses; 797 NV_DECLARE_ALIGNED(NvP64 classList, 8); 798 } NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS; 799 800 801 /* 802 * NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO 803 * 804 * This command returns the fault properties of the specified engine type. 805 * 806 * engineType 807 * Input parameter. 808 * This field specifies the engine type being queried. 809 * Engine type is specified using the NV2080_ENGINE_TYPE_* defines in cl2080.h. 810 * The list of engines supported by a chip can be got using the 811 * NV2080_CTRL_CMD_GPU_GET_ENGINES ctrl call. 812 * 813 * mmuFaultId 814 * Output parameter. 815 * This field returns the MMU fault ID for the specified engine. 816 * If the engine supports subcontext, this field provides the base fault id. 817 * 818 * bSubcontextSupported 819 * Output parameter. 820 * Returns TRUE if subcontext faulting is supported by the engine. 821 * Engine that support subcontext use fault IDs in the range [mmuFaultId, mmuFaultId + maxSubCtx). 822 * "maxSubctx" can be found using the NV2080_CTRL_FIFO_INFO ctrl call with 823 * NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP as the index. 824 * 825 * Possible status values returned are: 826 * NV_OK 827 * NV_ERR_INVALID_ARGUMENT 828 * NV_ERR_INVALID_PARAM_STRUCT 829 */ 830 #define NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO (0x20800125U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID" */ 831 832 #define NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID (0x25U) 833 834 typedef struct NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS { 835 NvU32 engineType; 836 NvU32 mmuFaultId; 837 NvBool bSubcontextSupported; 838 } NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS; 839 840 841 842 /* 843 * NV2080_CTRL_CMD_GPU_QUERY_MODE 844 * 845 * This command is used to detect the mode of the GPU associated with the 846 * subdevice. 847 * 848 * mode 849 * This parameter returns the current mode of GPU. Legal values for 850 * this parameter include: 851 * NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE 852 * The GPU is currently operating in graphics mode. 853 * NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE 854 * The GPU is currently operating in compute mode. 855 * NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE 856 * The current mode of the GPU could not be determined. 857 * 858 * Possible status values returned are: 859 * NV_OK 860 */ 861 #define NV2080_CTRL_CMD_GPU_QUERY_MODE (0x20800128U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID" */ 862 863 /* valid mode parameter values */ 864 #define NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE (0x00000000U) 865 #define NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE (0x00000001U) 866 #define NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE (0x00000002U) 867 868 #define NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID (0x28U) 869 870 typedef struct NV2080_CTRL_GPU_QUERY_MODE_PARAMS { 871 NvU32 mode; 872 } NV2080_CTRL_GPU_QUERY_MODE_PARAMS; 873 874 875 876 /*! 877 * NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY 878 * Data block describing a virtual context buffer to be promoted 879 * 880 * gpuPhysAddr [IN] 881 * GPU Physical Address for the buffer 882 * gpuVirtAddr [IN] 883 * GPU Virtual Address for the buffer 884 * size[IN] 885 * Size of this virtual context buffer 886 * physAttr [IN] 887 * Physical memory attributes (aperture, cacheable) 888 * bufferId [IN] 889 * Virtual context buffer type, data type NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_* 890 * bInitialize [IN] 891 * Flag indicating that this virtual context buffer should be initialized prior to promotion. 892 * The client must clear (memset) the buffer to 0x0 prior to initialization. 893 * Following buffers need initialization: 894 * 1. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN 895 * 2. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH 896 * 3. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP 897 * 4. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP 898 * bNonmapped [IN] 899 * Flag indicating that the virtual address is not to be promoted with this 900 * call. It is illegal to set this flag and not set bInitialize. 901 */ 902 typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY { 903 NV_DECLARE_ALIGNED(NvU64 gpuPhysAddr, 8); 904 NV_DECLARE_ALIGNED(NvU64 gpuVirtAddr, 8); 905 NV_DECLARE_ALIGNED(NvU64 size, 8); 906 NvU32 physAttr; 907 NvU16 bufferId; 908 NvU8 bInitialize; 909 NvU8 bNonmapped; 910 } NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY; 911 912 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN 0U 913 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM 1U 914 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH 2U 915 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB 3U 916 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL 4U 917 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB 5U 918 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL 6U 919 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL 7U 920 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK 8U 921 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT 9U 922 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP 10U 923 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP 11U 924 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP 12U 925 926 #define NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES 16U 927 928 /* 929 * NV2080_CTRL_CMD_GPU_PROMOTE_CTX 930 * 931 * This command is used to promote a Virtual Context 932 * 933 * engineType 934 * Engine Virtual Context is for 935 * hClient 936 * Client Handle for hVirtMemory 937 * ChID 938 * Hw Channel -- Actually hw index for channel (deprecated) 939 * hChanClient 940 * The client handle for hObject 941 * hObject 942 * Passed in object handle for either a single channel or a channel group 943 * hVirtMemory 944 * Virtual Address handle to map Virtual Context to 945 * virtAddress 946 * Virtual Address to map Virtual Context to 947 * size 948 * size of the Virtual Context 949 * entryCount 950 * Number of valid entries in the promotion entry list 951 * promoteEntry 952 * List of context buffer entries to issue promotions for. 953 * 954 * When not using promoteEntry, only hVirtMemory or (virtAddress, size) should be 955 * specified, the code cases based on hVirtMemory(NULL vs non-NULL) so 956 * if both are specified, hVirtMemory has precedence. 957 * 958 * Possible status values returned are: 959 * NV_OK 960 * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval 961 * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. 962 * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. 963 */ 964 #define NV2080_CTRL_CMD_GPU_PROMOTE_CTX (0x2080012bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID" */ 965 966 #define NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID (0x2BU) 967 968 typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS { 969 NvU32 engineType; 970 NvHandle hClient; 971 NvU32 ChID; 972 NvHandle hChanClient; 973 NvHandle hObject; 974 NvHandle hVirtMemory; 975 NV_DECLARE_ALIGNED(NvU64 virtAddress, 8); 976 NV_DECLARE_ALIGNED(NvU64 size, 8); 977 NvU32 entryCount; 978 // C form: NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES]; 979 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES], 8); 980 } NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS; 981 typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *PNV2080_CTRL_GPU_PROMOTE_CTX_PARAMS; 982 983 /* 984 * NV2080_CTRL_CMD_GPU_EVICT_CTX 985 * 986 * This command is used to evict a Virtual Context 987 * 988 * engineType 989 * Engine Virtual Context is for 990 * hClient 991 * Client Handle 992 * ChID 993 * Hw Channel -- Actually hw index for channel (deprecated) 994 * hChanClient 995 * Client handle for hObject 996 * hObject 997 * Passed in object handle for either a single channel or a channel group 998 * 999 * Possible status values returned are: 1000 * NV_OK 1001 * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval 1002 * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. 1003 * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. 1004 */ 1005 #define NV2080_CTRL_CMD_GPU_EVICT_CTX (0x2080012cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID" */ 1006 1007 #define NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID (0x2CU) 1008 1009 typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS { 1010 NvU32 engineType; 1011 NvHandle hClient; 1012 NvU32 ChID; 1013 NvHandle hChanClient; 1014 NvHandle hObject; 1015 } NV2080_CTRL_GPU_EVICT_CTX_PARAMS; 1016 typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS *PNV2080_CTRL_GPU_EVICT_CTX_PARAMS; 1017 1018 /* 1019 * NV2080_CTRL_CMD_GPU_INITIALIZE_CTX 1020 * 1021 * This command is used to initialize a Virtual Context. The ctx buffer must be 1022 * cleared (zerod) by the caller prior to invoking this method. 1023 * 1024 * engineType 1025 * Engine Virtual Context is for 1026 * hClient 1027 * Client Handle for the hVirtMemory 1028 * ChID 1029 * Hw channel -- Actually channel index (deprecated) 1030 * hChanClient 1031 * The client handle for hObject 1032 * hObject 1033 * Passed in object handle for either a single channel or a channel group 1034 * hVirtMemory 1035 * Virtual Address where to map Virtual Context to 1036 * physAddress 1037 * Physical offset in FB to use as Virtual Context 1038 * physAttr 1039 * Physical memory attributes 1040 * hDmaHandle 1041 * Dma Handle when using discontiguous context buffers 1042 * index 1043 * Start offset in Virtual DMA Context 1044 * size 1045 * Size of the Virtual Context 1046 * 1047 * Only hVirtMemory or size should be specified, the code cases based on hVirtMemory 1048 * (NULL vs non-NULL) so if both are specified, hVirtMemory has precedence. 1049 * 1050 * Possible status values returned are: 1051 * NV_OK 1052 * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval 1053 * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. 1054 * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. 1055 */ 1056 #define NV2080_CTRL_CMD_GPU_INITIALIZE_CTX (0x2080012dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID" */ 1057 1058 #define NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID (0x2DU) 1059 1060 typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS { 1061 NvU32 engineType; 1062 NvHandle hClient; 1063 NvU32 ChID; 1064 NvHandle hChanClient; 1065 NvHandle hObject; 1066 NvHandle hVirtMemory; 1067 NV_DECLARE_ALIGNED(NvU64 physAddress, 8); 1068 NvU32 physAttr; 1069 NvHandle hDmaHandle; 1070 NvU32 index; 1071 NV_DECLARE_ALIGNED(NvU64 size, 8); 1072 } NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS; 1073 typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS; 1074 1075 #define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE 1:0 1076 #define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM (0x00000000U) 1077 #define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS (0x00000001U) 1078 #define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS (0x00000002U) 1079 1080 #define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE 2:2 1081 #define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES (0x00000000U) 1082 #define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO (0x00000001U) 1083 1084 /* 1085 * NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX - Tells RM Whether this Ctx buffer needs to 1086 * do a full initialization (Load the golden image). When a context is promoted on a different 1087 * channel than it was originally inited, the client can use this flag to tell RM 1088 * that this is an already inited Context. In such cases RM will update the internal state 1089 * to update the context address and state variables. 1090 */ 1091 1092 #define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX 3:3 1093 #define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO (0x00000000U) 1094 #define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES (0x00000001U) 1095 1096 /* 1097 * NV2080_CTRL_CMD_CPU_QUERY_ECC_INTR 1098 * Queries the top level ECC PMC PRI register 1099 * TODO remove these parameters, tracked in bug #1975721 1100 */ 1101 #define NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR (0x2080012eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2E" */ 1102 1103 typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS { 1104 NvU32 eccIntrStatus; 1105 } NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS; 1106 1107 /** 1108 * NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS 1109 * 1110 * This command is used to query the ECC status of a GPU by a subdevice 1111 * handle. Please see the NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS 1112 * data structure description below for details on the data reported 1113 * per hardware unit. 1114 * 1115 * units 1116 * Array of structures used to describe per-unit state 1117 * 1118 * flags 1119 * See interface flag definitions below. 1120 * 1121 * Possible status values returned are: 1122 * NV_OK 1123 * NV_ERR_NOT_SUPPORTED 1124 */ 1125 1126 1127 1128 #define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */ 1129 1130 1131 #define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x0000001FU) 1132 1133 1134 1135 // Deprecated do not use 1136 #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE 0:0 1137 #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED (0x00000000U) 1138 #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW (0x00000001U) 1139 1140 #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE 0U 1141 #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE 1U 1142 #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE 2U 1143 1144 /* 1145 * NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS 1146 * 1147 * This structure represents the exception status of a class of per-unit 1148 * exceptions 1149 * 1150 * count 1151 * number of exceptions that have occurred since boot 1152 */ 1153 typedef struct NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS { 1154 NV_DECLARE_ALIGNED(NvU64 count, 8); 1155 } NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS; 1156 1157 /* 1158 * NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS 1159 * 1160 * This structure represents the per-unit ECC exception status 1161 * 1162 * enabled 1163 * ECC enabled yes/no for this unit 1164 * scrubComplete 1165 * Scrub has completed yes/no. A scrub is performed for some units to ensure 1166 * the checkbits are consistent with the protected data. 1167 * supported 1168 * Whether HW supports ECC in this unit for this GPU 1169 * dbe 1170 * Double bit error (DBE) status. The value returned reflects a counter 1171 * that is monotonic, but can be reset by clients. 1172 * dbeNonResettable (deprecated do not use) 1173 * Double bit error (DBE) status, not client resettable. 1174 * sbe 1175 * Single bit error (SBE) status. The value returned reflects a counter 1176 * that is monotonic, but can be reset by clients. 1177 * sbeNonResettable (deprecated do not use) 1178 * Single bit error (SBE) status, not client resettable. 1179 * 1180 */ 1181 typedef struct NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS { 1182 NvBool enabled; 1183 NvBool scrubComplete; 1184 NvBool supported; 1185 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS dbe, 8); 1186 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS dbeNonResettable, 8); 1187 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS sbe, 8); 1188 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS sbeNonResettable, 8); 1189 } NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS; 1190 1191 /* 1192 * NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS 1193 * 1194 * This structure returns ECC exception status and GPU Fatal Poison for all units 1195 * 1196 * units 1197 * This structure represents ECC exception status for all Units. 1198 * bFatalPoisonError 1199 * Whether GPU Fatal poison error occurred in this GPU. This will be set for Ampere_and_later 1200 * uncorrectableError 1201 * Indicates whether any uncorrectable GR ECC errors have occurred. When 1202 * SMC is enabled, uncorrectableError is only valid when the client is 1203 * subscribed to a partition. Check QUERY_ECC_STATUS_UNC_ERR_* 1204 * flags 1205 * Flags passed by caller. Refer NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_* for details. 1206 * grRouteInfo 1207 * SMC partition information. This input is only valid when SMC is 1208 * enabled on Ampere_and_later. 1209 * 1210 */ 1211 #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID (0x2FU) 1212 1213 typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS { 1214 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS units[NV2080_CTRL_GPU_ECC_UNIT_COUNT], 8); 1215 NvBool bFatalPoisonError; 1216 NvU8 uncorrectableError; 1217 NvU32 flags; 1218 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 1219 } NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS; 1220 1221 /* 1222 * NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES 1223 * 1224 * This command sets the compute mode rules for the associated subdevice. The 1225 * default mode is equivalent to NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE. This 1226 * command is available to clients with administrator privileges only. An 1227 * attempt to use this command by a client without administrator privileged 1228 * results in the return of an NV_ERR_INSUFFICIENT_PERMISSIONS status. 1229 * 1230 * rules 1231 * This parameter is used to specify the rules that govern the GPU with 1232 * respect to NV50_COMPUTE objects. Legal values for this parameter include: 1233 * 1234 * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE 1235 * This mode indicate that no special restrictions apply to the 1236 * allocation of NV50_COMPUTE objects. 1237 * 1238 * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE 1239 * This mode means that only one instance of NV50_COMPUTE will be 1240 * allowed at a time. This restriction is enforced at each subsequent 1241 * NV50_COMPUTE allocation attempt. Setting this mode will not affect 1242 * any existing compute programs that may be running. For example, 1243 * if this mode is set while three compute programs are running, then 1244 * all of those programs will be allowed to continue running. However, 1245 * until they all finish running, no new NV50_COMPUTE objects may be 1246 * allocated. User-mode clients should treat this as restricting access 1247 * to a NV50_COMPUTE object to a single thread within a process. 1248 * 1249 * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED 1250 * This mode means that that GPU is not ever allowed to instantiate an 1251 * NV50_COMPUTE object, and thus cannot run any new compute programs. 1252 * This restriction is enforced at each subsequent NV50_COMPUTE object 1253 * allocation attempt. Setting this mode will not affect any existing 1254 * compute programs that may be running. For example, if this mode is 1255 * set while three compute programs are running, then all of those 1256 * programs will be allowed to continue running. However, no new 1257 * NV50_COMPUTE objects may be allocated. 1258 * 1259 * 1260 * NV2080_CTRL_GPU_COMPUTE_MODE_EXCLUSIVE_COMPUTE_PROCESS 1261 * This mode is identical to EXCLUSIVE_COMPUTE, where only one instance 1262 * of NV50_COMPUTE will be allowed at a time. It is separate from 1263 * EXCLUSIVE_COMPUTE to allow user-mode clients to differentiate 1264 * exclusive access to a compute object from a single thread of a 1265 * process from exclusive access to a compute object from all threads 1266 * of a process. User-mode clients should not limit access to a 1267 * NV50_COMPUTE object to a single thread when the GPU is set to 1268 * EXCLUSIVE_COMPUTE_PROCESS. 1269 * 1270 * An invalid rules parameter value results in the return of an 1271 * NV_ERR_INVALID_ARGUMENT status. 1272 * 1273 * flags 1274 * Reserved. Caller should set this field to zero. 1275 * 1276 * Possible status return values are: 1277 * NV_OK 1278 * NV_ERR_INVALID_ARGUMENT (if an invalid rule number is provided) 1279 * NV_ERR_INSUFFICIENT_PERMISSIONS (if the user is not the Administrator or superuser) 1280 * NV_ERR_NOT_SUPPORTED 1281 */ 1282 #define NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES (0x20800130U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */ 1283 1284 /* valid rules parameter values */ 1285 #define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE (0x00000000U) 1286 #define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE (0x00000001U) 1287 #define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED (0x00000002U) 1288 #define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS (0x00000003U) 1289 1290 #define NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x30U) 1291 1292 typedef struct NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS { 1293 NvU32 rules; 1294 NvU32 flags; 1295 } NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS; 1296 1297 /* 1298 * NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES 1299 * 1300 * This command queries the compute mode rules for the associated subdevice. 1301 * Please see the NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES command, above, for 1302 * details as to what the rules mean. 1303 * 1304 * rules 1305 * Specifies the rules that govern the GPU, with respect to NV50_COMPUTE 1306 * objects. 1307 * 1308 * Possible status return values are: 1309 * NV_OK 1310 * NV_ERR_NOT_SUPPORTED 1311 */ 1312 #define NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES (0x20800131U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */ 1313 1314 #define NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x31U) 1315 1316 typedef struct NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS { 1317 NvU32 rules; 1318 } NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS; 1319 1320 /* 1321 * NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION 1322 * 1323 * This command returns the current ECC configuration setting for 1324 * a GPU given its subdevice handle. The value returned is 1325 * the current ECC setting for the GPU stored in non-volatile 1326 * memory on the board. 1327 * 1328 * currentConfiguration 1329 * The current ECC configuration setting. 1330 * 1331 * defaultConfiguration 1332 * The factory default ECC configuration setting. 1333 * 1334 * Please see the NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS command if 1335 * you wish to determine if ECC is currently enabled. 1336 * 1337 * Possible status return values are: 1338 * NV_OK 1339 * NV_ERR_NOT_SUPPORTED 1340 * NV_ERR_INVALID_STATE 1341 */ 1342 #define NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION (0x20800133U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */ 1343 1344 #define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED (0x00000000U) 1345 #define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED (0x00000001U) 1346 1347 #define NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x33U) 1348 1349 typedef struct NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS { 1350 NvU32 currentConfiguration; 1351 NvU32 defaultConfiguration; 1352 } NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS; 1353 1354 /* 1355 * NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION 1356 * 1357 * This command changes the ECC configuration setting for a GPU 1358 * given its subdevice handle. The value specified is 1359 * stored in non-volatile memory on the board and will take 1360 * effect with the next GPU reset 1361 * 1362 * newConfiguration 1363 * The new configuration setting to take effect with 1364 * the next GPU reset. 1365 * 1366 * Possible status return values are: 1367 * NV_OK 1368 * NV_ERR_INVALID_ARGUMENT 1369 * NV_ERR_NOT_SUPPORTED 1370 */ 1371 #define NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION (0x20800134U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */ 1372 1373 #define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE (0x00000000U) 1374 #define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE (0x00000001U) 1375 1376 #define NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x34U) 1377 1378 typedef struct NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS { 1379 NvU32 newConfiguration; 1380 } NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS; 1381 1382 1383 1384 /* 1385 * NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS 1386 * 1387 * This command resets volatile and/or persistent ECC error 1388 * status information for a GPU given its subdevice 1389 * handle. 1390 * 1391 * statuses 1392 * The ECC error statuses (the current, volatile 1393 * and/or the persistent error counter(s)) to 1394 * be reset by the command. 1395 * flags 1396 * FORCE_PURGE 1397 * Forcibly clean all the ECC InfoROM state if this flag is set 1398 * 1399 * Possible status return values are: 1400 * NV_OK 1401 * NV_ERR_INVALID_ARGUMENT 1402 * NV_ERR_NOT_SUPPORTED 1403 */ 1404 #define NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS (0x20800136U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID" */ 1405 1406 #define NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE (0x00000000U) 1407 #define NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE (0x00000001U) 1408 #define NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE (0x00000002U) 1409 1410 #define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE 0:0 1411 #define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE 0U 1412 #define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE 1U 1413 1414 #define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID (0x36U) 1415 1416 typedef struct NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS { 1417 NvU32 statuses; 1418 NvU8 flags; 1419 } NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS; 1420 1421 /* 1422 * NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO 1423 * 1424 * This command returns a mask of enabled GPCs for the associated GPU. 1425 * 1426 * gpcMask 1427 * This parameter returns a mask of enabled GPCs. Each GPC has an ID 1428 * that's equivalent to the corresponding bit position in the mask. 1429 * 1430 * Possible status values returned are: 1431 * NV_OK 1432 * NV_ERR_NOT_SUPPORTED 1433 * NV_ERR_INVALID_PARAM_STRUCT 1434 */ 1435 #define NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO (0x20800137U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID" */ 1436 1437 #define NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID (0x37U) 1438 1439 typedef struct NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS { 1440 NvU32 gpcMask; 1441 } NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS; 1442 1443 /* 1444 * NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO 1445 * 1446 * This command returns a mask of enabled TPCs for a specified GPC. 1447 * 1448 * gpcId 1449 * This parameter specifies the GPC for which TPC information is 1450 * to be retrieved. If the GPC with this ID is not enabled this command 1451 * will return an tpcMask value of zero. 1452 * 1453 * tpcMask 1454 * This parameter returns a mask of enabled TPCs for the specified GPC. 1455 * Each TPC has an ID that's equivalent to the corresponding bit 1456 * position in the mask. 1457 * 1458 * Possible status values returned are: 1459 * NV_OK 1460 * NV_ERR_NOT_SUPPORTED 1461 * NV_ERR_INVALID_PARAM_STRUCT 1462 */ 1463 #define NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO (0x20800138U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID" */ 1464 1465 #define NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID (0x38U) 1466 1467 typedef struct NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS { 1468 NvU32 gpcId; 1469 NvU32 tpcMask; 1470 } NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS; 1471 1472 /* 1473 * NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO 1474 * 1475 * This command returns a mask of enabled ZCULLs for a specified GPC. 1476 * 1477 * gpcId 1478 * This parameter specifies the GPC for which ZCULL information is to be 1479 * retrieved. If the GPC with this ID is not enabled this command will 1480 * return an zcullMask value of zero. 1481 * 1482 * zcullMask 1483 * This parameter returns a mask of enabled ZCULLs for the specified GPC. 1484 * Each ZCULL has an ID that's equivalent to the corresponding bit 1485 * position in the mask. 1486 * 1487 * Possible status values returned are: 1488 * NV_OK 1489 * NV_ERR_NOT_SUPPORTED 1490 * NV_ERR_INVALID_PARAM_STRUCT 1491 * 1492 * Deprecated: Please use GR based control call 1493 * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK 1494 * 1495 */ 1496 #define NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO (0x20800139U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID" */ 1497 1498 #define NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID (0x39U) 1499 1500 typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS { 1501 NvU32 gpcId; 1502 NvU32 zcullMask; 1503 } NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS; 1504 1505 1506 1507 /* 1508 * NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO 1509 * 1510 * If an InfoROM with a valid OEM Board Object is present, this 1511 * command returns relevant information from the object to the 1512 * caller. 1513 * 1514 * The following data are currently reported: 1515 * 1516 * buildDate 1517 * The board's build date (8 digit BCD in format YYYYMMDD). 1518 * 1519 * marketingName 1520 * The board's marketing name (24 ASCII letters e.g. "Quadro FX5800"). 1521 * 1522 * boardSerialNumber 1523 * The board's serial number. 1524 * 1525 * memoryManufacturer 1526 * The board's memory manufacturer ('S'amsung/'H'ynix/'I'nfineon). 1527 * 1528 * memoryDateCode 1529 * The board's memory datecode (LSB justified ASCII field with 0x00 1530 * denoting empty space). 1531 * 1532 * productPartNumber 1533 * The board's 900 product part number (LSB justified ASCII field with 0x00 1534 * denoting empty space e.g. "900-21228-0208-200"). 1535 * 1536 * boardRevision 1537 * The board's revision (for e.g. A02, B01) 1538 * 1539 * boardType 1540 * The board's type ('E'ngineering/'P'roduction) 1541 * 1542 * board699PartNumber 1543 * The board's 699 product part number (LSB justified ASCII field with 0x00 1544 * denoting empty space e.g. "699-21228-0208-200"). 1545 * 1546 * board965PartNumber 1547 * The board's 965 product part number (LSB justified ASCII field with 0x00 1548 * denoting empty space e.g. "965-21228-0208-200"). 1549 * 1550 * Possible status return values are: 1551 * NV_OK 1552 * NV_ERR_NOT_SUPPORTED 1553 */ 1554 #define NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO (0x2080013fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID" */ 1555 1556 #define NV2080_GPU_MAX_MARKETING_NAME_LENGTH (0x00000018U) 1557 #define NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH (0x00000010U) 1558 #define NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH (0x00000014U) 1559 #define NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH (0x00000006U) 1560 #define NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH (0x00000014U) 1561 1562 #define NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID (0x3FU) 1563 1564 typedef struct NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS { 1565 NvU32 buildDate; 1566 NvU8 marketingName[NV2080_GPU_MAX_MARKETING_NAME_LENGTH]; 1567 NvU8 serialNumber[NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH]; 1568 NvU8 memoryManufacturer; 1569 NvU8 memoryPartID[NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH]; 1570 NvU8 memoryDateCode[NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH]; 1571 NvU8 productPartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; 1572 NvU8 boardRevision[3]; 1573 NvU8 boardType; 1574 NvU8 board699PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; 1575 NvU8 board965PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; 1576 } NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS; 1577 1578 1579 1580 /* 1581 * NV2080_CTRL_CMD_GPU_GET_ID 1582 * 1583 * This command returns the gpuId of the associated object. 1584 * 1585 * gpuId 1586 * This field return the gpuId. 1587 * 1588 * Possible status return values are: 1589 * NV_OK 1590 * NV_ERR_NOT_SUPPORTED 1591 */ 1592 #define NV2080_CTRL_CMD_GPU_GET_ID (0x20800142U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID" */ 1593 1594 #define NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID (0x42U) 1595 1596 typedef struct NV2080_CTRL_GPU_GET_ID_PARAMS { 1597 NvU32 gpuId; 1598 } NV2080_CTRL_GPU_GET_ID_PARAMS; 1599 1600 /* 1601 * NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE 1602 * 1603 * This command is used to enable or disable GPU debug mode. While this mode 1604 * is enabled, some client RM calls that can potentially timeout return 1605 * NV_ERR_BUSY_RETRY, signalling the client to try again once GPU 1606 * debug mode is disabled. 1607 * 1608 * mode 1609 * This parameter specifies whether GPU debug mode is to be enabled or 1610 * disabled. Possible values are: 1611 * 1612 * NV2080_CTRL_GPU_DEBUG_MODE_ENABLED 1613 * NV2080_CTRL_GPU_DEBUG_MODE_DISABLED 1614 * 1615 * Possible return status values are 1616 * NV_OK 1617 * NV_ERR_INVALID_ARGUMENT 1618 * 1619 */ 1620 #define NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE (0x20800143U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */ 1621 1622 #define NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x43U) 1623 1624 typedef struct NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS { 1625 NvU32 mode; 1626 } NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS; 1627 1628 #define NV2080_CTRL_GPU_DEBUG_MODE_ENABLED (0x00000001U) 1629 #define NV2080_CTRL_GPU_DEBUG_MODE_DISABLED (0x00000002U) 1630 1631 /* 1632 * NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE 1633 * 1634 * This command is used to query whether debug mode is enabled on the current 1635 * GPU. Please see the description of NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE 1636 * for more details on GPU debug mode. 1637 * 1638 * currentMode 1639 * This parameter returns the state of GPU debug mode for the current GPU. 1640 * Possible values are: 1641 * 1642 * NV2080_CTRL_GPU_DEBUG_MODE_ENABLED 1643 * NV2080_CTRL_GPU_DEBUG_MODE_DISABLED 1644 * 1645 * Possible return status values are 1646 * NV_OK 1647 * NV_ERR_INVALID_ARGUMENT 1648 * 1649 */ 1650 #define NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE (0x20800144U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */ 1651 1652 #define NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x44U) 1653 1654 typedef struct NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS { 1655 NvU32 currentMode; 1656 } NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS; 1657 1658 1659 1660 /* 1661 * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST 1662 * 1663 * Returns a list of engines that can partner or coexist 1664 * when using the target channel or partnership class. 1665 * This list may include all engines (pre-Kepler), or as few 1666 * as 1 engine (Kepler and beyond). 1667 * 1668 * engineType 1669 * This field specifies the target engine type. 1670 * See cl2080.h for a list of valid engines. 1671 * 1672 * partnershipClassId 1673 * This field specifies the target channel 1674 * or partnership class ID. 1675 * An example of such a class is GF100_CHANNEL_GPFIFO. 1676 * 1677 * runqueue 1678 * This field is an index which indicates the runqueue to 1679 * return the list of supported engines for. This is the 1680 * same field as what NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE 1681 * specifies. This is only valid for TSG. 1682 * 1683 * numPartners; 1684 * This field returns the number of 1685 * valid entries in the partnersList array 1686 * 1687 * partnerList 1688 * This field is an array containing the list of supported 1689 * partner engines types, in no particular order, and 1690 * may even be empty (numPartners = 0). 1691 * See cl2080.h for a list of possible engines. 1692 * 1693 * Possible status values returned are: 1694 * NV_OK 1695 * NV_ERR_INVALID_ARGUMENT 1696 * NV_ERR_INVALID_PARAM_STRUCT 1697 */ 1698 1699 #define NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST (0x20800147U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID" */ 1700 1701 /* this macro specifies the maximum number of partner entries */ 1702 #define NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS (0x00000020U) 1703 1704 #define NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID (0x47U) 1705 1706 typedef struct NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS { 1707 NvU32 engineType; 1708 NvU32 partnershipClassId; 1709 NvU32 runqueue; 1710 NvU32 numPartners; 1711 // C form: NvU32 partnerList[NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS]; 1712 NvU32 partnerList[NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS]; 1713 } NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS; 1714 1715 1716 1717 /* 1718 * NV2080_CTRL_CMD_GPU_GET_GID_INFO 1719 * 1720 * This command returns the GPU ID (GID) string for the associated 1721 * GPU. This value can be useful for GPU identification and security 1722 * system validation. 1723 * 1724 * The GPU ID is a SHA-1 based 16 byte ID, formatted as a 32 character 1725 * hexadecimal string as "GPU-%08x-%04x-%04x-%04x-%012x" (the 1726 * canonical format of a UUID) 1727 * 1728 * The GPU IDs are generated using the ECID, PMC_BOOT_0, and 1729 * PMC_BOOT_42 of the GPU as the hash message. 1730 * 1731 * index 1732 * (Input) "Select which GID set to get." Or so the original documentation 1733 * said. In reality, there is only one GID per GPU, and the implementation 1734 * completely ignores this parameter. You can too. 1735 * 1736 * flags (Input) The _FORMAT* flags designate ascii or binary format. Binary 1737 * format returns the raw bytes of either the 16-byte SHA-1 ID or the 1738 * 32-byte SHA-256 ID. 1739 * 1740 * The _TYPE* flags needs to specify the _SHA1 type. 1741 * 1742 * length 1743 * (Output) Actual GID length, in bytes. 1744 * 1745 * data[NV2080_BUS_MAX_GID_LENGTH] 1746 * (Output) Result buffer: the GID itself, in a format that is determined by 1747 * the "flags" field (described above). 1748 * 1749 * Possible status return values are: 1750 * NV_OK 1751 * NV_ERR_NOT_SUPPORTED 1752 * NV_ERR_INVALID_STATE 1753 */ 1754 #define NV2080_CTRL_CMD_GPU_GET_GID_INFO (0x2080014aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID" */ 1755 1756 /* maximum possible number of bytes of GID information returned */ 1757 #define NV2080_GPU_MAX_GID_LENGTH (0x000000100ULL) 1758 1759 /* maximum possible number of bytes of GID information returned if given the BINARY and SHA1 flags */ 1760 #define NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH (0x000000010ULL) 1761 1762 #define NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID (0x4AU) 1763 1764 typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS { 1765 NvU32 index; 1766 NvU32 flags; 1767 NvU32 length; 1768 NvU8 data[NV2080_GPU_MAX_GID_LENGTH]; 1769 } NV2080_CTRL_GPU_GET_GID_INFO_PARAMS; 1770 1771 /* valid flags values */ 1772 #define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT 1:0 1773 #define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII (0x00000000U) 1774 #define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY (0x00000002U) 1775 1776 #define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE 2:2 1777 #define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1 (0x00000000U) 1778 1779 /* 1780 * NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION 1781 * 1782 * This command can be used by clients to retrieve the version of an 1783 * InfoROM object. 1784 * 1785 * objectType 1786 * This parameter specifies the name of the InfoROM object whose version 1787 * should be queried. 1788 * 1789 * version 1790 * This parameter returns the version of the InfoROM object specified by 1791 * the objectType parameter. 1792 * 1793 * subversion 1794 * This parameter returns the subversion of the InfoROM object specified 1795 * by the objectType parameter. 1796 * 1797 * Possible return status values: 1798 * NV_OK 1799 * NV_ERR_STATE_IN_USE 1800 * NV_ERR_INVALID_ARGUMENT 1801 * NV_ERR_NOT_SUPPORTED 1802 * 1803 */ 1804 #define NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION (0x2080014bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID" */ 1805 1806 #define NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN 3U 1807 1808 #define NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID (0x4BU) 1809 1810 typedef struct NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS { 1811 char objectType[NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN]; 1812 NvU8 version; 1813 NvU8 subversion; 1814 } NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS; 1815 1816 1817 /* 1818 * NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO 1819 * 1820 * This command will specify that system is Optimus enabled. 1821 * 1822 * isOptimusEnabled 1823 * Set NV_TRUE if system is Optimus enabled. 1824 * 1825 * Possible status return values are: 1826 * NV_OK 1827 */ 1828 #define NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO (0x2080014cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID" */ 1829 1830 #define NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID (0x4CU) 1831 1832 typedef struct NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS { 1833 NvBool isOptimusEnabled; 1834 } NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS; 1835 1836 /* 1837 * NV2080_CTRL_CMD_GPU_GET_IP_VERSION 1838 * 1839 * Will return the IP VERSION on the given engine for engines that support 1840 * this capability. 1841 * 1842 * targetEngine 1843 * This parameter specifies the target engine type to query for IP_VERSION. 1844 * 1845 * ipVersion 1846 * This parameter returns the IP VERSION read from the unit's IP_VER 1847 * register. 1848 * 1849 * Possible status values returned are: 1850 * NV_OK 1851 * NV_ERR_INVALID_ARGUMENT 1852 * NV_ERR_NOT_SUPPORTED 1853 */ 1854 1855 #define NV2080_CTRL_CMD_GPU_GET_IP_VERSION (0x2080014dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID" */ 1856 1857 #define NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4DU) 1858 1859 typedef struct NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS { 1860 NvU32 targetEngine; 1861 NvU32 ipVersion; 1862 } NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS; 1863 1864 #define NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY (0x00000001U) 1865 #define NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC (0x00000002U) 1866 #define NV2080_CTRL_GPU_GET_IP_VERSION_PMGR (0x00000003U) 1867 #define NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU (0x00000004U) 1868 #define NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON (0x00000005U) 1869 1870 1871 1872 /* 1873 * NV2080_CTRL_CMD_GPU_ID_ILLUM_SUPPORT 1874 * 1875 * This command returns an indicator which reports if the specified Illumination control 1876 * attribute is supported 1877 * 1878 * Possible status return values are: 1879 * NV_OK 1880 * NV_ERR_NOT_SUPPORTED 1881 */ 1882 #define NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS 0U 1883 #define NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS 1U 1884 #define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT (0x20800153U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID" */ 1885 1886 #define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID (0x53U) 1887 1888 typedef struct NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS { 1889 NvU32 attribute; 1890 NvBool bSupported; 1891 } NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS; 1892 1893 /* 1894 * NV2080_CTRL_CMD_GPU_GET_ID_ILLUM 1895 * 1896 * This command returns the current value of the specified Illumination control attribute. 1897 * 1898 * Possible status return values are: 1899 * NV_OK 1900 * NV_ERR_NOT_SUPPORTED 1901 */ 1902 #define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID" */ 1903 1904 typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS { 1905 NvU32 attribute; 1906 NvU32 value; 1907 } NV2080_CTRL_CMD_GPU_ILLUM_PARAMS; 1908 1909 #define NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID (0x54U) 1910 1911 typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_GET_ILLUM_PARAMS; 1912 1913 /* 1914 * NV2080_CTRL_CMD_GPU_SET_ID_ILLUM 1915 * 1916 * This command sets a new valuefor the specified Illumination control attribute. 1917 * 1918 * Possible status return values are: 1919 * NV_OK 1920 * NV_ERR_NOT_SUPPORTED 1921 */ 1922 #define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */ 1923 1924 #define NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID (0x55U) 1925 1926 typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_SET_ILLUM_PARAMS; 1927 1928 /* 1929 * NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION 1930 * 1931 * This command can be used by clients to retrieve the version of the entire 1932 * InfoROM image. 1933 * 1934 * version 1935 * This parameter returns the version of the InfoROM image as a NULL- 1936 * terminated character string of the form "XXXX.XXXX.XX.XX" where each 1937 * 'X' is an integer character. 1938 * 1939 * Possible status return values are: 1940 * NVOS_STATUS_SUCCES 1941 * NV_ERR_INSUFFICIENT_RESOURCES 1942 * NV_ERR_NOT_SUPPORTED 1943 * NV_ERR_INVALID_DATA 1944 */ 1945 #define NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION (0x20800156U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID" */ 1946 1947 #define NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN 16U 1948 1949 #define NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID (0x56U) 1950 1951 typedef struct NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS { 1952 NvU8 version[NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN]; 1953 } NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS; 1954 1955 /* 1956 * NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT 1957 * 1958 * This command returns whether or not ECC is supported via the InfoROM. 1959 * 1960 * Possible status return values are: 1961 * NV_OK 1962 * NV_ERR_NOT_SUPPORTED 1963 */ 1964 #define NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT (0x20800157U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x57" */ 1965 1966 /* 1967 * NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION 1968 * 1969 * This structure contains information about a single physical bridge. 1970 * 1971 * fwVersion 1972 * This field specifies Firmware Version of the bridge stored in 1973 * bridge EEPROM. 1974 * oemVersion 1975 * This field specifies Oem Version of the firmware stored in 1976 * bridge EEPROM. 1977 * siliconRevision 1978 * This field contains the silicon revision of the bridge hardware. 1979 * It is set by the chip manufacturer. 1980 * hwbcResourceType 1981 * This field specifies the hardware broadcast resource type. 1982 * Value denotes the kind of bridge - PLX or BR04 1983 * 1984 */ 1985 1986 typedef struct NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS { 1987 NvU32 fwVersion; 1988 NvU8 oemVersion; 1989 NvU8 siliconRevision; 1990 NvU8 hwbcResourceType; 1991 } NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS; 1992 1993 /* 1994 * NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO 1995 * 1996 * This command returns physical bridge information in the system. 1997 * Information consists of bridgeCount and a list of bridgeId's. 1998 * The bridge Id's are used by NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION 1999 * to get firmware version, oem version and silicon revision info. 2000 * 2001 * bridgeCount 2002 * This field specifies the number of physical brides present 2003 * in the system. 2004 * hPhysicalBridges 2005 * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. 2006 * In this array, the bridge Id's are stored. 2007 * bridgeList 2008 * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. 2009 * In this array, the bridge version details are stored. 2010 * 2011 * Possible status values returned are: 2012 * NV_OK 2013 * NV_ERR_INVALID_ARGUMENT 2014 * NV_ERR_NOT_SUPPORTED 2015 */ 2016 #define NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO (0x2080015aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID" */ 2017 2018 #define NV2080_CTRL_MAX_PHYSICAL_BRIDGE (100U) 2019 #define NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID (0x5AU) 2020 2021 typedef struct NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS { 2022 NvU8 bridgeCount; 2023 NvHandle hPhysicalBridges[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; 2024 NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; 2025 } NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS; 2026 2027 /* 2028 * NV2080_CTRL_GPU_BRIDGE_VERSION 2029 * 2030 * This structure contains information about a single physical bridge. 2031 * 2032 * bus 2033 * This field specifies the bus id of the bridge. 2034 * device 2035 * This field specifies the device id of the bridge. 2036 * func 2037 * This field specifies the function id of the bridge. 2038 * oemVersion 2039 * This field specifies Oem Version of the firmware stored in 2040 * bridge EEPROM. 2041 * siliconRevision 2042 * This field contains the silicon revision of the bridge hardware. 2043 * It is set by the chip manufacturer. 2044 * hwbcResourceType 2045 * This field specifies the hardware broadcast resource type. 2046 * Value denotes the kind of bridge - PLX or BR04 2047 * domain 2048 * This field specifies the respective domain of the PCI device. 2049 * fwVersion 2050 * This field specifies Firmware Version of the bridge stored in 2051 * bridge EEPROM. 2052 * 2053 * If (fwVersion, oemVersion, siliconRevision) == 0, it would mean that RM 2054 * was unable to fetch the value from the bridge device. 2055 * 2056 */ 2057 2058 typedef struct NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS { 2059 NvU8 bus; 2060 NvU8 device; 2061 NvU8 func; 2062 NvU8 oemVersion; 2063 NvU8 siliconRevision; 2064 NvU8 hwbcResourceType; 2065 NvU32 domain; 2066 NvU32 fwVersion; 2067 } NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS; 2068 2069 /* 2070 * NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU 2071 * 2072 * This command returns information about all the upstream bridges of the GPU. 2073 * Information consists of bridge firmware version and its bus topology. 2074 * 2075 * bridgeCount 2076 * This field specifies the number of physical brides present 2077 * in the system. 2078 * physicalBridgeIds 2079 * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. 2080 * In this array, the bridge Ids are stored. 2081 * bridgeList 2082 * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. 2083 * In this array, the bridge version details are stored. 2084 * 2085 * Possible status values returned are: 2086 * NV_OK 2087 * NV_ERR_INVALID_ARGUMENT 2088 * NV_ERR_NOT_SUPPORTED 2089 */ 2090 #define NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU (0x2080015bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID" */ 2091 2092 #define NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID (0x5BU) 2093 2094 typedef struct NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS { 2095 NvU8 bridgeCount; 2096 NvU32 physicalBridgeIds[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; 2097 NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; 2098 } NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS; 2099 2100 /* 2101 * NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS 2102 * 2103 * This command is used to query the status of the HW scrubber. If a scrub is 2104 * in progress then the range which is being scrubbed is also reported back. 2105 * 2106 * scrubberStatus 2107 * Reports the status of the scrubber unit - running/idle. 2108 * 2109 * remainingtimeMs 2110 * If scrubbing is going on, reports the remaining time in milliseconds 2111 * required to finish the scrub. 2112 * 2113 * scrubStartAddr 2114 * This parameter reports the start address of the ongoing scrub if scrub 2115 * is going on, otherwise reports the start addr of the last finished scrub 2116 * 2117 * scrubEndAddr 2118 * This parameter reports the end address of the ongoing scrub if scrub 2119 * is going on, otherwise reports the end addr of the last finished scrub. 2120 * 2121 * Possible status values returned are: 2122 * NV_OK 2123 * NV_ERR_NOT_SUPPORTED 2124 */ 2125 2126 #define NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS (0x2080015fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID" */ 2127 2128 #define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID (0x5FU) 2129 2130 typedef struct NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS { 2131 NvU32 scrubberStatus; 2132 NvU32 remainingTimeMs; 2133 NV_DECLARE_ALIGNED(NvU64 scrubStartAddr, 8); 2134 NV_DECLARE_ALIGNED(NvU64 scrubEndAddr, 8); 2135 } NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS; 2136 2137 /* valid values for scrubber status */ 2138 #define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING (0x00000000U) 2139 #define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE (0x00000001U) 2140 2141 /* 2142 * NV2080_CTRL_CMD_GPU_GET_VPR_CAPS 2143 * 2144 * This command is used to query the VPR capability information for a 2145 * GPU. If VPR is supported, the parameters are filled accordingly. 2146 * The addresses returned are all physical addresses. 2147 * 2148 * minStartAddr 2149 * Returns the minimum start address that can be possible for VPR. 2150 * 2151 * maxEndAddr 2152 * Returns the maximum end address that can be possible for VPR. 2153 * 2154 * Possible status values returned are: 2155 * NV_OK 2156 * NV_ERR_NOT_SUPPORTED 2157 */ 2158 2159 #define NV2080_CTRL_CMD_GPU_GET_VPR_CAPS (0x20800160U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID" */ 2160 2161 #define NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID (0x60U) 2162 2163 typedef struct NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS { 2164 NV_DECLARE_ALIGNED(NvU64 minStartAddr, 8); 2165 NV_DECLARE_ALIGNED(NvU64 maxEndAddr, 8); 2166 } NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS; 2167 2168 2169 2170 /* 2171 * NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR 2172 * 2173 * Communicates to RM to handle GPU Surprise Removal 2174 * Called from client when it receives SR IRP from OS 2175 * Possible status values returned are: 2176 * NVOS_STATUS_SUCCESS 2177 */ 2178 #define NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR (0x20800167U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x67" */ 2179 2180 2181 /* 2182 * NV2080_CTRL_CMD_GPU_GET_PES_INFO 2183 * 2184 * This command provides the PES count and mask of enabled PES for a 2185 * specified GPC. It also returns the TPC to PES mapping information 2186 * for a given GPU. 2187 * 2188 * gpcId[IN] 2189 * This parameter specifies the GPC for which PES information is to be 2190 * retrieved. If the GPC with this ID is not enabled this command will 2191 * return an activePesMask of zero 2192 * 2193 * numPesInGpc[OUT] 2194 * This parameter returns the number of PES in this GPC. 2195 * 2196 * activePesMask[OUT] 2197 * This parameter returns a mask of enabled PESs for the specified GPC. 2198 * Each PES has an ID that is equivalent to the corresponding bit position 2199 * in the mask. 2200 * 2201 * maxTpcPerGpcCount[OUT] 2202 * This parameter returns the max number of TPCs in a GPC. 2203 * 2204 * tpcToPesMap[OUT] 2205 * This array stores the TPC to PES mappings. The value at tpcToPesMap[tpcIndex] 2206 * is the index of the PES it belongs to. 2207 * 2208 * Possible status values returned are: 2209 * NV_OK 2210 * NV_ERR_NOT_SUPPORTED 2211 */ 2212 #define NV2080_CTRL_CMD_GPU_GET_PES_INFO (0x20800168U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID" */ 2213 2214 #define NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT 10U 2215 2216 #define NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID (0x68U) 2217 2218 typedef struct NV2080_CTRL_GPU_GET_PES_INFO_PARAMS { 2219 NvU32 gpcId; 2220 NvU32 numPesInGpc; 2221 NvU32 activePesMask; 2222 NvU32 maxTpcPerGpcCount; 2223 NvU32 tpcToPesMap[NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT]; 2224 } NV2080_CTRL_GPU_GET_PES_INFO_PARAMS; 2225 2226 /* NV2080_CTRL_CMD_GPU_GET_OEM_INFO 2227 * 2228 * If an InfoROM with a valid OEM Object is present, this 2229 * command returns relevant information from the object to the 2230 * caller. 2231 * 2232 * oemInfo 2233 * This array stores information specifically for OEM use 2234 * (e.g. "their own serial number", "lot codes", etc) 2235 * "The byte definition is up to the OEM" 2236 * 2237 * Possible status return values are: 2238 * NV_OK 2239 * NV_ERR_NOT_SUPPORTED 2240 */ 2241 2242 #define NV2080_CTRL_CMD_GPU_GET_OEM_INFO (0x20800169U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID" */ 2243 2244 #define NV2080_GPU_MAX_OEM_INFO_LENGTH (0x000001F8U) 2245 2246 #define NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID (0x69U) 2247 2248 typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS { 2249 NvU8 oemInfo[NV2080_GPU_MAX_OEM_INFO_LENGTH]; 2250 } NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS; 2251 2252 /* 2253 * NV2080_CTRL_CMD_GPU_GET_VPR_INFO 2254 * 2255 * This command is used to query the VPR information for a GPU. 2256 * The following VPR related information can be queried by selecting the queryType: 2257 * 1. The current VPR range. 2258 * 2. The max VPR range ever possible on this GPU. 2259 * 2260 * queryType [in] 2261 * This input parameter is used to select the type of information to query. 2262 * Possible values for this parameter are: 2263 * 1. NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS: Use this to query the 2264 * max VPR range ever possible on this GPU. 2265 * 2. NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE: Use this to query 2266 * the current VPR range on this GPU. 2267 * 2268 * bVprEnabled [out] 2269 * For query type "NV2080_CTRL_GPU_GET_VPR_INFO_CUR_RANGE", this parameter 2270 * returns if VPR is currently enabled or not. 2271 * 2272 * vprStartAddress [out] 2273 * For NV2080_CTRL_GPU_GET_VPR_INFO_CAPS, it returns minimum allowed VPR start address. 2274 * For NV2080_CTRL_GPU_GET_VPR_INFO_RANGE, it returns current VPR start address. 2275 * 2276 * vprEndAddress [out] 2277 * For NV2080_CTRL_GPU_GET_VPR_INFO_CAPS, it returns maximum allowed VPR end address. 2278 * For NV2080_CTRL_GPU_GET_VPR_INFO_RANGE, it returns current VPR end address. 2279 * 2280 * Possible status values returned are: 2281 * NV_OK 2282 * NV_ERR_NOT_SUPPORTED 2283 */ 2284 #define NV2080_CTRL_CMD_GPU_GET_VPR_INFO (0x2080016bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */ 2285 2286 2287 typedef enum NV2080_CTRL_VPR_INFO_QUERY_TYPE { 2288 NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS = 0, 2289 NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE = 1, 2290 } NV2080_CTRL_VPR_INFO_QUERY_TYPE; 2291 2292 #define NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID (0x6BU) 2293 2294 typedef struct NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS { 2295 NV2080_CTRL_VPR_INFO_QUERY_TYPE queryType; 2296 NvBool bIsVprEnabled; 2297 NV_DECLARE_ALIGNED(NvU64 vprStartAddressInBytes, 8); 2298 NV_DECLARE_ALIGNED(NvU64 vprEndAddressInBytes, 8); 2299 } NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS; 2300 2301 /* 2302 * NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY 2303 * 2304 * This command is used to query the encoder capacity of the GPU. 2305 * 2306 * queryType [in] 2307 * This input parameter is used to select the type of information to query. 2308 * Possible values for this parameter are: 2309 * 1. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264: Use this to query the 2310 * H.264 encoding capacity on this GPU. 2311 * 2. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC: Use this to query the 2312 * H.265/HEVC encoding capacity on this GPU. 2313 * 3. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1: Use this to query the 2314 * AV1 encoding capacity on this GPU. 2315 * 2316 * encoderCapacity [out] 2317 * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance 2318 * may be minimal for this GPU and software should fall back to CPU-based encode. 2319 * 2320 * Possible status values returned are: 2321 * NV_OK 2322 * NV_ERR_INVALID_ARGUMENT 2323 */ 2324 2325 #define NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY (0x2080016cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ 2326 2327 typedef enum NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE { 2328 NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = 0, 2329 NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = 1, 2330 NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1 = 2, 2331 } NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE; 2332 2333 #define NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x6CU) 2334 2335 typedef struct NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS { 2336 NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE queryType; 2337 NvU32 encoderCapacity; 2338 } NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS; 2339 2340 /* 2341 * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS 2342 * 2343 * This command is used to retrieve the GPU's count of encoder sessions, 2344 * trailing average FPS and encode latency over all active sessions. 2345 * 2346 * encoderSessionCount 2347 * This field specifies count of all active encoder sessions on this GPU. 2348 * 2349 * averageEncodeFps 2350 * This field specifies the average encode FPS for this GPU. 2351 * 2352 * averageEncodeLatency 2353 * This field specifies the average encode latency in microseconds for this GPU. 2354 * 2355 * Possible status values returned are: 2356 * NV_OK 2357 * NV_ERR_INVALID_ARGUMENT 2358 */ 2359 #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS (0x2080016dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */ 2360 2361 #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x6DU) 2362 2363 typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS { 2364 NvU32 encoderSessionCount; 2365 NvU32 averageEncodeFps; 2366 NvU32 averageEncodeLatency; 2367 } NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS; 2368 2369 #define NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES 0x200U // 512 entries. 2370 2371 /* 2372 * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO 2373 * 2374 * This command returns NVENC software sessions information for the associate GPU. 2375 * Request to retrieve session information use a list of one or more 2376 * NV2080_CTRL_NVENC_SW_SESSION_INFO structures. 2377 * 2378 * sessionInfoTblEntry 2379 * This field specifies the number of entries on the that are filled inside 2380 * sessionInfoTbl. Max value of this field once returned from RM would be 2381 * NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES, 2382 * 2383 * sessionInfoTbl 2384 * This field specifies a pointer in the caller's address space 2385 * to the buffer into which the NVENC session information is to be returned. 2386 * When buffer is NULL, RM assume that client is querying sessions count value 2387 * and return the current encoder session counts in sessionInfoTblEntry field. 2388 * To get actual buffer data, client should allocate sessionInfoTbl of size 2389 * NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES multiplied by the 2390 * size of the NV2080_CTRL_NVENC_SW_SESSION_INFO structure. RM will fill the 2391 * current session data in sessionInfoTbl buffer and then update the 2392 * sessionInfoTblEntry to reflect current session count value. 2393 * 2394 * Possible status values returned are: 2395 * NV_OK 2396 * NV_ERR_NO_MEMORY 2397 * NV_ERR_INVALID_LOCK_STATE 2398 * NV_ERR_INVALID_ARGUMENT 2399 */ 2400 2401 typedef struct NV2080_CTRL_NVENC_SW_SESSION_INFO { 2402 NvU32 processId; 2403 NvU32 subProcessId; 2404 NvU32 sessionId; 2405 NvU32 codecType; 2406 NvU32 hResolution; 2407 NvU32 vResolution; 2408 NvU32 averageEncodeFps; 2409 NvU32 averageEncodeLatency; 2410 } NV2080_CTRL_NVENC_SW_SESSION_INFO; 2411 2412 #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x6EU) 2413 2414 typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS { 2415 NvU32 sessionInfoTblEntry; 2416 NV_DECLARE_ALIGNED(NvP64 sessionInfoTbl, 8); 2417 } NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS; 2418 2419 #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO (0x2080016eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */ 2420 2421 /* 2422 * NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR 2423 * 2424 * The command sets fabric base address which represents top N bits of a 2425 * peer memory address. These N bits will be used to index NvSwitch routing 2426 * tables to forward peer memory accesses to associated GPUs. 2427 * 2428 * The command is available to clients with administrator privileges only. 2429 * An attempt to use this command by a client without administrator privileged 2430 * results in the return of NV_ERR_INSUFFICIENT_PERMISSIONS status. 2431 * 2432 * The command allows to set fabricAddr once in a lifetime of a GPU. A GPU must 2433 * be destroyed in order to re-assign a different fabricAddr. An attempt to 2434 * re-assign address without destroying a GPU would result in the return of 2435 * NV_ERR_STATE_IN_USE status. 2436 * 2437 * fabricBaseAddr[IN] 2438 * - An address with at least 32GB alignment. 2439 * 2440 * Possible status values returned are: 2441 * NV_OK 2442 * NV_ERR_INVALID_ARGUMENT 2443 * NV_ERR_INSUFFICIENT_PERMISSIONS 2444 * NV_ERR_NOT_SUPPORTED 2445 * NV_ERR_STATE_IN_USE 2446 */ 2447 2448 #define NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID (0x6FU) 2449 2450 typedef struct NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS { 2451 NV_DECLARE_ALIGNED(NvU64 fabricBaseAddr, 8); 2452 } NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS; 2453 2454 #define NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR (0x2080016fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */ 2455 2456 /* 2457 * NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT 2458 * 2459 * The command will trigger the specified interrupt on the host from a guest. 2460 * 2461 * handle[IN] 2462 * - An opaque handle that will be passed in along with the interrupt 2463 * 2464 * Possible status values returned are: 2465 * NV_OK 2466 * NV_ERR_INVALID_ARGUMENT 2467 * NV_ERR_NOT_SUPPORTED 2468 */ 2469 2470 #define NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID (0x72U) 2471 2472 typedef struct NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS { 2473 NvU32 handle; 2474 } NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS; 2475 2476 #define NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT (0x20800172U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID" */ 2477 2478 /* 2479 * NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS 2480 * 2481 * This control call is to query the status of gpu function registers 2482 * 2483 * statusMask[IN] 2484 * - Input mask of required status registers 2485 * xusbData[OUT] 2486 * - data from querying XUSB status register 2487 * ppcData[OUT] 2488 * - data from querying PPC status register 2489 * 2490 * Possible status values returned are: 2491 * NV_OK 2492 * NV_ERR_INVALID_ARGUMENT 2493 * NV_ERR_NOT_SUPPORTED 2494 */ 2495 2496 2497 2498 #define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID (0x73U) 2499 2500 typedef struct NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS { 2501 NvU32 statusMask; 2502 NvU32 xusbData; 2503 NvU32 ppcData; 2504 } NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS; 2505 2506 #define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS (0x20800173U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID" */ 2507 2508 /* 2509 * NV2080_CTRL_GPU_PARTITION_SPAN 2510 * 2511 * This struct represents the span of a memory partition, which represents the 2512 * slices a given partition occupies (or may occupy) within a fixed range which 2513 * is defined per-chip. A partition containing more resources will cover more 2514 * GPU slices and therefore cover a larger span. 2515 * 2516 * lo 2517 * - The starting unit of this span, inclusive 2518 * 2519 * hi 2520 * - The ending unit of this span, inclusive 2521 * 2522 */ 2523 typedef struct NV2080_CTRL_GPU_PARTITION_SPAN { 2524 NV_DECLARE_ALIGNED(NvU64 lo, 8); 2525 NV_DECLARE_ALIGNED(NvU64 hi, 8); 2526 } NV2080_CTRL_GPU_PARTITION_SPAN; 2527 2528 #define NV_GI_UUID_LEN 16U 2529 2530 /* 2531 * NV2080_CTRL_GPU_SET_PARTITION_INFO 2532 * 2533 * This command partitions a GPU into different SMC-Memory partitions. 2534 * The command will configure HW partition table to create work and memory 2535 * isolation. 2536 * 2537 * The command is available to clients with administrator privileges only. 2538 * An attempt to use this command by a client without administrator privileged 2539 * results in the return of NV_ERR_INSUFFICIENT_PERMISSIONS status. 2540 * 2541 * The command allows partitioning an invalid partition only. An attempt to 2542 * re-partition a valid partition will resule in NV_ERR_STATE_IN_USE. 2543 * Repartitioning can be done only if a partition has been destroyed/invalidated 2544 * before re-partitioning. 2545 * 2546 * swizzId[IN/OUT] 2547 * - PartitionID associated with a newly created partition. Input in case 2548 * of partition invalidation. 2549 * 2550 * uuid[OUT] 2551 * - Uuid of a newly created partition. 2552 * 2553 * partitionFlag[IN] 2554 * - Flags to determine if GPU is requested to be partitioned in FULL, 2555 * HALF, QUARTER or ONE_EIGHTHED and whether the partition requires 2556 * any additional resources. 2557 * When flags include NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 2558 * partition will be created with at least one video decode, jpeg and 2559 * optical flow engines. This flag is valid only for partitions with 2560 * a single GPC. 2561 * 2562 * bValid[IN] 2563 * - NV_TRUE if creating a partition. NV_FALSE if destroying a partition. 2564 * 2565 * placement[IN] 2566 * - Optional placement span to allocate the partition into. Valid 2567 * placements are returned from NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY. 2568 * The partition flag NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN must 2569 * be set for this parameter to be used. If the flag is set and the given 2570 * placement is not valid, an error will be returned. 2571 * 2572 * Possible status values returned are: 2573 * NV_OK 2574 * NV_ERR_INVALID_ARGUMENT 2575 * NV_ERR_INSUFFICIENT_PERMISSIONS 2576 * NV_ERR_NOT_SUPPORTED 2577 * NV_ERR_STATE_IN_USE 2578 */ 2579 typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO { 2580 NvU32 swizzId; 2581 NvU8 uuid[NV_GI_UUID_LEN]; 2582 NvU32 partitionFlag; 2583 NvBool bValid; 2584 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN placement, 8); 2585 } NV2080_CTRL_GPU_SET_PARTITION_INFO; 2586 2587 #define PARTITIONID_INVALID NV2080_CTRL_GPU_PARTITION_ID_INVALID 2588 #define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFFU 2589 #define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008U 2590 #define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009U 2591 #define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008U 2592 #define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000cU 2593 #define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008U 2594 2595 #define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE 1:0 2596 #define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000U 2597 #define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001U 2598 #define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002U 2599 #define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003U 2600 #define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4U 2601 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE 4:2 2602 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000U 2603 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001U 2604 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002U 2605 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003U 2606 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER 0x00000004U 2607 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000005U 2608 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 6U 2609 2610 2611 #define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 20U 2612 #define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30 2613 #define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U 2614 #define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U 2615 #define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN 31:31 2616 #define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0U 2617 #define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1U 2618 2619 // TODO XXX Bug 2657907 Remove these once clients update 2620 #define NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _FULL) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _FULL)) 2621 #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _HALF)) 2622 #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_HALF)) 2623 #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _QUARTER)) 2624 #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_QUARTER)) 2625 #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _EIGHTH) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _EIGHTH)) 2626 2627 #define NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID (0x74U) 2628 2629 typedef struct NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS { 2630 NvU32 partitionCount; 2631 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_SET_PARTITION_INFO partitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); 2632 } NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS; 2633 2634 #define NV2080_CTRL_CMD_GPU_SET_PARTITIONS (0x20800174U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID" */ 2635 2636 /* 2637 * NV2080_CTRL_GPU_GET_PARTITION_INFO 2638 * 2639 * This command gets the partition information for requested partitions. 2640 * If GPU is not partitioned, the control call will return NV_ERR_NOT_SUPPORTED. 2641 * 2642 * The command will can return global partition information as well as single 2643 * partition information if global flag is not set. 2644 * In bare-metal user-mode can request all partition info while in virtualization 2645 * plugin should make an RPC with swizzId which is assigned to the requesting 2646 * VM. 2647 * 2648 * swizzId[IN] 2649 * - HW Partition ID associated with the requested partition. 2650 * 2651 * partitionFlag[OUT] 2652 * - partitionFlag that was provided during partition creation. 2653 * 2654 * grEngCount[OUT] 2655 * - Number of SMC engines/GR engines allocated in partition 2656 * GrIDs in a partition will always start from 0 and end at grEngCount-1 2657 * 2658 * veidCount[OUT] 2659 * - VEID Count assigned to a partition. These will be divided across 2660 * SMC engines once CONFIGURE_PARTITION call has been made. The current 2661 * algorithm is to assign veidPerGpc * gpcCountPerSmc to a SMC engine. 2662 * 2663 * smCount[OUT] 2664 * - SMs assigned to a partition. 2665 * 2666 * ceCount[OUT] 2667 * - Copy Engines assigned to a partition. 2668 * 2669 * nvEncCount[OUT] 2670 * - NvEnc Engines assigned to a partition. 2671 * 2672 * nvDecCount[OUT] 2673 * - NvDec Engines assigned to a partition. 2674 * 2675 * nvJpgCount[OUT] 2676 * - NvJpg Engines assigned to a partition. 2677 * 2678 * gpcCount[OUT] 2679 * - Max GPCs assigned to a partition, including the GfxCapable ones. 2680 * 2681 * virtualGpcCount[OUT] 2682 * - Virtualized GPC count assigned to partition 2683 * 2684 * gfxGpcCount[OUT] 2685 * - Max GFX GPCs assigned to a partition. This is a subset of the GPCs incuded in gpcCount. 2686 * 2687 * gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] 2688 * - GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX 2689 * 2690 * virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] 2691 * - Virtualized GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX 2692 * 2693 * gfxGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] 2694 * - GFX GPC count associated with every valid SMC/Gr. This is a subset of the GPCs included in gfxGpcCount 2695 * 2696 * veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] 2697 * - VEID count associated with every valid SMC. VEIDs within this SMC 2698 * will start from 0 and go till veidCount[SMC_ID] - 1. 2699 * 2700 * span[OUT] 2701 * - The span covered by this partition 2702 * 2703 * bValid[OUT] 2704 * - NV_TRUE if partition is valid else NV_FALSE. 2705 * 2706 * bPartitionError[OUT] 2707 * - NV_TRUE if partition had poison error which requires drain and reset 2708 * else NV_FALSE. 2709 * 2710 * validCTSIdMask[OUT] 2711 * - Mask of CTS IDs usable by this partition, not reflecting current allocations 2712 * 2713 * validGfxCTSIdMask[OUT] 2714 * - Mask of CTS IDs that contain Gfx capable Grs usable by this partition, not reflecting current allocations 2715 * 2716 * Possible status values returned are: 2717 * NV_OK 2718 * NV_ERR_INVALID_ARGUMENT 2719 * NV_ERR_INSUFFICIENT_PERMISSIONS 2720 * NV_ERR_NOT_SUPPORTED 2721 */ 2722 typedef struct NV2080_CTRL_GPU_GET_PARTITION_INFO { 2723 NvU32 swizzId; 2724 NvU32 partitionFlag; 2725 NvU32 grEngCount; 2726 NvU32 veidCount; 2727 NvU32 smCount; 2728 NvU32 ceCount; 2729 NvU32 nvEncCount; 2730 NvU32 nvDecCount; 2731 NvU32 nvJpgCount; 2732 NvU32 nvOfaCount; 2733 NvU32 gpcCount; 2734 NvU32 virtualGpcCount; 2735 NvU32 gfxGpcCount; 2736 NvU32 gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; 2737 NvU32 virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; 2738 NvU32 gfxGpcPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; 2739 NvU32 veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; 2740 NV_DECLARE_ALIGNED(NvU64 memSize, 8); 2741 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN span, 8); 2742 NvBool bValid; 2743 NvBool bPartitionError; 2744 NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); 2745 NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8); 2746 } NV2080_CTRL_GPU_GET_PARTITION_INFO; 2747 2748 /* 2749 * NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS 2750 * 2751 * queryPartitionInfo[IN] 2752 * - Max sized array of NV2080_CTRL_GPU_GET_PARTITION_INFO to get partition 2753 * Info 2754 * 2755 * bGetAllPartitionInfo[In] 2756 * - Flag to get all partitions info. Only root client will receive all 2757 * partition's info. Non-Root clients should not use this flag 2758 * 2759 * validPartitionCount[Out] 2760 * - Valid partition count which has been filled by RM as part of the call 2761 * 2762 */ 2763 #define NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID (0x75U) 2764 2765 typedef struct NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS { 2766 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_GET_PARTITION_INFO queryPartitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); 2767 NvU32 validPartitionCount; 2768 NvBool bGetAllPartitionInfo; 2769 } NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS; 2770 2771 #define NV2080_CTRL_CMD_GPU_GET_PARTITIONS (0x20800175U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID" */ 2772 2773 /* 2774 * NV2080_CTRL_GPU_CONFIGURE_PARTITION 2775 * 2776 * This command configures a partition by associating GPCs with SMC Engines 2777 * available in that partition. Engines which are to have GPCs assigned to them 2778 * shall not already have any GPCs assigned to them. It is not valid to both 2779 * assign GPCs and remove GPCs as part of a single call to this function. 2780 * 2781 * swizzId[IN] 2782 * - PartitionID for configuring partition. If partition has a valid 2783 * context created, then configuration is not allowed. 2784 * 2785 * gpcCountPerSmcEng[IN] 2786 * - Number of GPCs expected to be configured per SMC. Supported 2787 * configurations are 0, 1, 2, 4 or 8. "0" means a particular SMC 2788 * engine will be disabled with no GPC connected to it. 2789 * 2790 * updateSmcEngMask[IN] 2791 * - Mask tracking valid entries of gpcCountPerSmcEng. A value of 2792 * 0 in bit index i indicates that engine i will keep its current 2793 * configuration. 2794 * 2795 * bUseAllGPCs[IN] 2796 * - Flag specifying alternate configuration mode, indicating that in 2797 * swizzid 0 only, all non-floorswept GPCs should be connected to the 2798 * engine indicated by a raised bit in updateSmcEngMask. Only a single 2799 * engine may be targeted by this operation. The gpcCountPerSmcEng 2800 * parameter should not be used with this flag. 2801 * 2802 * Possible status values returned are: 2803 * NV_OK 2804 * NV_ERR_INVALID_ARGUMENT 2805 * NV_ERR_INSUFFICIENT_PERMISSIONS 2806 * NV_ERR_INSUFFICIENT_RESOURCES 2807 * NV_ERR_NOT_SUPPORTED 2808 * NV_ERR_STATE_IN_USE 2809 */ 2810 #define NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION (0x20800176U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID" */ 2811 2812 #define NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID (0x76U) 2813 2814 typedef struct NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS { 2815 NvU32 swizzId; 2816 NvU32 gpcCountPerSmcEng[NV2080_CTRL_GPU_MAX_SMC_IDS]; 2817 NvU32 updateSmcEngMask; 2818 NvBool bUseAllGPCs; 2819 } NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS; 2820 2821 2822 /* 2823 * NV2080_CTRL_GPU_FAULT_PACKET 2824 * 2825 * This struct represents a GMMU fault packet. 2826 * 2827 */ 2828 #define NV2080_CTRL_GPU_FAULT_PACKET_SIZE 32U 2829 typedef struct NV2080_CTRL_GPU_FAULT_PACKET { 2830 NvU8 data[NV2080_CTRL_GPU_FAULT_PACKET_SIZE]; 2831 } NV2080_CTRL_GPU_FAULT_PACKET; 2832 2833 /* 2834 * NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT 2835 * 2836 * This command reports a nonreplayable fault packet to RM. 2837 * It is only used by UVM. 2838 * 2839 * pFaultPacket[IN] 2840 * - A fault packet that will be later cast to GMMU_FAULT_PACKET *. 2841 * 2842 * Possible status values returned are: 2843 * NV_OK 2844 * NV_ERR_INVALID_ARGUMENT 2845 */ 2846 #define NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT (0x20800177U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID" */ 2847 2848 #define NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID (0x77U) 2849 2850 typedef struct NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS { 2851 NV2080_CTRL_GPU_FAULT_PACKET faultPacket; 2852 } NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS; 2853 2854 /* 2855 * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU 2856 * 2857 * This command is similar to NV2080_CTRL_CMD_GPU_EXEC_REG_OPS, except it is used 2858 * by the VGPU plugin client only. This command provides access to the subset of 2859 * privileged registers. 2860 * 2861 * See confluence page "vGPU UMED Security" for details. 2862 * 2863 */ 2864 #define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID" */ 2865 2866 #define NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID (0x78U) 2867 2868 typedef NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS; 2869 2870 /* 2871 * NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE 2872 * 2873 * This command returns the runlist pri base of the specified engine(s). 2874 * 2875 * engineList 2876 * Input array. 2877 * This array specifies the engines being queried for information. 2878 * The list of engines supported by a chip can be fetched using the 2879 * NV2080_CTRL_CMD_GPU_GET_ENGINES/GET_ENGINES_V2 ctrl call. 2880 * 2881 * runlistPriBase 2882 * Output array. 2883 * Returns the runlist pri base for the specified engines 2884 * Else, will return _NULL when the input is a NV2080_ENGINE_TYPE_NULL 2885 * and will return _ERROR when the control call fails due to an invalid argument 2886 * 2887 * Possible status values returned are: 2888 * NV_OK 2889 * NV_ERR_INVALID_ARGUMENT 2890 * NV_ERR_NOT_SUPPORTED 2891 */ 2892 #define NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE (0x20800179U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID" */ 2893 2894 #define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID (0x79U) 2895 2896 typedef struct NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS { 2897 NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; 2898 NvU32 runlistPriBase[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; 2899 } NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS; 2900 2901 #define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL (0xFFFFFFFFU) 2902 #define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR (0xFFFFFFFBU) 2903 2904 /* 2905 * NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID 2906 * 2907 * This command returns the host hardware defined engine ID of the specified engine(s). 2908 * 2909 * engineList 2910 * Input array. 2911 * This array specifies the engines being queried for information. 2912 * The list of engines supported by a chip can be fetched using the 2913 * NV2080_CTRL_CMD_GPU_GET_ENGINES/GET_ENGINES_V2 ctrl call. 2914 * 2915 * hwEngineID 2916 * Output array. 2917 * Returns the host hardware engine ID(s) for the specified engines 2918 * Else, will return _NULL when the input is a NV2080_ENGINE_TYPE_NULL 2919 * and will return _ERROR when the control call fails due to an invalid argument 2920 * 2921 * Possible status values returned are: 2922 * NV_OK 2923 * NV_ERR_INVALID_ARGUMENT 2924 * NV_ERR_NOT_SUPPORTED 2925 */ 2926 #define NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID (0x2080017aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID" */ 2927 2928 #define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID (0x7AU) 2929 2930 typedef struct NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS { 2931 NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; 2932 NvU32 hwEngineID[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; 2933 } NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS; 2934 2935 #define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL (0xFFFFFFFFU) 2936 #define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR (0xFFFFFFFBU) 2937 2938 /* 2939 * NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS 2940 * 2941 * This command is used to retrieve the GPU's count of FBC sessions, 2942 * average FBC calls and FBC latency over all active sessions. 2943 * 2944 * sessionCount 2945 * This field specifies count of all active fbc sessions on this GPU. 2946 * 2947 * averageFPS 2948 * This field specifies the average frames captured. 2949 * 2950 * averageLatency 2951 * This field specifies the average FBC latency in microseconds. 2952 * 2953 * Possible status values returned are : 2954 * NV_OK 2955 * NV_ERR_INVALID_ARGUMENT 2956 */ 2957 #define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS (0x2080017bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */ 2958 2959 #define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x7BU) 2960 2961 typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS { 2962 NvU32 sessionCount; 2963 NvU32 averageFPS; 2964 NvU32 averageLatency; 2965 } NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS; 2966 2967 /* 2968 * NV2080_CTRL_NVFBC_SW_SESSION_INFO 2969 * 2970 * processId[OUT] 2971 * Process id of the process owning the NvFBC session. 2972 * On VGX host, this will specify the vGPU plugin process id. 2973 * subProcessId[OUT] 2974 * Process id of the process owning the NvFBC session if the 2975 * session is on VGX guest, else the value is zero. 2976 * vgpuInstanceId[OUT] 2977 * vGPU on which the process owning the NvFBC session 2978 * is running if session is on VGX guest, else 2979 * the value is zero. 2980 * sessionId[OUT] 2981 * Unique session id of the NvFBC session. 2982 * sessionType[OUT] 2983 * Type of NvFBC session. 2984 * displayOrdinal[OUT] 2985 * Display identifier associated with the NvFBC session. 2986 * sessionFlags[OUT] 2987 * One or more of NV2080_CTRL_NVFBC_SESSION_FLAG_xxx. 2988 * hMaxResolution[OUT] 2989 * Max horizontal resolution supported by the NvFBC session. 2990 * vMaxResolution[OUT] 2991 * Max vertical resolution supported by the NvFBC session. 2992 * hResolution[OUT] 2993 * Horizontal resolution requested by caller in grab call. 2994 * vResolution[OUT] 2995 * Vertical resolution requested by caller in grab call. 2996 * averageFPS[OUT] 2997 * Average no. of frames captured per second. 2998 * averageLatency[OUT] 2999 * Average frame capture latency in microseconds. 3000 */ 3001 3002 #define NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED 0x00000001U 3003 #define NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED 0x00000002U 3004 #define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT 0x00000004U 3005 #define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE 0x00000008U 3006 #define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT 0x00000010U 3007 3008 typedef struct NV2080_CTRL_NVFBC_SW_SESSION_INFO { 3009 NvU32 processId; 3010 NvU32 subProcessId; 3011 NvU32 vgpuInstanceId; 3012 NvU32 sessionId; 3013 NvU32 sessionType; 3014 NvU32 displayOrdinal; 3015 NvU32 sessionFlags; 3016 NvU32 hMaxResolution; 3017 NvU32 vMaxResolution; 3018 NvU32 hResolution; 3019 NvU32 vResolution; 3020 NvU32 averageFPS; 3021 NvU32 averageLatency; 3022 } NV2080_CTRL_NVFBC_SW_SESSION_INFO; 3023 3024 /* 3025 * NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO 3026 * 3027 * This command returns NVFBC software sessions information for the associate GPU. 3028 * 3029 * sessionInfoCount 3030 * This field specifies the number of entries that are filled inside 3031 * sessionInfoTbl. Max value of this field once returned from RM would be 3032 * NV2080_GPU_NVFBC_MAX_COUNT. 3033 * 3034 * sessionInfoTbl 3035 * This field specifies the array in which the NVFBC session information is to 3036 * be returned. RM will fill the current session data in sessionInfoTbl array 3037 * and then update the sessionInfoCount to reflect current session count value. 3038 * 3039 * Possible status values returned are: 3040 * NV_OK 3041 * NV_ERR_NO_MEMORY 3042 * NV_ERR_INVALID_LOCK_STATE 3043 * NV_ERR_INVALID_ARGUMENT 3044 */ 3045 3046 #define NV2080_GPU_NVFBC_MAX_SESSION_COUNT 256U 3047 3048 #define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x7CU) 3049 3050 typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS { 3051 NvU32 sessionInfoCount; 3052 NV2080_CTRL_NVFBC_SW_SESSION_INFO sessionInfoTbl[NV2080_GPU_NVFBC_MAX_SESSION_COUNT]; 3053 } NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS; 3054 3055 #define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO (0x2080017cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */ 3056 3057 3058 3059 /* 3060 * NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE 3061 * 3062 * This command returns the VMMU page size 3063 * 3064 * vmmuSegmentSize 3065 * Output parameter. 3066 * Returns the VMMU segment size (in bytes) 3067 * 3068 * Possible status values returned are: 3069 * NV_OK 3070 * NV_ERR_NOT_SUPPORTED 3071 */ 3072 #define NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE (0x2080017eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID" */ 3073 3074 #define NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID (0x7EU) 3075 3076 typedef struct NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS { 3077 NV_DECLARE_ALIGNED(NvU64 vmmuSegmentSize, 8); 3078 } NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS; 3079 3080 #define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB 0x02000000U 3081 #define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB 0x04000000U 3082 #define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB 0x08000000U 3083 #define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB 0x10000000U 3084 #define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB 0x20000000U 3085 3086 3087 3088 /* 3089 * NV2080_CTRL_GPU_GET_PARTITION_CAPACITY 3090 * 3091 * This command returns the count of partitions of given size (represented by 3092 * NV2080_CTRL_GPU_PARTITION_FLAG_*) which can be requested via 3093 * NV2080_CTRL_GPU_SET_PARTITIONS ctrl call. 3094 * Note that this API does not "reserve" any partitions, and there is no 3095 * guarantee that the reported count of available partitions of a given size 3096 * will remain consistent following creation of partitions of different size 3097 * through NV2080_CTRL_GPU_SET_PARTITIONS. 3098 * Note that this API is unsupported if SMC is feature-disabled. 3099 * 3100 * partitionFlag[IN] 3101 * - Partition flag indicating size of requested partitions 3102 * 3103 * partitionCount[OUT] 3104 * - Available number of partitions of the given size which can currently be created. 3105 * 3106 * availableSpans[OUT] 3107 * - For each partition able to be created of the specified size, the span 3108 * it could occupy. 3109 * 3110 * availableSpansCount[OUT] 3111 * - Number of valid entries in availableSpans. 3112 * 3113 * totalPartitionCount[OUT] 3114 * - Total number of partitions of the given size which can be created. 3115 * 3116 * totalSpans[OUT] 3117 * - List of spans which can possibly be occupied by partitions of the 3118 * given type. 3119 * 3120 * totalSpansCount[OUT] 3121 * - Number of valid entries in totalSpans. 3122 * 3123 * bStaticInfo[IN] 3124 * - Flag indicating that client requests only the information from 3125 * totalPartitionCount and totalSpans. 3126 * 3127 * Possible status values returned are: 3128 * NV_OK 3129 * NV_ERR_INVALID_ARGUMENT 3130 * NV_ERR_NOT_SUPPORTED 3131 */ 3132 #define NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY (0x20800181U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID" */ 3133 3134 #define NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID (0x81U) 3135 3136 typedef struct NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS { 3137 NvU32 partitionFlag; 3138 NvU32 partitionCount; 3139 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN availableSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); 3140 NvU32 availableSpansCount; 3141 NvU32 totalPartitionCount; 3142 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN totalSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); 3143 NvU32 totalSpansCount; 3144 NvBool bStaticInfo; 3145 } NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS; 3146 3147 /* 3148 * NV2080_CTRL_CMD_GPU_GET_CACHED_INFO 3149 * 3150 * This command returns cached(SW only) gpu information for the associated GPU. 3151 * Requests to retrieve gpu information use a list of one or more NV2080_CTRL_GPU_INFO 3152 * structures. 3153 * The gpuInfoList is aligned with NV2080_CTRL_GPU_GET_INFO_V2_PARAMS for security concern 3154 * 3155 * gpuInfoListSize 3156 * This field specifies the number of entries on the caller's 3157 * gpuInfoList. 3158 * gpuInfoList 3159 * This field specifies a pointer in the caller's address space 3160 * to the buffer into which the gpu information is to be returned. 3161 * This buffer must be at least as big as gpuInfoListSize multiplied 3162 * by the size of the NV2080_CTRL_GPU_INFO structure. 3163 * 3164 * Possible status values returned are: 3165 * NV_OK 3166 * NV_ERR_INVALID_PARAM_STRUCT 3167 * NV_ERR_INVALID_ARGUMENT 3168 * NV_ERR_NOT_SUPPORTED 3169 * NV_ERR_OPERATING_SYSTEM 3170 */ 3171 #define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID" */ 3172 3173 #define NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID (0x82U) 3174 3175 typedef NV2080_CTRL_GPU_GET_INFO_V2_PARAMS NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS; 3176 3177 /* 3178 * NV2080_CTRL_GPU_SET_PARTITIONING_MODE 3179 * 3180 * This command configures this GPU to control global mode for partitioning. 3181 * This command may not be sent to a GPU with any active partitions. 3182 * This command may be used to set the following modes: 3183 * 3184 * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING 3185 * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY 3186 * This is the default mode. While this GPU is in this mode, no partitions 3187 * will be allowed to be created via SET_PARTITIONS - a client must set one 3188 * of the below modes prior to partitioning the GPU. When a client sets a 3189 * GPU into this mode, any performance changes resulting from partitions 3190 * made while in either of the below modes will be cleared. A 3191 * physical-function-level reset is required after setting this mode. 3192 * 3193 * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF 3194 * In this mode, when the GPU is partitioned, each partition will have the 3195 * maximum possible performance which can be evenly distributed among all 3196 * partitions. The total performance of the GPU, taking into account all 3197 * partitions created in this mode, may be less than that of a GPU running 3198 * in legacy non-SMC mode. Partitions created while in this mode require a 3199 * physical-function-level reset before the partitioning may take full 3200 * effect. Destroying all partitions while in this mode may be 3201 * insufficient to restore full performance to the GPU - only by setting 3202 * the mode to _LEGACY can this be achieved. A physical-function-level 3203 * reset is NOT required after setting this mode. 3204 * 3205 * NV2080_CTRL_GPU_SET_PARTIITONING_MODE_REPARTITIONING_FAST_RECONFIG 3206 * By setting this mode, the performance of the GPU will be restricted such 3207 * that all partitions will have a consistent fraction of the total 3208 * available performance, which may be less than the maximum possible 3209 * performance available to each partition. Creating or destroying 3210 * partitions on this GPU while in this mode will not require a 3211 * physical-function-level reset, and will not affect other active 3212 * partitions. Destroying all partitions while in this mode may be 3213 * insufficient to restore full performance to the GPU - only by setting 3214 * the mode to _LEGACY can this be achieved. A physical-function-level 3215 * reset is required after setting this mode. 3216 * 3217 * Parameters: 3218 * partitioningMode[IN] 3219 * - Partitioning Mode to set for this GPU. 3220 * 3221 * Possible status values returned are: 3222 * NV_OK 3223 * NV_ERR_INVALID_STATE 3224 * NV_ERR_INVALID_ARGUMENT 3225 * NV_ERR_NOT_SUPPORTED 3226 */ 3227 #define NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE (0x20800183U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */ 3228 3229 #define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING 1:0 3230 #define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY 0U 3231 #define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF 1U 3232 #define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG 2U 3233 3234 #define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0x83U) 3235 3236 typedef struct NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS { 3237 NvU32 partitioningMode; 3238 } NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS; 3239 3240 3241 3242 /* NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO 3243 * 3244 * This structure describes resources available in a partition requested of a 3245 * given type. 3246 * 3247 * [OUT] partitionFlag 3248 * - Flags to specify in NV2080_CTRL_CMD_GPU_SET_PARTITIONS to request this 3249 * partition 3250 * 3251 * [OUT] grCount 3252 * - Total Number of SMC engines/GR engines (including GFX capable ones in this parition) 3253 * 3254 * [OUT] gfxGrCount 3255 * - Number of SMC engines/GR engines capable of GFX. This is a subset of the engines included in grCount 3256 * 3257 * [OUT] gpcCount 3258 * - Number of GPCs in this partition, including the GFX Capable ones. 3259 * 3260 * [OUT] virtualGpcCount 3261 * - Number of virtualized GPCs in this partition, including the GFX Capable ones. 3262 * 3263 * [OUT] gfxGpcCount 3264 * - Number of GFX Capable GPCs in this partition. This is a subset of the GPCs included in gpcCount. 3265 * 3266 * [OUT] veidCount 3267 * - Number of VEIDS in this partition 3268 * 3269 * [OUT] smCount 3270 * - Number of SMs in this partition 3271 * 3272 * [OUT] ceCount 3273 * - Copy Engines in this partition 3274 * 3275 * [OUT] nvEncCount 3276 * - Encoder Engines in this partition 3277 * 3278 * [OUT] nvDecCount 3279 * - Decoder Engines in this partition 3280 * 3281 * [OUT] nvJpgCount 3282 * - Jpg Engines in this partition 3283 * 3284 * [OUT] nvOfaCount 3285 * - Ofa engines in this partition 3286 * [OUT] memorySize 3287 * - Total available memory within this partition 3288 */ 3289 typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO { 3290 NvU32 partitionFlag; 3291 NvU32 grCount; 3292 NvU32 gfxGrCount; 3293 NvU32 gpcCount; 3294 NvU32 virtualGpcCount; 3295 NvU32 gfxGpcCount; 3296 NvU32 veidCount; 3297 NvU32 smCount; 3298 NvU32 ceCount; 3299 NvU32 nvEncCount; 3300 NvU32 nvDecCount; 3301 NvU32 nvJpgCount; 3302 NvU32 nvOfaCount; 3303 NV_DECLARE_ALIGNED(NvU64 memorySize, 8); 3304 } NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO; 3305 3306 /* 3307 * NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS 3308 * 3309 * This command returns information regarding GPU partitions which can be 3310 * requested via NV2080_CTRL_CMD_GPU_SET_PARTITIONS. 3311 * 3312 * [OUT] descCount 3313 * - Number of valid partition types 3314 * 3315 * [OUT] partitionDescs 3316 * - Information describing available partitions 3317 * 3318 * Possible status values returned are: 3319 * NV_OK 3320 * NV_ERR_NOT_SUPPORTED 3321 */ 3322 #define NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID (0x85U) 3323 3324 typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS { 3325 NvU32 descCount; 3326 // C form: NV2080_CTRL_GPU_DESCRIBE_PARTITION_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES]; 3327 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES], 8); 3328 } NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS; 3329 3330 #define NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS (0x20800185U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID" */ 3331 3332 3333 3334 /* 3335 * NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE 3336 * 3337 * This command returns information regarding maximum page size supported 3338 * by GMMU on the platform on which RM is running. 3339 * 3340 * [OUT] maxSupportedPageSize 3341 * - Maximum local vidmem page size supported by GMMU of a given GPU (HW) 3342 * on a given platform (OS) 3343 * 3344 * Possible status values returned are: 3345 * NV_OK 3346 * NV_ERR_NOT_SUPPORTED 3347 */ 3348 #define NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE (0x20800188U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID" */ 3349 3350 #define NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID (0x88U) 3351 3352 typedef struct NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS { 3353 NV_DECLARE_ALIGNED(NvU64 maxSupportedPageSize, 8); 3354 } NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS; 3355 3356 3357 3358 /* 3359 * NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC 3360 * 3361 * This command returns the max number of MMUs per GPC 3362 * 3363 * gpcId [IN] 3364 * Logical GPC id 3365 * count [OUT] 3366 * The number of MMUs per GPC 3367 * grRouteInfo 3368 * This parameter specifies the routing information used to 3369 * disambiguate the target GR engine. When SMC is enabled, this 3370 * is a mandatory parameter. 3371 */ 3372 #define NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID (0x8AU) 3373 3374 typedef struct NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS { 3375 NvU32 gpcId; 3376 NvU32 count; 3377 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 3378 } NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS; 3379 3380 #define NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC (0x2080018aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID" */ 3381 3382 /* 3383 * NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS 3384 * 3385 * This command returns the GPU partition IDs for all active partitions 3386 * If GPU is not partitioned, the control call will return partition count as "0" 3387 * 3388 * swizzId[OUT] 3389 * - HW Partition ID associated with the active partitions 3390 * 3391 * partitionCount[OUT] 3392 * - Number of active partitions in system 3393 * 3394 * Possible status values returned are: 3395 * NV_OK 3396 * NV_ERR_INVALID_ARGUMENT 3397 * NV_ERR_NOT_SUPPORTED 3398 */ 3399 #define NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID (0x8BU) 3400 3401 typedef struct NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS { 3402 NvU32 swizzId[NV2080_CTRL_GPU_MAX_PARTITION_IDS]; 3403 NvU32 partitionCount; 3404 } NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS; 3405 3406 #define NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS (0x2080018bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID" */ 3407 3408 3409 3410 /* 3411 * NV2080_CTRL_CMD_GPU_GET_PIDS 3412 * 3413 * Given a resource identifier and its type, this command returns a set of 3414 * process identifiers (PIDs) of processes that have instantiated this resource. 3415 * For example, given a class number, this command returns a list of all 3416 * processes with clients that have matching object allocations. 3417 * This is a SMC aware call and the scope of the information gets restricted 3418 * based on partition subscription. 3419 * The call enforces partition subscription if SMC is enabled, and client is not 3420 * a monitoring client. 3421 * Monitoring clients get global information without any scope based filtering. 3422 * Monitoring clients are also not expected to subscribe to a partition when 3423 * SMC is enabled. 3424 * 3425 * idType 3426 * Type of the resource identifier. See below for a list of valid types. 3427 * id 3428 * Resource identifier. 3429 * pidTblCount 3430 * Number of entries in the PID table. 3431 * pidTbl 3432 * Table which will contain the PIDs. Each table entry is of type NvU32. 3433 * 3434 * Possible status values returned are: 3435 * NV_OK 3436 * NV_ERR_INVALID_PARAM_STRUCT 3437 * NV_ERR_INVALID_ARGUMENT 3438 */ 3439 #define NV2080_CTRL_CMD_GPU_GET_PIDS (0x2080018dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID" */ 3440 3441 /* max size of pidTable */ 3442 #define NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT 950U 3443 3444 #define NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID (0x8DU) 3445 3446 typedef struct NV2080_CTRL_GPU_GET_PIDS_PARAMS { 3447 NvU32 idType; 3448 NvU32 id; 3449 NvU32 pidTblCount; 3450 NvU32 pidTbl[NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT]; 3451 } NV2080_CTRL_GPU_GET_PIDS_PARAMS; 3452 3453 /* 3454 * Use class NV20_SUBDEVICE_0 with NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS to query 3455 * PIDs with or without GPU contexts. For any other class id, PIDs only with GPU 3456 * contexts are returned. 3457 */ 3458 #define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS (0x00000000U) 3459 #define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST (0x00000001U) 3460 3461 /* 3462 * NV2080_CTRL_SMC_SUBSCRIPTION_INFO 3463 * 3464 * This structure contains information about the SMC subscription type. 3465 * If MIG is enabled a valid ID is returned, it is set to PARTITIONID_INVALID otherwise. 3466 * 3467 * computeInstanceId 3468 * This parameter returns a valid compute instance ID 3469 * gpuInstanceId 3470 * This parameter returns a valid GPU instance ID 3471 */ 3472 typedef struct NV2080_CTRL_SMC_SUBSCRIPTION_INFO { 3473 NvU32 computeInstanceId; 3474 NvU32 gpuInstanceId; 3475 } NV2080_CTRL_SMC_SUBSCRIPTION_INFO; 3476 3477 /* 3478 * NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA 3479 * 3480 * This structure contains the video memory usage information. 3481 * 3482 * memPrivate 3483 * This parameter returns the amount of memory exclusively owned 3484 * (i.e. private) to the client 3485 * memSharedOwned 3486 * This parameter returns the amount of shared memory owned by the client 3487 * memSharedDuped 3488 * This parameter returns the amount of shared memory duped by the client 3489 * protectedMemPrivate 3490 * This parameter returns the amount of protected memory exclusively owned 3491 * (i.e. private) to the client whenever memory protection is enabled 3492 * protectedMemSharedOwned 3493 * This parameter returns the amount of shared protected memory owned by the 3494 * client whenever memory protection is enabled 3495 * protectedMemSharedDuped 3496 * This parameter returns the amount of shared protected memory duped by the 3497 * client whenever memory protection is enabled 3498 */ 3499 typedef struct NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA { 3500 NV_DECLARE_ALIGNED(NvU64 memPrivate, 8); 3501 NV_DECLARE_ALIGNED(NvU64 memSharedOwned, 8); 3502 NV_DECLARE_ALIGNED(NvU64 memSharedDuped, 8); 3503 NV_DECLARE_ALIGNED(NvU64 protectedMemPrivate, 8); 3504 NV_DECLARE_ALIGNED(NvU64 protectedMemSharedOwned, 8); 3505 NV_DECLARE_ALIGNED(NvU64 protectedMemSharedDuped, 8); 3506 } NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA; 3507 3508 #define NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE (0x00000000U) 3509 3510 #define NV2080_CTRL_GPU_PID_INFO_INDEX_MAX NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE 3511 3512 typedef union NV2080_CTRL_GPU_PID_INFO_DATA { 3513 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA vidMemUsage, 8); 3514 } NV2080_CTRL_GPU_PID_INFO_DATA; 3515 3516 3517 /* 3518 * NV2080_CTRL_GPU_PID_INFO 3519 * 3520 * This structure contains the per pid information. Each type of information 3521 * retrievable via NV2080_CTRL_CMD_GET_PID_INFO is assigned a unique index 3522 * below. In addition the process for which the lookup is for is also defined. 3523 * This is a SMC aware call and the scope of the information gets restricted 3524 * based on partition subscription. 3525 * The call enforces partition subscription if SMC is enabled, and client is not 3526 * a monitoring client. 3527 * Monitoring clients get global information without any scope based filtering. 3528 * Monitoring clients are also not expected to subscribe to a partition when 3529 * SMC is enabled. 3530 * 3531 * pid 3532 * This parameter specifies the PID of the process for which information is 3533 * to be queried. 3534 * index 3535 * This parameter specifies the type of information being queried for the 3536 * process of interest. 3537 * result 3538 * This parameter returns the result of the instruction's execution. 3539 * data 3540 * This parameter returns the data corresponding to the information which is 3541 * being queried. 3542 * 3543 * Possible status values returned are: 3544 * NV_OK 3545 * NV_ERR_INVALID_ARGUMENT 3546 * NV_ERR_INVALID_PARAM_STRUCT 3547 * 3548 * Valid PID information indices are: 3549 * 3550 * NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE 3551 * This index is used to request the amount of video memory on this GPU 3552 * allocated to the process. 3553 */ 3554 typedef struct NV2080_CTRL_GPU_PID_INFO { 3555 NvU32 pid; 3556 NvU32 index; 3557 NvU32 result; 3558 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO_DATA data, 8); 3559 NV2080_CTRL_SMC_SUBSCRIPTION_INFO smcSubscription; 3560 } NV2080_CTRL_GPU_PID_INFO; 3561 3562 /* 3563 * NV2080_CTRL_CMD_GPU_GET_PID_INFO 3564 * 3565 * This command allows querying per-process information from the RM. Clients 3566 * request information by specifying a unique informational index and the 3567 * Process ID of the process in question. The result is set to indicate success 3568 * and the information queried (if available) is returned in the data parameter. 3569 * 3570 * pidInfoListCount 3571 * The number of valid entries in the pidInfoList array. 3572 * pidInfoList 3573 * An array of NV2080_CTRL_GPU_PID_INFO of maximum length 3574 * NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT. 3575 * 3576 * Possible status values returned are: 3577 * NV_OK 3578 * NV_ERR_INVALID_PARAM_STRUCT 3579 * NV_ERR_INVALID_ARGUMENT 3580 */ 3581 #define NV2080_CTRL_CMD_GPU_GET_PID_INFO (0x2080018eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID" */ 3582 3583 /* max size of pidInfoList */ 3584 #define NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT 200U 3585 3586 #define NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID (0x8EU) 3587 3588 typedef struct NV2080_CTRL_GPU_GET_PID_INFO_PARAMS { 3589 NvU32 pidInfoListCount; 3590 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO pidInfoList[NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT], 8); 3591 } NV2080_CTRL_GPU_GET_PID_INFO_PARAMS; 3592 3593 3594 3595 /*! 3596 * NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT 3597 * 3598 * @brief Handle VF PRI faults 3599 * 3600 * faultType 3601 * BAR1, BAR2, PHYSICAL or UNBOUND_INSTANCE 3602 * 3603 * Possible status values returned are: 3604 * NV_OK 3605 * NV_ERR_NOT_SUPPORTED 3606 * 3607 */ 3608 3609 #define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT (0x20800192U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID" */ 3610 3611 #define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID 0U 3612 #define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1 1U 3613 #define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2 2U 3614 #define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL 3U 3615 #define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE 4U 3616 3617 #define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID (0x92U) 3618 3619 typedef struct NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS { 3620 NvU32 faultType; 3621 } NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS; 3622 3623 3624 /*! 3625 * Compute policy types to be specified by callers to set a config. 3626 * 3627 * _TIMESLICE 3628 * Set the timeslice config for the requested GPU. 3629 * Check @ref NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE for 3630 * permissible timeslice values. 3631 */ 3632 #define NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE 0U 3633 #define NV2080_CTRL_GPU_COMPUTE_POLICY_MAX 1U 3634 3635 /*! 3636 * Enum consisting of permissible timeslice options that can configured 3637 * for a GPU. These can be queried by compute clients and the exact 3638 * timeslice values can be chosen appropriately as per GPU support 3639 */ 3640 typedef enum NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE { 3641 NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT = 0, 3642 NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT = 1, 3643 NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM = 2, 3644 NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG = 3, 3645 NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX = 4, 3646 } NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE; 3647 3648 typedef struct NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG { 3649 /*! 3650 * NV2080_CTRL_GPU_COMPUTE_POLICY_<xyz> 3651 */ 3652 NvU32 type; 3653 3654 /*! 3655 * Union of type-specific data 3656 */ 3657 union { 3658 NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE timeslice; 3659 } data; 3660 } NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG; 3661 3662 #define NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x94U) 3663 3664 typedef struct NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS { 3665 NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG config; 3666 } NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS; 3667 3668 /* 3669 * NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG 3670 * 3671 * This command retrieves all compute policies configs for the associated gpu. 3672 * 3673 * Possible status values returned are: 3674 * NV_OK 3675 * NV_ERR_INVALID_ARGUMENT 3676 * NV_ERR_OBJECT_NOT_FOUND 3677 */ 3678 #define NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG (0x20800195U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID" */ 3679 3680 /*! 3681 * This define limits the max number of policy configs that can be handled by 3682 * NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG command. 3683 * 3684 * @note Needs to be in sync (greater or equal) to NV2080_CTRL_GPU_COMPUTE_POLICY_MAX. 3685 */ 3686 3687 #define NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX 32U 3688 3689 #define NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x95U) 3690 3691 typedef struct NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS { 3692 NvU32 numConfigs; 3693 3694 /*! 3695 * C form: 3696 * NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX]; 3697 */ 3698 NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX]; 3699 } NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS; 3700 3701 /* 3702 * NV2080_CTRL_CMD_GPU_GET_GFID 3703 * 3704 * This command returns the GFID (GPU Function ID) for a given SR-IOV 3705 * Virtual Function (VF) of the physical GPU. 3706 * 3707 * domain [IN] 3708 * This field specifies the respective domain of the PCI device. 3709 * bus [IN] 3710 * This field specifies the bus id for a given VF. 3711 * device [IN] 3712 * This field specifies the device id for a given VF. 3713 * func [IN] 3714 * This field specifies the function id for a given VF. 3715 * gfid[OUT] 3716 * - This field returns GFID for a given VF BDF. 3717 * gfidMask[OUT] 3718 * - This field returns GFID mask value. 3719 * 3720 * Possible status values returned are: 3721 * NV_OK 3722 * NV_ERR_INVALID_PARAM_STRUCT 3723 * NV_ERR_INVALID_ARGUMENT 3724 * NV_ERR_OPERATING_SYSTEM 3725 */ 3726 3727 #define NV2080_CTRL_CMD_GPU_GET_GFID (0x20800196U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID" */ 3728 3729 #define NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID (0x96U) 3730 3731 typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS { 3732 NvU32 domain; 3733 NvU8 bus; 3734 NvU8 device; 3735 NvU8 func; 3736 NvU32 gfid; 3737 NvU32 gfidMask; 3738 } NV2080_CTRL_GPU_GET_GFID_PARAMS; 3739 3740 /* 3741 * NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY 3742 * 3743 * This command informs the GPU driver that the GPU partition associated with 3744 * a given GFID has been activated or will be deactivated. 3745 * 3746 * gfid[IN] 3747 * - The GPU function identifier for a given VF BDF 3748 * bEnable [IN] 3749 * - Set to NV_TRUE if the GPU partition has been activated. 3750 * - Set to NV_FALSE if the GPU partition will be deactivated. 3751 * fabricPartitionId [IN] 3752 * - Set the fabric manager partition ID dring partition activation. 3753 * - Ignored during partition deactivation. 3754 * 3755 * Possible status values returned are: 3756 * NV_OK 3757 * NV_ERR_INVALID_PARAM_STRUCT 3758 * NV_ERR_INVALID_ARGUMENT 3759 * NV_ERR_OPERATING_SYSTEM 3760 */ 3761 3762 #define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY (0x20800197U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID" */ 3763 3764 #define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID (0x97U) 3765 3766 typedef struct NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS { 3767 NvU32 gfid; 3768 NvBool bEnable; 3769 NvU32 fabricPartitionId; 3770 } NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS; 3771 3772 /*! 3773 * NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST 3774 * 3775 * @brief Validate the address range for memory map request by comparing the 3776 * user supplied address range with GPU BAR0/BAR1 range. 3777 * 3778 * @param[in] addressStart Start address for memory map request 3779 * @param[in] addressLength Length for for memory map request 3780 * @param[out] protection NV_PROTECT_READ_WRITE, if both read/write is allowed 3781 * NV_PROTECT_READABLE, if only read is allowed 3782 * 3783 * Possible status values returned are: 3784 * NV_OK 3785 * NV_ERR_PROTECTION_FAULT 3786 * 3787 */ 3788 #define NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST (0x20800198U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID" */ 3789 3790 #define NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID (0x98U) 3791 3792 typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS { 3793 NV_DECLARE_ALIGNED(NvU64 addressStart, 8); 3794 NV_DECLARE_ALIGNED(NvU64 addressLength, 8); 3795 NvU32 protection; 3796 } NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS; 3797 3798 /* 3799 * NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR 3800 * 3801 * @brief This command is similar to NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR 3802 * but will be used to set the EGM fabric base addr associated with the gpu. 3803 * Note: For EGM FLA, we will be making use of the existing control call i.e 3804 * NV2080_CTRL_CMD_FLA_RANGE 3805 * 3806 */ 3807 #define NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR (0x20800199U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */ 3808 3809 #define NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID (0x99U) 3810 3811 typedef struct NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS { 3812 NV_DECLARE_ALIGNED(NvU64 egmGpaFabricBaseAddr, 8); 3813 } NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS; 3814 3815 /* 3816 * NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES 3817 * 3818 * This command is used to retrieve the load time (latency) of each engine. 3819 * 3820 * engineCount 3821 * This field specifies the number of entries of the following 3822 * three arrays. 3823 * 3824 * engineList[NV2080_GPU_MAX_ENGINE_OBJECTS] 3825 * An array of NvU32 which stores each engine's descriptor. 3826 * 3827 * engineStateLoadTime[NV2080_GPU_MAX_ENGINE_OBJECTS] 3828 * A array of NvU64 which stores each engine's load time. 3829 * 3830 * engineIsInit[NV2080_GPU_MAX_ENGINE_OBJECTS] 3831 * A array of NvBool which stores each engine's initialization status. 3832 * 3833 * Possible status values returned are: 3834 * NV_OK 3835 */ 3836 #define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */ 3837 3838 #define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xC8U 3839 3840 #define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU) 3841 3842 typedef struct NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS { 3843 NvU32 engineCount; 3844 NvU32 engineList[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; 3845 NV_DECLARE_ALIGNED(NvU64 engineStateLoadTime[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS], 8); 3846 NvBool engineIsInit[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; 3847 } NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS; 3848 3849 /* 3850 * NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING 3851 * 3852 * This command is used to retrieve the mapping of engine ID and engine Name. 3853 * 3854 * engineCount 3855 * This field specifies the size of the mapping. 3856 * 3857 * engineID 3858 * An array of NvU32 which stores each engine's descriptor. 3859 * 3860 * engineName 3861 * An array of char[100] which stores each engine's name. 3862 * 3863 * Possible status values returned are: 3864 * NV_OK 3865 */ 3866 #define NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING (0x2080019cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID" */ 3867 3868 #define NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID (0x9CU) 3869 3870 typedef struct NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS { 3871 NvU32 engineCount; 3872 NvU32 engineID[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; 3873 char engineName[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS][100]; 3874 } NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS; 3875 3876 /* 3877 * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS 3878 * 3879 * Same as above NV2080_CTRL_CMD_GPU_EXEC_REG_OPS except that this CTRL CMD will 3880 * not allow any embedded pointers. The regOps array is inlined as part of the 3881 * struct. 3882 * NOTE: This intended for gsp plugin only as it may override regOp access 3883 * restrictions 3884 * 3885 * Possible status values returned are: 3886 * NV_OK 3887 * NV_ERR_NOT_SUPPORTED 3888 * NV_ERR_INVALID_ARGUMENT 3889 * NV_ERR_INVALID_PARAM_STRUCT 3890 */ 3891 #define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS (0x2080019dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID" */ 3892 3893 /* setting this to 100 keeps it right below 4k in size */ 3894 #define NV2080_CTRL_REG_OPS_ARRAY_MAX 100U 3895 #define NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID (0x9DU) 3896 3897 typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS { 3898 NvHandle hClientTarget; 3899 NvHandle hChannelTarget; 3900 NvU32 bNonTransactional; 3901 NvU32 reserved00[2]; 3902 NvU32 regOpCount; 3903 NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_REG_OPS_ARRAY_MAX]; 3904 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 3905 } NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS; 3906 3907 3908 3909 3910 /*! 3911 * NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO 3912 * 3913 * [in/out] gpuId 3914 * GPU ID for which the capabilities are queried. 3915 * For the NV2080_CTRL_CMD_GET_P2P_CAPS control: 3916 * If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to 3917 * the GPU ID of an attached GPU. 3918 * If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester 3919 * should set it to the ID of the GPU that needs to be queried from. 3920 * [in] gpuUuid 3921 * Alternative to gpuId; used to identify target GPU for which caps are being queried. 3922 * Option only available for Guest RPCs. 3923 * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. 3924 * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. 3925 * If bAllCaps == NV_TRUE, gpuUuid is ignored. 3926 * [out] p2pCaps 3927 * Peer to peer capabilities discovered between the GPUs. 3928 * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. 3929 * [out] p2pOptimalReadCEs 3930 * Mask of CEs to use for p2p reads over Nvlink. 3931 * [out] p2pOptimalWriteCEs 3932 * Mask of CEs to use for p2p writes over Nvlink. 3933 * [out] p2pCapsStatus 3934 * Status of all supported p2p capabilities. 3935 * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. 3936 * [out] busPeerId 3937 * Bus peer ID. For an invalid or a non-existent peer this field 3938 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 3939 * [out] busEgmPeerId 3940 * Bus EGM peer ID. For an invalid or a non-existent peer this field 3941 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 3942 */ 3943 #define NV2080_GET_P2P_CAPS_UUID_LEN 16U 3944 3945 typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO { 3946 NvU32 gpuId; 3947 NvU8 gpuUuid[NV2080_GET_P2P_CAPS_UUID_LEN]; 3948 NvU32 p2pCaps; 3949 NvU32 p2pOptimalReadCEs; 3950 NvU32 p2pOptimalWriteCEs; 3951 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 3952 NvU32 busPeerId; 3953 NvU32 busEgmPeerId; 3954 } NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO; 3955 3956 /*! 3957 * NV2080_CTRL_CMD_GET_P2P_CAPS 3958 * 3959 * Returns peer to peer capabilities present between GPUs. 3960 * The caller must either specify bAllCaps to query the capabilities for 3961 * all the attached GPUs or they must pass a valid list of GPU IDs. 3962 * 3963 * [in] bAllCaps 3964 * Set to NV_TRUE to query the capabilities for all the attached GPUs. 3965 * Set to NV_FALSE and specify peerGpuCount and peerGpuCaps[].gpuId 3966 * to retrieve the capabilities only for the specified GPUs. 3967 * [in] bUseUuid 3968 * Option only available for Guest RPCs. 3969 * Set to NV_TRUE to use gpuUuid in lieu of gpuId to identify target GPU. 3970 * If bAllCaps == NV_TRUE, bUseUuid is ignored. 3971 * [in/out] peerGpuCount 3972 * The number of the peerGpuCaps entries. 3973 * If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to 3974 * the total number of the attached GPUs. 3975 * If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester 3976 * should set it to the number of the peerGpuCaps entries. 3977 * [in/out] peerGpuCaps 3978 * The array of NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO entries, describing 3979 * the peer to peer capabilities of the GPUs. 3980 * 3981 * Possible status values returned are: 3982 * NV_OK 3983 * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount 3984 * NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuCaps[].gpuId 3985 */ 3986 #define NV2080_CTRL_CMD_GET_P2P_CAPS (0x208001a0U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ 3987 3988 #define NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0xA0U) 3989 3990 typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS { 3991 NvBool bAllCaps; 3992 NvBool bUseUuid; 3993 NvU32 peerGpuCount; 3994 NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 3995 } NV2080_CTRL_GET_P2P_CAPS_PARAMS; 3996 3997 3998 3999 /*! 4000 * NV2080_CTRL_GPU_COMPUTE_PROFILE 4001 * 4002 * This structure specifies resources in an execution partition 4003 * 4004 * id[OUT] 4005 * - Total Number of GPCs in this partition 4006 * 4007 * computeSize[OUT] 4008 * - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile 4009 * 4010 * gpcCount[OUT] 4011 * - Total Number of GPCs in this partition (including GFX Supported GPCs) 4012 * 4013 * veidCount[OUT] 4014 * - Number of VEIDs allocated to this profile 4015 * 4016 * smCount[OUT] 4017 * - Number of SMs usable in this profile 4018 */ 4019 typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE { 4020 NvU8 computeSize; 4021 NvU32 gfxGpcCount; 4022 NvU32 gpcCount; 4023 NvU32 veidCount; 4024 NvU32 smCount; 4025 } NV2080_CTRL_GPU_COMPUTE_PROFILE; 4026 4027 /*! 4028 * NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS 4029 * 4030 * This structure specifies resources in an execution partition 4031 * 4032 * profileCount[OUT] 4033 * - Total Number of profiles filled 4034 * 4035 * profiles[OUT] 4036 * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles 4037 */ 4038 #define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U) 4039 4040 typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS { 4041 NvU32 profileCount; 4042 NV2080_CTRL_GPU_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; 4043 } NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS; 4044 4045 #define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES (0x208001a2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ 4046 4047 #define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED 0U 4048 #define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED 1U 4049 #define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS 2U 4050 #define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE 3U 4051 4052 #define NV2080_GPU_FABRIC_CLUSTER_UUID_LEN 16U 4053 4054 #define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0) 4055 4056 #define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_MUTLINODE_SUPPORTED NVBIT64(1) 4057 4058 4059 4060 #define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0 4061 #define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0 4062 #define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE 1 4063 #define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE 2 4064 4065 /*! 4066 * NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS 4067 * 4068 * This structure provides the GPU<-->FM probe state info on NVSwitch based 4069 * systems 4070 * 4071 * state[OUT] 4072 * - Current state of GPU<-->FM probe req/rsp 4073 * Following values can be returned 4074 * _UNSUPPORTED - system does not support this feature 4075 * _NOT_STARTED - probe request is not yet sent to the FM 4076 * _IN_PROGRESS - probe response is not yet received 4077 * _COMPLETE - probe response is received 4078 * When state is NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE 4079 * status has to be checked for probe response success/failure 4080 * status[OUT] 4081 * - Inband Probe response status 4082 * A GPU which returns NV_OK status upon receiving the probe response 4083 * can participate in P2P 4084 * clusterUuid[OUT] 4085 * - Uuid of the cluster to which this node belongs 4086 * fabricPartitionId[OUT] 4087 * - Fabric partition Id 4088 * fabricCaps[OUT] 4089 * - Summary of fabric capabilities received from probe resp 4090 * Possible values are 4091 * NV2080_CTRL_GPU_FABRIC_PROBE_CAP_* 4092 * fabricCliqueId[OUT] 4093 * - Unique ID of a set of GPUs within a fabric partition that can perform P2P 4094 * fabricHealthMask[OUT] 4095 * - Mask where bits indicate different status about the health of the fabric 4096 */ 4097 #define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U) 4098 4099 typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS { 4100 NvU8 state; 4101 NV_STATUS status; 4102 NvU8 clusterUuid[NV2080_GPU_FABRIC_CLUSTER_UUID_LEN]; 4103 NvU16 fabricPartitionId; 4104 NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8); 4105 NvU32 fabricCliqueId; 4106 NvU32 fabricHealthMask; 4107 } NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS; 4108 4109 #define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ 4110 4111 /* 4112 * NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS 4113 * 4114 * This command retrieves and constructs the GPU partnumber from the VBIOS. 4115 * 4116 * The following data are currently supported: 4117 * 4118 * pciDevId 4119 * The PCI device ID 4120 * 4121 * chipSku 4122 * The chip SKU information 4123 * 4124 * chipMajor 4125 * The chip major number 4126 * 4127 * chipMinor 4128 * The chip minor number 4129 * 4130 */ 4131 #define NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS (0x208001a4U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID" */ 4132 4133 /* 4134 * The string format for a GPU part number 4135 * The GPU part number is formatted with 4 hexadecimal digits for the PCI device ID, the chip SKU string, 4136 * the chip major number, and then the chip minor number. 4137 * Ordering of the fields for the string format must be synced with the NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS 4138 * struct fields. 4139 */ 4140 #define GPU_PART_NUMBER_FMT "%04X-%s-%X%X" 4141 4142 /* The maximum length for the chip sku */ 4143 #define NV2080_MAX_CHIP_SKU_LENGTH 0x00000004U 4144 4145 #define NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID (0xA4U) 4146 4147 typedef struct NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS { 4148 NvU32 pciDevId; 4149 NvU8 chipSku[NV2080_MAX_CHIP_SKU_LENGTH]; 4150 NvU32 chipMajor; 4151 NvU32 chipMinor; 4152 } NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS; 4153 4154 /* 4155 * NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP 4156 * 4157 * This command returns the host hardware defined engine ID of the specified engine(s). 4158 * 4159 * swizzId[IN] 4160 * - HW Partition ID associated with the requested partition. 4161 * 4162 * Possible status values returned are: 4163 * NV_OK 4164 * NV_ERR_INVALID_ARGUMENT 4165 * NV_ERR_NOT_SUPPORTED 4166 */ 4167 #define NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP (0x208001a5U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID" */ 4168 4169 #define NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID (0xA5U) 4170 4171 typedef struct NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS { 4172 NvU32 swizzId; 4173 } NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS; 4174 4175 #define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS (0x208001a6U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID" */ 4176 #define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP (0x208001a7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID" */ 4177 #define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU (0x208001a8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID" */ 4178 4179 /* setting this to 100 keeps it right below 4k in size */ 4180 #define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX 50U 4181 typedef struct NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS { 4182 NvHandle hClientTarget; 4183 NvHandle hChannelTarget; 4184 NvU32 bNonTransactional; 4185 NvU32 regOpCount; 4186 NvU32 smIds[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX]; 4187 NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX]; 4188 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 4189 } NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS; 4190 4191 #define NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID (0xA6U) 4192 4193 typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS; 4194 #define NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID (0xA7U) 4195 4196 typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS; 4197 #define NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID (0xA8U) 4198 4199 typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS; 4200 4201 /* 4202 * NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET 4203 * 4204 * INTERNAL DEBUG/TESTING USE ONLY 4205 * 4206 * Marks the device for reset. 4207 * 4208 * Possible status return values are: 4209 * NV_OK 4210 * NV_ERR_NOT_SUPPORTED 4211 */ 4212 #define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET (0x208001a9U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xA9" */ 4213 4214 /* 4215 * NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET 4216 * 4217 * INTERNAL DEBUG/TESTING USE ONLY 4218 * 4219 * Unmarks the device for reset. 4220 * 4221 * Possible status return values are: 4222 * NV_OK 4223 * NV_ERR_NOT_SUPPORTED 4224 */ 4225 #define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET (0x208001aaU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAA" */ 4226 4227 /* 4228 * NV2080_CTRL_CMD_GPU_GET_RESET_STATUS 4229 * 4230 * Gets the current reset status of the device. 4231 * 4232 * bResetNeeded 4233 * Set to NV_TRUE if the device needs to be reset. 4234 * 4235 * Possible status return values are: 4236 * NV_OK 4237 * NV_ERR_NOT_SUPPORTED 4238 */ 4239 #define NV2080_CTRL_CMD_GPU_GET_RESET_STATUS (0x208001abU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID" */ 4240 4241 #define NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID (0xABU) 4242 4243 typedef struct NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS { 4244 NvBool bResetRequired; 4245 } NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS; 4246 4247 /* 4248 * NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET 4249 * 4250 * INTERNAL DEBUG/TESTING USE ONLY 4251 * 4252 * Marks the device for drain and reset. 4253 * 4254 * Possible status return values are: 4255 * NV_OK 4256 * NV_ERR_NOT_SUPPORTED 4257 */ 4258 #define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001acU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAC" */ 4259 4260 /* 4261 * NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET 4262 * 4263 * INTERNAL DEBUG/TESTING USE ONLY 4264 * 4265 * Unmarks the device for drain and reset. 4266 * 4267 * Possible status return values are: 4268 * NV_OK 4269 * NV_ERR_NOT_SUPPORTED 4270 */ 4271 #define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001adU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAD" */ 4272 4273 /* 4274 * NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS 4275 * 4276 * Gets the current drain and reset status of the device. Drain and reset is used only SMC configs. 4277 * 4278 * bDrainRecommended 4279 * Set to NV_TRUE if a drain and reset is recommended for the device. 4280 * 4281 * Possible status return values are: 4282 * NV_OK 4283 * NV_ERR_NOT_SUPPORTED 4284 */ 4285 #define NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS (0x208001aeU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID" */ 4286 4287 #define NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID (0xAEU) 4288 4289 typedef struct NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS { 4290 NvBool bDrainRecommended; 4291 } NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS; 4292 4293 /* 4294 * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 4295 * 4296 * This command returns NVENC software sessions information for the associate GPU. 4297 * This command is similar to NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO but doesn't have 4298 * embedded pointers. 4299 * 4300 * Check NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO for detailed information. 4301 */ 4302 4303 #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID (0xAFU) 4304 4305 typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS { 4306 NvU32 sessionInfoTblEntry; 4307 NV2080_CTRL_NVENC_SW_SESSION_INFO sessionInfoTbl[NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES]; 4308 } NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS; 4309 4310 #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 (0x208001afU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID" */ 4311 4312 typedef struct NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO { 4313 NvU32 engDesc; 4314 NvU32 ctxAttr; 4315 NvU32 ctxBufferSize; 4316 NvU32 addrSpaceList; 4317 NvU32 registerBase; 4318 } NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO; 4319 #define NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS 0x40 4320 4321 #define NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO (0x208001b0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */ 4322 4323 #define NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID (0xB0U) 4324 4325 typedef struct NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS { 4326 NvU32 numConstructedFalcons; 4327 NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS]; 4328 } NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS; 4329 4330 /* 4331 * NV2080_CTRL_CMD_GPU_GET_VF_CAPS 4332 * 4333 * This command will return the MSIX capabilities for virtual function 4334 * Parameters: 4335 * 4336 * gfid [IN] 4337 * The GPU function identifier for a given VF BDF 4338 * 4339 * vfMsixCap [out] 4340 * This field returns the VF MSIX cap values 4341 * 4342 * Possible status values returned are: 4343 * NV_OK 4344 */ 4345 typedef struct NV2080_VF_MSIX_CAPS { 4346 NvU32 msix_header; 4347 NvU32 msix_table; 4348 NvU32 msix_pba; 4349 } NV2080_VF_MSIX_CAPS; 4350 4351 #define NV2080_CTRL_CMD_GPU_GET_VF_CAPS (0x208001b1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID" */ 4352 4353 #define NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID (0xB1U) 4354 4355 typedef struct NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS { 4356 NvU32 gfid; 4357 NV2080_VF_MSIX_CAPS vfMsixCap; 4358 } NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS; 4359 4360 /* 4361 * NV2080_CTRL_GPU_GET_FIPS_STATUS 4362 * 4363 * @brief get FIPS status (enabled/disabled) from GSP-RM 4364 * 4365 * 4366 * @return NV_OK on success 4367 * @return NV_ERR_ otherwise 4368 */ 4369 #define NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID (0xe4U) 4370 4371 typedef struct NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS { 4372 NvBool bFipsEnabled; 4373 } NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS; 4374 #define NV2080_CTRL_GPU_GET_FIPS_STATUS (0x208001e4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID" */ 4375 4376 4377 /* _ctrl2080gpu_h_ */ 4378