1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 #pragma once 24 25 #include <nvtypes.h> 26 27 // 28 // This file was generated with FINN, an NVIDIA coding tool. 29 // Source file: ctrl/ctrl2080/ctrl2080gpu.finn 30 // 31 32 #include "ctrl/ctrl2080/ctrl2080base.h" 33 #include "ctrl/ctrl2080/ctrl2080gr.h" 34 #include "ctrl/ctrl0000/ctrl0000system.h" 35 #include "nvcfg_sdk.h" 36 #include "nvstatus.h" 37 38 #define NV_GRID_LICENSE_INFO_MAX_LENGTH (128) 39 40 /* License info strings for vGPU products */ 41 #define NV_GRID_LICENSE_FEATURE_VPC_EDITION "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" 42 #define NV_GRID_LICENSE_FEATURE_VAPPS_EDITION "GRID-Virtual-Apps,3.0" 43 #define NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" 44 #define NV_GRID_LICENSE_FEATURE_GAMING_EDITION "GRID-vGaming,8.0" 45 #define NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION "NVIDIA-vComputeServer,9.0;Quadro-Virtual-DWS,5.0" 46 47 #define NV_GRID_LICENSED_PRODUCT_VWS "NVIDIA RTX Virtual Workstation" 48 #define NV_GRID_LICENSED_PRODUCT_GAMING "NVIDIA Cloud Gaming" 49 #define NV_GRID_LICENSED_PRODUCT_VPC "NVIDIA Virtual PC" 50 #define NV_GRID_LICENSED_PRODUCT_VAPPS "NVIDIA Virtual Applications" 51 #define NV_GRID_LICENSED_PRODUCT_COMPUTE "NVIDIA Virtual Compute Server" 52 53 54 55 /* NV20_SUBDEVICE_XX gpu control commands and parameters */ 56 57 58 59 typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO; 60 61 /* valid gpu info index values */ 62 63 64 65 #define NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT (0x00000004U) 66 67 68 #define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0 (0x00000012U) 69 #define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1 (0x00000013U) 70 71 72 #define NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS (0x0000001fU) 73 74 75 #define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD (0x00000022U) 76 77 78 #define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE (0x00000025U) 79 #define NV2080_CTRL_GPU_INFO_INDEX_IBMNPU_RELAXED_ORDERING (0x00000026U) 80 #define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED (0x00000027U) 81 #define NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED (0x00000028U) 82 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT (0x00000029U) 83 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE (0x0000002aU) 84 #define NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM (0x0000002bU) 85 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION (0x0000002cU) 86 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY (0x0000002dU) 87 88 89 #define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM (0x0000002fU) 90 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY (0x00000030U) 91 #define NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE (0x00000031U) 92 93 94 #define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED (0x00000033U) 95 #define NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED (0x00000034U) 96 #define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED (0x00000035U) 97 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY (0x00000036U) 98 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY (0x00000037U) 99 100 101 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY (0x0000003aU) 102 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY (0x0000003bU) 103 104 105 #define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003cU) 106 #define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003dU) 107 108 109 #define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED (0x0000003fU) 110 111 112 113 #define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000041U) 114 115 /* valid minor revision extended values */ 116 #define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U) 117 #define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P (0x00000001U) 118 #define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V (0x00000002U) 119 #define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV (0x00000003U) 120 121 122 123 /* valid system memory access capability values */ 124 #define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO (0x00000000U) 125 #define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES (0x00000001U) 126 127 128 129 /* valid gemini board values */ 130 #define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO (0x00000000U) 131 #define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES (0x00000001U) 132 133 /* valid surprise removal values */ 134 #define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO (0x00000000U) 135 #define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES (0x00000001U) 136 137 /* valid relaxed ordering values */ 138 #define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_DISABLED (0x00000000U) 139 #define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_ENABLED (0x00000001U) 140 #define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_UNSUPPORTED (0xFFFFFFFFU) 141 142 /* valid poison fuse capability values */ 143 #define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO (0x00000000U) 144 #define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES (0x00000001U) 145 146 /* valid nvswitch proxy detected values */ 147 #define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO (0x00000000U) 148 #define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES (0x00000001U) 149 150 /* valid NVSR GPU support info values */ 151 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO (0x00000000U) 152 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES (0x00000001U) 153 154 /* valid SMC mode values */ 155 #define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED (0x00000000U) 156 #define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED (0x00000001U) 157 #define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED (0x00000002U) 158 #define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING (0x00000003U) 159 #define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING (0x00000004U) 160 161 /* valid split VAS mode values */ 162 #define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO (0x00000000U) 163 #define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES (0x00000001U) 164 165 /* valid grid capability values */ 166 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO (0x00000000U) 167 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES (0x00000001U) 168 169 /* valid per runlist channel ram capability values */ 170 #define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED (0x00000000U) 171 #define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED (0x00000001U) 172 173 /* valid ATS capability values */ 174 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO (0x00000000U) 175 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES (0x00000001U) 176 177 /* valid Nvenc Session Stats reporting state values */ 178 #define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED (0x00000000U) 179 #define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED (0x00000001U) 180 #define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED (0x00000002U) 181 182 /* valid 4K PAGE isolation requirement values */ 183 #define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_NO (0x00000000U) 184 #define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES (0x00000001U) 185 186 /* valid display enabled values */ 187 #define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO (0x00000000U) 188 #define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES (0x00000001U) 189 190 /* valid mobile config enabled values */ 191 #define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO (0x00000000U) 192 #define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES (0x00000001U) 193 194 195 /* valid profiling capability values */ 196 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED (0x00000000U) 197 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED (0x00000001U) 198 199 /* valid debugging capability values */ 200 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED (0x00000000U) 201 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED (0x00000001U) 202 203 204 /* valid local EGM supported values */ 205 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO (0x00000000U) 206 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES (0x00000001U) 207 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_PEERID 31:1 208 209 /* valid self hosted values */ 210 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO (0x00000000U) 211 #define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES (0x00000001U) 212 213 214 215 /* valid CMP (Crypto Mining Processor) SKU values */ 216 #define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO (0x00000000U) 217 #define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES (0x00000001U) 218 219 220 /* valid dma-buf suport values */ 221 #define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO (0x00000000U) 222 #define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES (0x00000001U) 223 224 /* valid resetless MIG device supported values */ 225 #define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO (0x00000000U) 226 #define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES (0x00000001U) 227 228 /* 229 * NV2080_CTRL_CMD_GPU_GET_INFO 230 * 231 * This command returns gpu information for the associated GPU. Requests 232 * to retrieve gpu information use a list of one or more NV2080_CTRL_GPU_INFO 233 * structures. 234 * 235 * gpuInfoListSize 236 * This field specifies the number of entries on the caller's 237 * gpuInfoList. 238 * gpuInfoList 239 * This field specifies a pointer in the caller's address space 240 * to the buffer into which the gpu information is to be returned. 241 * This buffer must be at least as big as gpuInfoListSize multiplied 242 * by the size of the NV2080_CTRL_GPU_INFO structure. 243 * 244 * Possible status values returned are: 245 * NV_OK 246 * NV_ERR_INVALID_PARAM_STRUCT 247 * NV_ERR_INVALID_ARGUMENT 248 * NV_ERR_NOT_SUPPORTED 249 * NV_ERR_OPERATING_SYSTEM 250 */ 251 #define NV2080_CTRL_CMD_GPU_GET_INFO (0x20800101U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID" */ 252 253 #define NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID (0x1U) 254 255 typedef struct NV2080_CTRL_GPU_GET_INFO_PARAMS { 256 NvU32 gpuInfoListSize; 257 NV_DECLARE_ALIGNED(NvP64 gpuInfoList, 8); 258 } NV2080_CTRL_GPU_GET_INFO_PARAMS; 259 260 #define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID" */ 261 262 #define NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID (0x2U) 263 264 typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS { 265 NvU32 gpuInfoListSize; 266 NV2080_CTRL_GPU_INFO gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE]; 267 } NV2080_CTRL_GPU_GET_INFO_V2_PARAMS; 268 269 /* 270 * NV2080_CTRL_CMD_GPU_GET_NAME_STRING 271 * 272 * This command returns the name of the GPU in string form in either ASCII 273 * or UNICODE format. 274 * 275 * gpuNameStringFlags 276 * This field specifies flags to use while creating the GPU name string. 277 * Valid flags values: 278 * NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII 279 * The returned name string should be in standard ASCII format. 280 * NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE 281 * The returned name string should be in unicode format. 282 * gpuNameString 283 * This field contains the buffer into which the name string should be 284 * returned. The length of the returned string will be no more than 285 * NV2080_CTRL_GPU_MAX_NAME_STRING_LENGTH bytes in size. 286 * 287 * Possible status values returned are: 288 * NV_OK 289 * NV_ERR_INVALID_PARAM_STRUCT 290 * NV_ERR_INVALID_ARGUMENT 291 * NV_ERR_OPERATING_SYSTEM 292 */ 293 #define NV2080_CTRL_CMD_GPU_GET_NAME_STRING (0x20800110U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID" */ 294 295 #define NV2080_GPU_MAX_NAME_STRING_LENGTH (0x0000040U) 296 297 // This field is deprecated - 'gpuNameStringFlags' is now a simple scalar. 298 // Field maintained (and extended from 0:0) for compile-time compatibility. 299 #define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE 31:0 300 301 /* valid gpu name string flags */ 302 #define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII (0x00000000U) 303 #define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE (0x00000001U) 304 305 #define NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID (0x10U) 306 307 typedef struct NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS { 308 NvU32 gpuNameStringFlags; 309 union { 310 NvU8 ascii[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 311 NvU16 unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 312 } gpuNameString; 313 } NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS; 314 315 /* 316 * NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING 317 * 318 * This command returns the short name of the GPU in ASCII string form. 319 * 320 * gpuShortNameString 321 * This field contains the buffer into which the short name string should 322 * be returned. The length of the returned string will be no more than 323 * NV2080_MAX_NAME_STRING_LENGTH bytes in size. 324 * 325 * Possible status values returned are: 326 * NV_OK 327 * NV_ERR_INVALID_PARAM_STRUCT 328 * NV_ERR_INVALID_ARGUMENT 329 * NV_ERR_OPERATING_SYSTEM 330 */ 331 #define NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING (0x20800111U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID" */ 332 333 #define NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID (0x11U) 334 335 typedef struct NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS { 336 NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; 337 } NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS; 338 339 /* 340 * NV2080_CTRL_CMD_GPU_SET_POWER 341 * 342 * This command sets the power state for the GPU as a whole, various engines, 343 * or clocks. 344 * 345 * target 346 * One of NV2080_CTRL_GPU_SET_POWER_TARGET_* 347 * 348 * newLevel 349 * One of NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_* 350 * NV2080_CTRL_GPU_SET_POWER_STATE_ENGINE_LEVEL_* 351 * NV2080_CTRL_GPU_SET_POWER_STATE_CLOCK_LEVEL_* 352 * depending on the target above. 353 * 354 * oldLevel 355 * Previous level as appropriate. 356 * 357 * Possible status values returned are: 358 * NV_OK 359 * NV_ERR_INVALID_ARGUMENT 360 */ 361 #define NV2080_CTRL_CMD_GPU_SET_POWER (0x20800112U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID" */ 362 363 #define NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID (0x12U) 364 365 typedef struct NV2080_CTRL_GPU_SET_POWER_PARAMS { 366 NvU32 target; 367 NvU32 newLevel; 368 NvU32 oldLevel; 369 } NV2080_CTRL_GPU_SET_POWER_PARAMS; 370 371 372 373 #define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0 (0x00000000U) 374 #define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1 (0x00000001U) 375 #define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2 (0x00000002U) 376 #define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 (0x00000003U) 377 #define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4 (0x00000004U) 378 #define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7 (0x00000007U) 379 380 /* 381 * NV2080_CTRL_CMD_GPU_GET_SDM 382 * 383 * This command returns the subdevice mask value for the associated subdevice. 384 * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction 385 * provided by the NV36_CHANNEL_DMA and newer channel dma classes. 386 * 387 * subdeviceMask [out] 388 * This field return the subdevice mask value. 389 * 390 * Possible status values returned are: 391 * NV_OK 392 * NV_ERR_INVALID_PARAM_STRUCT 393 */ 394 #define NV2080_CTRL_CMD_GPU_GET_SDM (0x20800118U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID" */ 395 396 #define NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID (0x18U) 397 398 typedef struct NV2080_CTRL_GPU_GET_SDM_PARAMS { 399 NvU32 subdeviceMask; 400 } NV2080_CTRL_GPU_GET_SDM_PARAMS; 401 402 /* 403 * NV2080_CTRL_CMD_GPU_SET_SDM 404 * 405 * This command sets the subdevice instance and mask value for the associated subdevice. 406 * The subdevice mask value can be used with the SET_SUBDEVICE_MASK instruction 407 * provided by the NV36_CHANNEL_DMA and newer channel dma classes. 408 * It must be called before the GPU HW is initialized otherwise 409 * NV_ERR_INVALID_STATE is being returned. 410 * 411 * subdeviceMask [in] 412 * This field configures the subdevice mask value for the GPU/Subdevice 413 * 414 * Possible status values returned are: 415 * NV_OK 416 * NV_ERR_INVALID_STATE 417 * NV_ERR_INVALID_DATA 418 * NV_ERR_INVALID_PARAM_STRUCT 419 */ 420 #define NV2080_CTRL_CMD_GPU_SET_SDM (0x20800120U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID" */ 421 422 #define NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID (0x20U) 423 424 typedef struct NV2080_CTRL_GPU_SET_SDM_PARAMS { 425 NvU32 subdeviceMask; 426 } NV2080_CTRL_GPU_SET_SDM_PARAMS; 427 428 /* 429 * NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO 430 * 431 * This command returns the associated subdevices' simulation information. 432 * 433 * type 434 * This field returns the simulation type. 435 * One of NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_* 436 * 437 * Possible status values returned are: 438 * NV_OK 439 * NV_ERR_NOT_SUPPORTED 440 */ 441 #define NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO (0x20800119U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID" */ 442 443 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID (0x19U) 444 445 typedef struct NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS { 446 NvU32 type; 447 } NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS; 448 449 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE (0x00000000U) 450 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL (0x00000001U) 451 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL (0x00000002U) 452 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL (0x00000003U) 453 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL (0x00000004U) 454 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU (0x00000005U) 455 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER (0x00000006U) 456 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA (0x00000007U) 457 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL (0x00000008U) 458 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL (0x00000009U) 459 #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN (0xFFFFFFFFU) 460 461 /* 462 * NV2080_CTRL_GPU_REG_OP 463 * 464 * This structure describes register operation information for use with 465 * the NV2080_CTRL_CMD_GPU_EXEC_REG_OPS command. The structure describes 466 * a single register operation. The operation can be a read or write and 467 * can involve either 32bits or 64bits of data. 468 * 469 * For 32bit read operations, the operation takes the following form: 470 * 471 * regValueLo = read(bar0 + regOffset) 472 * regValueHi = 0 473 * 474 * For 64bit read operations, the operation takes the following form: 475 * 476 * regValueLo = read(bar0 + regOffset) 477 * regValueHi = read(bar0 + regOffset + 4) 478 * 479 * For 32bit write operations, the operation takes the following form: 480 * 481 * new = ((read(bar0 + regOffset) & ~regAndNMaskLo) | regValueLo) 482 * write(bar0 + regOffset, new) 483 * 484 * For 64bit write operations, the operation takes the following form: 485 * 486 * new_lo = ((read(bar0 + regOffset) & ~regAndNMaskLo) | regValueLo) 487 * new_hi = ((read(bar0 + regOffset + 4) & ~regAndNMaskHi) | regValueHi) 488 * write(bar0 + regOffset, new_lo) 489 * write(bar0 + regOffset + 4, new_hi) 490 * 491 * Details on the parameters follow: 492 * 493 * regOp 494 * This field specifies the operation to be applied to the register 495 * specified by the regOffset parameter. Valid values for this 496 * parameter are: 497 * NV2080_CTRL_GPU_REG_OP_READ_08 498 * The register operation should be a 8bit global privileged register read. 499 * NV2080_CTRL_GPU_REG_OP_WRITE_08 500 * The register operation should be a 8bit global privileged register write. 501 * NV2080_CTRL_GPU_REG_OP_READ_32 502 * The register operation should be a 32bit register read. 503 * NV2080_CTRL_GPU_REG_OP_WRITE_32 504 * The register operation should be a 32bit register write. 505 * NV2080_CTRL_GPU_REG_OP_READ_64 506 * The register operation should be a 64bit register read. 507 * NV2080_CTRL_GPU_REG_OP_WRITE_64 508 * The register operation should be a 64bit register write. 509 * regType 510 * This field specifies the type of the register specified by the 511 * regOffset parameter. Valid values for this parameter are: 512 * NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL 513 * The register is a global privileged register. Read operations 514 * return the current value from the associated global register. 515 * Write operations for registers of this type take effect immediately. 516 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX 517 * The register is a graphics context register. Read operations 518 * return the current value from the associated global register. 519 * Write operations are applied to all existing graphics engine 520 * contexts. Any newly created graphics engine contexts will also 521 * be modified. 522 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC 523 * This is a graphics context TPC register group. Write operations are 524 * applied to TPC group(s) specified by regGroupMask. 525 * This field is ignored for read operations. 526 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM 527 * This is a graphics context SM register group that is inside TPC 528 * group. Write operations are applied to SM group(s) specified by 529 * regGroupMask (TPC) and regSubGroupMask (SM). This field is ignored 530 * for read operations. 531 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP 532 * This is a graphics context CROP register group. Write operations 533 * are applied to registers specified by regGroupMask. This field is 534 * ignored for read operations. 535 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP 536 * This is a graphics context ZROP register group. Write operations 537 * are applied to registers specified by regGroupMask. This field is 538 * ignored for read operations. 539 * NV2080_CTRL_GPU_REG_OP_TYPE_FB 540 * This is a fb register group. Write operations are applied to 541 * registers specified by regGroupMask. This field is 542 * ignored for read operations. 543 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD 544 * This is a graphics context QUAD register group. Operations 545 * are applied to registers specified by regQuad value. 546 * regQuad 547 * This field specifies the quad to be accessed for register regOffsetwhen 548 * the regType specified is NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD. 549 * regGroupMask 550 * This field specifies which registers inside an array should be updated. 551 * This field is used when regType is one of below: 552 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC 553 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM 554 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP 555 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP 556 * NV2080_CTRL_GPU_REG_OP_TYPE_FB 557 * When regGroupMask is used, the regOffset MUST be the first register in 558 * an array. 559 * regSubGroupMask 560 * This field specifies which registers inside a group should be updated. 561 * This field is used for updating SM registers when regType is: 562 * NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC 563 * When regSubGroupMask is used, regOffset MUST be the first register in an 564 * array AND also the first one in sub array. regGroupMask specifies 565 * TPC(X) and regSubGroupMask specifies SM_CTX_N(Y) 566 * regStatus 567 * This field returns the completion status for the associated register 568 * operation in the form of a bitmask. Possible status values for this 569 * field are: 570 * NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS 571 * This value indicates the operation completed successfully. 572 * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP 573 * This bit value indicates that the regOp value is not valid. 574 * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE 575 * This bit value indicates that the regType value is not valid. 576 * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET 577 * This bit value indicates that the regOffset value is invalid. 578 * The regOffset value must be within the legal BAR0 range for the 579 * associated GPU and must target a supported register with a 580 * supported operation. 581 * NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OFFSET 582 * This bit value indicates that the operation to the register 583 * specified by the regOffset value is not supported for the 584 * associated GPU. 585 * NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK 586 * This bit value indicates that the regTpcMask value is invalid. 587 * The regTpcMask must be a subset of TPCs that are enabled on the 588 * associated GPU. 589 * NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS 590 * The caller does not have access to the register at given offset 591 * regOffset 592 * This field specifies the register offset to access. The specified 593 * offset must be a valid BAR0 offset for the associated GPU. 594 * regValueLo 595 * This field contains the low 32bits of the register value. 596 * For read operations, this value returns the current value of the 597 * register specified by regOffset. For write operations, this field 598 * specifies the logical OR value applied to the current value 599 * contained in the register specified by regOffset. 600 * regValueHi 601 * This field contains the high 32bits of the register value. 602 * For read operations, this value returns the current value of the 603 * register specified by regOffset + 4. For write operations, this field 604 * specifies the logical OR value applied to the current value 605 * contained in the register specified by regOffset + 4. 606 * regAndNMaskLo 607 * This field contains the mask used to clear a desired field from 608 * the current value contained in the register specified by regOffsetLo. 609 * This field is negated and ANDed to this current register value. 610 * This field is only used for write operations. This field is ignored 611 * for read operations. 612 * regAndNMaskHi 613 * This field contains the mask used to clear a desired field from 614 * the current value contained in the register specified by regOffsetHi. 615 * This field is negated and ANDed to this current register value. 616 * This field is only used for write operations. This field is ignored 617 * for read operations. 618 */ 619 typedef struct NV2080_CTRL_GPU_REG_OP { 620 NvU8 regOp; 621 NvU8 regType; 622 NvU8 regStatus; 623 NvU8 regQuad; 624 NvU32 regGroupMask; 625 NvU32 regSubGroupMask; 626 NvU32 regOffset; 627 NvU32 regValueHi; 628 NvU32 regValueLo; 629 NvU32 regAndNMaskHi; 630 NvU32 regAndNMaskLo; 631 } NV2080_CTRL_GPU_REG_OP; 632 633 /* valid regOp values */ 634 #define NV2080_CTRL_GPU_REG_OP_READ_32 (0x00000000U) 635 #define NV2080_CTRL_GPU_REG_OP_WRITE_32 (0x00000001U) 636 #define NV2080_CTRL_GPU_REG_OP_READ_64 (0x00000002U) 637 #define NV2080_CTRL_GPU_REG_OP_WRITE_64 (0x00000003U) 638 #define NV2080_CTRL_GPU_REG_OP_READ_08 (0x00000004U) 639 #define NV2080_CTRL_GPU_REG_OP_WRITE_08 (0x00000005U) 640 641 /* valid regType values */ 642 #define NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL (0x00000000U) 643 #define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX (0x00000001U) 644 #define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC (0x00000002U) 645 #define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM (0x00000004U) 646 #define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP (0x00000008U) 647 #define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP (0x00000010U) 648 #define NV2080_CTRL_GPU_REG_OP_TYPE_FB (0x00000020U) 649 #define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD (0x00000040U) 650 #define NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE (0x00000080U) 651 652 /* valid regStatus values (note: NvU8 ie, 1 byte) */ 653 #define NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS (0x00U) 654 #define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP (0x01U) 655 #define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE (0x02U) 656 #define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET (0x04U) 657 #define NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP (0x08U) 658 #define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK (0x10U) 659 #define NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS (0x20U) 660 661 /* 662 * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS 663 * 664 * This command is used to submit a buffer containing one or more 665 * NV2080_CTRL_GPU_REG_OP structures for processing. Each entry in the 666 * buffer specifies a single read or write operation. Each entry is checked 667 * for validity in an initial pass over the buffer with the results for 668 * each operation stored in the corresponding regStatus field. Unless 669 * bNonTransactional flag is set to true, if any invalid entries are found 670 * during this initial pass then none of the operations are executed. Entries 671 * are processed in order within each regType with NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL 672 * entries processed first followed by NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX entries. 673 * 674 * hClientTarget 675 * This parameter specifies the handle of the client that owns the channel 676 * specified by hChannelTarget. If this parameter is set to 0 then the set 677 * of channel-specific register operations are applied to all current and 678 * future channels. 679 * hChannelTarget 680 * This parameter specifies the handle of the target channel (or channel 681 * group) object instance to which channel-specific register operations are 682 * to be directed. If hClientTarget is set to 0 then this parameter must 683 * also be set to 0. 684 * bNonTransactional 685 * This field specifies if command is non-transactional i.e. if set to 686 * true, all the valid operations will be executed. 687 * reserved00 688 * This parameter is reserved for future use. It should be initialized to 689 * zero for correct operation. 690 * regOpCount 691 * This field specifies the number of entries on the caller's regOps 692 * list. 693 * regOps 694 * This field specifies a pointer in the caller's address space 695 * to the buffer from which the desired register information is to be 696 * retrieved. This buffer must be at least as big as regInfoCount 697 * multiplied by the size of the NV2080_CTRL_GPU_REG_OP structure. 698 * grRouteInfo 699 * This parameter specifies the routing information used to 700 * disambiguate the target GR engine. When SMC is enabled, this 701 * is a mandatory parameter. 702 * 703 * Possible status values returned are: 704 * NV_OK 705 * NV_ERR_INVALID_ARGUMENT 706 * NV_ERR_INVALID_PARAM_STRUCT 707 */ 708 #define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */ 709 710 #define NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0x22U) 711 712 typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS { 713 NvHandle hClientTarget; 714 NvHandle hChannelTarget; 715 NvU32 bNonTransactional; 716 NvU32 reserved00[2]; 717 NvU32 regOpCount; 718 NV_DECLARE_ALIGNED(NvP64 regOps, 8); 719 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 720 } NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS; 721 722 /* 723 * NV2080_CTRL_CMD_GPU_GET_ENGINES 724 * 725 * Returns a list of supported engine types along with the number of instances 726 * of each type. Querying with engineList NULL returns engineCount. 727 * 728 * engineCount 729 * This field specifies the number of entries on the caller's engineList 730 * field. 731 * engineList 732 * This field is a pointer to a buffer of NvU32 values representing the 733 * set of engines supported by the associated subdevice. Refer to cl2080.h 734 * for the complete set of supported engine types. 735 * 736 * Possible status values returned are: 737 * NV_OK 738 */ 739 #define NV2080_CTRL_CMD_GPU_GET_ENGINES (0x20800123U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID" */ 740 741 #define NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID (0x23U) 742 743 typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS { 744 NvU32 engineCount; 745 NV_DECLARE_ALIGNED(NvP64 engineList, 8); 746 } NV2080_CTRL_GPU_GET_ENGINES_PARAMS; 747 748 #define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */ 749 750 /* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */ 751 #define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x40U 752 753 #define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U) 754 755 typedef struct NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS { 756 NvU32 engineCount; 757 NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; 758 } NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS; 759 760 /* 761 * NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST 762 * 763 * Returns a list of classes supported by a given engine type. 764 * 765 * engineType 766 * This field specifies the engine type being queried. 767 * NV2080_CTRL_ENGINE_TYPE_ALLENGINES will return classes 768 * supported by all engines. 769 * 770 * numClasses 771 * This field specifies the number of classes supported by 772 * engineType. 773 * 774 * classList 775 * This field is an array containing the list of supported 776 * classes. Is of type (NvU32*) 777 * 778 * Possible status values returned are: 779 * NV_OK 780 * NV_ERR_INVALID_ARGUMENT 781 * NV_ERR_INVALID_PARAM_STRUCT 782 */ 783 #define NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST (0x20800124U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID" */ 784 785 #define NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID (0x24U) 786 787 typedef struct NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS { 788 NvU32 engineType; 789 NvU32 numClasses; 790 NV_DECLARE_ALIGNED(NvP64 classList, 8); 791 } NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS; 792 793 794 /* 795 * NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO 796 * 797 * This command returns the fault properties of the specified engine type. 798 * 799 * engineType 800 * Input parameter. 801 * This field specifies the engine type being queried. 802 * Engine type is specified using the NV2080_ENGINE_TYPE_* defines in cl2080.h. 803 * The list of engines supported by a chip can be got using the 804 * NV2080_CTRL_CMD_GPU_GET_ENGINES ctrl call. 805 * 806 * mmuFaultId 807 * Output parameter. 808 * This field returns the MMU fault ID for the specified engine. 809 * If the engine supports subcontext, this field provides the base fault id. 810 * 811 * bSubcontextSupported 812 * Output parameter. 813 * Returns TRUE if subcontext faulting is supported by the engine. 814 * Engine that support subcontext use fault IDs in the range [mmuFaultId, mmuFaultId + maxSubCtx). 815 * "maxSubctx" can be found using the NV2080_CTRL_FIFO_INFO ctrl call with 816 * NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP as the index. 817 * 818 * Possible status values returned are: 819 * NV_OK 820 * NV_ERR_INVALID_ARGUMENT 821 * NV_ERR_INVALID_PARAM_STRUCT 822 */ 823 #define NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO (0x20800125U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID" */ 824 825 #define NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID (0x25U) 826 827 typedef struct NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS { 828 NvU32 engineType; 829 NvU32 mmuFaultId; 830 NvBool bSubcontextSupported; 831 } NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS; 832 833 834 835 /* 836 * NV2080_CTRL_CMD_GPU_QUERY_MODE 837 * 838 * This command is used to detect the mode of the GPU associated with the 839 * subdevice. 840 * 841 * mode 842 * This parameter returns the current mode of GPU. Legal values for 843 * this parameter include: 844 * NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE 845 * The GPU is currently operating in graphics mode. 846 * NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE 847 * The GPU is currently operating in compute mode. 848 * NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE 849 * The current mode of the GPU could not be determined. 850 * 851 * Possible status values returned are: 852 * NV_OK 853 */ 854 #define NV2080_CTRL_CMD_GPU_QUERY_MODE (0x20800128U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID" */ 855 856 /* valid mode parameter values */ 857 #define NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE (0x00000000U) 858 #define NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE (0x00000001U) 859 #define NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE (0x00000002U) 860 861 #define NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID (0x28U) 862 863 typedef struct NV2080_CTRL_GPU_QUERY_MODE_PARAMS { 864 NvU32 mode; 865 } NV2080_CTRL_GPU_QUERY_MODE_PARAMS; 866 867 868 869 /*! 870 * NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY 871 * Data block describing a virtual context buffer to be promoted 872 * 873 * gpuPhysAddr [IN] 874 * GPU Physical Address for the buffer 875 * gpuVirtAddr [IN] 876 * GPU Virtual Address for the buffer 877 * size[IN] 878 * Size of this virtual context buffer 879 * physAttr [IN] 880 * Physical memory attributes (aperture, cacheable) 881 * bufferId [IN] 882 * Virtual context buffer type, data type NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_* 883 * bInitialize [IN] 884 * Flag indicating that this virtual context buffer should be initialized prior to promotion. 885 * The client must clear (memset) the buffer to 0x0 prior to initialization. 886 * Following buffers need initialization: 887 * 1. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN 888 * 2. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH 889 * 3. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP 890 * 4. NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP 891 * bNonmapped [IN] 892 * Flag indicating that the virtual address is not to be promoted with this 893 * call. It is illegal to set this flag and not set bInitialize. 894 */ 895 typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY { 896 NV_DECLARE_ALIGNED(NvU64 gpuPhysAddr, 8); 897 NV_DECLARE_ALIGNED(NvU64 gpuVirtAddr, 8); 898 NV_DECLARE_ALIGNED(NvU64 size, 8); 899 NvU32 physAttr; 900 NvU16 bufferId; 901 NvU8 bInitialize; 902 NvU8 bNonmapped; 903 } NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY; 904 905 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN 0U 906 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM 1U 907 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH 2U 908 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB 3U 909 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL 4U 910 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB 5U 911 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL 6U 912 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL 7U 913 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK 8U 914 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT 9U 915 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP 10U 916 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP 11U 917 #define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP 12U 918 919 #define NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES 16U 920 921 /* 922 * NV2080_CTRL_CMD_GPU_PROMOTE_CTX 923 * 924 * This command is used to promote a Virtual Context 925 * 926 * engineType 927 * Engine Virtual Context is for 928 * hClient 929 * Client Handle for hVirtMemory 930 * ChID 931 * Hw Channel -- Actually hw index for channel (deprecated) 932 * hChanClient 933 * The client handle for hObject 934 * hObject 935 * Passed in object handle for either a single channel or a channel group 936 * hVirtMemory 937 * Virtual Address handle to map Virtual Context to 938 * virtAddress 939 * Virtual Address to map Virtual Context to 940 * size 941 * size of the Virtual Context 942 * entryCount 943 * Number of valid entries in the promotion entry list 944 * promoteEntry 945 * List of context buffer entries to issue promotions for. 946 * 947 * When not using promoteEntry, only hVirtMemory or (virtAddress, size) should be 948 * specified, the code cases based on hVirtMemory(NULL vs non-NULL) so 949 * if both are specified, hVirtMemory has precedence. 950 * 951 * Possible status values returned are: 952 * NV_OK 953 * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval 954 * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. 955 * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. 956 */ 957 #define NV2080_CTRL_CMD_GPU_PROMOTE_CTX (0x2080012bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID" */ 958 959 #define NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID (0x2BU) 960 961 typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS { 962 NvU32 engineType; 963 NvHandle hClient; 964 NvU32 ChID; 965 NvHandle hChanClient; 966 NvHandle hObject; 967 NvHandle hVirtMemory; 968 NV_DECLARE_ALIGNED(NvU64 virtAddress, 8); 969 NV_DECLARE_ALIGNED(NvU64 size, 8); 970 NvU32 entryCount; 971 // C form: NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES]; 972 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES], 8); 973 } NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS; 974 typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *PNV2080_CTRL_GPU_PROMOTE_CTX_PARAMS; 975 976 /* 977 * NV2080_CTRL_CMD_GPU_EVICT_CTX 978 * 979 * This command is used to evict a Virtual Context 980 * 981 * engineType 982 * Engine Virtual Context is for 983 * hClient 984 * Client Handle 985 * ChID 986 * Hw Channel -- Actually hw index for channel (deprecated) 987 * hChanClient 988 * Client handle for hObject 989 * hObject 990 * Passed in object handle for either a single channel or a channel group 991 * 992 * Possible status values returned are: 993 * NV_OK 994 * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval 995 * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. 996 * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. 997 */ 998 #define NV2080_CTRL_CMD_GPU_EVICT_CTX (0x2080012cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID" */ 999 1000 #define NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID (0x2CU) 1001 1002 typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS { 1003 NvU32 engineType; 1004 NvHandle hClient; 1005 NvU32 ChID; 1006 NvHandle hChanClient; 1007 NvHandle hObject; 1008 } NV2080_CTRL_GPU_EVICT_CTX_PARAMS; 1009 typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS *PNV2080_CTRL_GPU_EVICT_CTX_PARAMS; 1010 1011 /* 1012 * NV2080_CTRL_CMD_GPU_INITIALIZE_CTX 1013 * 1014 * This command is used to initialize a Virtual Context. The ctx buffer must be 1015 * cleared (zerod) by the caller prior to invoking this method. 1016 * 1017 * engineType 1018 * Engine Virtual Context is for 1019 * hClient 1020 * Client Handle for the hVirtMemory 1021 * ChID 1022 * Hw channel -- Actually channel index (deprecated) 1023 * hChanClient 1024 * The client handle for hObject 1025 * hObject 1026 * Passed in object handle for either a single channel or a channel group 1027 * hVirtMemory 1028 * Virtual Address where to map Virtual Context to 1029 * physAddress 1030 * Physical offset in FB to use as Virtual Context 1031 * physAttr 1032 * Physical memory attributes 1033 * hDmaHandle 1034 * Dma Handle when using discontiguous context buffers 1035 * index 1036 * Start offset in Virtual DMA Context 1037 * size 1038 * Size of the Virtual Context 1039 * 1040 * Only hVirtMemory or size should be specified, the code cases based on hVirtMemory 1041 * (NULL vs non-NULL) so if both are specified, hVirtMemory has precedence. 1042 * 1043 * Possible status values returned are: 1044 * NV_OK 1045 * NV_ERR_NOT_SUPPORTED - The Class does not support version info retrieval 1046 * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. 1047 * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. 1048 */ 1049 #define NV2080_CTRL_CMD_GPU_INITIALIZE_CTX (0x2080012dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID" */ 1050 1051 #define NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID (0x2DU) 1052 1053 typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS { 1054 NvU32 engineType; 1055 NvHandle hClient; 1056 NvU32 ChID; 1057 NvHandle hChanClient; 1058 NvHandle hObject; 1059 NvHandle hVirtMemory; 1060 NV_DECLARE_ALIGNED(NvU64 physAddress, 8); 1061 NvU32 physAttr; 1062 NvHandle hDmaHandle; 1063 NvU32 index; 1064 NV_DECLARE_ALIGNED(NvU64 size, 8); 1065 } NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS; 1066 typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS; 1067 1068 #define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE 1:0 1069 #define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM (0x00000000U) 1070 #define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS (0x00000001U) 1071 #define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS (0x00000002U) 1072 1073 #define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE 2:2 1074 #define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES (0x00000000U) 1075 #define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO (0x00000001U) 1076 1077 /* 1078 * NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX - Tells RM Whether this Ctx buffer needs to 1079 * do a full initialization (Load the golden image). When a context is promoted on a different 1080 * channel than it was originally inited, the client can use this flag to tell RM 1081 * that this is an already inited Context. In such cases RM will update the internal state 1082 * to update the context address and state variables. 1083 */ 1084 1085 #define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX 3:3 1086 #define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO (0x00000000U) 1087 #define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES (0x00000001U) 1088 1089 /* 1090 * NV2080_CTRL_CMD_CPU_QUERY_ECC_INTR 1091 * Queries the top level ECC PMC PRI register 1092 * TODO remove these parameters, tracked in bug #1975721 1093 */ 1094 #define NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR (0x2080012eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2E" */ 1095 1096 typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS { 1097 NvU32 eccIntrStatus; 1098 } NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS; 1099 1100 /** 1101 * NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS 1102 * 1103 * This command is used to query the ECC status of a GPU by a subdevice 1104 * handle. Please see the NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS 1105 * data structure description below for details on the data reported 1106 * per hardware unit. 1107 * 1108 * units 1109 * Array of structures used to describe per-unit state 1110 * 1111 * flags 1112 * See interface flag definitions below. 1113 * 1114 * Possible status values returned are: 1115 * NV_OK 1116 * NV_ERR_NOT_SUPPORTED 1117 */ 1118 1119 1120 1121 #define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */ 1122 1123 1124 #define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000019U) 1125 1126 1127 1128 // Deprecated do not use 1129 #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE 0:0 1130 #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED (0x00000000U) 1131 #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW (0x00000001U) 1132 1133 #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE 0U 1134 #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE 1U 1135 #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE 2U 1136 1137 /* 1138 * NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS 1139 * 1140 * This structure represents the exception status of a class of per-unit 1141 * exceptions 1142 * 1143 * count 1144 * number of exceptions that have occurred since boot 1145 */ 1146 typedef struct NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS { 1147 NV_DECLARE_ALIGNED(NvU64 count, 8); 1148 } NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS; 1149 1150 /* 1151 * NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS 1152 * 1153 * This structure represents the per-unit ECC exception status 1154 * 1155 * enabled 1156 * ECC enabled yes/no for this unit 1157 * scrubComplete 1158 * Scrub has completed yes/no. A scrub is performed for some units to ensure 1159 * the checkbits are consistent with the protected data. 1160 * supported 1161 * Whether HW supports ECC in this unit for this GPU 1162 * dbe 1163 * Double bit error (DBE) status. The value returned reflects a counter 1164 * that is monotonic, but can be reset by clients. 1165 * dbeNonResettable (deprecated do not use) 1166 * Double bit error (DBE) status, not client resettable. 1167 * sbe 1168 * Single bit error (SBE) status. The value returned reflects a counter 1169 * that is monotonic, but can be reset by clients. 1170 * sbeNonResettable (deprecated do not use) 1171 * Single bit error (SBE) status, not client resettable. 1172 * 1173 */ 1174 typedef struct NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS { 1175 NvBool enabled; 1176 NvBool scrubComplete; 1177 NvBool supported; 1178 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS dbe, 8); 1179 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS dbeNonResettable, 8); 1180 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS sbe, 8); 1181 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS sbeNonResettable, 8); 1182 } NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS; 1183 1184 /* 1185 * NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS 1186 * 1187 * This structure returns ECC exception status and GPU Fatal Poison for all units 1188 * 1189 * units 1190 * This structure represents ECC exception status for all Units. 1191 * bFatalPoisonError 1192 * Whether GPU Fatal poison error occurred in this GPU. This will be set for Ampere_and_later 1193 * uncorrectableError 1194 * Indicates whether any uncorrectable GR ECC errors have occurred. When 1195 * SMC is enabled, uncorrectableError is only valid when the client is 1196 * subscribed to a partition. Check QUERY_ECC_STATUS_UNC_ERR_* 1197 * flags 1198 * Flags passed by caller. Refer NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_* for details. 1199 * grRouteInfo 1200 * SMC partition information. This input is only valid when SMC is 1201 * enabled on Ampere_and_later. 1202 * 1203 */ 1204 #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID (0x2FU) 1205 1206 typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS { 1207 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS units[NV2080_CTRL_GPU_ECC_UNIT_COUNT], 8); 1208 NvBool bFatalPoisonError; 1209 NvU8 uncorrectableError; 1210 NvU32 flags; 1211 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 1212 } NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS; 1213 1214 /* 1215 * NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES 1216 * 1217 * This command sets the compute mode rules for the associated subdevice. The 1218 * default mode is equivalent to NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE. This 1219 * command is available to clients with administrator privileges only. An 1220 * attempt to use this command by a client without administrator privileged 1221 * results in the return of an NV_ERR_INSUFFICIENT_PERMISSIONS status. 1222 * 1223 * rules 1224 * This parameter is used to specify the rules that govern the GPU with 1225 * respect to NV50_COMPUTE objects. Legal values for this parameter include: 1226 * 1227 * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE 1228 * This mode indicate that no special restrictions apply to the 1229 * allocation of NV50_COMPUTE objects. 1230 * 1231 * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE 1232 * This mode means that only one instance of NV50_COMPUTE will be 1233 * allowed at a time. This restriction is enforced at each subsequent 1234 * NV50_COMPUTE allocation attempt. Setting this mode will not affect 1235 * any existing compute programs that may be running. For example, 1236 * if this mode is set while three compute programs are running, then 1237 * all of those programs will be allowed to continue running. However, 1238 * until they all finish running, no new NV50_COMPUTE objects may be 1239 * allocated. User-mode clients should treat this as restricting access 1240 * to a NV50_COMPUTE object to a single thread within a process. 1241 * 1242 * NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED 1243 * This mode means that that GPU is not ever allowed to instantiate an 1244 * NV50_COMPUTE object, and thus cannot run any new compute programs. 1245 * This restriction is enforced at each subsequent NV50_COMPUTE object 1246 * allocation attempt. Setting this mode will not affect any existing 1247 * compute programs that may be running. For example, if this mode is 1248 * set while three compute programs are running, then all of those 1249 * programs will be allowed to continue running. However, no new 1250 * NV50_COMPUTE objects may be allocated. 1251 * 1252 * 1253 * NV2080_CTRL_GPU_COMPUTE_MODE_EXCLUSIVE_COMPUTE_PROCESS 1254 * This mode is identical to EXCLUSIVE_COMPUTE, where only one instance 1255 * of NV50_COMPUTE will be allowed at a time. It is separate from 1256 * EXCLUSIVE_COMPUTE to allow user-mode clients to differentiate 1257 * exclusive access to a compute object from a single thread of a 1258 * process from exclusive access to a compute object from all threads 1259 * of a process. User-mode clients should not limit access to a 1260 * NV50_COMPUTE object to a single thread when the GPU is set to 1261 * EXCLUSIVE_COMPUTE_PROCESS. 1262 * 1263 * An invalid rules parameter value results in the return of an 1264 * NV_ERR_INVALID_ARGUMENT status. 1265 * 1266 * flags 1267 * Reserved. Caller should set this field to zero. 1268 * 1269 * Possible status return values are: 1270 * NV_OK 1271 * NV_ERR_INVALID_ARGUMENT (if an invalid rule number is provided) 1272 * NV_ERR_INSUFFICIENT_PERMISSIONS (if the user is not the Administrator or superuser) 1273 * NV_ERR_NOT_SUPPORTED 1274 */ 1275 #define NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES (0x20800130U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */ 1276 1277 /* valid rules parameter values */ 1278 #define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE (0x00000000U) 1279 #define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE (0x00000001U) 1280 #define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED (0x00000002U) 1281 #define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS (0x00000003U) 1282 1283 #define NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x30U) 1284 1285 typedef struct NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS { 1286 NvU32 rules; 1287 NvU32 flags; 1288 } NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS; 1289 1290 /* 1291 * NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES 1292 * 1293 * This command queries the compute mode rules for the associated subdevice. 1294 * Please see the NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES command, above, for 1295 * details as to what the rules mean. 1296 * 1297 * rules 1298 * Specifies the rules that govern the GPU, with respect to NV50_COMPUTE 1299 * objects. 1300 * 1301 * Possible status return values are: 1302 * NV_OK 1303 * NV_ERR_NOT_SUPPORTED 1304 */ 1305 #define NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES (0x20800131U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */ 1306 1307 #define NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x31U) 1308 1309 typedef struct NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS { 1310 NvU32 rules; 1311 } NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS; 1312 1313 /* 1314 * NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION 1315 * 1316 * This command returns the current ECC configuration setting for 1317 * a GPU given its subdevice handle. The value returned is 1318 * the current ECC setting for the GPU stored in non-volatile 1319 * memory on the board. 1320 * 1321 * currentConfiguration 1322 * The current ECC configuration setting. 1323 * 1324 * defaultConfiguration 1325 * The factory default ECC configuration setting. 1326 * 1327 * Please see the NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS command if 1328 * you wish to determine if ECC is currently enabled. 1329 * 1330 * Possible status return values are: 1331 * NV_OK 1332 * NV_ERR_NOT_SUPPORTED 1333 * NV_ERR_INVALID_STATE 1334 */ 1335 #define NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION (0x20800133U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */ 1336 1337 #define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED (0x00000000U) 1338 #define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED (0x00000001U) 1339 1340 #define NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x33U) 1341 1342 typedef struct NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS { 1343 NvU32 currentConfiguration; 1344 NvU32 defaultConfiguration; 1345 } NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS; 1346 1347 /* 1348 * NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION 1349 * 1350 * This command changes the ECC configuration setting for a GPU 1351 * given its subdevice handle. The value specified is 1352 * stored in non-volatile memory on the board and will take 1353 * effect with the next GPU reset 1354 * 1355 * newConfiguration 1356 * The new configuration setting to take effect with 1357 * the next GPU reset. 1358 * 1359 * Possible status return values are: 1360 * NV_OK 1361 * NV_ERR_INVALID_ARGUMENT 1362 * NV_ERR_NOT_SUPPORTED 1363 */ 1364 #define NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION (0x20800134U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */ 1365 1366 #define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE (0x00000000U) 1367 #define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE (0x00000001U) 1368 1369 #define NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x34U) 1370 1371 typedef struct NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS { 1372 NvU32 newConfiguration; 1373 } NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS; 1374 1375 1376 1377 /* 1378 * NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS 1379 * 1380 * This command resets volatile and/or persistent ECC error 1381 * status information for a GPU given its subdevice 1382 * handle. 1383 * 1384 * statuses 1385 * The ECC error statuses (the current, volatile 1386 * and/or the persistent error counter(s)) to 1387 * be reset by the command. 1388 * flags 1389 * FORCE_PURGE 1390 * Forcibly clean all the ECC InfoROM state if this flag is set 1391 * 1392 * Possible status return values are: 1393 * NV_OK 1394 * NV_ERR_INVALID_ARGUMENT 1395 * NV_ERR_NOT_SUPPORTED 1396 */ 1397 #define NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS (0x20800136U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID" */ 1398 1399 #define NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE (0x00000000U) 1400 #define NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE (0x00000001U) 1401 #define NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE (0x00000002U) 1402 1403 #define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE 0:0 1404 #define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE 0U 1405 #define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE 1U 1406 1407 #define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID (0x36U) 1408 1409 typedef struct NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS { 1410 NvU32 statuses; 1411 NvU8 flags; 1412 } NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS; 1413 1414 /* 1415 * NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO 1416 * 1417 * This command returns a mask of enabled GPCs for the associated GPU. 1418 * 1419 * gpcMask 1420 * This parameter returns a mask of enabled GPCs. Each GPC has an ID 1421 * that's equivalent to the corresponding bit position in the mask. 1422 * 1423 * Possible status values returned are: 1424 * NV_OK 1425 * NV_ERR_NOT_SUPPORTED 1426 * NV_ERR_INVALID_PARAM_STRUCT 1427 */ 1428 #define NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO (0x20800137U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID" */ 1429 1430 #define NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID (0x37U) 1431 1432 typedef struct NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS { 1433 NvU32 gpcMask; 1434 } NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS; 1435 1436 /* 1437 * NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO 1438 * 1439 * This command returns a mask of enabled TPCs for a specified GPC. 1440 * 1441 * gpcId 1442 * This parameter specifies the GPC for which TPC information is 1443 * to be retrieved. If the GPC with this ID is not enabled this command 1444 * will return an tpcMask value of zero. 1445 * 1446 * tpcMask 1447 * This parameter returns a mask of enabled TPCs for the specified GPC. 1448 * Each TPC has an ID that's equivalent to the corresponding bit 1449 * position in the mask. 1450 * 1451 * Possible status values returned are: 1452 * NV_OK 1453 * NV_ERR_NOT_SUPPORTED 1454 * NV_ERR_INVALID_PARAM_STRUCT 1455 */ 1456 #define NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO (0x20800138U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID" */ 1457 1458 #define NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID (0x38U) 1459 1460 typedef struct NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS { 1461 NvU32 gpcId; 1462 NvU32 tpcMask; 1463 } NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS; 1464 1465 /* 1466 * NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO 1467 * 1468 * This command returns a mask of enabled ZCULLs for a specified GPC. 1469 * 1470 * gpcId 1471 * This parameter specifies the GPC for which ZCULL information is to be 1472 * retrieved. If the GPC with this ID is not enabled this command will 1473 * return an zcullMask value of zero. 1474 * 1475 * zcullMask 1476 * This parameter returns a mask of enabled ZCULLs for the specified GPC. 1477 * Each ZCULL has an ID that's equivalent to the corresponding bit 1478 * position in the mask. 1479 * 1480 * Possible status values returned are: 1481 * NV_OK 1482 * NV_ERR_NOT_SUPPORTED 1483 * NV_ERR_INVALID_PARAM_STRUCT 1484 * 1485 * Deprecated: Please use GR based control call 1486 * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK 1487 * 1488 */ 1489 #define NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO (0x20800139U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID" */ 1490 1491 #define NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID (0x39U) 1492 1493 typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS { 1494 NvU32 gpcId; 1495 NvU32 zcullMask; 1496 } NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS; 1497 1498 1499 1500 /* 1501 * NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO 1502 * 1503 * If an InfoROM with a valid OEM Board Object is present, this 1504 * command returns relevant information from the object to the 1505 * caller. 1506 * 1507 * The following data are currently reported: 1508 * 1509 * buildDate 1510 * The board's build date (8 digit BCD in format YYYYMMDD). 1511 * 1512 * marketingName 1513 * The board's marketing name (24 ASCII letters e.g. "Quadro FX5800"). 1514 * 1515 * boardSerialNumber 1516 * The board's serial number. 1517 * 1518 * memoryManufacturer 1519 * The board's memory manufacturer ('S'amsung/'H'ynix/'I'nfineon). 1520 * 1521 * memoryDateCode 1522 * The board's memory datecode (LSB justified ASCII field with 0x00 1523 * denoting empty space). 1524 * 1525 * productPartNumber 1526 * The board's 900 product part number (LSB justified ASCII field with 0x00 1527 * denoting empty space e.g. "900-21228-0208-200"). 1528 * 1529 * boardRevision 1530 * The board's revision (for e.g. A02, B01) 1531 * 1532 * boardType 1533 * The board's type ('E'ngineering/'P'roduction) 1534 * 1535 * board699PartNumber 1536 * The board's 699 product part number (LSB justified ASCII field with 0x00 1537 * denoting empty space e.g. "699-21228-0208-200"). 1538 * 1539 * board965PartNumber 1540 * The board's 965 product part number (LSB justified ASCII field with 0x00 1541 * denoting empty space e.g. "965-21228-0208-200"). 1542 * 1543 * Possible status return values are: 1544 * NV_OK 1545 * NV_ERR_NOT_SUPPORTED 1546 */ 1547 #define NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO (0x2080013fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID" */ 1548 1549 #define NV2080_GPU_MAX_MARKETING_NAME_LENGTH (0x00000018U) 1550 #define NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH (0x00000010U) 1551 #define NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH (0x00000014U) 1552 #define NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH (0x00000006U) 1553 #define NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH (0x00000014U) 1554 1555 #define NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID (0x3FU) 1556 1557 typedef struct NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS { 1558 NvU32 buildDate; 1559 NvU8 marketingName[NV2080_GPU_MAX_MARKETING_NAME_LENGTH]; 1560 NvU8 serialNumber[NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH]; 1561 NvU8 memoryManufacturer; 1562 NvU8 memoryPartID[NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH]; 1563 NvU8 memoryDateCode[NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH]; 1564 NvU8 productPartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; 1565 NvU8 boardRevision[3]; 1566 NvU8 boardType; 1567 NvU8 board699PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; 1568 NvU8 board965PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH]; 1569 } NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS; 1570 1571 1572 1573 /* 1574 * NV2080_CTRL_CMD_GPU_GET_ID 1575 * 1576 * This command returns the gpuId of the associated object. 1577 * 1578 * gpuId 1579 * This field return the gpuId. 1580 * 1581 * Possible status return values are: 1582 * NV_OK 1583 * NV_ERR_NOT_SUPPORTED 1584 */ 1585 #define NV2080_CTRL_CMD_GPU_GET_ID (0x20800142U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID" */ 1586 1587 #define NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID (0x42U) 1588 1589 typedef struct NV2080_CTRL_GPU_GET_ID_PARAMS { 1590 NvU32 gpuId; 1591 } NV2080_CTRL_GPU_GET_ID_PARAMS; 1592 1593 /* 1594 * NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE 1595 * 1596 * This command is used to enable or disable GPU debug mode. While this mode 1597 * is enabled, some client RM calls that can potentially timeout return 1598 * NV_ERR_BUSY_RETRY, signalling the client to try again once GPU 1599 * debug mode is disabled. 1600 * 1601 * mode 1602 * This parameter specifies whether GPU debug mode is to be enabled or 1603 * disabled. Possible values are: 1604 * 1605 * NV2080_CTRL_GPU_DEBUG_MODE_ENABLED 1606 * NV2080_CTRL_GPU_DEBUG_MODE_DISABLED 1607 * 1608 * Possible return status values are 1609 * NV_OK 1610 * NV_ERR_INVALID_ARGUMENT 1611 * 1612 */ 1613 #define NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE (0x20800143U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */ 1614 1615 #define NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x43U) 1616 1617 typedef struct NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS { 1618 NvU32 mode; 1619 } NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS; 1620 1621 #define NV2080_CTRL_GPU_DEBUG_MODE_ENABLED (0x00000001U) 1622 #define NV2080_CTRL_GPU_DEBUG_MODE_DISABLED (0x00000002U) 1623 1624 /* 1625 * NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE 1626 * 1627 * This command is used to query whether debug mode is enabled on the current 1628 * GPU. Please see the description of NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE 1629 * for more details on GPU debug mode. 1630 * 1631 * currentMode 1632 * This parameter returns the state of GPU debug mode for the current GPU. 1633 * Possible values are: 1634 * 1635 * NV2080_CTRL_GPU_DEBUG_MODE_ENABLED 1636 * NV2080_CTRL_GPU_DEBUG_MODE_DISABLED 1637 * 1638 * Possible return status values are 1639 * NV_OK 1640 * NV_ERR_INVALID_ARGUMENT 1641 * 1642 */ 1643 #define NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE (0x20800144U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */ 1644 1645 #define NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x44U) 1646 1647 typedef struct NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS { 1648 NvU32 currentMode; 1649 } NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS; 1650 1651 1652 1653 /* 1654 * NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST 1655 * 1656 * Returns a list of engines that can partner or coexist 1657 * when using the target channel or partnership class. 1658 * This list may include all engines (pre-Kepler), or as few 1659 * as 1 engine (Kepler and beyond). 1660 * 1661 * engineType 1662 * This field specifies the target engine type. 1663 * See cl2080.h for a list of valid engines. 1664 * 1665 * partnershipClassId 1666 * This field specifies the target channel 1667 * or partnership class ID. 1668 * An example of such a class is GF100_CHANNEL_GPFIFO. 1669 * 1670 * runqueue 1671 * This field is an index which indicates the runqueue to 1672 * return the list of supported engines for. This is the 1673 * same field as what NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE 1674 * specifies. This is only valid for TSG. 1675 * 1676 * numPartners; 1677 * This field returns the number of 1678 * valid entries in the partnersList array 1679 * 1680 * partnerList 1681 * This field is an array containing the list of supported 1682 * partner engines types, in no particular order, and 1683 * may even be empty (numPartners = 0). 1684 * See cl2080.h for a list of possible engines. 1685 * 1686 * Possible status values returned are: 1687 * NV_OK 1688 * NV_ERR_INVALID_ARGUMENT 1689 * NV_ERR_INVALID_PARAM_STRUCT 1690 */ 1691 1692 #define NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST (0x20800147U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID" */ 1693 1694 /* this macro specifies the maximum number of partner entries */ 1695 #define NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS (0x00000020U) 1696 1697 #define NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID (0x47U) 1698 1699 typedef struct NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS { 1700 NvU32 engineType; 1701 NvU32 partnershipClassId; 1702 NvU32 runqueue; 1703 NvU32 numPartners; 1704 // C form: NvU32 partnerList[NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS]; 1705 NvU32 partnerList[NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS]; 1706 } NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS; 1707 1708 1709 1710 /* 1711 * NV2080_CTRL_CMD_GPU_GET_GID_INFO 1712 * 1713 * This command returns the GPU ID (GID) string for the associated 1714 * GPU. This value can be useful for GPU identification and security 1715 * system validation. 1716 * 1717 * The GPU ID is a SHA-1 based 16 byte ID, formatted as a 32 character 1718 * hexadecimal string as "GPU-%08x-%04x-%04x-%04x-%012x" (the 1719 * canonical format of a UUID) 1720 * 1721 * The GPU IDs are generated using the ECID, PMC_BOOT_0, and 1722 * PMC_BOOT_42 of the GPU as the hash message. 1723 * 1724 * index 1725 * (Input) "Select which GID set to get." Or so the original documentation 1726 * said. In reality, there is only one GID per GPU, and the implementation 1727 * completely ignores this parameter. You can too. 1728 * 1729 * flags (Input) The _FORMAT* flags designate ascii or binary format. Binary 1730 * format returns the raw bytes of either the 16-byte SHA-1 ID or the 1731 * 32-byte SHA-256 ID. 1732 * 1733 * The _TYPE* flags needs to specify the _SHA1 type. 1734 * 1735 * length 1736 * (Output) Actual GID length, in bytes. 1737 * 1738 * data[NV2080_BUS_MAX_GID_LENGTH] 1739 * (Output) Result buffer: the GID itself, in a format that is determined by 1740 * the "flags" field (described above). 1741 * 1742 * Possible status return values are: 1743 * NV_OK 1744 * NV_ERR_NOT_SUPPORTED 1745 * NV_ERR_INVALID_STATE 1746 */ 1747 #define NV2080_CTRL_CMD_GPU_GET_GID_INFO (0x2080014aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID" */ 1748 1749 /* maximum possible number of bytes of GID information returned */ 1750 #define NV2080_GPU_MAX_GID_LENGTH (0x000000100ULL) 1751 1752 /* maximum possible number of bytes of GID information returned if given the BINARY and SHA1 flags */ 1753 #define NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH (0x000000010ULL) 1754 1755 #define NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID (0x4AU) 1756 1757 typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS { 1758 NvU32 index; 1759 NvU32 flags; 1760 NvU32 length; 1761 NvU8 data[NV2080_GPU_MAX_GID_LENGTH]; 1762 } NV2080_CTRL_GPU_GET_GID_INFO_PARAMS; 1763 1764 /* valid flags values */ 1765 #define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT 1:0 1766 #define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII (0x00000000U) 1767 #define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY (0x00000002U) 1768 1769 #define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE 2:2 1770 #define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1 (0x00000000U) 1771 1772 /* 1773 * NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION 1774 * 1775 * This command can be used by clients to retrieve the version of an 1776 * InfoROM object. 1777 * 1778 * objectType 1779 * This parameter specifies the name of the InfoROM object whose version 1780 * should be queried. 1781 * 1782 * version 1783 * This parameter returns the version of the InfoROM object specified by 1784 * the objectType parameter. 1785 * 1786 * subversion 1787 * This parameter returns the subversion of the InfoROM object specified 1788 * by the objectType parameter. 1789 * 1790 * Possible return status values: 1791 * NV_OK 1792 * NV_ERR_STATE_IN_USE 1793 * NV_ERR_INVALID_ARGUMENT 1794 * NV_ERR_NOT_SUPPORTED 1795 * 1796 */ 1797 #define NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION (0x2080014bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID" */ 1798 1799 #define NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN 3U 1800 1801 #define NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID (0x4BU) 1802 1803 typedef struct NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS { 1804 char objectType[NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN]; 1805 NvU8 version; 1806 NvU8 subversion; 1807 } NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS; 1808 1809 1810 /* 1811 * NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO 1812 * 1813 * This command will specify that system is Optimus enabled. 1814 * 1815 * isOptimusEnabled 1816 * Set NV_TRUE if system is Optimus enabled. 1817 * 1818 * Possible status return values are: 1819 * NV_OK 1820 */ 1821 #define NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO (0x2080014cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID" */ 1822 1823 #define NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID (0x4CU) 1824 1825 typedef struct NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS { 1826 NvBool isOptimusEnabled; 1827 } NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS; 1828 1829 /* 1830 * NV2080_CTRL_CMD_GPU_GET_IP_VERSION 1831 * 1832 * Will return the IP VERSION on the given engine for engines that support 1833 * this capability. 1834 * 1835 * targetEngine 1836 * This parameter specifies the target engine type to query for IP_VERSION. 1837 * 1838 * ipVersion 1839 * This parameter returns the IP VERSION read from the unit's IP_VER 1840 * register. 1841 * 1842 * Possible status values returned are: 1843 * NV_OK 1844 * NV_ERR_INVALID_ARGUMENT 1845 * NV_ERR_NOT_SUPPORTED 1846 */ 1847 1848 #define NV2080_CTRL_CMD_GPU_GET_IP_VERSION (0x2080014dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID" */ 1849 1850 #define NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4DU) 1851 1852 typedef struct NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS { 1853 NvU32 targetEngine; 1854 NvU32 ipVersion; 1855 } NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS; 1856 1857 #define NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY (0x00000001U) 1858 #define NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC (0x00000002U) 1859 #define NV2080_CTRL_GPU_GET_IP_VERSION_PMGR (0x00000003U) 1860 #define NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU (0x00000004U) 1861 #define NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON (0x00000005U) 1862 1863 1864 1865 /* 1866 * NV2080_CTRL_CMD_GPU_ID_ILLUM_SUPPORT 1867 * 1868 * This command returns an indicator which reports if the specified Illumination control 1869 * attribute is supported 1870 * 1871 * Possible status return values are: 1872 * NV_OK 1873 * NV_ERR_NOT_SUPPORTED 1874 */ 1875 #define NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS 0U 1876 #define NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS 1U 1877 #define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT (0x20800153U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID" */ 1878 1879 #define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID (0x53U) 1880 1881 typedef struct NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS { 1882 NvU32 attribute; 1883 NvBool bSupported; 1884 } NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS; 1885 1886 /* 1887 * NV2080_CTRL_CMD_GPU_GET_ID_ILLUM 1888 * 1889 * This command returns the current value of the specified Illumination control attribute. 1890 * 1891 * Possible status return values are: 1892 * NV_OK 1893 * NV_ERR_NOT_SUPPORTED 1894 */ 1895 #define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID" */ 1896 1897 typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS { 1898 NvU32 attribute; 1899 NvU32 value; 1900 } NV2080_CTRL_CMD_GPU_ILLUM_PARAMS; 1901 1902 #define NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID (0x54U) 1903 1904 typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_GET_ILLUM_PARAMS; 1905 1906 /* 1907 * NV2080_CTRL_CMD_GPU_SET_ID_ILLUM 1908 * 1909 * This command sets a new valuefor the specified Illumination control attribute. 1910 * 1911 * Possible status return values are: 1912 * NV_OK 1913 * NV_ERR_NOT_SUPPORTED 1914 */ 1915 #define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */ 1916 1917 #define NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID (0x55U) 1918 1919 typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_SET_ILLUM_PARAMS; 1920 1921 /* 1922 * NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION 1923 * 1924 * This command can be used by clients to retrieve the version of the entire 1925 * InfoROM image. 1926 * 1927 * version 1928 * This parameter returns the version of the InfoROM image as a NULL- 1929 * terminated character string of the form "XXXX.XXXX.XX.XX" where each 1930 * 'X' is an integer character. 1931 * 1932 * Possible status return values are: 1933 * NVOS_STATUS_SUCCES 1934 * NV_ERR_INSUFFICIENT_RESOURCES 1935 * NV_ERR_NOT_SUPPORTED 1936 * NV_ERR_INVALID_DATA 1937 */ 1938 #define NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION (0x20800156U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID" */ 1939 1940 #define NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN 16U 1941 1942 #define NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID (0x56U) 1943 1944 typedef struct NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS { 1945 NvU8 version[NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN]; 1946 } NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS; 1947 1948 /* 1949 * NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT 1950 * 1951 * This command returns whether or not ECC is supported via the InfoROM. 1952 * 1953 * Possible status return values are: 1954 * NV_OK 1955 * NV_ERR_NOT_SUPPORTED 1956 */ 1957 #define NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT (0x20800157U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x57" */ 1958 1959 /* 1960 * NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION 1961 * 1962 * This structure contains information about a single physical bridge. 1963 * 1964 * fwVersion 1965 * This field specifies Firmware Version of the bridge stored in 1966 * bridge EEPROM. 1967 * oemVersion 1968 * This field specifies Oem Version of the firmware stored in 1969 * bridge EEPROM. 1970 * siliconRevision 1971 * This field contains the silicon revision of the bridge hardware. 1972 * It is set by the chip manufacturer. 1973 * hwbcResourceType 1974 * This field specifies the hardware broadcast resource type. 1975 * Value denotes the kind of bridge - PLX or BR04 1976 * 1977 */ 1978 1979 typedef struct NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS { 1980 NvU32 fwVersion; 1981 NvU8 oemVersion; 1982 NvU8 siliconRevision; 1983 NvU8 hwbcResourceType; 1984 } NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS; 1985 1986 /* 1987 * NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO 1988 * 1989 * This command returns physical bridge information in the system. 1990 * Information consists of bridgeCount and a list of bridgeId's. 1991 * The bridge Id's are used by NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION 1992 * to get firmware version, oem version and silicon revision info. 1993 * 1994 * bridgeCount 1995 * This field specifies the number of physical brides present 1996 * in the system. 1997 * hPhysicalBridges 1998 * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. 1999 * In this array, the bridge Id's are stored. 2000 * bridgeList 2001 * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. 2002 * In this array, the bridge version details are stored. 2003 * 2004 * Possible status values returned are: 2005 * NV_OK 2006 * NV_ERR_INVALID_ARGUMENT 2007 * NV_ERR_NOT_SUPPORTED 2008 */ 2009 #define NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO (0x2080015aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID" */ 2010 2011 #define NV2080_CTRL_MAX_PHYSICAL_BRIDGE (100U) 2012 #define NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID (0x5AU) 2013 2014 typedef struct NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS { 2015 NvU8 bridgeCount; 2016 NvHandle hPhysicalBridges[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; 2017 NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; 2018 } NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS; 2019 2020 /* 2021 * NV2080_CTRL_GPU_BRIDGE_VERSION 2022 * 2023 * This structure contains information about a single physical bridge. 2024 * 2025 * bus 2026 * This field specifies the bus id of the bridge. 2027 * device 2028 * This field specifies the device id of the bridge. 2029 * func 2030 * This field specifies the function id of the bridge. 2031 * oemVersion 2032 * This field specifies Oem Version of the firmware stored in 2033 * bridge EEPROM. 2034 * siliconRevision 2035 * This field contains the silicon revision of the bridge hardware. 2036 * It is set by the chip manufacturer. 2037 * hwbcResourceType 2038 * This field specifies the hardware broadcast resource type. 2039 * Value denotes the kind of bridge - PLX or BR04 2040 * domain 2041 * This field specifies the respective domain of the PCI device. 2042 * fwVersion 2043 * This field specifies Firmware Version of the bridge stored in 2044 * bridge EEPROM. 2045 * 2046 * If (fwVersion, oemVersion, siliconRevision) == 0, it would mean that RM 2047 * was unable to fetch the value from the bridge device. 2048 * 2049 */ 2050 2051 typedef struct NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS { 2052 NvU8 bus; 2053 NvU8 device; 2054 NvU8 func; 2055 NvU8 oemVersion; 2056 NvU8 siliconRevision; 2057 NvU8 hwbcResourceType; 2058 NvU32 domain; 2059 NvU32 fwVersion; 2060 } NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS; 2061 2062 /* 2063 * NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU 2064 * 2065 * This command returns information about all the upstream bridges of the GPU. 2066 * Information consists of bridge firmware version and its bus topology. 2067 * 2068 * bridgeCount 2069 * This field specifies the number of physical brides present 2070 * in the system. 2071 * physicalBridgeIds 2072 * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. 2073 * In this array, the bridge Ids are stored. 2074 * bridgeList 2075 * This field specifies an array of size NV2080_CTRL_MAX_PHYSICAL_BRIDGE. 2076 * In this array, the bridge version details are stored. 2077 * 2078 * Possible status values returned are: 2079 * NV_OK 2080 * NV_ERR_INVALID_ARGUMENT 2081 * NV_ERR_NOT_SUPPORTED 2082 */ 2083 #define NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU (0x2080015bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID" */ 2084 2085 #define NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID (0x5BU) 2086 2087 typedef struct NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS { 2088 NvU8 bridgeCount; 2089 NvU32 physicalBridgeIds[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; 2090 NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE]; 2091 } NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS; 2092 2093 /* 2094 * NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS 2095 * 2096 * This command is used to query the status of the HW scrubber. If a scrub is 2097 * in progress then the range which is being scrubbed is also reported back. 2098 * 2099 * scrubberStatus 2100 * Reports the status of the scrubber unit - running/idle. 2101 * 2102 * remainingtimeMs 2103 * If scrubbing is going on, reports the remaining time in milliseconds 2104 * required to finish the scrub. 2105 * 2106 * scrubStartAddr 2107 * This parameter reports the start address of the ongoing scrub if scrub 2108 * is going on, otherwise reports the start addr of the last finished scrub 2109 * 2110 * scrubEndAddr 2111 * This parameter reports the end address of the ongoing scrub if scrub 2112 * is going on, otherwise reports the end addr of the last finished scrub. 2113 * 2114 * Possible status values returned are: 2115 * NV_OK 2116 * NV_ERR_NOT_SUPPORTED 2117 */ 2118 2119 #define NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS (0x2080015fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID" */ 2120 2121 #define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID (0x5FU) 2122 2123 typedef struct NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS { 2124 NvU32 scrubberStatus; 2125 NvU32 remainingTimeMs; 2126 NV_DECLARE_ALIGNED(NvU64 scrubStartAddr, 8); 2127 NV_DECLARE_ALIGNED(NvU64 scrubEndAddr, 8); 2128 } NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS; 2129 2130 /* valid values for scrubber status */ 2131 #define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING (0x00000000U) 2132 #define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE (0x00000001U) 2133 2134 /* 2135 * NV2080_CTRL_CMD_GPU_GET_VPR_CAPS 2136 * 2137 * This command is used to query the VPR capability information for a 2138 * GPU. If VPR is supported, the parameters are filled accordingly. 2139 * The addresses returned are all physical addresses. 2140 * 2141 * minStartAddr 2142 * Returns the minimum start address that can be possible for VPR. 2143 * 2144 * maxEndAddr 2145 * Returns the maximum end address that can be possible for VPR. 2146 * 2147 * Possible status values returned are: 2148 * NV_OK 2149 * NV_ERR_NOT_SUPPORTED 2150 */ 2151 2152 #define NV2080_CTRL_CMD_GPU_GET_VPR_CAPS (0x20800160U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID" */ 2153 2154 #define NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID (0x60U) 2155 2156 typedef struct NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS { 2157 NV_DECLARE_ALIGNED(NvU64 minStartAddr, 8); 2158 NV_DECLARE_ALIGNED(NvU64 maxEndAddr, 8); 2159 } NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS; 2160 2161 2162 2163 /* 2164 * NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR 2165 * 2166 * Communicates to RM to handle GPU Surprise Removal 2167 * Called from client when it receives SR IRP from OS 2168 * Possible status values returned are: 2169 * NVOS_STATUS_SUCCESS 2170 */ 2171 #define NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR (0x20800167U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x67" */ 2172 2173 2174 /* 2175 * NV2080_CTRL_CMD_GPU_GET_PES_INFO 2176 * 2177 * This command provides the PES count and mask of enabled PES for a 2178 * specified GPC. It also returns the TPC to PES mapping information 2179 * for a given GPU. 2180 * 2181 * gpcId[IN] 2182 * This parameter specifies the GPC for which PES information is to be 2183 * retrieved. If the GPC with this ID is not enabled this command will 2184 * return an activePesMask of zero 2185 * 2186 * numPesInGpc[OUT] 2187 * This parameter returns the number of PES in this GPC. 2188 * 2189 * activePesMask[OUT] 2190 * This parameter returns a mask of enabled PESs for the specified GPC. 2191 * Each PES has an ID that is equivalent to the corresponding bit position 2192 * in the mask. 2193 * 2194 * maxTpcPerGpcCount[OUT] 2195 * This parameter returns the max number of TPCs in a GPC. 2196 * 2197 * tpcToPesMap[OUT] 2198 * This array stores the TPC to PES mappings. The value at tpcToPesMap[tpcIndex] 2199 * is the index of the PES it belongs to. 2200 * 2201 * Possible status values returned are: 2202 * NV_OK 2203 * NV_ERR_NOT_SUPPORTED 2204 */ 2205 #define NV2080_CTRL_CMD_GPU_GET_PES_INFO (0x20800168U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID" */ 2206 2207 #define NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT 10U 2208 2209 #define NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID (0x68U) 2210 2211 typedef struct NV2080_CTRL_GPU_GET_PES_INFO_PARAMS { 2212 NvU32 gpcId; 2213 NvU32 numPesInGpc; 2214 NvU32 activePesMask; 2215 NvU32 maxTpcPerGpcCount; 2216 NvU32 tpcToPesMap[NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT]; 2217 } NV2080_CTRL_GPU_GET_PES_INFO_PARAMS; 2218 2219 /* NV2080_CTRL_CMD_GPU_GET_OEM_INFO 2220 * 2221 * If an InfoROM with a valid OEM Object is present, this 2222 * command returns relevant information from the object to the 2223 * caller. 2224 * 2225 * oemInfo 2226 * This array stores information specifically for OEM use 2227 * (e.g. "their own serial number", "lot codes", etc) 2228 * "The byte definition is up to the OEM" 2229 * 2230 * Possible status return values are: 2231 * NV_OK 2232 * NV_ERR_NOT_SUPPORTED 2233 */ 2234 2235 #define NV2080_CTRL_CMD_GPU_GET_OEM_INFO (0x20800169U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID" */ 2236 2237 #define NV2080_GPU_MAX_OEM_INFO_LENGTH (0x000001F8U) 2238 2239 #define NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID (0x69U) 2240 2241 typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS { 2242 NvU8 oemInfo[NV2080_GPU_MAX_OEM_INFO_LENGTH]; 2243 } NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS; 2244 2245 /* 2246 * NV2080_CTRL_CMD_GPU_GET_VPR_INFO 2247 * 2248 * This command is used to query the VPR information for a GPU. 2249 * The following VPR related information can be queried by selecting the queryType: 2250 * 1. The current VPR range. 2251 * 2. The max VPR range ever possible on this GPU. 2252 * 2253 * queryType [in] 2254 * This input parameter is used to select the type of information to query. 2255 * Possible values for this parameter are: 2256 * 1. NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS: Use this to query the 2257 * max VPR range ever possible on this GPU. 2258 * 2. NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE: Use this to query 2259 * the current VPR range on this GPU. 2260 * 2261 * bVprEnabled [out] 2262 * For query type "NV2080_CTRL_GPU_GET_VPR_INFO_CUR_RANGE", this parameter 2263 * returns if VPR is currently enabled or not. 2264 * 2265 * vprStartAddress [out] 2266 * For NV2080_CTRL_GPU_GET_VPR_INFO_CAPS, it returns minimum allowed VPR start address. 2267 * For NV2080_CTRL_GPU_GET_VPR_INFO_RANGE, it returns current VPR start address. 2268 * 2269 * vprEndAddress [out] 2270 * For NV2080_CTRL_GPU_GET_VPR_INFO_CAPS, it returns maximum allowed VPR end address. 2271 * For NV2080_CTRL_GPU_GET_VPR_INFO_RANGE, it returns current VPR end address. 2272 * 2273 * Possible status values returned are: 2274 * NV_OK 2275 * NV_ERR_NOT_SUPPORTED 2276 */ 2277 #define NV2080_CTRL_CMD_GPU_GET_VPR_INFO (0x2080016bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */ 2278 2279 2280 typedef enum NV2080_CTRL_VPR_INFO_QUERY_TYPE { 2281 NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS = 0, 2282 NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE = 1, 2283 } NV2080_CTRL_VPR_INFO_QUERY_TYPE; 2284 2285 #define NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID (0x6BU) 2286 2287 typedef struct NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS { 2288 NV2080_CTRL_VPR_INFO_QUERY_TYPE queryType; 2289 NvBool bIsVprEnabled; 2290 NV_DECLARE_ALIGNED(NvU64 vprStartAddressInBytes, 8); 2291 NV_DECLARE_ALIGNED(NvU64 vprEndAddressInBytes, 8); 2292 } NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS; 2293 2294 /* 2295 * NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY 2296 * 2297 * This command is used to query the encoder capacity of the GPU. 2298 * 2299 * queryType [in] 2300 * This input parameter is used to select the type of information to query. 2301 * Possible values for this parameter are: 2302 * 1. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264: Use this to query the 2303 * H.264 encoding capacity on this GPU. 2304 * 2. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC: Use this to query the 2305 * H.265/HEVC encoding capacity on this GPU. 2306 * 3. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1: Use this to query the 2307 * AV1 encoding capacity on this GPU. 2308 * 2309 * encoderCapacity [out] 2310 * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance 2311 * may be minimal for this GPU and software should fall back to CPU-based encode. 2312 * 2313 * Possible status values returned are: 2314 * NV_OK 2315 * NV_ERR_INVALID_ARGUMENT 2316 */ 2317 2318 #define NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY (0x2080016cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ 2319 2320 typedef enum NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE { 2321 NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = 0, 2322 NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = 1, 2323 NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1 = 2, 2324 } NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE; 2325 2326 #define NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x6CU) 2327 2328 typedef struct NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS { 2329 NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE queryType; 2330 NvU32 encoderCapacity; 2331 } NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS; 2332 2333 /* 2334 * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS 2335 * 2336 * This command is used to retrieve the GPU's count of encoder sessions, 2337 * trailing average FPS and encode latency over all active sessions. 2338 * 2339 * encoderSessionCount 2340 * This field specifies count of all active encoder sessions on this GPU. 2341 * 2342 * averageEncodeFps 2343 * This field specifies the average encode FPS for this GPU. 2344 * 2345 * averageEncodeLatency 2346 * This field specifies the average encode latency in microseconds for this GPU. 2347 * 2348 * Possible status values returned are: 2349 * NV_OK 2350 * NV_ERR_INVALID_ARGUMENT 2351 */ 2352 #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS (0x2080016dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */ 2353 2354 #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x6DU) 2355 2356 typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS { 2357 NvU32 encoderSessionCount; 2358 NvU32 averageEncodeFps; 2359 NvU32 averageEncodeLatency; 2360 } NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS; 2361 2362 #define NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES 0x200U // 512 entries. 2363 2364 /* 2365 * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO 2366 * 2367 * This command returns NVENC software sessions information for the associate GPU. 2368 * Request to retrieve session information use a list of one or more 2369 * NV2080_CTRL_NVENC_SW_SESSION_INFO structures. 2370 * 2371 * sessionInfoTblEntry 2372 * This field specifies the number of entries on the that are filled inside 2373 * sessionInfoTbl. Max value of this field once returned from RM would be 2374 * NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES, 2375 * 2376 * sessionInfoTbl 2377 * This field specifies a pointer in the caller's address space 2378 * to the buffer into which the NVENC session information is to be returned. 2379 * When buffer is NULL, RM assume that client is querying sessions count value 2380 * and return the current encoder session counts in sessionInfoTblEntry field. 2381 * To get actual buffer data, client should allocate sessionInfoTbl of size 2382 * NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES multiplied by the 2383 * size of the NV2080_CTRL_NVENC_SW_SESSION_INFO structure. RM will fill the 2384 * current session data in sessionInfoTbl buffer and then update the 2385 * sessionInfoTblEntry to reflect current session count value. 2386 * 2387 * Possible status values returned are: 2388 * NV_OK 2389 * NV_ERR_NO_MEMORY 2390 * NV_ERR_INVALID_LOCK_STATE 2391 * NV_ERR_INVALID_ARGUMENT 2392 */ 2393 2394 typedef struct NV2080_CTRL_NVENC_SW_SESSION_INFO { 2395 NvU32 processId; 2396 NvU32 subProcessId; 2397 NvU32 sessionId; 2398 NvU32 codecType; 2399 NvU32 hResolution; 2400 NvU32 vResolution; 2401 NvU32 averageEncodeFps; 2402 NvU32 averageEncodeLatency; 2403 } NV2080_CTRL_NVENC_SW_SESSION_INFO; 2404 2405 #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x6EU) 2406 2407 typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS { 2408 NvU32 sessionInfoTblEntry; 2409 NV_DECLARE_ALIGNED(NvP64 sessionInfoTbl, 8); 2410 } NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS; 2411 2412 #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO (0x2080016eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */ 2413 2414 /* 2415 * NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR 2416 * 2417 * The command sets fabric base address which represents top N bits of a 2418 * peer memory address. These N bits will be used to index NvSwitch routing 2419 * tables to forward peer memory accesses to associated GPUs. 2420 * 2421 * The command is available to clients with administrator privileges only. 2422 * An attempt to use this command by a client without administrator privileged 2423 * results in the return of NV_ERR_INSUFFICIENT_PERMISSIONS status. 2424 * 2425 * The command allows to set fabricAddr once in a lifetime of a GPU. A GPU must 2426 * be destroyed in order to re-assign a different fabricAddr. An attempt to 2427 * re-assign address without destroying a GPU would result in the return of 2428 * NV_ERR_STATE_IN_USE status. 2429 * 2430 * fabricBaseAddr[IN] 2431 * - An address with at least 32GB alignment. 2432 * 2433 * Possible status values returned are: 2434 * NV_OK 2435 * NV_ERR_INVALID_ARGUMENT 2436 * NV_ERR_INSUFFICIENT_PERMISSIONS 2437 * NV_ERR_NOT_SUPPORTED 2438 * NV_ERR_STATE_IN_USE 2439 */ 2440 2441 #define NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID (0x6FU) 2442 2443 typedef struct NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS { 2444 NV_DECLARE_ALIGNED(NvU64 fabricBaseAddr, 8); 2445 } NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS; 2446 2447 #define NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR (0x2080016fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */ 2448 2449 /* 2450 * NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT 2451 * 2452 * The command will trigger the specified interrupt on the host from a guest. 2453 * 2454 * handle[IN] 2455 * - An opaque handle that will be passed in along with the interrupt 2456 * 2457 * Possible status values returned are: 2458 * NV_OK 2459 * NV_ERR_INVALID_ARGUMENT 2460 * NV_ERR_NOT_SUPPORTED 2461 */ 2462 2463 #define NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID (0x72U) 2464 2465 typedef struct NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS { 2466 NvU32 handle; 2467 } NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS; 2468 2469 #define NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT (0x20800172U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID" */ 2470 2471 /* 2472 * NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS 2473 * 2474 * This control call is to query the status of gpu function registers 2475 * 2476 * statusMask[IN] 2477 * - Input mask of required status registers 2478 * xusbData[OUT] 2479 * - data from querying XUSB status register 2480 * ppcData[OUT] 2481 * - data from querying PPC status register 2482 * 2483 * Possible status values returned are: 2484 * NV_OK 2485 * NV_ERR_INVALID_ARGUMENT 2486 * NV_ERR_NOT_SUPPORTED 2487 */ 2488 2489 2490 2491 #define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID (0x73U) 2492 2493 typedef struct NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS { 2494 NvU32 statusMask; 2495 NvU32 xusbData; 2496 NvU32 ppcData; 2497 } NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS; 2498 2499 #define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS (0x20800173U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID" */ 2500 2501 /* 2502 * NV2080_CTRL_GPU_PARTITION_SPAN 2503 * 2504 * This struct represents the span of a memory partition, which represents the 2505 * slices a given partition occupies (or may occupy) within a fixed range which 2506 * is defined per-chip. A partition containing more resources will cover more 2507 * GPU slices and therefore cover a larger span. 2508 * 2509 * lo 2510 * - The starting unit of this span, inclusive 2511 * 2512 * hi 2513 * - The ending unit of this span, inclusive 2514 * 2515 */ 2516 typedef struct NV2080_CTRL_GPU_PARTITION_SPAN { 2517 NV_DECLARE_ALIGNED(NvU64 lo, 8); 2518 NV_DECLARE_ALIGNED(NvU64 hi, 8); 2519 } NV2080_CTRL_GPU_PARTITION_SPAN; 2520 2521 #define NV_GI_UUID_LEN 16U 2522 2523 /* 2524 * NV2080_CTRL_GPU_SET_PARTITION_INFO 2525 * 2526 * This command partitions a GPU into different SMC-Memory partitions. 2527 * The command will configure HW partition table to create work and memory 2528 * isolation. 2529 * 2530 * The command is available to clients with administrator privileges only. 2531 * An attempt to use this command by a client without administrator privileged 2532 * results in the return of NV_ERR_INSUFFICIENT_PERMISSIONS status. 2533 * 2534 * The command allows partitioning an invalid partition only. An attempt to 2535 * re-partition a valid partition will resule in NV_ERR_STATE_IN_USE. 2536 * Repartitioning can be done only if a partition has been destroyed/invalidated 2537 * before re-partitioning. 2538 * 2539 * swizzId[IN/OUT] 2540 * - PartitionID associated with a newly created partition. Input in case 2541 * of partition invalidation. 2542 * 2543 * uuid[OUT] 2544 * - Uuid of a newly created partition. 2545 * 2546 * partitionFlag[IN] 2547 * - Flags to determine if GPU is requested to be partitioned in FULL, 2548 * HALF, QUARTER or ONE_EIGHTHED and whether the partition requires 2549 * any additional resources. 2550 * When flags include NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 2551 * partition will be created with at least one video decode, jpeg and 2552 * optical flow engines. This flag is valid only for partitions with 2553 * a single GPC. 2554 * 2555 * bValid[IN] 2556 * - NV_TRUE if creating a partition. NV_FALSE if destroying a partition. 2557 * 2558 * placement[IN] 2559 * - Optional placement span to allocate the partition into. Valid 2560 * placements are returned from NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY. 2561 * The partition flag NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN must 2562 * be set for this parameter to be used. If the flag is set and the given 2563 * placement is not valid, an error will be returned. 2564 * 2565 * Possible status values returned are: 2566 * NV_OK 2567 * NV_ERR_INVALID_ARGUMENT 2568 * NV_ERR_INSUFFICIENT_PERMISSIONS 2569 * NV_ERR_NOT_SUPPORTED 2570 * NV_ERR_STATE_IN_USE 2571 */ 2572 typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO { 2573 NvU32 swizzId; 2574 NvU8 uuid[NV_GI_UUID_LEN]; 2575 NvU32 partitionFlag; 2576 NvBool bValid; 2577 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN placement, 8); 2578 } NV2080_CTRL_GPU_SET_PARTITION_INFO; 2579 2580 #define PARTITIONID_INVALID NV2080_CTRL_GPU_PARTITION_ID_INVALID 2581 #define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFFU 2582 #define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008U 2583 #define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009U 2584 #define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008U 2585 #define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000cU 2586 #define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008U 2587 2588 #define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE 1:0 2589 #define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000U 2590 #define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001U 2591 #define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002U 2592 #define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003U 2593 #define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4U 2594 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE 4:2 2595 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000U 2596 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001U 2597 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002U 2598 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003U 2599 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER 0x00000004U 2600 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000005U 2601 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 6U 2602 2603 2604 #define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 20U 2605 #define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30 2606 #define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U 2607 #define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U 2608 #define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN 31:31 2609 #define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0U 2610 #define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1U 2611 2612 // TODO XXX Bug 2657907 Remove these once clients update 2613 #define NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _FULL) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _FULL)) 2614 #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _HALF)) 2615 #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_HALF)) 2616 #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _QUARTER)) 2617 #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_QUARTER)) 2618 #define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _EIGHTH) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _EIGHTH)) 2619 2620 #define NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID (0x74U) 2621 2622 typedef struct NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS { 2623 NvU32 partitionCount; 2624 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_SET_PARTITION_INFO partitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); 2625 } NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS; 2626 2627 #define NV2080_CTRL_CMD_GPU_SET_PARTITIONS (0x20800174U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID" */ 2628 2629 /* 2630 * NV2080_CTRL_GPU_GET_PARTITION_INFO 2631 * 2632 * This command gets the partition information for requested partitions. 2633 * If GPU is not partitioned, the control call will return NV_ERR_NOT_SUPPORTED. 2634 * 2635 * The command will can return global partition information as well as single 2636 * partition information if global flag is not set. 2637 * In bare-metal user-mode can request all partition info while in virtualization 2638 * plugin should make an RPC with swizzId which is assigned to the requesting 2639 * VM. 2640 * 2641 * swizzId[IN] 2642 * - HW Partition ID associated with the requested partition. 2643 * 2644 * partitionFlag[OUT] 2645 * - partitionFlag that was provided during partition creation. 2646 * 2647 * grEngCount[OUT] 2648 * - Number of SMC engines/GR engines allocated in partition 2649 * GrIDs in a partition will always start from 0 and end at grEngCount-1 2650 * 2651 * veidCount[OUT] 2652 * - VEID Count assigned to a partition. These will be divided across 2653 * SMC engines once CONFIGURE_PARTITION call has been made. The current 2654 * algorithm is to assign veidPerGpc * gpcCountPerSmc to a SMC engine. 2655 * 2656 * smCount[OUT] 2657 * - SMs assigned to a partition. 2658 * 2659 * ceCount[OUT] 2660 * - Copy Engines assigned to a partition. 2661 * 2662 * nvEncCount[OUT] 2663 * - NvEnc Engines assigned to a partition. 2664 * 2665 * nvDecCount[OUT] 2666 * - NvDec Engines assigned to a partition. 2667 * 2668 * nvJpgCount[OUT] 2669 * - NvJpg Engines assigned to a partition. 2670 * 2671 * gpcCount[OUT] 2672 * - Max GPCs assigned to a partition, including the GfxCapable ones. 2673 * 2674 * virtualGpcCount[OUT] 2675 * - Virtualized GPC count assigned to partition 2676 * 2677 * gfxGpcCount[OUT] 2678 * - Max GFX GPCs assigned to a partition. This is a subset of the GPCs incuded in gpcCount. 2679 * 2680 * gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] 2681 * - GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX 2682 * 2683 * virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] 2684 * - Virtualized GPC count associated with every valid SMC/Gr, including the GPCs capable of GFX 2685 * 2686 * gfxGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] 2687 * - GFX GPC count associated with every valid SMC/Gr. This is a subset of the GPCs included in gfxGpcCount 2688 * 2689 * veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS][OUT] 2690 * - VEID count associated with every valid SMC. VEIDs within this SMC 2691 * will start from 0 and go till veidCount[SMC_ID] - 1. 2692 * 2693 * span[OUT] 2694 * - The span covered by this partition 2695 * 2696 * bValid[OUT] 2697 * - NV_TRUE if partition is valid else NV_FALSE. 2698 * 2699 * bPartitionError[OUT] 2700 * - NV_TRUE if partition had poison error which requires drain and reset 2701 * else NV_FALSE. 2702 * 2703 * validCTSIdMask[OUT] 2704 * - Mask of CTS IDs usable by this partition, not reflecting current allocations 2705 * 2706 * validGfxCTSIdMask[OUT] 2707 * - Mask of CTS IDs that contain Gfx capable Grs usable by this partition, not reflecting current allocations 2708 * 2709 * Possible status values returned are: 2710 * NV_OK 2711 * NV_ERR_INVALID_ARGUMENT 2712 * NV_ERR_INSUFFICIENT_PERMISSIONS 2713 * NV_ERR_NOT_SUPPORTED 2714 */ 2715 typedef struct NV2080_CTRL_GPU_GET_PARTITION_INFO { 2716 NvU32 swizzId; 2717 NvU32 partitionFlag; 2718 NvU32 grEngCount; 2719 NvU32 veidCount; 2720 NvU32 smCount; 2721 NvU32 ceCount; 2722 NvU32 nvEncCount; 2723 NvU32 nvDecCount; 2724 NvU32 nvJpgCount; 2725 NvU32 nvOfaCount; 2726 NvU32 gpcCount; 2727 NvU32 virtualGpcCount; 2728 NvU32 gfxGpcCount; 2729 NvU32 gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; 2730 NvU32 virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; 2731 NvU32 gfxGpcPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; 2732 NvU32 veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; 2733 NV_DECLARE_ALIGNED(NvU64 memSize, 8); 2734 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN span, 8); 2735 NvBool bValid; 2736 NvBool bPartitionError; 2737 NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); 2738 NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8); 2739 } NV2080_CTRL_GPU_GET_PARTITION_INFO; 2740 2741 /* 2742 * NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS 2743 * 2744 * queryPartitionInfo[IN] 2745 * - Max sized array of NV2080_CTRL_GPU_GET_PARTITION_INFO to get partition 2746 * Info 2747 * 2748 * bGetAllPartitionInfo[In] 2749 * - Flag to get all partitions info. Only root client will receive all 2750 * partition's info. Non-Root clients should not use this flag 2751 * 2752 * validPartitionCount[Out] 2753 * - Valid partition count which has been filled by RM as part of the call 2754 * 2755 */ 2756 #define NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID (0x75U) 2757 2758 typedef struct NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS { 2759 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_GET_PARTITION_INFO queryPartitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); 2760 NvU32 validPartitionCount; 2761 NvBool bGetAllPartitionInfo; 2762 } NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS; 2763 2764 #define NV2080_CTRL_CMD_GPU_GET_PARTITIONS (0x20800175U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID" */ 2765 2766 /* 2767 * NV2080_CTRL_GPU_CONFIGURE_PARTITION 2768 * 2769 * This command configures a partition by associating GPCs with SMC Engines 2770 * available in that partition. Engines which are to have GPCs assigned to them 2771 * shall not already have any GPCs assigned to them. It is not valid to both 2772 * assign GPCs and remove GPCs as part of a single call to this function. 2773 * 2774 * swizzId[IN] 2775 * - PartitionID for configuring partition. If partition has a valid 2776 * context created, then configuration is not allowed. 2777 * 2778 * gpcCountPerSmcEng[IN] 2779 * - Number of GPCs expected to be configured per SMC. Supported 2780 * configurations are 0, 1, 2, 4 or 8. "0" means a particular SMC 2781 * engine will be disabled with no GPC connected to it. 2782 * 2783 * updateSmcEngMask[IN] 2784 * - Mask tracking valid entries of gpcCountPerSmcEng. A value of 2785 * 0 in bit index i indicates that engine i will keep its current 2786 * configuration. 2787 * 2788 * bUseAllGPCs[IN] 2789 * - Flag specifying alternate configuration mode, indicating that in 2790 * swizzid 0 only, all non-floorswept GPCs should be connected to the 2791 * engine indicated by a raised bit in updateSmcEngMask. Only a single 2792 * engine may be targeted by this operation. The gpcCountPerSmcEng 2793 * parameter should not be used with this flag. 2794 * 2795 * Possible status values returned are: 2796 * NV_OK 2797 * NV_ERR_INVALID_ARGUMENT 2798 * NV_ERR_INSUFFICIENT_PERMISSIONS 2799 * NV_ERR_INSUFFICIENT_RESOURCES 2800 * NV_ERR_NOT_SUPPORTED 2801 * NV_ERR_STATE_IN_USE 2802 */ 2803 #define NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION (0x20800176U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID" */ 2804 2805 #define NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID (0x76U) 2806 2807 typedef struct NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS { 2808 NvU32 swizzId; 2809 NvU32 gpcCountPerSmcEng[NV2080_CTRL_GPU_MAX_SMC_IDS]; 2810 NvU32 updateSmcEngMask; 2811 NvBool bUseAllGPCs; 2812 } NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS; 2813 2814 2815 /* 2816 * NV2080_CTRL_GPU_FAULT_PACKET 2817 * 2818 * This struct represents a GMMU fault packet. 2819 * 2820 */ 2821 #define NV2080_CTRL_GPU_FAULT_PACKET_SIZE 32U 2822 typedef struct NV2080_CTRL_GPU_FAULT_PACKET { 2823 NvU8 data[NV2080_CTRL_GPU_FAULT_PACKET_SIZE]; 2824 } NV2080_CTRL_GPU_FAULT_PACKET; 2825 2826 /* 2827 * NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT 2828 * 2829 * This command reports a nonreplayable fault packet to RM. 2830 * It is only used by UVM. 2831 * 2832 * pFaultPacket[IN] 2833 * - A fault packet that will be later cast to GMMU_FAULT_PACKET *. 2834 * 2835 * Possible status values returned are: 2836 * NV_OK 2837 * NV_ERR_INVALID_ARGUMENT 2838 */ 2839 #define NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT (0x20800177U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID" */ 2840 2841 #define NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID (0x77U) 2842 2843 typedef struct NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS { 2844 NV2080_CTRL_GPU_FAULT_PACKET faultPacket; 2845 } NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS; 2846 2847 /* 2848 * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU 2849 * 2850 * This command is similar to NV2080_CTRL_CMD_GPU_EXEC_REG_OPS, except it is used 2851 * by the VGPU plugin client only. This command provides access to the subset of 2852 * privileged registers. 2853 * 2854 * See confluence page "vGPU UMED Security" for details. 2855 * 2856 */ 2857 #define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID" */ 2858 2859 #define NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID (0x78U) 2860 2861 typedef NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS; 2862 2863 /* 2864 * NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE 2865 * 2866 * This command returns the runlist pri base of the specified engine(s). 2867 * 2868 * engineList 2869 * Input array. 2870 * This array specifies the engines being queried for information. 2871 * The list of engines supported by a chip can be fetched using the 2872 * NV2080_CTRL_CMD_GPU_GET_ENGINES/GET_ENGINES_V2 ctrl call. 2873 * 2874 * runlistPriBase 2875 * Output array. 2876 * Returns the runlist pri base for the specified engines 2877 * Else, will return _NULL when the input is a NV2080_ENGINE_TYPE_NULL 2878 * and will return _ERROR when the control call fails due to an invalid argument 2879 * 2880 * Possible status values returned are: 2881 * NV_OK 2882 * NV_ERR_INVALID_ARGUMENT 2883 * NV_ERR_NOT_SUPPORTED 2884 */ 2885 #define NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE (0x20800179U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID" */ 2886 2887 #define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID (0x79U) 2888 2889 typedef struct NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS { 2890 NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; 2891 NvU32 runlistPriBase[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; 2892 } NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS; 2893 2894 #define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL (0xFFFFFFFFU) 2895 #define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR (0xFFFFFFFBU) 2896 2897 /* 2898 * NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID 2899 * 2900 * This command returns the host hardware defined engine ID of the specified engine(s). 2901 * 2902 * engineList 2903 * Input array. 2904 * This array specifies the engines being queried for information. 2905 * The list of engines supported by a chip can be fetched using the 2906 * NV2080_CTRL_CMD_GPU_GET_ENGINES/GET_ENGINES_V2 ctrl call. 2907 * 2908 * hwEngineID 2909 * Output array. 2910 * Returns the host hardware engine ID(s) for the specified engines 2911 * Else, will return _NULL when the input is a NV2080_ENGINE_TYPE_NULL 2912 * and will return _ERROR when the control call fails due to an invalid argument 2913 * 2914 * Possible status values returned are: 2915 * NV_OK 2916 * NV_ERR_INVALID_ARGUMENT 2917 * NV_ERR_NOT_SUPPORTED 2918 */ 2919 #define NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID (0x2080017aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID" */ 2920 2921 #define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID (0x7AU) 2922 2923 typedef struct NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS { 2924 NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; 2925 NvU32 hwEngineID[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; 2926 } NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS; 2927 2928 #define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL (0xFFFFFFFFU) 2929 #define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR (0xFFFFFFFBU) 2930 2931 /* 2932 * NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS 2933 * 2934 * This command is used to retrieve the GPU's count of FBC sessions, 2935 * average FBC calls and FBC latency over all active sessions. 2936 * 2937 * sessionCount 2938 * This field specifies count of all active fbc sessions on this GPU. 2939 * 2940 * averageFPS 2941 * This field specifies the average frames captured. 2942 * 2943 * averageLatency 2944 * This field specifies the average FBC latency in microseconds. 2945 * 2946 * Possible status values returned are : 2947 * NV_OK 2948 * NV_ERR_INVALID_ARGUMENT 2949 */ 2950 #define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS (0x2080017bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */ 2951 2952 #define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x7BU) 2953 2954 typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS { 2955 NvU32 sessionCount; 2956 NvU32 averageFPS; 2957 NvU32 averageLatency; 2958 } NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS; 2959 2960 /* 2961 * NV2080_CTRL_NVFBC_SW_SESSION_INFO 2962 * 2963 * processId[OUT] 2964 * Process id of the process owning the NvFBC session. 2965 * On VGX host, this will specify the vGPU plugin process id. 2966 * subProcessId[OUT] 2967 * Process id of the process owning the NvFBC session if the 2968 * session is on VGX guest, else the value is zero. 2969 * vgpuInstanceId[OUT] 2970 * vGPU on which the process owning the NvFBC session 2971 * is running if session is on VGX guest, else 2972 * the value is zero. 2973 * sessionId[OUT] 2974 * Unique session id of the NvFBC session. 2975 * sessionType[OUT] 2976 * Type of NvFBC session. 2977 * displayOrdinal[OUT] 2978 * Display identifier associated with the NvFBC session. 2979 * sessionFlags[OUT] 2980 * One or more of NV2080_CTRL_NVFBC_SESSION_FLAG_xxx. 2981 * hMaxResolution[OUT] 2982 * Max horizontal resolution supported by the NvFBC session. 2983 * vMaxResolution[OUT] 2984 * Max vertical resolution supported by the NvFBC session. 2985 * hResolution[OUT] 2986 * Horizontal resolution requested by caller in grab call. 2987 * vResolution[OUT] 2988 * Vertical resolution requested by caller in grab call. 2989 * averageFPS[OUT] 2990 * Average no. of frames captured per second. 2991 * averageLatency[OUT] 2992 * Average frame capture latency in microseconds. 2993 */ 2994 2995 #define NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED 0x00000001U 2996 #define NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED 0x00000002U 2997 #define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT 0x00000004U 2998 #define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE 0x00000008U 2999 #define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT 0x00000010U 3000 3001 typedef struct NV2080_CTRL_NVFBC_SW_SESSION_INFO { 3002 NvU32 processId; 3003 NvU32 subProcessId; 3004 NvU32 vgpuInstanceId; 3005 NvU32 sessionId; 3006 NvU32 sessionType; 3007 NvU32 displayOrdinal; 3008 NvU32 sessionFlags; 3009 NvU32 hMaxResolution; 3010 NvU32 vMaxResolution; 3011 NvU32 hResolution; 3012 NvU32 vResolution; 3013 NvU32 averageFPS; 3014 NvU32 averageLatency; 3015 } NV2080_CTRL_NVFBC_SW_SESSION_INFO; 3016 3017 /* 3018 * NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO 3019 * 3020 * This command returns NVFBC software sessions information for the associate GPU. 3021 * 3022 * sessionInfoCount 3023 * This field specifies the number of entries that are filled inside 3024 * sessionInfoTbl. Max value of this field once returned from RM would be 3025 * NV2080_GPU_NVFBC_MAX_COUNT. 3026 * 3027 * sessionInfoTbl 3028 * This field specifies the array in which the NVFBC session information is to 3029 * be returned. RM will fill the current session data in sessionInfoTbl array 3030 * and then update the sessionInfoCount to reflect current session count value. 3031 * 3032 * Possible status values returned are: 3033 * NV_OK 3034 * NV_ERR_NO_MEMORY 3035 * NV_ERR_INVALID_LOCK_STATE 3036 * NV_ERR_INVALID_ARGUMENT 3037 */ 3038 3039 #define NV2080_GPU_NVFBC_MAX_SESSION_COUNT 256U 3040 3041 #define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x7CU) 3042 3043 typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS { 3044 NvU32 sessionInfoCount; 3045 NV2080_CTRL_NVFBC_SW_SESSION_INFO sessionInfoTbl[NV2080_GPU_NVFBC_MAX_SESSION_COUNT]; 3046 } NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS; 3047 3048 #define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO (0x2080017cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */ 3049 3050 3051 3052 /* 3053 * NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE 3054 * 3055 * This command returns the VMMU page size 3056 * 3057 * vmmuSegmentSize 3058 * Output parameter. 3059 * Returns the VMMU segment size (in bytes) 3060 * 3061 * Possible status values returned are: 3062 * NV_OK 3063 * NV_ERR_NOT_SUPPORTED 3064 */ 3065 #define NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE (0x2080017eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID" */ 3066 3067 #define NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID (0x7EU) 3068 3069 typedef struct NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS { 3070 NV_DECLARE_ALIGNED(NvU64 vmmuSegmentSize, 8); 3071 } NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS; 3072 3073 #define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB 0x02000000U 3074 #define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB 0x04000000U 3075 #define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB 0x08000000U 3076 #define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB 0x10000000U 3077 #define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB 0x20000000U 3078 3079 3080 3081 /* 3082 * NV2080_CTRL_GPU_GET_PARTITION_CAPACITY 3083 * 3084 * This command returns the count of partitions of given size (represented by 3085 * NV2080_CTRL_GPU_PARTITION_FLAG_*) which can be requested via 3086 * NV2080_CTRL_GPU_SET_PARTITIONS ctrl call. 3087 * Note that this API does not "reserve" any partitions, and there is no 3088 * guarantee that the reported count of available partitions of a given size 3089 * will remain consistent following creation of partitions of different size 3090 * through NV2080_CTRL_GPU_SET_PARTITIONS. 3091 * Note that this API is unsupported if SMC is feature-disabled. 3092 * 3093 * partitionFlag[IN] 3094 * - Partition flag indicating size of requested partitions 3095 * 3096 * partitionCount[OUT] 3097 * - Available number of partitions of the given size which can currently be created. 3098 * 3099 * availableSpans[OUT] 3100 * - For each partition able to be created of the specified size, the span 3101 * it could occupy. 3102 * 3103 * availableSpansCount[OUT] 3104 * - Number of valid entries in availableSpans. 3105 * 3106 * totalPartitionCount[OUT] 3107 * - Total number of partitions of the given size which can be created. 3108 * 3109 * totalSpans[OUT] 3110 * - List of spans which can possibly be occupied by partitions of the 3111 * given type. 3112 * 3113 * totalSpansCount[OUT] 3114 * - Number of valid entries in totalSpans. 3115 * 3116 * bStaticInfo[IN] 3117 * - Flag indicating that client requests only the information from 3118 * totalPartitionCount and totalSpans. 3119 * 3120 * Possible status values returned are: 3121 * NV_OK 3122 * NV_ERR_INVALID_ARGUMENT 3123 * NV_ERR_NOT_SUPPORTED 3124 */ 3125 #define NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY (0x20800181U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID" */ 3126 3127 #define NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID (0x81U) 3128 3129 typedef struct NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS { 3130 NvU32 partitionFlag; 3131 NvU32 partitionCount; 3132 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN availableSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); 3133 NvU32 availableSpansCount; 3134 NvU32 totalPartitionCount; 3135 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN totalSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); 3136 NvU32 totalSpansCount; 3137 NvBool bStaticInfo; 3138 } NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS; 3139 3140 /* 3141 * NV2080_CTRL_CMD_GPU_GET_CACHED_INFO 3142 * 3143 * This command returns cached(SW only) gpu information for the associated GPU. 3144 * Requests to retrieve gpu information use a list of one or more NV2080_CTRL_GPU_INFO 3145 * structures. 3146 * The gpuInfoList is aligned with NV2080_CTRL_GPU_GET_INFO_V2_PARAMS for security concern 3147 * 3148 * gpuInfoListSize 3149 * This field specifies the number of entries on the caller's 3150 * gpuInfoList. 3151 * gpuInfoList 3152 * This field specifies a pointer in the caller's address space 3153 * to the buffer into which the gpu information is to be returned. 3154 * This buffer must be at least as big as gpuInfoListSize multiplied 3155 * by the size of the NV2080_CTRL_GPU_INFO structure. 3156 * 3157 * Possible status values returned are: 3158 * NV_OK 3159 * NV_ERR_INVALID_PARAM_STRUCT 3160 * NV_ERR_INVALID_ARGUMENT 3161 * NV_ERR_NOT_SUPPORTED 3162 * NV_ERR_OPERATING_SYSTEM 3163 */ 3164 #define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID" */ 3165 3166 #define NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID (0x82U) 3167 3168 typedef NV2080_CTRL_GPU_GET_INFO_V2_PARAMS NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS; 3169 3170 /* 3171 * NV2080_CTRL_GPU_SET_PARTITIONING_MODE 3172 * 3173 * This command configures this GPU to control global mode for partitioning. 3174 * This command may not be sent to a GPU with any active partitions. 3175 * This command may be used to set the following modes: 3176 * 3177 * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING 3178 * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY 3179 * This is the default mode. While this GPU is in this mode, no partitions 3180 * will be allowed to be created via SET_PARTITIONS - a client must set one 3181 * of the below modes prior to partitioning the GPU. When a client sets a 3182 * GPU into this mode, any performance changes resulting from partitions 3183 * made while in either of the below modes will be cleared. A 3184 * physical-function-level reset is required after setting this mode. 3185 * 3186 * NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF 3187 * In this mode, when the GPU is partitioned, each partition will have the 3188 * maximum possible performance which can be evenly distributed among all 3189 * partitions. The total performance of the GPU, taking into account all 3190 * partitions created in this mode, may be less than that of a GPU running 3191 * in legacy non-SMC mode. Partitions created while in this mode require a 3192 * physical-function-level reset before the partitioning may take full 3193 * effect. Destroying all partitions while in this mode may be 3194 * insufficient to restore full performance to the GPU - only by setting 3195 * the mode to _LEGACY can this be achieved. A physical-function-level 3196 * reset is NOT required after setting this mode. 3197 * 3198 * NV2080_CTRL_GPU_SET_PARTIITONING_MODE_REPARTITIONING_FAST_RECONFIG 3199 * By setting this mode, the performance of the GPU will be restricted such 3200 * that all partitions will have a consistent fraction of the total 3201 * available performance, which may be less than the maximum possible 3202 * performance available to each partition. Creating or destroying 3203 * partitions on this GPU while in this mode will not require a 3204 * physical-function-level reset, and will not affect other active 3205 * partitions. Destroying all partitions while in this mode may be 3206 * insufficient to restore full performance to the GPU - only by setting 3207 * the mode to _LEGACY can this be achieved. A physical-function-level 3208 * reset is required after setting this mode. 3209 * 3210 * Parameters: 3211 * partitioningMode[IN] 3212 * - Partitioning Mode to set for this GPU. 3213 * 3214 * Possible status values returned are: 3215 * NV_OK 3216 * NV_ERR_INVALID_STATE 3217 * NV_ERR_INVALID_ARGUMENT 3218 * NV_ERR_NOT_SUPPORTED 3219 */ 3220 #define NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE (0x20800183U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */ 3221 3222 #define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING 1:0 3223 #define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY 0U 3224 #define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF 1U 3225 #define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG 2U 3226 3227 #define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0x83U) 3228 3229 typedef struct NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS { 3230 NvU32 partitioningMode; 3231 } NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS; 3232 3233 3234 3235 /* NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO 3236 * 3237 * This structure describes resources available in a partition requested of a 3238 * given type. 3239 * 3240 * [OUT] partitionFlag 3241 * - Flags to specify in NV2080_CTRL_CMD_GPU_SET_PARTITIONS to request this 3242 * partition 3243 * 3244 * [OUT] grCount 3245 * - Total Number of SMC engines/GR engines (including GFX capable ones in this parition) 3246 * 3247 * [OUT] gfxGrCount 3248 * - Number of SMC engines/GR engines capable of GFX. This is a subset of the engines included in grCount 3249 * 3250 * [OUT] gpcCount 3251 * - Number of GPCs in this partition, including the GFX Capable ones. 3252 * 3253 * [OUT] virtualGpcCount 3254 * - Number of virtualized GPCs in this partition, including the GFX Capable ones. 3255 * 3256 * [OUT] gfxGpcCount 3257 * - Number of GFX Capable GPCs in this partition. This is a subset of the GPCs included in gpcCount. 3258 * 3259 * [OUT] veidCount 3260 * - Number of VEIDS in this partition 3261 * 3262 * [OUT] smCount 3263 * - Number of SMs in this partition 3264 * 3265 * [OUT] ceCount 3266 * - Copy Engines in this partition 3267 * 3268 * [OUT] nvEncCount 3269 * - Encoder Engines in this partition 3270 * 3271 * [OUT] nvDecCount 3272 * - Decoder Engines in this partition 3273 * 3274 * [OUT] nvJpgCount 3275 * - Jpg Engines in this partition 3276 * 3277 * [OUT] nvOfaCount 3278 * - Ofa engines in this partition 3279 * [OUT] memorySize 3280 * - Total available memory within this partition 3281 */ 3282 typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO { 3283 NvU32 partitionFlag; 3284 NvU32 grCount; 3285 NvU32 gfxGrCount; 3286 NvU32 gpcCount; 3287 NvU32 virtualGpcCount; 3288 NvU32 gfxGpcCount; 3289 NvU32 veidCount; 3290 NvU32 smCount; 3291 NvU32 ceCount; 3292 NvU32 nvEncCount; 3293 NvU32 nvDecCount; 3294 NvU32 nvJpgCount; 3295 NvU32 nvOfaCount; 3296 NV_DECLARE_ALIGNED(NvU64 memorySize, 8); 3297 } NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO; 3298 3299 /* 3300 * NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS 3301 * 3302 * This command returns information regarding GPU partitions which can be 3303 * requested via NV2080_CTRL_CMD_GPU_SET_PARTITIONS. 3304 * 3305 * [OUT] descCount 3306 * - Number of valid partition types 3307 * 3308 * [OUT] partitionDescs 3309 * - Information describing available partitions 3310 * 3311 * Possible status values returned are: 3312 * NV_OK 3313 * NV_ERR_NOT_SUPPORTED 3314 */ 3315 #define NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID (0x85U) 3316 3317 typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS { 3318 NvU32 descCount; 3319 // C form: NV2080_CTRL_GPU_DESCRIBE_PARTITION_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES]; 3320 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES], 8); 3321 } NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS; 3322 3323 #define NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS (0x20800185U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID" */ 3324 3325 3326 3327 /* 3328 * NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE 3329 * 3330 * This command returns information regarding maximum page size supported 3331 * by GMMU on the platform on which RM is running. 3332 * 3333 * [OUT] maxSupportedPageSize 3334 * - Maximum local vidmem page size supported by GMMU of a given GPU (HW) 3335 * on a given platform (OS) 3336 * 3337 * Possible status values returned are: 3338 * NV_OK 3339 * NV_ERR_NOT_SUPPORTED 3340 */ 3341 #define NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE (0x20800188U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID" */ 3342 3343 #define NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID (0x88U) 3344 3345 typedef struct NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS { 3346 NV_DECLARE_ALIGNED(NvU64 maxSupportedPageSize, 8); 3347 } NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS; 3348 3349 3350 3351 /* 3352 * NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC 3353 * 3354 * This command returns the max number of MMUs per GPC 3355 * 3356 * gpcId [IN] 3357 * Logical GPC id 3358 * count [OUT] 3359 * The number of MMUs per GPC 3360 * grRouteInfo 3361 * This parameter specifies the routing information used to 3362 * disambiguate the target GR engine. When SMC is enabled, this 3363 * is a mandatory parameter. 3364 */ 3365 #define NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID (0x8AU) 3366 3367 typedef struct NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS { 3368 NvU32 gpcId; 3369 NvU32 count; 3370 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 3371 } NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS; 3372 3373 #define NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC (0x2080018aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID" */ 3374 3375 /* 3376 * NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS 3377 * 3378 * This command returns the GPU partition IDs for all active partitions 3379 * If GPU is not partitioned, the control call will return partition count as "0" 3380 * 3381 * swizzId[OUT] 3382 * - HW Partition ID associated with the active partitions 3383 * 3384 * partitionCount[OUT] 3385 * - Number of active partitions in system 3386 * 3387 * Possible status values returned are: 3388 * NV_OK 3389 * NV_ERR_INVALID_ARGUMENT 3390 * NV_ERR_NOT_SUPPORTED 3391 */ 3392 #define NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID (0x8BU) 3393 3394 typedef struct NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS { 3395 NvU32 swizzId[NV2080_CTRL_GPU_MAX_PARTITION_IDS]; 3396 NvU32 partitionCount; 3397 } NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS; 3398 3399 #define NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS (0x2080018bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID" */ 3400 3401 3402 3403 /* 3404 * NV2080_CTRL_CMD_GPU_GET_PIDS 3405 * 3406 * Given a resource identifier and its type, this command returns a set of 3407 * process identifiers (PIDs) of processes that have instantiated this resource. 3408 * For example, given a class number, this command returns a list of all 3409 * processes with clients that have matching object allocations. 3410 * This is a SMC aware call and the scope of the information gets restricted 3411 * based on partition subscription. 3412 * The call enforces partition subscription if SMC is enabled, and client is not 3413 * a monitoring client. 3414 * Monitoring clients get global information without any scope based filtering. 3415 * Monitoring clients are also not expected to subscribe to a partition when 3416 * SMC is enabled. 3417 * 3418 * idType 3419 * Type of the resource identifier. See below for a list of valid types. 3420 * id 3421 * Resource identifier. 3422 * pidTblCount 3423 * Number of entries in the PID table. 3424 * pidTbl 3425 * Table which will contain the PIDs. Each table entry is of type NvU32. 3426 * 3427 * Possible status values returned are: 3428 * NV_OK 3429 * NV_ERR_INVALID_PARAM_STRUCT 3430 * NV_ERR_INVALID_ARGUMENT 3431 */ 3432 #define NV2080_CTRL_CMD_GPU_GET_PIDS (0x2080018dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID" */ 3433 3434 /* max size of pidTable */ 3435 #define NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT 950U 3436 3437 #define NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID (0x8DU) 3438 3439 typedef struct NV2080_CTRL_GPU_GET_PIDS_PARAMS { 3440 NvU32 idType; 3441 NvU32 id; 3442 NvU32 pidTblCount; 3443 NvU32 pidTbl[NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT]; 3444 } NV2080_CTRL_GPU_GET_PIDS_PARAMS; 3445 3446 /* 3447 * Use class NV20_SUBDEVICE_0 with NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS to query 3448 * PIDs with or without GPU contexts. For any other class id, PIDs only with GPU 3449 * contexts are returned. 3450 */ 3451 #define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS (0x00000000U) 3452 #define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST (0x00000001U) 3453 3454 /* 3455 * NV2080_CTRL_SMC_SUBSCRIPTION_INFO 3456 * 3457 * This structure contains information about the SMC subscription type. 3458 * If MIG is enabled a valid ID is returned, it is set to PARTITIONID_INVALID otherwise. 3459 * 3460 * computeInstanceId 3461 * This parameter returns a valid compute instance ID 3462 * gpuInstanceId 3463 * This parameter returns a valid GPU instance ID 3464 */ 3465 typedef struct NV2080_CTRL_SMC_SUBSCRIPTION_INFO { 3466 NvU32 computeInstanceId; 3467 NvU32 gpuInstanceId; 3468 } NV2080_CTRL_SMC_SUBSCRIPTION_INFO; 3469 3470 /* 3471 * NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA 3472 * 3473 * This structure contains the video memory usage information. 3474 * 3475 * memPrivate 3476 * This parameter returns the amount of memory exclusively owned 3477 * (i.e. private) to the client 3478 * memSharedOwned 3479 * This parameter returns the amount of shared memory owned by the client 3480 * memSharedDuped 3481 * This parameter returns the amount of shared memory duped by the client 3482 * protectedMemPrivate 3483 * This parameter returns the amount of protected memory exclusively owned 3484 * (i.e. private) to the client whenever memory protection is enabled 3485 * protectedMemSharedOwned 3486 * This parameter returns the amount of shared protected memory owned by the 3487 * client whenever memory protection is enabled 3488 * protectedMemSharedDuped 3489 * This parameter returns the amount of shared protected memory duped by the 3490 * client whenever memory protection is enabled 3491 */ 3492 typedef struct NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA { 3493 NV_DECLARE_ALIGNED(NvU64 memPrivate, 8); 3494 NV_DECLARE_ALIGNED(NvU64 memSharedOwned, 8); 3495 NV_DECLARE_ALIGNED(NvU64 memSharedDuped, 8); 3496 NV_DECLARE_ALIGNED(NvU64 protectedMemPrivate, 8); 3497 NV_DECLARE_ALIGNED(NvU64 protectedMemSharedOwned, 8); 3498 NV_DECLARE_ALIGNED(NvU64 protectedMemSharedDuped, 8); 3499 } NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA; 3500 3501 #define NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE (0x00000000U) 3502 3503 #define NV2080_CTRL_GPU_PID_INFO_INDEX_MAX NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE 3504 3505 typedef union NV2080_CTRL_GPU_PID_INFO_DATA { 3506 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA vidMemUsage, 8); 3507 } NV2080_CTRL_GPU_PID_INFO_DATA; 3508 3509 3510 /* 3511 * NV2080_CTRL_GPU_PID_INFO 3512 * 3513 * This structure contains the per pid information. Each type of information 3514 * retrievable via NV2080_CTRL_CMD_GET_PID_INFO is assigned a unique index 3515 * below. In addition the process for which the lookup is for is also defined. 3516 * This is a SMC aware call and the scope of the information gets restricted 3517 * based on partition subscription. 3518 * The call enforces partition subscription if SMC is enabled, and client is not 3519 * a monitoring client. 3520 * Monitoring clients get global information without any scope based filtering. 3521 * Monitoring clients are also not expected to subscribe to a partition when 3522 * SMC is enabled. 3523 * 3524 * pid 3525 * This parameter specifies the PID of the process for which information is 3526 * to be queried. 3527 * index 3528 * This parameter specifies the type of information being queried for the 3529 * process of interest. 3530 * result 3531 * This parameter returns the result of the instruction's execution. 3532 * data 3533 * This parameter returns the data corresponding to the information which is 3534 * being queried. 3535 * 3536 * Possible status values returned are: 3537 * NV_OK 3538 * NV_ERR_INVALID_ARGUMENT 3539 * NV_ERR_INVALID_PARAM_STRUCT 3540 * 3541 * Valid PID information indices are: 3542 * 3543 * NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE 3544 * This index is used to request the amount of video memory on this GPU 3545 * allocated to the process. 3546 */ 3547 typedef struct NV2080_CTRL_GPU_PID_INFO { 3548 NvU32 pid; 3549 NvU32 index; 3550 NvU32 result; 3551 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO_DATA data, 8); 3552 NV2080_CTRL_SMC_SUBSCRIPTION_INFO smcSubscription; 3553 } NV2080_CTRL_GPU_PID_INFO; 3554 3555 /* 3556 * NV2080_CTRL_CMD_GPU_GET_PID_INFO 3557 * 3558 * This command allows querying per-process information from the RM. Clients 3559 * request information by specifying a unique informational index and the 3560 * Process ID of the process in question. The result is set to indicate success 3561 * and the information queried (if available) is returned in the data parameter. 3562 * 3563 * pidInfoListCount 3564 * The number of valid entries in the pidInfoList array. 3565 * pidInfoList 3566 * An array of NV2080_CTRL_GPU_PID_INFO of maximum length 3567 * NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT. 3568 * 3569 * Possible status values returned are: 3570 * NV_OK 3571 * NV_ERR_INVALID_PARAM_STRUCT 3572 * NV_ERR_INVALID_ARGUMENT 3573 */ 3574 #define NV2080_CTRL_CMD_GPU_GET_PID_INFO (0x2080018eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID" */ 3575 3576 /* max size of pidInfoList */ 3577 #define NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT 200U 3578 3579 #define NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID (0x8EU) 3580 3581 typedef struct NV2080_CTRL_GPU_GET_PID_INFO_PARAMS { 3582 NvU32 pidInfoListCount; 3583 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PID_INFO pidInfoList[NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT], 8); 3584 } NV2080_CTRL_GPU_GET_PID_INFO_PARAMS; 3585 3586 3587 3588 /*! 3589 * NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT 3590 * 3591 * @brief Handle VF PRI faults 3592 * 3593 * faultType 3594 * BAR1, BAR2, PHYSICAL or UNBOUND_INSTANCE 3595 * 3596 * Possible status values returned are: 3597 * NV_OK 3598 * NV_ERR_NOT_SUPPORTED 3599 * 3600 */ 3601 3602 #define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT (0x20800192U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID" */ 3603 3604 #define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID 0U 3605 #define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1 1U 3606 #define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2 2U 3607 #define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL 3U 3608 #define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE 4U 3609 3610 #define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID (0x92U) 3611 3612 typedef struct NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS { 3613 NvU32 faultType; 3614 } NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS; 3615 3616 3617 /*! 3618 * Compute policy types to be specified by callers to set a config. 3619 * 3620 * _TIMESLICE 3621 * Set the timeslice config for the requested GPU. 3622 * Check @ref NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE for 3623 * permissible timeslice values. 3624 */ 3625 #define NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE 0U 3626 #define NV2080_CTRL_GPU_COMPUTE_POLICY_MAX 1U 3627 3628 /*! 3629 * Enum consisting of permissible timeslice options that can configured 3630 * for a GPU. These can be queried by compute clients and the exact 3631 * timeslice values can be chosen appropriately as per GPU support 3632 */ 3633 typedef enum NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE { 3634 NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT = 0, 3635 NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT = 1, 3636 NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM = 2, 3637 NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG = 3, 3638 NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX = 4, 3639 } NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE; 3640 3641 typedef struct NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG { 3642 /*! 3643 * NV2080_CTRL_GPU_COMPUTE_POLICY_<xyz> 3644 */ 3645 NvU32 type; 3646 3647 /*! 3648 * Union of type-specific data 3649 */ 3650 union { 3651 NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE timeslice; 3652 } data; 3653 } NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG; 3654 3655 #define NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x94U) 3656 3657 typedef struct NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS { 3658 NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG config; 3659 } NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS; 3660 3661 /* 3662 * NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG 3663 * 3664 * This command retrieves all compute policies configs for the associated gpu. 3665 * 3666 * Possible status values returned are: 3667 * NV_OK 3668 * NV_ERR_INVALID_ARGUMENT 3669 * NV_ERR_OBJECT_NOT_FOUND 3670 */ 3671 #define NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG (0x20800195U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID" */ 3672 3673 /*! 3674 * This define limits the max number of policy configs that can be handled by 3675 * NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG command. 3676 * 3677 * @note Needs to be in sync (greater or equal) to NV2080_CTRL_GPU_COMPUTE_POLICY_MAX. 3678 */ 3679 3680 #define NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX 32U 3681 3682 #define NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x95U) 3683 3684 typedef struct NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS { 3685 NvU32 numConfigs; 3686 3687 /*! 3688 * C form: 3689 * NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX]; 3690 */ 3691 NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX]; 3692 } NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS; 3693 3694 /* 3695 * NV2080_CTRL_CMD_GPU_GET_GFID 3696 * 3697 * This command returns the GFID (GPU Function ID) for a given SR-IOV 3698 * Virtual Function (VF) of the physical GPU. 3699 * 3700 * domain [IN] 3701 * This field specifies the respective domain of the PCI device. 3702 * bus [IN] 3703 * This field specifies the bus id for a given VF. 3704 * device [IN] 3705 * This field specifies the device id for a given VF. 3706 * func [IN] 3707 * This field specifies the function id for a given VF. 3708 * gfid[OUT] 3709 * - This field returns GFID for a given VF BDF. 3710 * gfidMask[OUT] 3711 * - This field returns GFID mask value. 3712 * 3713 * Possible status values returned are: 3714 * NV_OK 3715 * NV_ERR_INVALID_PARAM_STRUCT 3716 * NV_ERR_INVALID_ARGUMENT 3717 * NV_ERR_OPERATING_SYSTEM 3718 */ 3719 3720 #define NV2080_CTRL_CMD_GPU_GET_GFID (0x20800196U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID" */ 3721 3722 #define NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID (0x96U) 3723 3724 typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS { 3725 NvU32 domain; 3726 NvU8 bus; 3727 NvU8 device; 3728 NvU8 func; 3729 NvU32 gfid; 3730 NvU32 gfidMask; 3731 } NV2080_CTRL_GPU_GET_GFID_PARAMS; 3732 3733 /* 3734 * NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY 3735 * 3736 * This command informs the GPU driver that the GPU partition associated with 3737 * a given GFID has been activated or will be deactivated. 3738 * 3739 * gfid[IN] 3740 * - The GPU function identifier for a given VF BDF 3741 * bEnable [IN] 3742 * - Set to NV_TRUE if the GPU partition has been activated. 3743 * - Set to NV_FALSE if the GPU partition will be deactivated. 3744 * fabricPartitionId [IN] 3745 * - Set the fabric manager partition ID dring partition activation. 3746 * - Ignored during partition deactivation. 3747 * 3748 * Possible status values returned are: 3749 * NV_OK 3750 * NV_ERR_INVALID_PARAM_STRUCT 3751 * NV_ERR_INVALID_ARGUMENT 3752 * NV_ERR_OPERATING_SYSTEM 3753 */ 3754 3755 #define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY (0x20800197U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID" */ 3756 3757 #define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID (0x97U) 3758 3759 typedef struct NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS { 3760 NvU32 gfid; 3761 NvBool bEnable; 3762 NvU32 fabricPartitionId; 3763 } NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS; 3764 3765 /*! 3766 * NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST 3767 * 3768 * @brief Validate the address range for memory map request by comparing the 3769 * user supplied address range with GPU BAR0/BAR1 range. 3770 * 3771 * @param[in] addressStart Start address for memory map request 3772 * @param[in] addressLength Length for for memory map request 3773 * @param[out] protection NV_PROTECT_READ_WRITE, if both read/write is allowed 3774 * NV_PROTECT_READABLE, if only read is allowed 3775 * 3776 * Possible status values returned are: 3777 * NV_OK 3778 * NV_ERR_PROTECTION_FAULT 3779 * 3780 */ 3781 #define NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST (0x20800198U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID" */ 3782 3783 #define NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID (0x98U) 3784 3785 typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS { 3786 NV_DECLARE_ALIGNED(NvU64 addressStart, 8); 3787 NV_DECLARE_ALIGNED(NvU64 addressLength, 8); 3788 NvU32 protection; 3789 } NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS; 3790 3791 /* 3792 * NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR 3793 * 3794 * @brief This command is similar to NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR 3795 * but will be used to set the EGM fabric base addr associated with the gpu. 3796 * Note: For EGM FLA, we will be making use of the existing control call i.e 3797 * NV2080_CTRL_CMD_FLA_RANGE 3798 * 3799 */ 3800 #define NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR (0x20800199U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */ 3801 3802 #define NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID (0x99U) 3803 3804 typedef struct NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS { 3805 NV_DECLARE_ALIGNED(NvU64 egmGpaFabricBaseAddr, 8); 3806 } NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS; 3807 3808 3809 3810 /* 3811 * NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES 3812 * 3813 * This command is used to retrieve the load time (latency) of each engine. 3814 * 3815 * engineCount 3816 * This field specifies the number of entries of the following 3817 * three arrays. 3818 * 3819 * engineList[NV2080_GPU_MAX_ENGINE_OBJECTS] 3820 * An array of NvU32 which stores each engine's descriptor. 3821 * 3822 * engineStateLoadTime[NV2080_GPU_MAX_ENGINE_OBJECTS] 3823 * A array of NvU64 which stores each engine's load time. 3824 * 3825 * engineIsInit[NV2080_GPU_MAX_ENGINE_OBJECTS] 3826 * A array of NvBool which stores each engine's initialization status. 3827 * 3828 * Possible status values returned are: 3829 * NV_OK 3830 */ 3831 #define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */ 3832 3833 #define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xC8U 3834 3835 #define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU) 3836 3837 typedef struct NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS { 3838 NvU32 engineCount; 3839 NvU32 engineList[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; 3840 NV_DECLARE_ALIGNED(NvU64 engineStateLoadTime[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS], 8); 3841 NvBool engineIsInit[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; 3842 } NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS; 3843 3844 /* 3845 * NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING 3846 * 3847 * This command is used to retrieve the mapping of engine ID and engine Name. 3848 * 3849 * engineCount 3850 * This field specifies the size of the mapping. 3851 * 3852 * engineID 3853 * An array of NvU32 which stores each engine's descriptor. 3854 * 3855 * engineName 3856 * An array of char[100] which stores each engine's name. 3857 * 3858 * Possible status values returned are: 3859 * NV_OK 3860 */ 3861 #define NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING (0x2080019cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID" */ 3862 3863 #define NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID (0x9CU) 3864 3865 typedef struct NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS { 3866 NvU32 engineCount; 3867 NvU32 engineID[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS]; 3868 char engineName[NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS][100]; 3869 } NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS; 3870 3871 /* 3872 * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS 3873 * 3874 * Same as above NV2080_CTRL_CMD_GPU_EXEC_REG_OPS except that this CTRL CMD will 3875 * not allow any embedded pointers. The regOps array is inlined as part of the 3876 * struct. 3877 * NOTE: This intended for gsp plugin only as it may override regOp access 3878 * restrictions 3879 * 3880 * Possible status values returned are: 3881 * NV_OK 3882 * NV_ERR_NOT_SUPPORTED 3883 * NV_ERR_INVALID_ARGUMENT 3884 * NV_ERR_INVALID_PARAM_STRUCT 3885 */ 3886 #define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS (0x2080019dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID" */ 3887 3888 /* setting this to 100 keeps it right below 4k in size */ 3889 #define NV2080_CTRL_REG_OPS_ARRAY_MAX 100U 3890 #define NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID (0x9DU) 3891 3892 typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS { 3893 NvHandle hClientTarget; 3894 NvHandle hChannelTarget; 3895 NvU32 bNonTransactional; 3896 NvU32 reserved00[2]; 3897 NvU32 regOpCount; 3898 NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_REG_OPS_ARRAY_MAX]; 3899 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 3900 } NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS; 3901 3902 3903 3904 3905 /*! 3906 * NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO 3907 * 3908 * [in/out] gpuId 3909 * GPU ID for which the capabilities are queried. 3910 * For the NV2080_CTRL_CMD_GET_P2P_CAPS control: 3911 * If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to 3912 * the GPU ID of an attached GPU. 3913 * If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester 3914 * should set it to the ID of the GPU that needs to be queried from. 3915 * [in] gpuUuid 3916 * Alternative to gpuId; used to identify target GPU for which caps are being queried. 3917 * Option only available for Guest RPCs. 3918 * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. 3919 * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. 3920 * If bAllCaps == NV_TRUE, gpuUuid is ignored. 3921 * [out] p2pCaps 3922 * Peer to peer capabilities discovered between the GPUs. 3923 * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. 3924 * [out] p2pOptimalReadCEs 3925 * Mask of CEs to use for p2p reads over Nvlink. 3926 * [out] p2pOptimalWriteCEs 3927 * Mask of CEs to use for p2p writes over Nvlink. 3928 * [out] p2pCapsStatus 3929 * Status of all supported p2p capabilities. 3930 * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. 3931 * [out] busPeerId 3932 * Bus peer ID. For an invalid or a non-existent peer this field 3933 * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. 3934 */ 3935 #define NV2080_GET_P2P_CAPS_UUID_LEN 16U 3936 3937 typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO { 3938 NvU32 gpuId; 3939 NvU8 gpuUuid[NV2080_GET_P2P_CAPS_UUID_LEN]; 3940 NvU32 p2pCaps; 3941 NvU32 p2pOptimalReadCEs; 3942 NvU32 p2pOptimalWriteCEs; 3943 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; 3944 NvU32 busPeerId; 3945 } NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO; 3946 3947 /*! 3948 * NV2080_CTRL_CMD_GET_P2P_CAPS 3949 * 3950 * Returns peer to peer capabilities present between GPUs. 3951 * The caller must either specify bAllCaps to query the capabilities for 3952 * all the attached GPUs or they must pass a valid list of GPU IDs. 3953 * 3954 * [in] bAllCaps 3955 * Set to NV_TRUE to query the capabilities for all the attached GPUs. 3956 * Set to NV_FALSE and specify peerGpuCount and peerGpuCaps[].gpuId 3957 * to retrieve the capabilities only for the specified GPUs. 3958 * [in] bUseUuid 3959 * Option only available for Guest RPCs. 3960 * Set to NV_TRUE to use gpuUuid in lieu of gpuId to identify target GPU. 3961 * If bAllCaps == NV_TRUE, bUseUuid is ignored. 3962 * [in/out] peerGpuCount 3963 * The number of the peerGpuCaps entries. 3964 * If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to 3965 * the total number of the attached GPUs. 3966 * If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester 3967 * should set it to the number of the peerGpuCaps entries. 3968 * [in/out] peerGpuCaps 3969 * The array of NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO entries, describing 3970 * the peer to peer capabilities of the GPUs. 3971 * 3972 * Possible status values returned are: 3973 * NV_OK 3974 * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount 3975 * NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuCaps[].gpuId 3976 */ 3977 #define NV2080_CTRL_CMD_GET_P2P_CAPS (0x208001a0U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ 3978 3979 #define NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0xA0U) 3980 3981 typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS { 3982 NvBool bAllCaps; 3983 NvBool bUseUuid; 3984 NvU32 peerGpuCount; 3985 NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; 3986 } NV2080_CTRL_GET_P2P_CAPS_PARAMS; 3987 3988 3989 3990 /*! 3991 * NV2080_CTRL_GPU_COMPUTE_PROFILE 3992 * 3993 * This structure specifies resources in an execution partition 3994 * 3995 * id[OUT] 3996 * - Total Number of GPCs in this partition 3997 * 3998 * computeSize[OUT] 3999 * - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* associated with this profile 4000 * 4001 * gpcCount[OUT] 4002 * - Total Number of GPCs in this partition (including GFX Supported GPCs) 4003 * 4004 * veidCount[OUT] 4005 * - Number of VEIDs allocated to this profile 4006 * 4007 * smCount[OUT] 4008 * - Number of SMs usable in this profile 4009 */ 4010 typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE { 4011 NvU8 computeSize; 4012 NvU32 gfxGpcCount; 4013 NvU32 gpcCount; 4014 NvU32 veidCount; 4015 NvU32 smCount; 4016 } NV2080_CTRL_GPU_COMPUTE_PROFILE; 4017 4018 /*! 4019 * NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS 4020 * 4021 * This structure specifies resources in an execution partition 4022 * 4023 * profileCount[OUT] 4024 * - Total Number of profiles filled 4025 * 4026 * profiles[OUT] 4027 * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles 4028 */ 4029 #define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U) 4030 4031 typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS { 4032 NvU32 profileCount; 4033 NV2080_CTRL_GPU_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; 4034 } NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS; 4035 4036 #define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES (0x208001a2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ 4037 4038 #define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED 0U 4039 #define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED 1U 4040 #define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS 2U 4041 #define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE 3U 4042 4043 #define NV2080_GPU_FABRIC_CLUSTER_UUID_LEN 16U 4044 4045 #define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0) 4046 4047 #define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_MUTLINODE_SUPPORTED NVBIT64(1) 4048 4049 4050 4051 #define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0 4052 #define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0 4053 #define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE 1 4054 #define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE 2 4055 4056 /*! 4057 * NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS 4058 * 4059 * This structure provides the GPU<-->FM probe state info on NVSwitch based 4060 * systems 4061 * 4062 * state[OUT] 4063 * - Current state of GPU<-->FM probe req/rsp 4064 * Following values can be returned 4065 * _UNSUPPORTED - system does not support this feature 4066 * _NOT_STARTED - probe request is not yet sent to the FM 4067 * _IN_PROGRESS - probe response is not yet received 4068 * _COMPLETE - probe response is received 4069 * When state is NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE 4070 * status has to be checked for probe response success/failure 4071 * status[OUT] 4072 * - Inband Probe response status 4073 * A GPU which returns NV_OK status upon receiving the probe response 4074 * can participate in P2P 4075 * clusterUuid[OUT] 4076 * - Uuid of the cluster to which this node belongs 4077 * fabricPartitionId[OUT] 4078 * - Fabric partition Id 4079 * fabricCaps[OUT] 4080 * - Summary of fabric capabilities received from probe resp 4081 * Possible values are 4082 * NV2080_CTRL_GPU_FABRIC_PROBE_CAP_* 4083 * fabricCliqueId[OUT] 4084 * - Unique ID of a set of GPUs within a fabric partition that can perform P2P 4085 * fabricHealthMask[OUT] 4086 * - Mask where bits indicate different status about the health of the fabric 4087 */ 4088 #define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U) 4089 4090 typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS { 4091 NvU8 state; 4092 NV_STATUS status; 4093 NvU8 clusterUuid[NV2080_GPU_FABRIC_CLUSTER_UUID_LEN]; 4094 NvU16 fabricPartitionId; 4095 NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8); 4096 NvU32 fabricCliqueId; 4097 NvU32 fabricHealthMask; 4098 } NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS; 4099 4100 #define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ 4101 4102 /* 4103 * NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS 4104 * 4105 * This command retrieves and constructs the GPU partnumber from the VBIOS. 4106 * 4107 * The following data are currently supported: 4108 * 4109 * pciDevId 4110 * The PCI device ID 4111 * 4112 * chipSku 4113 * The chip SKU information 4114 * 4115 * chipMajor 4116 * The chip major number 4117 * 4118 * chipMinor 4119 * The chip minor number 4120 * 4121 */ 4122 #define NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS (0x208001a4U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID" */ 4123 4124 /* 4125 * The string format for a GPU part number 4126 * The GPU part number is formatted with 4 hexadecimal digits for the PCI device ID, the chip SKU string, 4127 * the chip major number, and then the chip minor number. 4128 * Ordering of the fields for the string format must be synced with the NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS 4129 * struct fields. 4130 */ 4131 #define GPU_PART_NUMBER_FMT "%04X-%s-%X%X" 4132 4133 /* The maximum length for the chip sku */ 4134 #define NV2080_MAX_CHIP_SKU_LENGTH 0x00000004U 4135 4136 #define NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID (0xA4U) 4137 4138 typedef struct NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS { 4139 NvU32 pciDevId; 4140 NvU8 chipSku[NV2080_MAX_CHIP_SKU_LENGTH]; 4141 NvU32 chipMajor; 4142 NvU32 chipMinor; 4143 } NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS; 4144 4145 /* 4146 * NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP 4147 * 4148 * This command returns the host hardware defined engine ID of the specified engine(s). 4149 * 4150 * swizzId[IN] 4151 * - HW Partition ID associated with the requested partition. 4152 * 4153 * Possible status values returned are: 4154 * NV_OK 4155 * NV_ERR_INVALID_ARGUMENT 4156 * NV_ERR_NOT_SUPPORTED 4157 */ 4158 #define NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP (0x208001a5U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID" */ 4159 4160 #define NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID (0xA5U) 4161 4162 typedef struct NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS { 4163 NvU32 swizzId; 4164 } NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS; 4165 4166 #define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS (0x208001a6U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID" */ 4167 #define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP (0x208001a7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID" */ 4168 #define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU (0x208001a8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID" */ 4169 4170 /* setting this to 100 keeps it right below 4k in size */ 4171 #define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX 50U 4172 typedef struct NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS { 4173 NvHandle hClientTarget; 4174 NvHandle hChannelTarget; 4175 NvU32 bNonTransactional; 4176 NvU32 regOpCount; 4177 NvU32 smIds[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX]; 4178 NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX]; 4179 NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); 4180 } NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS; 4181 4182 #define NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID (0xA6U) 4183 4184 typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS; 4185 #define NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID (0xA7U) 4186 4187 typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS; 4188 #define NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID (0xA8U) 4189 4190 typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS; 4191 4192 /* 4193 * NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET 4194 * 4195 * INTERNAL DEBUG/TESTING USE ONLY 4196 * 4197 * Marks the device for reset. 4198 * 4199 * Possible status return values are: 4200 * NV_OK 4201 * NV_ERR_NOT_SUPPORTED 4202 */ 4203 #define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET (0x208001a9U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xA9" */ 4204 4205 /* 4206 * NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET 4207 * 4208 * INTERNAL DEBUG/TESTING USE ONLY 4209 * 4210 * Unmarks the device for reset. 4211 * 4212 * Possible status return values are: 4213 * NV_OK 4214 * NV_ERR_NOT_SUPPORTED 4215 */ 4216 #define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET (0x208001aaU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAA" */ 4217 4218 /* 4219 * NV2080_CTRL_CMD_GPU_GET_RESET_STATUS 4220 * 4221 * Gets the current reset status of the device. 4222 * 4223 * bResetNeeded 4224 * Set to NV_TRUE if the device needs to be reset. 4225 * 4226 * Possible status return values are: 4227 * NV_OK 4228 * NV_ERR_NOT_SUPPORTED 4229 */ 4230 #define NV2080_CTRL_CMD_GPU_GET_RESET_STATUS (0x208001abU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID" */ 4231 4232 #define NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID (0xABU) 4233 4234 typedef struct NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS { 4235 NvBool bResetRequired; 4236 } NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS; 4237 4238 /* 4239 * NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET 4240 * 4241 * INTERNAL DEBUG/TESTING USE ONLY 4242 * 4243 * Marks the device for drain and reset. 4244 * 4245 * Possible status return values are: 4246 * NV_OK 4247 * NV_ERR_NOT_SUPPORTED 4248 */ 4249 #define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001acU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAC" */ 4250 4251 /* 4252 * NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET 4253 * 4254 * INTERNAL DEBUG/TESTING USE ONLY 4255 * 4256 * Unmarks the device for drain and reset. 4257 * 4258 * Possible status return values are: 4259 * NV_OK 4260 * NV_ERR_NOT_SUPPORTED 4261 */ 4262 #define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001adU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAD" */ 4263 4264 /* 4265 * NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS 4266 * 4267 * Gets the current drain and reset status of the device. Drain and reset is used only SMC configs. 4268 * 4269 * bDrainRecommended 4270 * Set to NV_TRUE if a drain and reset is recommended for the device. 4271 * 4272 * Possible status return values are: 4273 * NV_OK 4274 * NV_ERR_NOT_SUPPORTED 4275 */ 4276 #define NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS (0x208001aeU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID" */ 4277 4278 #define NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID (0xAEU) 4279 4280 typedef struct NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS { 4281 NvBool bDrainRecommended; 4282 } NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS; 4283 4284 /* 4285 * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 4286 * 4287 * This command returns NVENC software sessions information for the associate GPU. 4288 * This command is similar to NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO but doesn't have 4289 * embedded pointers. 4290 * 4291 * Check NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO for detailed information. 4292 */ 4293 4294 #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID (0xAFU) 4295 4296 typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS { 4297 NvU32 sessionInfoTblEntry; 4298 NV2080_CTRL_NVENC_SW_SESSION_INFO sessionInfoTbl[NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES]; 4299 } NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS; 4300 4301 #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 (0x208001afU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID" */ 4302 4303 typedef struct NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO { 4304 NvU32 engDesc; 4305 NvU32 ctxAttr; 4306 NvU32 ctxBufferSize; 4307 NvU32 addrSpaceList; 4308 NvU32 registerBase; 4309 } NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO; 4310 #define NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS 0x40 4311 4312 #define NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO (0x208001b0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */ 4313 4314 #define NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID (0xB0U) 4315 4316 typedef struct NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS { 4317 NvU32 numConstructedFalcons; 4318 NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS]; 4319 } NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS; 4320 4321 /* 4322 * NV2080_CTRL_GPU_GET_FIPS_STATUS 4323 * 4324 * @brief get FIPS status (enabled/disabled) from GSP-RM 4325 * 4326 * 4327 * @return NV_OK on success 4328 * @return NV_ERR_ otherwise 4329 */ 4330 #define NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID (0xe4U) 4331 4332 typedef struct NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS { 4333 NvBool bFipsEnabled; 4334 } NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS; 4335 #define NV2080_CTRL_GPU_GET_FIPS_STATUS (0x208001e4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID" */ 4336 4337 4338 /* _ctrl2080gpu_h_ */ 4339