1 /*
2 * SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23 /*
24 * WARNING: This is an autogenerated file. DO NOT EDIT.
25 * This file is generated using below files:
26 * template file: inc/kernel/vgpu/gt_sdk-structures.h
27 * definition file: inc/kernel/vgpu/sdk-structures.def
28 */
29
30
31 #ifdef SDK_STRUCTURES
32 // These are copy of sdk structures, that will be used for the communication between the vmioplugin & guest RM.
33 // #if condition can be removed when this file is included in OpenRM-Orin build.
34 #include "vgpu/sdk-structures.h"
35 typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05
36 {
37 NvU64 physAddress NV_ALIGN_BYTES(8);
38 NvU32 numEntries;
39 NvU32 flags;
40 NvHandle hVASpace;
41 NvU32 chId;
42 NvU32 subDeviceId;
43 NvU32 pasid;
44 } NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05;
45
46 typedef NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05 NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v;
47
48 typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v03_00
49 {
50 NvU64 physAddr NV_ALIGN_BYTES(8);
51 NvU32 numEntries;
52 NvU32 aperture;
53 } NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v03_00;
54
55 typedef NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v03_00 NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v;
56
57 typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v03_00
58 {
59 NvU32 pdeIndex;
60 NvU32 flags;
61 NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS_v03_00 ptParams[NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE];
62 NvHandle hVASpace;
63 NvP64 pPdeBuffer NV_ALIGN_BYTES(8);
64 NvU32 subDeviceId;
65 } NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v03_00;
66
67 typedef NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v03_00 NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v;
68
69 typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00
70 {
71 NvU32 engineType;
72 NvHandle hClient;
73 NvU32 ChID;
74 NvHandle hChanClient;
75 NvHandle hObject;
76 NvHandle hVirtMemory;
77 NvU64 physAddress NV_ALIGN_BYTES(8);
78 NvU32 physAttr;
79 NvHandle hDmaHandle;
80 NvU32 index;
81 NvU64 size NV_ALIGN_BYTES(8);
82 } NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00;
83
84 typedef NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00 NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v;
85
86 typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20
87 {
88 NvU64 gpuPhysAddr NV_ALIGN_BYTES(8);
89 NvU64 gpuVirtAddr NV_ALIGN_BYTES(8);
90 NvU64 size NV_ALIGN_BYTES(8);
91 NvU32 physAttr;
92 NvU16 bufferId;
93 NvU8 bInitialize;
94 NvU8 bNonmapped;
95 } NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20;
96
97 typedef NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20 NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v;
98
99 typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20
100 {
101 NvU32 engineType;
102 NvHandle hClient;
103 NvU32 ChID;
104 NvHandle hChanClient;
105 NvHandle hObject;
106 NvHandle hVirtMemory;
107 NvU64 virtAddress NV_ALIGN_BYTES(8);
108 NvU64 size NV_ALIGN_BYTES(8);
109 NvU32 entryCount;
110 NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20 promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES];
111 } NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20;
112
113 typedef NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20 NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v;
114
115 typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00
116 {
117 NvU32 engineType;
118 NvHandle hClient;
119 NvU32 ChID;
120 NvHandle hChanClient;
121 NvHandle hObject;
122 } NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00;
123
124 typedef NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00 NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v;
125
126 typedef struct NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v03_00
127 {
128 NvHandle hClient;
129 NvHandle hDevice;
130 NvU32 engine;
131 NvHandle hVASpace;
132 } NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v03_00;
133
134 typedef NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v03_00 NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v;
135
136 typedef union NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v06_00
137 {
138 NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00 InitCtx;
139 NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00 EvictCtx;
140 NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v03_00 InvalidateTlb;
141 } NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v06_00;
142
143 typedef NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v06_00 NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v;
144
145 typedef struct NV5080_CTRL_DEFERRED_API_V2_PARAMS_v06_00
146 {
147 NvHandle hApiHandle;
148 NvU32 cmd;
149 NvU32 flags;
150 NvHandle hClientVA;
151 NvHandle hDeviceVA;
152 NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v06_00 api_bundle;
153 } NV5080_CTRL_DEFERRED_API_V2_PARAMS_v06_00;
154
155 typedef NV5080_CTRL_DEFERRED_API_V2_PARAMS_v06_00 NV5080_CTRL_DEFERRED_API_V2_PARAMS_v;
156
157 typedef struct NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00
158 {
159 NvU32 headIndex;
160 NvU32 blankingEnabled;
161 } NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00;
162
163 typedef NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00 NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v;
164
165 typedef struct NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07
166 {
167 NvU32 headIndex;
168 NvU32 isPrimary;
169 NvU32 offset;
170 NvU32 surfaceType;
171 NvU32 surfaceBlockHeight;
172 NvU32 surfacePitch;
173 NvU32 surfaceFormat;
174 NvU32 surfaceWidth;
175 NvU32 surfaceHeight;
176 NvU32 rectX;
177 NvU32 rectY;
178 NvU32 rectWidth;
179 NvU32 rectHeight;
180 NvU32 surfaceSize;
181 NvU32 surfaceKind;
182 NvU32 hHwResDevice;
183 NvU32 hHwResHandle;
184 NvU32 effectiveFbPageSize;
185 } NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07;
186
187 typedef NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07 NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v;
188
189 typedef struct NV_MEMORY_DESC_PARAMS_v18_01
190 {
191 NvU64 base NV_ALIGN_BYTES(8);
192 NvU64 size NV_ALIGN_BYTES(8);
193 NvU32 addressSpace;
194 NvU32 cacheAttrib;
195 } NV_MEMORY_DESC_PARAMS_v18_01;
196
197 typedef NV_MEMORY_DESC_PARAMS_v18_01 NV_MEMORY_DESC_PARAMS_v;
198
199 typedef struct NV_CHANNEL_ALLOC_PARAMS_v1F_04
200 {
201 NvHandle hObjectError;
202 NvHandle hObjectBuffer;
203 NvU64 gpFifoOffset NV_ALIGN_BYTES(8);
204 NvU32 gpFifoEntries;
205 NvU32 flags;
206 NvHandle hContextShare;
207 NvHandle hVASpace;
208 NvHandle hUserdMemory[1];
209 NvU64 userdOffset[1] NV_ALIGN_BYTES(8);
210 NvU32 engineType;
211 NvHandle hObjectEccError;
212 NV_MEMORY_DESC_PARAMS_v18_01 instanceMem;
213 NV_MEMORY_DESC_PARAMS_v18_01 ramfcMem;
214 NV_MEMORY_DESC_PARAMS_v18_01 userdMem;
215 NV_MEMORY_DESC_PARAMS_v18_01 mthdbufMem;
216 NvHandle hPhysChannelGroup;
217 NvHandle subDeviceId;
218 NvU32 internalFlags;
219 NV_MEMORY_DESC_PARAMS_v18_01 errorNotifierMem;
220 NV_MEMORY_DESC_PARAMS_v18_01 eccErrorNotifierMem;
221 } NV_CHANNEL_ALLOC_PARAMS_v1F_04;
222
223 typedef NV_CHANNEL_ALLOC_PARAMS_v1F_04 NV_CHANNEL_ALLOC_PARAMS_v;
224
225 typedef struct NV_DEVICE_ALLOCATION_PARAMETERS_v03_00
226 {
227 NvP64 szName NV_ALIGN_BYTES(8);
228 NvHandle hClientShare;
229 NvHandle hTargetClient;
230 NvHandle hTargetDevice;
231 NvV32 flags;
232 NvU64 vaSpaceSize NV_ALIGN_BYTES(8);
233 NvV32 vaMode;
234 NvU64 vaBase NV_ALIGN_BYTES(8);
235 } NV_DEVICE_ALLOCATION_PARAMETERS_v03_00;
236
237 typedef NV_DEVICE_ALLOCATION_PARAMETERS_v03_00 NV_DEVICE_ALLOCATION_PARAMETERS_v;
238
239 typedef struct NVOS00_PARAMETERS_v03_00
240 {
241 NvHandle hRoot;
242 NvHandle hObjectParent;
243 NvHandle hObjectOld;
244 NvV32 status;
245 } NVOS00_PARAMETERS_v03_00;
246
247 typedef NVOS00_PARAMETERS_v03_00 NVOS00_PARAMETERS_v;
248
249 typedef struct NVOS21_PARAMETERS_v03_00
250 {
251 NvHandle hRoot;
252 NvHandle hObjectParent;
253 NvHandle hObjectNew;
254 NvV32 hClass;
255 NvP64 pAllocParms NV_ALIGN_BYTES(8);
256 NvV32 status;
257 } NVOS21_PARAMETERS_v03_00;
258
259 typedef NVOS21_PARAMETERS_v03_00 NVOS21_PARAMETERS_v;
260
261 typedef struct NVOS33_PARAMETERS_v09_0B
262 {
263 NvHandle hClient;
264 NvHandle hDevice;
265 NvHandle hMemory;
266 NvU64 offset NV_ALIGN_BYTES(8);
267 NvU64 length NV_ALIGN_BYTES(8);
268 NvP64 pLinearAddress NV_ALIGN_BYTES(8);
269 NvU32 status;
270 NvU32 flags;
271 NvU64 bar1_offset NV_ALIGN_BYTES(8);
272 } NVOS33_PARAMETERS_v09_0B;
273
274 typedef NVOS33_PARAMETERS_v09_0B NVOS33_PARAMETERS_v;
275
276 typedef struct NVOS34_PARAMETERS_v03_00
277 {
278 NvHandle hClient;
279 NvHandle hDevice;
280 NvHandle hMemory;
281 NvP64 pLinearAddress NV_ALIGN_BYTES(8);
282 NvU32 status;
283 NvU32 flags;
284 } NVOS34_PARAMETERS_v03_00;
285
286 typedef NVOS34_PARAMETERS_v03_00 NVOS34_PARAMETERS_v;
287
288 typedef struct NVOS39_PARAMETERS_v03_00
289 {
290 NvHandle hClient;
291 NvHandle hObjectParent;
292 NvHandle hObjectNew;
293 NvV32 hClass;
294 NvV32 flags;
295 NvU32 selector;
296 NvHandle hMemory;
297 NvU64 offset NV_ALIGN_BYTES(8);
298 NvU64 limit NV_ALIGN_BYTES(8);
299 NvV32 status;
300 } NVOS39_PARAMETERS_v03_00;
301
302 typedef NVOS39_PARAMETERS_v03_00 NVOS39_PARAMETERS_v;
303
304 typedef struct NVOS46_PARAMETERS_v03_00
305 {
306 NvHandle hClient;
307 NvHandle hDevice;
308 NvHandle hDma;
309 NvHandle hMemory;
310 NvU64 offset NV_ALIGN_BYTES(8);
311 NvU64 length NV_ALIGN_BYTES(8);
312 NvV32 flags;
313 NvU64 dmaOffset NV_ALIGN_BYTES(8);
314 NvV32 status;
315 } NVOS46_PARAMETERS_v03_00;
316
317 typedef NVOS46_PARAMETERS_v03_00 NVOS46_PARAMETERS_v;
318
319 typedef struct NVOS47_PARAMETERS_v03_00
320 {
321 NvHandle hClient;
322 NvHandle hDevice;
323 NvHandle hDma;
324 NvHandle hMemory;
325 NvV32 flags;
326 NvU64 dmaOffset NV_ALIGN_BYTES(8);
327 NvV32 status;
328 } NVOS47_PARAMETERS_v03_00;
329
330 typedef NVOS47_PARAMETERS_v03_00 NVOS47_PARAMETERS_v;
331
332 typedef struct NVOS54_PARAMETERS_v03_00
333 {
334 NvHandle hClient;
335 NvHandle hObject;
336 NvRmctrlCmd cmd;
337 NvP64 params NV_ALIGN_BYTES(8);
338 NvU32 paramsSize;
339 NvV32 status;
340 } NVOS54_PARAMETERS_v03_00;
341
342 typedef NVOS54_PARAMETERS_v03_00 NVOS54_PARAMETERS_v;
343
344 typedef struct NVOS55_PARAMETERS_v03_00
345 {
346 NvHandle hClient;
347 NvHandle hParent;
348 NvHandle hObject;
349 NvHandle hClientSrc;
350 NvHandle hObjectSrc;
351 NvU32 flags;
352 NvU32 status;
353 } NVOS55_PARAMETERS_v03_00;
354
355 typedef NVOS55_PARAMETERS_v03_00 NVOS55_PARAMETERS_v;
356
357 typedef struct NV2080_CTRL_GR_ROUTE_INFO_v12_01
358 {
359 NvU32 flags;
360 NvU64 route NV_ALIGN_BYTES(8);
361 } NV2080_CTRL_GR_ROUTE_INFO_v12_01;
362
363 typedef NV2080_CTRL_GR_ROUTE_INFO_v12_01 NV2080_CTRL_GR_ROUTE_INFO_v;
364
365 typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01
366 {
367 NvHandle hClientTarget;
368 NvHandle hChannelTarget;
369 NvU32 reserved00[3];
370 NvU32 regOpCount;
371 NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo;
372 NvP64 regOps NV_ALIGN_BYTES(8);
373 } NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01;
374
375 typedef NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01 NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v;
376
377 typedef struct NV2080_CTRL_GPU_REG_OP_v03_00
378 {
379 NvU8 regOp;
380 NvU8 regType;
381 NvU8 regStatus;
382 NvU8 regQuad;
383 NvU32 regGroupMask;
384 NvU32 regSubGroupMask;
385 NvU32 regOffset;
386 NvU32 regValueHi;
387 NvU32 regValueLo;
388 NvU32 regAndNMaskHi;
389 NvU32 regAndNMaskLo;
390 } NV2080_CTRL_GPU_REG_OP_v03_00;
391
392 typedef NV2080_CTRL_GPU_REG_OP_v03_00 NV2080_CTRL_GPU_REG_OP_v;
393
394 typedef struct NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C
395 {
396 NvU32 frameRateLimiter;
397 NvU32 swVSyncEnabled;
398 NvU32 cudaEnabled;
399 NvU32 pluginPteBlitEnabled;
400 NvU32 disableWddm1xPreemption;
401 NvU32 debugBufferSize;
402 NvP64 debugBuffer NV_ALIGN_BYTES(8);
403 NvU64 guestFbOffset NV_ALIGN_BYTES(8);
404 NvU64 mappableCpuHostAperture NV_ALIGN_BYTES(8);
405 NvU32 linuxInterruptOptimization;
406 NvU32 vgpuDeviceCapsBits;
407 NvU32 maxPixels;
408 NvU32 uvmEnabledFeatures;
409 NvBool enableKmdSysmemScratch;
410 } NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C;
411
412 typedef NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v;
413
414 typedef struct NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00
415 {
416 char szHostDriverVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
417 char szHostVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
418 char szHostTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
419 char szPluginTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
420 char szHostUnameBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
421 NvU32 iHostChangelistNumber;
422 NvU32 iPluginChangelistNumber;
423 } NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00;
424
425 typedef NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00 NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v;
426
427 typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00
428 {
429 NvU32 index;
430 NvU32 flags;
431 NvU32 length;
432 NvU8 data[NV2080_GPU_MAX_GID_LENGTH];
433 } NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00;
434
435 typedef NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00 NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v;
436
437 typedef struct NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_v03_00
438 {
439 NvU32 gpcMask;
440 } NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_v03_00;
441
442 typedef NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_v03_00 NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_v;
443
444 typedef struct NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_v03_00
445 {
446 NvU32 gpcId;
447 NvU32 tpcMask;
448 } NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_v03_00;
449
450 typedef NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_v03_00 NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_v;
451
452 typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_v03_00
453 {
454 NvU32 gpcId;
455 NvU32 zcullMask;
456 } NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_v03_00;
457
458 typedef NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_v03_00 NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_v;
459
460 typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v03_00
461 {
462 NvU32 BoardID;
463 char chipSKU[4];
464 char chipSKUMod[2];
465 char project[5];
466 char projectSKU[5];
467 char CDP[6];
468 char projectSKUMod[2];
469 NvU32 businessCycle;
470 } NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v03_00;
471
472 typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E
473 {
474 NvU32 BoardID;
475 char chipSKU[9];
476 char chipSKUMod[5];
477 NvU32 skuConfigVersion;
478 char project[5];
479 char projectSKU[5];
480 char CDP[6];
481 char projectSKUMod[2];
482 NvU32 businessCycle;
483 } NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E;
484
485 typedef NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v;
486
487 typedef struct NV2080_CTRL_GPU_PARTITION_SPAN_v18_03
488 {
489 NvU64 lo NV_ALIGN_BYTES(8);
490 NvU64 hi NV_ALIGN_BYTES(8);
491 } NV2080_CTRL_GPU_PARTITION_SPAN_v18_03;
492
493 typedef NV2080_CTRL_GPU_PARTITION_SPAN_v18_03 NV2080_CTRL_GPU_PARTITION_SPAN_v;
494
495 typedef struct GPU_PARTITION_INFO_v24_05
496 {
497 NvU32 swizzId;
498 NvU32 grEngCount;
499 NvU32 veidCount;
500 NvU32 ceCount;
501 NvU32 gpcCount;
502 NvU32 virtualGpcCount;
503 NvU32 gfxGpcCount;
504 NvU32 gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
505 NvU32 virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
506 NvU32 gfxGpcPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
507 NvU32 veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS];
508 NvU32 nvDecCount;
509 NvU32 nvEncCount;
510 NvU32 nvJpgCount;
511 NvU32 partitionFlag;
512 NvU32 smCount;
513 NvU32 nvOfaCount;
514 NvU64 memSize NV_ALIGN_BYTES(8);
515 NvBool bValid;
516 NV2080_CTRL_GPU_PARTITION_SPAN_v18_03 span;
517 NvU64 validCTSIdMask NV_ALIGN_BYTES(8);
518 } GPU_PARTITION_INFO_v24_05;
519
520 typedef GPU_PARTITION_INFO_v24_05 GPU_PARTITION_INFO_v;
521
522 typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO_v03_00
523 {
524 NvU64 base NV_ALIGN_BYTES(8);
525 NvU64 limit NV_ALIGN_BYTES(8);
526 NvU64 reserved NV_ALIGN_BYTES(8);
527 NvU32 performance;
528 NvBool supportCompressed;
529 NvBool supportISO;
530 NvBool bProtected;
531 NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG_v03_00 blackList;
532 } NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO_v03_00;
533
534 typedef NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO_v03_00 NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO_v;
535
536 typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00
537 {
538 NvU32 numFBRegions;
539 NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO_v03_00 fbRegion[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES];
540 } NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00;
541
542 typedef NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00 NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v;
543
544 typedef struct NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00
545 {
546 NV2080_CTRL_CMD_PERF_VID_ENG engineType;
547 NvU32 clkPercentBusy;
548 NvU32 samplingPeriodUs;
549 } NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00;
550
551 typedef NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00 NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v;
552
553 typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00
554 {
555 NvU32 util;
556 NvU32 procId;
557 NvU32 subProcessID;
558 } NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00;
559
560 typedef NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v;
561
562 typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E
563 {
564 NvU64 timeStamp NV_ALIGN_BYTES(8);
565 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 fb;
566 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 gr;
567 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 nvenc;
568 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 nvdec;
569 } NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E;
570
571 typedef NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v;
572
573 typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E
574 {
575 NvU8 type;
576 NvU32 bufSize;
577 NvU32 count;
578 NvU32 tracker;
579 NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E];
580 } NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E;
581
582 typedef NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v;
583
584 typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00
585 {
586 NvU32 flags;
587 NvBool bBridgeless;
588 NvU32 currLimits[NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM];
589 } NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00;
590
591 typedef NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00 NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v;
592
593 typedef struct NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C
594 {
595 NvU32 gpuId;
596 NvU32 vmPid;
597 NvU32 state;
598 } NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C;
599
600 typedef NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v;
601
602 typedef struct NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C
603 {
604 NvU32 gpuId;
605 NvU32 vmPid;
606 NvU32 newState;
607 } NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C;
608
609 typedef NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v;
610
611 typedef struct NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C
612 {
613 NvU32 gpuId;
614 NvU32 vmPid;
615 NvU32 passIndex;
616 NvU32 pidCount;
617 NvU32 pidTable[NV0000_GPUACCT_RPC_PID_MAX_QUERY_COUNT];
618 } NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C;
619
620 typedef NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v;
621
622 typedef struct NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C
623 {
624 NvU32 gpuId;
625 NvU32 pid;
626 NvU32 subPid;
627 NvU32 gpuUtil;
628 NvU32 fbUtil;
629 NvU64 maxFbUsage NV_ALIGN_BYTES(8);
630 NvU64 startTime NV_ALIGN_BYTES(8);
631 NvU64 endTime NV_ALIGN_BYTES(8);
632 } NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C;
633
634 typedef NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v;
635
636 typedef struct NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C
637 {
638 NvU32 gpuId;
639 NvU32 vmPid;
640 } NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C;
641
642 typedef NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v;
643
644 typedef union vgpuGetEngineUtilization_data_v1F_0E
645 {
646 NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00 vidPerfmonSample;
647 NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C getAccountingState;
648 NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C setAccountingState;
649 NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C getAccountingPidList;
650 NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C procAccountingInfo;
651 NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C clearAccountingInfo;
652 NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E gpumonPerfmonsampleV2[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E];
653 } vgpuGetEngineUtilization_data_v1F_0E;
654
655 typedef vgpuGetEngineUtilization_data_v1F_0E vgpuGetEngineUtilization_data_v;
656
657 typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_v01_00
658 {
659 NvU32 totalVFs;
660 NvU32 firstVfOffset;
661 NvU32 vfFeatureMask;
662 NvU64 FirstVFBar0Address NV_ALIGN_BYTES(8);
663 NvU64 FirstVFBar1Address NV_ALIGN_BYTES(8);
664 NvU64 FirstVFBar2Address NV_ALIGN_BYTES(8);
665 NvU64 bar0Size NV_ALIGN_BYTES(8);
666 NvU64 bar1Size NV_ALIGN_BYTES(8);
667 NvU64 bar2Size NV_ALIGN_BYTES(8);
668 NvBool b64bitBar0;
669 NvBool b64bitBar1;
670 NvBool b64bitBar2;
671 NvBool bSriovEnabled;
672 NvBool bSriovHeavyEnabled;
673 } NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_v01_00;
674
675 typedef NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_v01_00 NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_v;
676
677 typedef struct UpdateBarPde_v15_00
678 {
679 NV_RPC_UPDATE_PDE_BAR_TYPE barType;
680 NvU64 entryValue NV_ALIGN_BYTES(8);
681 NvU64 entryLevelShift NV_ALIGN_BYTES(8);
682 } UpdateBarPde_v15_00;
683
684 typedef UpdateBarPde_v15_00 UpdateBarPde_v;
685
686 typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00
687 {
688 NvU32 dataSize;
689 NvU8 data[256];
690 } NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00;
691
692 typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v;
693
694 typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00
695 {
696 NvU32 dataSize;
697 NvU8 data[512];
698 } NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00;
699
700 typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v;
701
702 typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00
703 {
704 NvU32 dataSize;
705 NvU8 data[1024];
706 } NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00;
707
708 typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v;
709
710 typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00
711 {
712 NvU32 dataSize;
713 NvU8 data[2048];
714 } NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00;
715
716 typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v;
717
718 typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00
719 {
720 NvU32 dataSize;
721 NvU8 data[4096];
722 } NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00;
723
724 typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v;
725
726 typedef struct NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00
727 {
728 NvU32 linkId;
729 NvBool bIsGpuDegraded;
730 } NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00;
731
732 typedef NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v;
733
734 typedef struct NV_DEVICE_NAME_v13_06
735 {
736 NvU8 adapterName[NV2080_GPU_MAX_NAME_STRING_LENGTH];
737 NvU8 shortGpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
738 NvU16 adapterName_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH];
739 } NV_DEVICE_NAME_v13_06;
740
741 typedef NV_DEVICE_NAME_v13_06 NV_DEVICE_NAME_v;
742
743 typedef struct NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00
744 {
745 NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE_V25_00];
746 NvU32 instanceId;
747 } NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00;
748
749 typedef NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00 NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v;
750
751 typedef struct NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO_v25_01
752 {
753 NvU32 engDesc;
754 NvU32 ctxAttr;
755 NvU32 ctxBufferSize;
756 NvU32 addrSpaceList;
757 NvU32 registerBase;
758 } NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO_v25_01;
759
760 typedef NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO_v25_01 NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO_v;
761
762 typedef struct NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01
763 {
764 NvU32 numConstructedFalcons;
765 NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO_v25_01 constructedFalconsTable[NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS_V25_01];
766 } NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01;
767
768 typedef NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01 NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v;
769
770 typedef struct VGPU_STATIC_PROPERTIES_v1B_01
771 {
772 NvU32 encSessionStatsReportingState;
773 NvBool bProfilingTracingEnabled;
774 NvBool bDebuggingEnabled;
775 NvU32 channelCount;
776 NvBool bPblObjNotPresent;
777 } VGPU_STATIC_PROPERTIES_v1B_01;
778
779 typedef struct VGPU_STATIC_PROPERTIES_v26_03
780 {
781 NvU32 encSessionStatsReportingState;
782 NvBool bProfilingTracingEnabled;
783 NvBool bDebuggingEnabled;
784 NvU32 channelCount;
785 NvBool bPblObjNotPresent;
786 NvU64 vmmuSegmentSize NV_ALIGN_BYTES(8);
787 } VGPU_STATIC_PROPERTIES_v26_03;
788
789 typedef VGPU_STATIC_PROPERTIES_v26_03 VGPU_STATIC_PROPERTIES_v;
790
791 typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE_v20_04
792 {
793 NvU8 computeSize;
794 NvU32 gfxGpcCount;
795 NvU32 gpcCount;
796 NvU32 veidCount;
797 NvU32 smCount;
798 } NV2080_CTRL_GPU_COMPUTE_PROFILE_v20_04;
799
800 typedef NV2080_CTRL_GPU_COMPUTE_PROFILE_v20_04 NV2080_CTRL_GPU_COMPUTE_PROFILE_v;
801
802 typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04
803 {
804 NvU32 profileCount;
805 NV2080_CTRL_GPU_COMPUTE_PROFILE_v20_04 profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE_v20_04];
806 } NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04;
807
808 typedef NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04 NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v;
809
810 typedef struct alloc_object_NV50_TESLA_v03_00
811 {
812 NvU32 version;
813 NvU32 flags;
814 NvU32 size;
815 NvU32 caps;
816 } alloc_object_NV50_TESLA_v03_00;
817
818 typedef alloc_object_NV50_TESLA_v03_00 alloc_object_NV50_TESLA_v;
819
820 typedef struct alloc_object_GT212_DMA_COPY_v03_00
821 {
822 NvU32 version;
823 NvU32 engineInstance;
824 } alloc_object_GT212_DMA_COPY_v03_00;
825
826 typedef alloc_object_GT212_DMA_COPY_v03_00 alloc_object_GT212_DMA_COPY_v;
827
828 typedef struct alloc_object_GF100_DISP_SW_v03_00
829 {
830 NvU32 _reserved1;
831 NvU64 _reserved2 NV_ALIGN_BYTES(8);
832 NvU32 logicalHeadId;
833 NvU32 displayMask;
834 NvU32 caps;
835 } alloc_object_GF100_DISP_SW_v03_00;
836
837 typedef alloc_object_GF100_DISP_SW_v03_00 alloc_object_GF100_DISP_SW_v;
838
839 typedef struct alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08
840 {
841 NvU32 hObjectError;
842 NvU32 hVASpace;
843 NvU32 engineType;
844 } alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08;
845
846 typedef alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08 alloc_object_KEPLER_CHANNEL_GROUP_A_v;
847
848 typedef struct alloc_object_FERMI_CONTEXT_SHARE_A_v04_00
849 {
850 NvU32 hVASpace;
851 NvU32 flags;
852 NvU32 subctxId;
853 } alloc_object_FERMI_CONTEXT_SHARE_A_v04_00;
854
855 typedef alloc_object_FERMI_CONTEXT_SHARE_A_v04_00 alloc_object_FERMI_CONTEXT_SHARE_A_v;
856
857 typedef struct alloc_object_NVD0B7_VIDEO_ENCODER_v03_00
858 {
859 NvU32 size;
860 NvU32 prohibitMultipleInstances;
861 NvU32 engineInstance;
862 } alloc_object_NVD0B7_VIDEO_ENCODER_v03_00;
863
864 typedef alloc_object_NVD0B7_VIDEO_ENCODER_v03_00 alloc_object_NVD0B7_VIDEO_ENCODER_v;
865
866 typedef struct alloc_object_FERMI_VASPACE_A_v03_00
867 {
868 NvU32 index;
869 NvU32 flags;
870 NvU64 vaSize NV_ALIGN_BYTES(8);
871 NvU32 bigPageSize;
872 NvU64 vaBase NV_ALIGN_BYTES(8);
873 } alloc_object_FERMI_VASPACE_A_v03_00;
874
875 typedef alloc_object_FERMI_VASPACE_A_v03_00 alloc_object_FERMI_VASPACE_A_v;
876
877 typedef struct alloc_object_NVB0B0_VIDEO_DECODER_v03_00
878 {
879 NvU32 size;
880 NvU32 prohibitMultipleInstances;
881 } alloc_object_NVB0B0_VIDEO_DECODER_v03_00;
882
883 typedef alloc_object_NVB0B0_VIDEO_DECODER_v03_00 alloc_object_NVB0B0_VIDEO_DECODER_v;
884
885 typedef struct alloc_object_NVC4B0_VIDEO_DECODER_v12_02
886 {
887 NvU32 size;
888 NvU32 prohibitMultipleInstances;
889 NvU32 engineInstance;
890 } alloc_object_NVC4B0_VIDEO_DECODER_v12_02;
891
892 typedef alloc_object_NVC4B0_VIDEO_DECODER_v12_02 alloc_object_NVC4B0_VIDEO_DECODER_v;
893
894 typedef struct alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00
895 {
896 NvHandle hDebuggerClient;
897 NvHandle hAppClient;
898 NvHandle hClass3dObject;
899 } alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00;
900
901 typedef alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00 alloc_object_NV83DE_ALLOC_PARAMETERS_v;
902
903 typedef struct alloc_object_NVENC_SW_SESSION_v06_01
904 {
905 NvU32 codecType;
906 NvU32 hResolution;
907 NvU32 vResolution;
908 } alloc_object_NVENC_SW_SESSION_v06_01;
909
910 typedef alloc_object_NVENC_SW_SESSION_v06_01 alloc_object_NVENC_SW_SESSION_v;
911
912 typedef struct alloc_object_NVFBC_SW_SESSION_v12_04
913 {
914 NvU32 displayOrdinal;
915 NvU32 sessionType;
916 NvU32 sessionFlags;
917 NvU32 hMaxResolution;
918 NvU32 vMaxResolution;
919 } alloc_object_NVFBC_SW_SESSION_v12_04;
920
921 typedef alloc_object_NVFBC_SW_SESSION_v12_04 alloc_object_NVFBC_SW_SESSION_v;
922
923 typedef struct alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02
924 {
925 NvU32 size;
926 NvU32 prohibitMultipleInstances;
927 NvU32 engineInstance;
928 } alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02;
929
930 typedef alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02 alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v;
931
932 typedef struct alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02
933 {
934 NvHandle hSubDevice;
935 NvHandle hPeerSubDevice;
936 NvU32 subDevicePeerIdMask;
937 NvU32 peerSubDevicePeerIdMask;
938 NvU64 mailboxBar1Addr NV_ALIGN_BYTES(8);
939 NvU32 mailboxTotalSize;
940 NvU32 flags;
941 } alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02;
942
943 typedef alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02 alloc_object_NV503B_ALLOC_PARAMETERS_v;
944
945 typedef struct alloc_object_NV503C_ALLOC_PARAMETERS_v18_15
946 {
947 NvU32 flags;
948 NvU64 p2pToken NV_ALIGN_BYTES(8);
949 } alloc_object_NV503C_ALLOC_PARAMETERS_v18_15;
950
951 typedef alloc_object_NV503C_ALLOC_PARAMETERS_v18_15 alloc_object_NV503C_ALLOC_PARAMETERS_v;
952
953 typedef struct alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00
954 {
955 NvU32 swizzId;
956 } alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00;
957
958 typedef alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00 alloc_object_NVC637_ALLOCATION_PARAMETERS_v;
959
960 typedef struct alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06
961 {
962 NvU32 execPartitionId;
963 } alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06;
964
965 typedef alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06 alloc_object_NVC638_ALLOCATION_PARAMETERS_v;
966
967 typedef struct alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03
968 {
969 NvU64 offset NV_ALIGN_BYTES(8);
970 NvU64 limit NV_ALIGN_BYTES(8);
971 NvHandle hVASpace;
972 } alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03;
973
974 typedef alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03 alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v;
975
976 typedef struct alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01
977 {
978 NvU32 numHeads;
979 NvU32 numSors;
980 NvU32 numDsis;
981 } alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01;
982
983 typedef alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01 alloc_object_NVC670_ALLOCATION_PARAMETERS_v;
984
985 typedef struct alloc_object_NVC9FA_VIDEO_OFA_v1F_00
986 {
987 NvU32 size;
988 NvU32 prohibitMultipleInstances;
989 } alloc_object_NVC9FA_VIDEO_OFA_v1F_00;
990
991 typedef alloc_object_NVC9FA_VIDEO_OFA_v1F_00 alloc_object_NVC9FA_VIDEO_OFA_v;
992
993 typedef struct alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03
994 {
995 NvHandle hClientTarget;
996 NvHandle hContextTarget;
997 } alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03;
998
999 typedef alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03 alloc_object_NVB2CC_ALLOC_PARAMETERS_v;
1000
1001 typedef struct NV_GR_ALLOCATION_PARAMETERS_v1A_17
1002 {
1003 NvU32 version;
1004 NvU32 flags;
1005 NvU32 size;
1006 NvU32 caps;
1007 } NV_GR_ALLOCATION_PARAMETERS_v1A_17;
1008
1009 typedef NV_GR_ALLOCATION_PARAMETERS_v1A_17 NV_GR_ALLOCATION_PARAMETERS_v;
1010
1011 typedef struct alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B
1012 {
1013 NvHandle hClient;
1014 NvHandle hChannel;
1015 } alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B;
1016
1017 typedef alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v;
1018
1019 typedef struct NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C
1020 {
1021 NvU64 offset NV_ALIGN_BYTES(8);
1022 NvHandle hVidMem;
1023 NvU32 flags;
1024 } NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C;
1025
1026 typedef NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v;
1027
1028 typedef struct alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C
1029 {
1030 NvU64 alignment NV_ALIGN_BYTES(8);
1031 NvU64 allocSize NV_ALIGN_BYTES(8);
1032 NvU32 pageSize;
1033 NvU32 allocFlags;
1034 NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C map;
1035 } alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C;
1036
1037 typedef alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C alloc_object_NV00F8_ALLOCATION_PARAMETERS_v;
1038
1039 typedef struct alloc_object_NV2081_ALLOC_PARAMETERS_v25_08
1040 {
1041 NvU32 reserved;
1042 } alloc_object_NV2081_ALLOC_PARAMETERS_v25_08;
1043
1044 typedef alloc_object_NV2081_ALLOC_PARAMETERS_v25_08 alloc_object_NV2081_ALLOC_PARAMETERS_v;
1045
1046 typedef union alloc_object_params_v25_08
1047 {
1048 alloc_object_NV50_TESLA_v03_00 param_NV50_TESLA;
1049 alloc_object_GT212_DMA_COPY_v03_00 param_GT212_DMA_COPY;
1050 alloc_object_GF100_DISP_SW_v03_00 param_GF100_DISP_SW;
1051 alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08 param_KEPLER_CHANNEL_GROUP_A;
1052 alloc_object_FERMI_CONTEXT_SHARE_A_v04_00 param_FERMI_CONTEXT_SHARE_A;
1053 alloc_object_NVD0B7_VIDEO_ENCODER_v03_00 param_NVD0B7_VIDEO_ENCODER;
1054 alloc_object_FERMI_VASPACE_A_v03_00 param_FERMI_VASPACE_A;
1055 alloc_object_NVB0B0_VIDEO_DECODER_v03_00 param_NVB0B0_VIDEO_DECODER;
1056 alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00 param_NV83DE_ALLOC_PARAMETERS;
1057 alloc_object_NVENC_SW_SESSION_v06_01 param_NVENC_SW_SESSION;
1058 alloc_object_NVC4B0_VIDEO_DECODER_v12_02 param_NVC4B0_VIDEO_DECODER;
1059 alloc_object_NVFBC_SW_SESSION_v12_04 param_NVFBC_SW_SESSION;
1060 alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02 param_NV_NVJPG_ALLOCATION_PARAMETERS;
1061 alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02 param_NV503B_ALLOC_PARAMETERS;
1062 alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00 param_NVC637_ALLOCATION_PARAMETERS;
1063 alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03 param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS;
1064 alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06 param_NVC638_ALLOCATION_PARAMETERS;
1065 alloc_object_NV503C_ALLOC_PARAMETERS_v18_15 param_NV503C_ALLOC_PARAMETERS;
1066 alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01 param_NVC670_ALLOCATION_PARAMETERS;
1067 alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03 param_NVB2CC_ALLOC_PARAMETERS;
1068 NV_GR_ALLOCATION_PARAMETERS_v1A_17 param_NV_GR_ALLOCATION_PARAMETERS;
1069 alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS;
1070 alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C param_NV00F8_ALLOCATION_PARAMETERS;
1071 alloc_object_NVC9FA_VIDEO_OFA_v1F_00 param_NVC9FA_VIDEO_OFA;
1072 alloc_object_NV2081_ALLOC_PARAMETERS_v25_08 param_NV2081_ALLOC_PARAMETERS;
1073 } alloc_object_params_v25_08;
1074
1075 typedef union alloc_object_params_v26_00
1076 {
1077 alloc_object_NV50_TESLA_v03_00 param_NV50_TESLA;
1078 alloc_object_GT212_DMA_COPY_v03_00 param_GT212_DMA_COPY;
1079 alloc_object_GF100_DISP_SW_v03_00 param_GF100_DISP_SW;
1080 alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08 param_KEPLER_CHANNEL_GROUP_A;
1081 alloc_object_FERMI_CONTEXT_SHARE_A_v04_00 param_FERMI_CONTEXT_SHARE_A;
1082 alloc_object_NVD0B7_VIDEO_ENCODER_v03_00 param_NVD0B7_VIDEO_ENCODER;
1083 alloc_object_FERMI_VASPACE_A_v03_00 param_FERMI_VASPACE_A;
1084 alloc_object_NVB0B0_VIDEO_DECODER_v03_00 param_NVB0B0_VIDEO_DECODER;
1085 alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00 param_NV83DE_ALLOC_PARAMETERS;
1086 alloc_object_NVENC_SW_SESSION_v06_01 param_NVENC_SW_SESSION;
1087 alloc_object_NVC4B0_VIDEO_DECODER_v12_02 param_NVC4B0_VIDEO_DECODER;
1088 alloc_object_NVFBC_SW_SESSION_v12_04 param_NVFBC_SW_SESSION;
1089 alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02 param_NV_NVJPG_ALLOCATION_PARAMETERS;
1090 alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02 param_NV503B_ALLOC_PARAMETERS;
1091 alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00 param_NVC637_ALLOCATION_PARAMETERS;
1092 alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03 param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS;
1093 alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06 param_NVC638_ALLOCATION_PARAMETERS;
1094 alloc_object_NV503C_ALLOC_PARAMETERS_v18_15 param_NV503C_ALLOC_PARAMETERS;
1095 alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01 param_NVC670_ALLOCATION_PARAMETERS;
1096 alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03 param_NVB2CC_ALLOC_PARAMETERS;
1097 NV_GR_ALLOCATION_PARAMETERS_v1A_17 param_NV_GR_ALLOCATION_PARAMETERS;
1098 alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS;
1099 alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C param_NV00F8_ALLOCATION_PARAMETERS;
1100 alloc_object_NVC9FA_VIDEO_OFA_v1F_00 param_NVC9FA_VIDEO_OFA;
1101 alloc_object_NV2081_ALLOC_PARAMETERS_v25_08 param_NV2081_ALLOC_PARAMETERS;
1102 NvU8 param_padding[NV_ALLOC_STRUCTURE_SIZE_v26_00];
1103 } alloc_object_params_v26_00;
1104
1105 typedef union alloc_object_params_v27_00
1106 {
1107 alloc_object_NV50_TESLA_v03_00 param_NV50_TESLA;
1108 alloc_object_GT212_DMA_COPY_v03_00 param_GT212_DMA_COPY;
1109 alloc_object_GF100_DISP_SW_v03_00 param_GF100_DISP_SW;
1110 alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08 param_KEPLER_CHANNEL_GROUP_A;
1111 alloc_object_FERMI_CONTEXT_SHARE_A_v04_00 param_FERMI_CONTEXT_SHARE_A;
1112 alloc_object_NVD0B7_VIDEO_ENCODER_v03_00 param_NVD0B7_VIDEO_ENCODER;
1113 alloc_object_FERMI_VASPACE_A_v03_00 param_FERMI_VASPACE_A;
1114 alloc_object_NVB0B0_VIDEO_DECODER_v03_00 param_NVB0B0_VIDEO_DECODER;
1115 alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00 param_NV83DE_ALLOC_PARAMETERS;
1116 alloc_object_NVENC_SW_SESSION_v06_01 param_NVENC_SW_SESSION;
1117 alloc_object_NVC4B0_VIDEO_DECODER_v12_02 param_NVC4B0_VIDEO_DECODER;
1118 alloc_object_NVFBC_SW_SESSION_v12_04 param_NVFBC_SW_SESSION;
1119 alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02 param_NV_NVJPG_ALLOCATION_PARAMETERS;
1120 alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02 param_NV503B_ALLOC_PARAMETERS;
1121 alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00 param_NVC637_ALLOCATION_PARAMETERS;
1122 alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03 param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS;
1123 alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06 param_NVC638_ALLOCATION_PARAMETERS;
1124 alloc_object_NV503C_ALLOC_PARAMETERS_v18_15 param_NV503C_ALLOC_PARAMETERS;
1125 alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01 param_NVC670_ALLOCATION_PARAMETERS;
1126 alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03 param_NVB2CC_ALLOC_PARAMETERS;
1127 NV_GR_ALLOCATION_PARAMETERS_v1A_17 param_NV_GR_ALLOCATION_PARAMETERS;
1128 alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS;
1129 alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C param_NV00F8_ALLOCATION_PARAMETERS;
1130 alloc_object_NVC9FA_VIDEO_OFA_v1F_00 param_NVC9FA_VIDEO_OFA;
1131 alloc_object_NV2081_ALLOC_PARAMETERS_v25_08 param_NV2081_ALLOC_PARAMETERS;
1132 NvU8 param_padding[NV_ALLOC_STRUCTURE_SIZE_v26_00];
1133 } alloc_object_params_v27_00;
1134
1135 typedef alloc_object_params_v27_00 alloc_object_params_v;
1136
1137 typedef struct gpu_exec_reg_ops_v12_01
1138 {
1139 NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01 reg_op_params;
1140 NV2080_CTRL_GPU_REG_OP_v03_00 operations[];
1141 } gpu_exec_reg_ops_v12_01;
1142
1143 typedef gpu_exec_reg_ops_v12_01 gpu_exec_reg_ops_v;
1144
1145 typedef struct idle_channel_list_v03_00
1146 {
1147 NvU32 phClient;
1148 NvU32 phDevice;
1149 NvU32 phChannel;
1150 } idle_channel_list_v03_00;
1151
1152 typedef idle_channel_list_v03_00 idle_channel_list_v;
1153
1154 typedef struct NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK_v03_00
1155 {
1156 NvU64 ptePhysAddr NV_ALIGN_BYTES(8);
1157 NvU32 pteCacheAttrib;
1158 NvU32 pteEntrySize;
1159 NvU32 pageSize;
1160 NvU32 pteAddrSpace;
1161 NvU32 pdeVASpaceSize;
1162 NvU32 pdeFlags;
1163 } NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK_v03_00;
1164
1165 typedef NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK_v03_00 NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK_v;
1166
1167 typedef struct NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_v03_00
1168 {
1169 NvU64 gpuAddr NV_ALIGN_BYTES(8);
1170 NvU64 pdeVirtAddr NV_ALIGN_BYTES(8);
1171 NvU32 pdeEntrySize;
1172 NvU32 pdeAddrSpace;
1173 NvU32 pdeSize;
1174 NvU32 subDeviceId;
1175 NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK_v03_00 pteBlocks[NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS];
1176 NvU64 pdbAddr NV_ALIGN_BYTES(8);
1177 NvHandle hVASpace;
1178 } NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_v03_00;
1179
1180 typedef NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_v03_00 NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_v;
1181
1182 typedef struct NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v03_00
1183 {
1184 NvHandle hVASpace;
1185 NvU32 flags;
1186 } NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v03_00;
1187
1188 typedef NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v03_00 NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v;
1189
1190 typedef struct NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00
1191 {
1192 NvHandle hVASpace;
1193 } NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00;
1194
1195 typedef NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00 NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v;
1196
1197 typedef struct NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_v03_00
1198 {
1199 NvU64 vaSpaceSize NV_ALIGN_BYTES(8);
1200 NvHandle hVASpace;
1201 } NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_v03_00;
1202
1203 typedef NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_v03_00 NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_v;
1204
1205 typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05
1206 {
1207 NvHandle hVASpace;
1208 NvU32 subDeviceId;
1209 } NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05;
1210
1211 typedef NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v;
1212
1213 typedef struct NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_v03_00
1214 {
1215 NvU32 engineId;
1216 NvU32 alignment;
1217 NvU32 size;
1218 } NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_v03_00;
1219
1220 typedef NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_v03_00 NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_v;
1221
1222 typedef struct NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_v03_00
1223 {
1224 NvU32 engineID;
1225 NvU32 gpEntries;
1226 NvU32 pbEntries;
1227 } NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_v03_00;
1228
1229 typedef NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_v03_00 NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_v;
1230
1231 typedef struct VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09
1232 {
1233 NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_v03_00 fifoLatencyBufferSize[NV2080_ENGINE_TYPE_LAST_v1C_09];
1234 } VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09;
1235
1236 typedef struct VGPU_GET_LATENCY_BUFFER_SIZE_v27_02
1237 {
1238 NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_v03_00 fifoLatencyBufferSize[NV2080_ENGINE_TYPE_LAST_v27_02];
1239 } VGPU_GET_LATENCY_BUFFER_SIZE_v27_02;
1240
1241 typedef VGPU_GET_LATENCY_BUFFER_SIZE_v27_02 VGPU_GET_LATENCY_BUFFER_SIZE_v;
1242
1243 typedef struct NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00
1244 {
1245 NvHandle hChannel;
1246 NvU32 property;
1247 NvU64 value NV_ALIGN_BYTES(8);
1248 } NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00;
1249
1250 typedef NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00 NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v;
1251
1252 typedef struct NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01
1253 {
1254 NvU32 flags;
1255 NvHandle hClient;
1256 NvHandle hChannel;
1257 NvU64 vMemPtrs[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END] NV_ALIGN_BYTES(8);
1258 NvU32 gfxpPreemptMode;
1259 NvU32 cilpPreemptMode;
1260 NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo;
1261 } NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01;
1262
1263 typedef NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01 NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v;
1264
1265 typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00
1266 {
1267 NvHandle hClient;
1268 NvHandle hChannel;
1269 NvU64 vMemPtr NV_ALIGN_BYTES(8);
1270 NvU32 zcullMode;
1271 } NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00;
1272
1273 typedef NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00 NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v;
1274
1275 typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_v12_01
1276 {
1277 NvHandle hChannel;
1278 NvHandle hShareClient;
1279 NvHandle hShareChannel;
1280 NvU32 zcullMode;
1281 NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo;
1282 } NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_v12_01;
1283
1284 typedef NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_v12_01 NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_v;
1285
1286 typedef struct NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01
1287 {
1288 NvU32 widthAlignPixels;
1289 NvU32 heightAlignPixels;
1290 NvU32 pixelSquaresByAliquots;
1291 NvU32 aliquotTotal;
1292 NvU32 zcullRegionByteMultiplier;
1293 NvU32 zcullRegionHeaderSize;
1294 NvU32 zcullSubregionHeaderSize;
1295 NvU32 subregionCount;
1296 NvU32 subregionWidthAlignPixels;
1297 NvU32 subregionHeightAlignPixels;
1298 NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo;
1299 } NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01;
1300
1301 typedef NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01 NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v;
1302
1303 typedef struct NV2080_CTRL_PERF_BOOST_PARAMS_v03_00
1304 {
1305 NvU32 flags;
1306 NvU32 duration;
1307 } NV2080_CTRL_PERF_BOOST_PARAMS_v03_00;
1308
1309 typedef NV2080_CTRL_PERF_BOOST_PARAMS_v03_00 NV2080_CTRL_PERF_BOOST_PARAMS_v;
1310
1311 typedef struct NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_v03_00
1312 {
1313 NvU32 currPstate;
1314 } NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_v03_00;
1315
1316 typedef NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_v03_00 NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_v;
1317
1318 typedef struct NV2080_CTRL_GPU_INFO_v25_11
1319 {
1320 NvU32 index;
1321 NvU32 data;
1322 } NV2080_CTRL_GPU_INFO_v25_11;
1323
1324 typedef NV2080_CTRL_GPU_INFO_v25_11 NV2080_CTRL_GPU_INFO_v;
1325
1326 typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11
1327 {
1328 NvU32 gpuInfoListSize;
1329 NV2080_CTRL_GPU_INFO_v25_11 gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11];
1330 } NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11;
1331
1332 typedef NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11 NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v;
1333
1334 typedef struct NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00
1335 {
1336 NvU32 exceptType;
1337 NvU32 engineID;
1338 } NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00;
1339
1340 typedef NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00 NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v;
1341
1342 typedef struct NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00
1343 {
1344 NvHandle hTargetChannel;
1345 NvU32 numSMsToClear;
1346 } NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00;
1347
1348 typedef NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00 NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v;
1349
1350 typedef struct NV83DE_SM_ERROR_STATE_REGISTERS_v21_06
1351 {
1352 NvU32 hwwGlobalEsr;
1353 NvU32 hwwWarpEsr;
1354 NvU32 hwwWarpEsrPc;
1355 NvU32 hwwGlobalEsrReportMask;
1356 NvU32 hwwWarpEsrReportMask;
1357 NvU64 hwwEsrAddr NV_ALIGN_BYTES(8);
1358 NvU64 hwwWarpEsrPc64 NV_ALIGN_BYTES(8);
1359 NvU32 hwwCgaEsr;
1360 NvU32 hwwCgaEsrReportMask;
1361 } NV83DE_SM_ERROR_STATE_REGISTERS_v21_06;
1362
1363 typedef NV83DE_SM_ERROR_STATE_REGISTERS_v21_06 NV83DE_SM_ERROR_STATE_REGISTERS_v;
1364
1365 typedef struct NV83DE_MMU_FAULT_INFO_v16_03
1366 {
1367 NvBool valid;
1368 NvU32 faultInfo;
1369 } NV83DE_MMU_FAULT_INFO_v16_03;
1370
1371 typedef NV83DE_MMU_FAULT_INFO_v16_03 NV83DE_MMU_FAULT_INFO_v;
1372
1373 typedef struct NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06
1374 {
1375 NvHandle hTargetChannel;
1376 NvU32 numSMsToRead;
1377 NV83DE_SM_ERROR_STATE_REGISTERS_v21_06 smErrorStateArray[VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06];
1378 NvU32 mmuFaultInfo;
1379 NV83DE_MMU_FAULT_INFO_v16_03 mmuFault;
1380 NvU32 startingSM;
1381 } NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06;
1382
1383 typedef NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06 NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v;
1384
1385 typedef struct NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00
1386 {
1387 NvU32 exceptionMask;
1388 } NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00;
1389
1390 typedef NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00 NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v;
1391
1392 typedef struct NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01
1393 {
1394 NvU32 engineID;
1395 NvU32 subdeviceInstance;
1396 NvU32 resetReason;
1397 } NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01;
1398
1399 typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01 NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v;
1400
1401 typedef struct NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_v03_00
1402 {
1403 NvHandle hObject;
1404 NvU32 classEngineID;
1405 NvU32 classID;
1406 NvU32 engineID;
1407 } NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_v03_00;
1408
1409 typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_v03_00 NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_v;
1410
1411 typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00
1412 {
1413 NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE];
1414 NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE];
1415 NvU32 depth;
1416 NvU32 stencil;
1417 } NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00;
1418
1419 typedef NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v;
1420
1421 typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00
1422 {
1423 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00 value;
1424 NvU32 indexSize;
1425 NvU32 indexUsed;
1426 NvU32 format;
1427 NvU32 valType;
1428 } NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00;
1429
1430 typedef NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v;
1431
1432 typedef struct NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00
1433 {
1434 NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE];
1435 NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE];
1436 NvU32 format;
1437 } NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00;
1438
1439 typedef NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00 NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v;
1440
1441 typedef struct NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00
1442 {
1443 NvU32 depth;
1444 NvU32 format;
1445 } NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00;
1446
1447 typedef NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00 NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v;
1448
1449 typedef struct NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06
1450 {
1451 NvU32 stencil;
1452 NvU32 format;
1453 NvBool bSkipL2Table;
1454 } NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06;
1455
1456 typedef NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06 NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v;
1457
1458 typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07
1459 {
1460 NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE];
1461 NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE];
1462 NvU32 depth;
1463 NvU32 stencil;
1464 } NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07;
1465
1466 typedef NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v;
1467
1468 typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07
1469 {
1470 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07 value;
1471 NvU32 format;
1472 NvU32 index;
1473 NvBool bIndexValid;
1474 NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE tableType;
1475 } NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07;
1476
1477 typedef NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v;
1478
1479 typedef struct NVA06F_CTRL_BIND_PARAMS_v03_00
1480 {
1481 NvU32 engineType;
1482 } NVA06F_CTRL_BIND_PARAMS_v03_00;
1483
1484 typedef NVA06F_CTRL_BIND_PARAMS_v03_00 NVA06F_CTRL_BIND_PARAMS_v;
1485
1486 typedef struct NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00
1487 {
1488 NvBool bEnable;
1489 } NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00;
1490
1491 typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00 NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v;
1492
1493 typedef struct MMU_FMT_LEVEL_v09_02
1494 {
1495 NvU8 virtAddrBitLo;
1496 NvU8 virtAddrBitHi;
1497 NvU8 entrySize ;
1498 NvBool bPageTable;
1499 NvU8 numSubLevels;
1500 } MMU_FMT_LEVEL_v09_02;
1501
1502 typedef MMU_FMT_LEVEL_v09_02 MMU_FMT_LEVEL_v;
1503
1504 typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_levels_v09_02
1505 {
1506 NvU64 physAddress NV_ALIGN_BYTES(8);
1507 NvU32 aperture;
1508 NvU64 size NV_ALIGN_BYTES(8);
1509 MMU_FMT_LEVEL_v09_02 levelFmt;
1510 MMU_FMT_LEVEL_v09_02 sublevelFmt[MMU_FMT_MAX_SUB_LEVELS_v09_02];
1511 } NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_levels_v09_02;
1512
1513 typedef NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_levels_v09_02 NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_levels_v;
1514
1515 typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_v1A_12
1516 {
1517 NvHandle hSubDevice;
1518 NvU32 subDeviceId;
1519 NvU64 virtAddress NV_ALIGN_BYTES(8);
1520 NvU64 pageSize NV_ALIGN_BYTES(8);
1521 NvU32 numLevels;
1522 NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_levels_v09_02 levels[GMMU_FMT_MAX_LEVELS_v1A_12];
1523 } NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_v1A_12;
1524
1525 typedef NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_v1A_12 NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_v;
1526
1527 typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04
1528 {
1529 NvU64 physAddress NV_ALIGN_BYTES(8);
1530 NvU64 size NV_ALIGN_BYTES(8);
1531 NvU32 aperture;
1532 NvU8 pageShift;
1533 } NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04;
1534
1535 typedef NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04 NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v;
1536
1537 typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04
1538 {
1539 NvHandle hSubDevice;
1540 NvU32 subDeviceId;
1541 NvU64 pageSize NV_ALIGN_BYTES(8);
1542 NvU64 virtAddrLo NV_ALIGN_BYTES(8);
1543 NvU64 virtAddrHi NV_ALIGN_BYTES(8);
1544 NvU32 numLevelsToCopy;
1545 NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04 levels[GMMU_FMT_MAX_LEVELS_v1A_12];
1546 } NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04;
1547
1548 typedef NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04 NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v;
1549
1550 typedef struct NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01
1551 {
1552 NvU32 flags;
1553 NvHandle hChannel;
1554 NvU32 gfxpPreemptMode;
1555 NvU32 cilpPreemptMode;
1556 NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo;
1557 } NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01;
1558
1559 typedef NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01 NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v;
1560
1561 typedef struct NVA06C_CTRL_TIMESLICE_PARAMS_v06_00
1562 {
1563 NvU64 timesliceUs NV_ALIGN_BYTES(8);
1564 } NVA06C_CTRL_TIMESLICE_PARAMS_v06_00;
1565
1566 typedef NVA06C_CTRL_TIMESLICE_PARAMS_v06_00 NVA06C_CTRL_TIMESLICE_PARAMS_v;
1567
1568 typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00
1569 {
1570 NvBool bDisable;
1571 NvU32 numChannels;
1572 NvBool bOnlyDisableScheduling;
1573 NvBool bRewindGpPut;
1574 NvP64 pRunlistPreemptEvent NV_ALIGN_BYTES(8);
1575 NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES];
1576 NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES];
1577 } NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00;
1578
1579 typedef NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00 NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v;
1580
1581 typedef struct NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_v06_00
1582 {
1583 NvHandle hSubDevice;
1584 NvU32 subDeviceId;
1585 NvU64 pageSize NV_ALIGN_BYTES(8);
1586 NvU64 virtAddrLo NV_ALIGN_BYTES(8);
1587 NvU64 virtAddrHi NV_ALIGN_BYTES(8);
1588 } NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_v06_00;
1589
1590 typedef NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_v06_00 NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_v;
1591
1592 typedef struct NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_v06_00
1593 {
1594 NvHandle hSubDevice;
1595 NvU32 subDeviceId;
1596 NvU64 pageSize NV_ALIGN_BYTES(8);
1597 NvU64 virtAddrLo NV_ALIGN_BYTES(8);
1598 NvU64 virtAddrHi NV_ALIGN_BYTES(8);
1599 } NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_v06_00;
1600
1601 typedef NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_v06_00 NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_v;
1602
1603 typedef struct NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01
1604 {
1605 NvU32 hResolution;
1606 NvU32 vResolution;
1607 NvU32 averageEncodeLatency;
1608 NvU32 averageEncodeFps;
1609 NvU32 timestampBufferSize;
1610 NvP64 timestampBuffer NV_ALIGN_BYTES(8);
1611 } NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01;
1612
1613 typedef NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01 NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v;
1614
1615 typedef struct NVA0BD_CTRL_NVFBC_TIMESTAMP_v12_04
1616 {
1617 NvU64 startTime NV_ALIGN_BYTES(8);
1618 NvU64 endTime NV_ALIGN_BYTES(8);
1619 } NVA0BD_CTRL_NVFBC_TIMESTAMP_v12_04;
1620
1621 typedef NVA0BD_CTRL_NVFBC_TIMESTAMP_v12_04 NVA0BD_CTRL_NVFBC_TIMESTAMP_v;
1622
1623 typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02
1624 {
1625 NvU64 fbUsed NV_ALIGN_BYTES(8);
1626 } NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02;
1627
1628 typedef NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02 NVA080_CTRL_SET_FB_USAGE_PARAMS_v;
1629
1630 typedef struct NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00
1631 {
1632 NvU32 workSubmitToken;
1633 } NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00;
1634
1635 typedef NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00 NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v;
1636
1637 typedef struct NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK_v09_00
1638 {
1639 NvU32 pageSize;
1640 NvU64 pteEntrySize NV_ALIGN_BYTES(8);
1641 NvU32 comptagLine;
1642 NvU32 kind;
1643 NvU32 pteFlags;
1644 } NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK_v09_00;
1645
1646 typedef NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK_v09_00 NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK_v;
1647
1648 typedef struct NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_v09_00
1649 {
1650 NvU64 gpuAddr NV_ALIGN_BYTES(8);
1651 NvU32 subDeviceId;
1652 NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK_v09_00 pteBlocks[NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS];
1653 NvHandle hVASpace;
1654 } NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_v09_00;
1655
1656 typedef NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_v09_00 NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_v;
1657
1658 typedef struct NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_v09_00
1659 {
1660 NvU64 gpuAddr NV_ALIGN_BYTES(8);
1661 NvU32 subDeviceId;
1662 NvU8 skipVASpaceInit;
1663 NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK_v09_00 pteBlocks[NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS];
1664 NvHandle hVASpace;
1665 } NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_v09_00;
1666
1667 typedef NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_v09_00 NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_v;
1668
1669 typedef struct NV0080_CTRL_DMA_GET_CAPS_PARAMS_v09_00
1670 {
1671 NvU32 capsTblSize;
1672 NvU8 capsTbl[NV0080_CTRL_DMA_CAPS_TBL_SIZE];
1673 } NV0080_CTRL_DMA_GET_CAPS_PARAMS_v09_00;
1674
1675 typedef NV0080_CTRL_DMA_GET_CAPS_PARAMS_v09_00 NV0080_CTRL_DMA_GET_CAPS_PARAMS_v;
1676
1677 typedef struct NV0080_CTRL_DMA_FLUSH_PARAMS_v09_00
1678 {
1679 NvU32 targetUnit;
1680 } NV0080_CTRL_DMA_FLUSH_PARAMS_v09_00;
1681
1682 typedef NV0080_CTRL_DMA_FLUSH_PARAMS_v09_00 NV0080_CTRL_DMA_FLUSH_PARAMS_v;
1683
1684 typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT_v09_00
1685 {
1686 NvU32 pageTableSize;
1687 NvU32 pageTableCoverage;
1688 } NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT_v09_00;
1689
1690 typedef NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT_v09_00 NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT_v;
1691
1692 typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_v13_02
1693 {
1694 NvU32 vaBitCount;
1695 NvU32 pdeCoverageBitCount;
1696 NvU32 num4KPageTableFormats;
1697 NvU32 bigPageSize;
1698 NvU32 compressionPageSize;
1699 NvU32 dualPageTableSupported;
1700 NvU32 idealVRAMPageSize;
1701 NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT_v09_00 pageTableBigFormat;
1702 NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT_v09_00 pageTable4KFormat[NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS];
1703 NvHandle hVASpace;
1704 NvU64 vaRangeLo NV_ALIGN_BYTES(8);
1705 NvU32 vaSpaceId;
1706 NvU64 supportedPageSizeMask NV_ALIGN_BYTES(8);
1707 } NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_v13_02;
1708
1709 typedef NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_v13_02 NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_v;
1710
1711 typedef struct NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_v09_03
1712 {
1713 NvU64 bar2Addr[NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES] NV_ALIGN_BYTES(8);
1714 } NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_v09_03;
1715
1716 typedef NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_v09_03 NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_v;
1717
1718 typedef struct NV2080_CTRL_FIFO_MEM_INFO_v09_01
1719 {
1720 NvU32 aperture;
1721 NvU64 base NV_ALIGN_BYTES(8);
1722 NvU64 size NV_ALIGN_BYTES(8);
1723 } NV2080_CTRL_FIFO_MEM_INFO_v09_01;
1724
1725 typedef NV2080_CTRL_FIFO_MEM_INFO_v09_01 NV2080_CTRL_FIFO_MEM_INFO_v;
1726
1727 typedef struct NV2080_CTRL_FIFO_CHANNEL_MEM_INFO_v09_01
1728 {
1729 NV2080_CTRL_FIFO_MEM_INFO_v09_01 inst;
1730 NV2080_CTRL_FIFO_MEM_INFO_v09_01 ramfc;
1731 } NV2080_CTRL_FIFO_CHANNEL_MEM_INFO_v09_01;
1732
1733 typedef NV2080_CTRL_FIFO_CHANNEL_MEM_INFO_v09_01 NV2080_CTRL_FIFO_CHANNEL_MEM_INFO_v;
1734
1735 typedef struct NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_v09_01
1736 {
1737 NvHandle hChannel;
1738 NV2080_CTRL_FIFO_CHANNEL_MEM_INFO_v09_01 chMemInfo;
1739 } NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_v09_01;
1740
1741 typedef NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_v09_01 NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_v;
1742
1743 typedef struct NVA06C_CTRL_PREEMPT_PARAMS_v09_0A
1744 {
1745 NvBool bWait;
1746 NvBool bManualTimeout;
1747 NvU32 timeoutUs;
1748 } NVA06C_CTRL_PREEMPT_PARAMS_v09_0A;
1749
1750 typedef NVA06C_CTRL_PREEMPT_PARAMS_v09_0A NVA06C_CTRL_PREEMPT_PARAMS_v;
1751
1752 typedef struct NV0080_CTRL_BSP_GET_CAPS_PARAMS_v09_10
1753 {
1754 NvU32 capsTblSize;
1755 NvU32 instanceId;
1756 NvU8 capsTblData[NV0080_CTRL_BSP_CAPS_TBL_SIZE_V09_10];
1757 } NV0080_CTRL_BSP_GET_CAPS_PARAMS_v09_10;
1758
1759 typedef NV0080_CTRL_BSP_GET_CAPS_PARAMS_v09_10 NV0080_CTRL_BSP_GET_CAPS_PARAMS_v;
1760
1761 typedef struct VGPU_BSP_GET_CAPS_v25_00
1762 {
1763 NV0080_CTRL_BSP_GET_CAPS_PARAMS_v09_10 bspCaps[MAX_NVDEC_ENGINES_V25_00];
1764 } VGPU_BSP_GET_CAPS_v25_00;
1765
1766 typedef VGPU_BSP_GET_CAPS_v25_00 VGPU_BSP_GET_CAPS_v;
1767
1768 typedef struct NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_v09_03
1769 {
1770 NvU32 engineID;
1771 } NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_v09_03;
1772
1773 typedef NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_v09_03 NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_v;
1774
1775 typedef struct NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_v09_03
1776 {
1777 NvU32 engineID;
1778 } NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_v09_03;
1779
1780 typedef NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_v09_03 NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_v;
1781
1782 typedef struct NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_v09_03
1783 {
1784 NvU64 virtualAddress NV_ALIGN_BYTES(8);
1785 NvU64 beginAddress NV_ALIGN_BYTES(8);
1786 NvU64 endAddress NV_ALIGN_BYTES(8);
1787 NvU64 alignedAddress NV_ALIGN_BYTES(8);
1788 NvU32 pageSize;
1789 NvHandle hVASpace;
1790 } NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_v09_03;
1791
1792 typedef NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_v09_03 NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_v;
1793
1794 typedef struct NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_v10_01
1795 {
1796 NvHandle hSubDevice;
1797 NvU32 lineMin;
1798 NvU32 lineMax;
1799 NvU32 format;
1800 } NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_v10_01;
1801
1802 typedef NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_v10_01 NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_v;
1803
1804 typedef struct NV2080_CTRL_FIFO_DEVICE_ENTRY_v19_01
1805 {
1806 NvU32 engineData[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES];
1807 NvU32 pbdmaIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];
1808 NvU32 pbdmaFaultIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];
1809 NvU32 numPbdmas;
1810 char engineName[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN];
1811 } NV2080_CTRL_FIFO_DEVICE_ENTRY_v19_01;
1812
1813 typedef NV2080_CTRL_FIFO_DEVICE_ENTRY_v19_01 NV2080_CTRL_FIFO_DEVICE_ENTRY_v;
1814
1815 typedef struct NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_v19_01
1816 {
1817 NvU32 baseIndex;
1818 NV2080_CTRL_FIFO_DEVICE_ENTRY_v19_01 entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES];
1819 NvU32 numEntries;
1820 NvBool bMore;
1821 } NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_v19_01;
1822
1823 typedef NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_v19_01 NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_v;
1824
1825 typedef struct VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07
1826 {
1827 NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_v19_01 fifoDeviceInfoTable[MAX_ITERATIONS_DEVICE_INFO_TABLE];
1828 } VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07;
1829
1830 typedef VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07 VGPU_FIFO_GET_DEVICE_INFO_TABLE_v;
1831
1832 typedef struct NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06
1833 {
1834 NvU32 waitForEvent;
1835 NvHandle hResidentChannel;
1836 } NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06;
1837
1838 typedef NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06 NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v;
1839
1840 typedef struct NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06
1841 {
1842 NvBool bNonTransactional;
1843 NvU32 regOpCount;
1844 NV2080_CTRL_GPU_REG_OP_v03_00 regOps[NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS];
1845 } NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06;
1846
1847 typedef NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06 NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v;
1848
1849 typedef struct NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07
1850 {
1851 NvHandle hClientTarget;
1852 NvHandle hChannelTarget;
1853 NvU32 bNonTransactional;
1854 NvU32 regOpCount;
1855 NvU32 smIds[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07];
1856 NV2080_CTRL_GPU_REG_OP_v03_00 regOps[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07];
1857 NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo;
1858 } NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07;
1859
1860 typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07 NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v;
1861
1862 typedef struct NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06
1863 {
1864 NvU32 action;
1865 } NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06;
1866
1867 typedef NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06 NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v;
1868
1869 typedef struct NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06
1870 {
1871 NvHandle hTargetChannel;
1872 NvU32 smID;
1873 NV83DE_SM_ERROR_STATE_REGISTERS_v21_06 smErrorState;
1874 } NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06;
1875
1876 typedef NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06 NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v;
1877
1878 typedef struct NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06
1879 {
1880 NvHandle hTargetChannel;
1881 NvU32 smID;
1882 } NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06;
1883
1884 typedef NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06 NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v;
1885
1886 typedef struct NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06
1887 {
1888 NvU32 action;
1889 } NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06;
1890
1891 typedef NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06 NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v;
1892
1893 typedef struct NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06
1894 {
1895 NvU32 stopTriggerType;
1896 } NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06;
1897
1898 typedef NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06 NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v;
1899
1900 typedef struct ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY_v16_00
1901 {
1902 NvU32 nv2080EngineType;
1903 NvU32 notificationIntrVector;
1904 } ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY_v16_00;
1905
1906 typedef ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY_v16_00 ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY_v;
1907
1908 typedef struct NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00
1909 {
1910 NvU32 numEntries;
1911 ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY_v16_00 entries[NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES];
1912 } NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00;
1913
1914 typedef NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00 NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v;
1915
1916 typedef struct STATIC_INTR_ENTRY_v1E_09
1917 {
1918 NvU32 nv2080IntrType;
1919 NvU32 pmcIntrMask;
1920 NvU32 intrVectorStall;
1921 NvU32 intrVectorNonStall;
1922 } STATIC_INTR_ENTRY_v1E_09;
1923
1924 typedef STATIC_INTR_ENTRY_v1E_09 STATIC_INTR_ENTRY_v;
1925
1926 typedef struct NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09
1927 {
1928 NvU32 numEntries;
1929 STATIC_INTR_ENTRY_v1E_09 entries[NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX_v1E_09];
1930 } NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09;
1931
1932 typedef NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09 NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v;
1933
1934 typedef struct NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04
1935 {
1936 NvU64 imbPhysAddr NV_ALIGN_BYTES(8);
1937 NvU32 addrSpace;
1938 NvU32 flaAction;
1939 } NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04;
1940
1941 typedef NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04 NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v;
1942
1943 typedef struct NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_v18_08
1944 {
1945 NvU32 engineType;
1946 NvU32 vChid;
1947 NvU32 faultType;
1948 } NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_v18_08;
1949
1950 typedef NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_v18_08 NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_v;
1951
1952 typedef struct NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01
1953 {
1954 NvU64 count NV_ALIGN_BYTES(8);
1955 } NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01;
1956
1957 typedef NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01 NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v;
1958
1959 typedef struct NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01
1960 {
1961 NvBool enabled;
1962 NvBool scrubComplete;
1963 NvBool supported;
1964 NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01 dbe;
1965 NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01 dbeNonResettable;
1966 NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01 sbe;
1967 NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01 sbeNonResettable;
1968 } NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01;
1969
1970 typedef NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v;
1971
1972 typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06
1973 {
1974 NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 units[NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06];
1975 NvBool bFatalPoisonError;
1976 NvU32 flags;
1977 } NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06;
1978
1979 typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v26_02
1980 {
1981 NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 units[NV2080_CTRL_GPU_ECC_UNIT_COUNT_v26_02];
1982 NvBool bFatalPoisonError;
1983 NvU32 flags;
1984 } NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v26_02;
1985
1986 typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v27_04
1987 {
1988 NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 units[NV2080_CTRL_GPU_ECC_UNIT_COUNT_v27_04];
1989 NvBool bFatalPoisonError;
1990 NvU32 flags;
1991 } NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v27_04;
1992
1993 typedef NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v27_04 NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v;
1994
1995 typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06
1996 {
1997 NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 units[NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06];
1998 NvBool bFatalPoisonError;
1999 NvU32 flags;
2000 } NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06;
2001
2002 typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v26_02
2003 {
2004 NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 units[NV2080_CTRL_GPU_ECC_UNIT_COUNT_v26_02];
2005 NvBool bFatalPoisonError;
2006 NvU32 flags;
2007 } NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v26_02;
2008
2009 typedef NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v26_02 NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v;
2010
2011 typedef struct NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01
2012 {
2013 NvU32 engines;
2014 } NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01;
2015
2016 typedef NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01 NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v;
2017
2018 typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02
2019 {
2020 NvU32 capsTbl;
2021 NvU8 lowestNvlinkVersion;
2022 NvU8 highestNvlinkVersion;
2023 NvU8 lowestNciVersion;
2024 NvU8 highestNciVersion;
2025 NvU32 discoveredLinkMask;
2026 NvU32 enabledLinkMask;
2027 } NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02;
2028
2029 typedef NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v;
2030
2031 typedef struct NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02
2032 {
2033 NvU32 deviceIdFlags;
2034 NvU32 domain;
2035 NvU16 bus;
2036 NvU16 device;
2037 NvU16 function;
2038 NvU32 pciDeviceId;
2039 NvU64 deviceType NV_ALIGN_BYTES(8);
2040 NvU8 deviceUUID[16];
2041 } NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02;
2042
2043 typedef NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02 NV2080_CTRL_NVLINK_DEVICE_INFO_v;
2044
2045 typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D
2046 {
2047 NvU32 capsTbl;
2048 NvU8 phyType;
2049 NvU8 subLinkWidth;
2050 NvU32 linkState;
2051 NvU8 rxSublinkStatus;
2052 NvU8 txSublinkStatus;
2053 NvU8 nvlinkVersion;
2054 NvU8 nciVersion;
2055 NvU8 phyVersion;
2056 NvU32 nvlinkLinkClockKHz;
2057 NvU32 nvlinkLineRateMbps;
2058 NvBool connected;
2059 NvU8 remoteDeviceLinkNumber;
2060 NvU8 localDeviceLinkNumber;
2061 NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02 remoteDeviceInfo;
2062 NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02 localDeviceInfo;
2063 } NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D;
2064
2065 typedef NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v;
2066
2067 typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04
2068 {
2069 NvU32 enabledLinkMask;
2070 NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS_v23_04];
2071 } NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04;
2072
2073 typedef NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v;
2074
2075 typedef struct NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18
2076 {
2077 NvU64 base NV_ALIGN_BYTES(8);
2078 NvU64 size NV_ALIGN_BYTES(8);
2079 } NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18;
2080
2081 typedef NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18 NV2080_CTRL_FLA_GET_RANGE_PARAMS_v;
2082
2083 typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_v15_02
2084 {
2085 NvU32 ceEngineType;
2086 NvU8 capsTbl[NV2080_CTRL_CE_CAPS_TBL_SIZE];
2087 } NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_v15_02;
2088
2089 typedef NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_v15_02 NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_v;
2090
2091 typedef struct VGPU_CE_GET_CAPS_V2_v24_09
2092 {
2093 NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_v15_02 ceCaps[NV2080_ENGINE_TYPE_COPY_SIZE_v24_09];
2094 } VGPU_CE_GET_CAPS_V2_v24_09;
2095
2096 typedef VGPU_CE_GET_CAPS_V2_v24_09 VGPU_CE_GET_CAPS_V2_v;
2097
2098 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D
2099 {
2100 NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
2101 NvU32 gpuCount;
2102 NvU32 p2pCaps;
2103 NvU32 p2pOptimalReadCEs;
2104 NvU32 p2pOptimalWriteCEs;
2105 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D];
2106 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D;
2107
2108 typedef NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v;
2109
2110 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_v1F_0D
2111 {
2112 NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
2113 NvU32 gpuCount;
2114 NvU32 p2pCaps;
2115 NvU32 p2pOptimalReadCEs;
2116 NvU32 p2pOptimalWriteCEs;
2117 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D];
2118 NvU32 busPeerIds[VGPU_RPC_GET_P2P_CAPS_V2_MAX_GPUS_SQUARED_PER_RPC];
2119 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_v1F_0D;
2120
2121 typedef NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_v1F_0D NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_v;
2122
2123 typedef struct NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03
2124 {
2125 NvU8 fbpIndex;
2126 NvU32 ltcMask;
2127 NvU32 ltcCount;
2128 } NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03;
2129
2130 typedef NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03 NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v;
2131
2132 typedef struct NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO_v15_04
2133 {
2134 NvU64 pageAddress NV_ALIGN_BYTES(8);
2135 NvU32 source;
2136 NvU32 status;
2137 NvU32 timestamp;
2138 } NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO_v15_04;
2139
2140 typedef NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO_v15_04 NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO_v;
2141
2142 typedef struct NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v15_04
2143 {
2144 NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO_v15_04 blackList[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES];
2145 NvU32 pageSize;
2146 NvU32 validEntries;
2147 NvBool bRetirementPending;
2148 NvU8 retirementPending;
2149 } NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v15_04;
2150
2151 typedef NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v15_04 NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v;
2152
2153 typedef struct NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_v16_01
2154 {
2155 NvU32 statuses;
2156 NvU8 flags;
2157 } NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_v16_01;
2158
2159 typedef NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_v16_01 NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_v;
2160
2161 typedef struct NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04
2162 {
2163 NvU32 index;
2164 } NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04;
2165
2166 typedef NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04 NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v;
2167
2168 typedef struct NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02
2169 {
2170 NvU32 tsgInterleaveLevel;
2171 } NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02;
2172
2173 typedef NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v;
2174
2175 typedef struct NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02
2176 {
2177 NvU32 channelInterleaveLevel;
2178 } NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02;
2179
2180 typedef NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v;
2181
2182 typedef struct NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05
2183 {
2184 NvU32 gpcCount;
2185 NvU32 gfxGpcCount;
2186 NvU32 veidCount;
2187 NvU32 ceCount;
2188 NvU32 nvEncCount;
2189 NvU32 nvDecCount;
2190 NvU32 nvJpgCount;
2191 NvU32 ofaCount;
2192 NvU32 sharedEngFlag;
2193 NvU32 smCount;
2194 NvU32 spanStart;
2195 NvU32 computeSize;
2196 } NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05;
2197
2198 typedef NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05 NVC637_CTRL_EXEC_PARTITIONS_INFO_v;
2199
2200 typedef struct NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05
2201 {
2202 NvBool bQuery;
2203 NvU32 execPartCount;
2204 NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05 execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05];
2205 NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05];
2206 } NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05;
2207
2208 typedef NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05 NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v;
2209
2210 typedef struct NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05
2211 {
2212 NvU32 execPartCount;
2213 NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05];
2214 } NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05;
2215
2216 typedef NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05 NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v;
2217
2218 typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05
2219 {
2220 NvU32 execPartCount;
2221 NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05];
2222 NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05 execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05];
2223 } NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05;
2224
2225 typedef NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05 NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v;
2226
2227 typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07
2228 {
2229 NvU32 indexStart;
2230 NvU32 indexEnd;
2231 } NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07;
2232
2233 typedef NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v;
2234
2235 typedef struct VGPU_STATIC_DATA_v25_0E
2236 {
2237 NvU64 fbTaxLength NV_ALIGN_BYTES(8);
2238 NvU64 fbLength NV_ALIGN_BYTES(8);
2239 NvU32 fbBusWidth;
2240 NvU32 fbioMask;
2241 NvU32 fbpMask;
2242 NvU32 ltcMask;
2243 NvU32 ltsCount;
2244 NvU32 subProcessIsolation;
2245 NvU64 engineList NV_ALIGN_BYTES(8);
2246 NvU32 sizeL2Cache;
2247 NvBool poisonFuseEnabled;
2248 NvBool guestManagedHwAlloc;
2249 NV_DEVICE_NAME_v13_06 gpuName;
2250 NvBool bSplitVasBetweenServerClientRm;
2251 NvU64 maxSupportedPageSize NV_ALIGN_BYTES(8);
2252 NvBool bFlaSupported;
2253 NvBool bPerRunlistChannelRamEnabled;
2254 NvBool bAtsSupported;
2255 NvBool bPerSubCtxheaderSupported;
2256 NvBool bC2CLinkUp;
2257 NvBool bLocalEgmEnabled;
2258 NvU32 localEgmPeerId;
2259 NvBool bSelfHostedMode;
2260 NvU32 ceFaultMethodBufferDepth;
2261 NvU32 pcieGpuLinkCaps;
2262 NvU8 grCapsBits[NV0080_CTRL_GR_CAPS_TBL_SIZE_v25_0E];
2263 NvU32 gfxpBufferSize[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E];
2264 NvU32 gfxpBufferAlignment[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E];
2265 NvU32 grBufferSize[RPC_GR_BUFFER_TYPE_GRAPHICS_MAX_v25_0E];
2266 NvU8 jpegCaps[NV0080_CTRL_NVJPG_CAPS_TBL_SIZE_V18_0C];
2267 } VGPU_STATIC_DATA_v25_0E;
2268
2269 typedef struct VGPU_STATIC_DATA_v27_00
2270 {
2271 NvU64 fbTaxLength NV_ALIGN_BYTES(8);
2272 NvU64 fbLength NV_ALIGN_BYTES(8);
2273 NvU32 fbBusWidth;
2274 NvU64 fbioMask NV_ALIGN_BYTES(8);
2275 NvU32 fbpMask;
2276 NvU64 ltcMask NV_ALIGN_BYTES(8);
2277 NvU32 ltsCount;
2278 NvU32 subProcessIsolation;
2279 NvU64 engineList NV_ALIGN_BYTES(8);
2280 NvU32 sizeL2Cache;
2281 NvBool poisonFuseEnabled;
2282 NvBool guestManagedHwAlloc;
2283 NV_DEVICE_NAME_v13_06 gpuName;
2284 NvBool bSplitVasBetweenServerClientRm;
2285 NvU64 maxSupportedPageSize NV_ALIGN_BYTES(8);
2286 NvBool bFlaSupported;
2287 NvBool bPerRunlistChannelRamEnabled;
2288 NvBool bAtsSupported;
2289 NvBool bPerSubCtxheaderSupported;
2290 NvBool bC2CLinkUp;
2291 NvBool bLocalEgmEnabled;
2292 NvU32 localEgmPeerId;
2293 NvBool bSelfHostedMode;
2294 NvU32 ceFaultMethodBufferDepth;
2295 NvU32 pcieGpuLinkCaps;
2296 NvU8 grCapsBits[NV0080_CTRL_GR_CAPS_TBL_SIZE_v25_0E];
2297 NvU32 gfxpBufferSize[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E];
2298 NvU32 gfxpBufferAlignment[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E];
2299 NvU32 grBufferSize[RPC_GR_BUFFER_TYPE_GRAPHICS_MAX_v25_0E];
2300 NvU8 jpegCaps[NV0080_CTRL_NVJPG_CAPS_TBL_SIZE_V18_0C];
2301 } VGPU_STATIC_DATA_v27_00;
2302
2303 typedef struct VGPU_STATIC_DATA_v27_01
2304 {
2305 NvU64 fbTaxLength NV_ALIGN_BYTES(8);
2306 NvU64 fbLength NV_ALIGN_BYTES(8);
2307 NvU32 fbBusWidth;
2308 NvU64 fbioMask NV_ALIGN_BYTES(8);
2309 NvU32 fbpMask;
2310 NvU64 ltcMask NV_ALIGN_BYTES(8);
2311 NvU32 ltsCount;
2312 NvU32 subProcessIsolation;
2313 NvU64 engineList[NVGPU_VGPU_ENGINE_LIST_MASK_ARRAY_MAX_v27_01] NV_ALIGN_BYTES(8);
2314 NvU32 sizeL2Cache;
2315 NvBool poisonFuseEnabled;
2316 NvBool guestManagedHwAlloc;
2317 NV_DEVICE_NAME_v13_06 gpuName;
2318 NvBool bSplitVasBetweenServerClientRm;
2319 NvU64 maxSupportedPageSize NV_ALIGN_BYTES(8);
2320 NvBool bFlaSupported;
2321 NvBool bPerRunlistChannelRamEnabled;
2322 NvBool bAtsSupported;
2323 NvBool bPerSubCtxheaderSupported;
2324 NvBool bC2CLinkUp;
2325 NvBool bLocalEgmEnabled;
2326 NvU32 localEgmPeerId;
2327 NvBool bSelfHostedMode;
2328 NvU32 ceFaultMethodBufferDepth;
2329 NvU32 pcieGpuLinkCaps;
2330 NvU8 grCapsBits[NV0080_CTRL_GR_CAPS_TBL_SIZE_v25_0E];
2331 NvU32 gfxpBufferSize[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E];
2332 NvU32 gfxpBufferAlignment[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E];
2333 NvU32 grBufferSize[RPC_GR_BUFFER_TYPE_GRAPHICS_MAX_v25_0E];
2334 NvU8 jpegCaps[NV0080_CTRL_NVJPG_CAPS_TBL_SIZE_V18_0C];
2335 } VGPU_STATIC_DATA_v27_01;
2336
2337 typedef VGPU_STATIC_DATA_v27_01 VGPU_STATIC_DATA_v;
2338
2339 typedef struct NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09
2340 {
2341 NvU32 faultType;
2342 } NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09;
2343
2344 typedef NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09 NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v;
2345
2346 typedef struct rpc_fb_region_descriptor_v17_00
2347 {
2348 NvU64 base NV_ALIGN_BYTES(8);
2349 NvU64 limit NV_ALIGN_BYTES(8);
2350 NvBool bRsvdRegion;
2351 } rpc_fb_region_descriptor_v17_00;
2352
2353 typedef rpc_fb_region_descriptor_v17_00 rpc_fb_region_descriptor_v;
2354
2355 typedef struct NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A
2356 {
2357 NvU32 array[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
2358 } NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A;
2359
2360 typedef NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v;
2361
2362 typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A
2363 {
2364 NvU32 grpACount;
2365 NvU32 grpBCount;
2366 NvU32 gpuIdGrpA[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
2367 NvU32 gpuIdGrpB[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
2368 NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A p2pCaps[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
2369 NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A a2bOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
2370 NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A a2bOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
2371 NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A b2aOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
2372 NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A b2aOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
2373 } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A;
2374
2375 typedef NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v;
2376
2377 typedef struct NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B
2378 {
2379 NvU32 eccMask;
2380 NvU32 nvlinkMask ;
2381 } NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B;
2382
2383 typedef struct NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13
2384 {
2385 NvU32 eccMask;
2386 NvU32 nvlinkMask ;
2387 } NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13;
2388
2389 typedef NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13 NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v;
2390
2391 typedef struct NV2080_CTRL_FLA_RANGE_PARAMS_v18_11
2392 {
2393 NvU64 base NV_ALIGN_BYTES(8);
2394 NvU64 size NV_ALIGN_BYTES(8);
2395 NvU32 mode;
2396 NvU32 hVASpace;
2397 } NV2080_CTRL_FLA_RANGE_PARAMS_v18_11;
2398
2399 typedef NV2080_CTRL_FLA_RANGE_PARAMS_v18_11 NV2080_CTRL_FLA_RANGE_PARAMS_v;
2400
2401 typedef struct NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO_v18_14
2402 {
2403 NvU64 pageNumber NV_ALIGN_BYTES(8);
2404 NvU8 source;
2405 } NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO_v18_14;
2406
2407 typedef NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO_v18_14 NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO_v;
2408
2409 typedef struct NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_v18_14
2410 {
2411 NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO_v18_14 blackList[NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES];
2412 NvU32 validEntries;
2413 NvU32 baseIndex;
2414 NvBool bMore;
2415 } NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_v18_14;
2416
2417 typedef NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_v18_14 NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_v;
2418
2419 typedef struct NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_v18_15
2420 {
2421 NvHandle hVASpace;
2422 NvU64 vaSpaceToken NV_ALIGN_BYTES(8);
2423 } NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_v18_15;
2424
2425 typedef NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_v18_15 NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_v;
2426
2427 typedef struct NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_v18_15
2428 {
2429 NvHandle hVASpace;
2430 } NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_v18_15;
2431
2432 typedef NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_v18_15 NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_v;
2433
2434 typedef struct NV503C_CTRL_REGISTER_VIDMEM_PARAMS_v18_15
2435 {
2436 NvHandle hMemory;
2437 NvU64 address NV_ALIGN_BYTES(8);
2438 NvU64 size NV_ALIGN_BYTES(8);
2439 NvU64 offset NV_ALIGN_BYTES(8);
2440 } NV503C_CTRL_REGISTER_VIDMEM_PARAMS_v18_15;
2441
2442 typedef NV503C_CTRL_REGISTER_VIDMEM_PARAMS_v18_15 NV503C_CTRL_REGISTER_VIDMEM_PARAMS_v;
2443
2444 typedef struct NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_v18_15
2445 {
2446 NvHandle hMemory;
2447 } NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_v18_15;
2448
2449 typedef NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_v18_15 NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_v;
2450
2451 typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07
2452 {
2453 NvU32 ceEngineType;
2454 NvU32 pceMask;
2455 } NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07;
2456
2457 typedef NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07 NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v;
2458
2459 typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_v1A_07
2460 {
2461 NvHandle hChannel;
2462 NvU64 totalBufferSize NV_ALIGN_BYTES(8);
2463 } NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_v1A_07;
2464
2465 typedef NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_v1A_07 NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_v;
2466
2467 typedef struct NV2080_CTRL_GR_CTX_BUFFER_INFO_v1A_1A
2468 {
2469 NvU64 alignment NV_ALIGN_BYTES(8);
2470 NvU64 size NV_ALIGN_BYTES(8);
2471 NvP64 bufferHandle NV_ALIGN_BYTES(8);
2472 NvU64 pageCount NV_ALIGN_BYTES(8);
2473 NvU64 physAddr NV_ALIGN_BYTES(8);
2474 NvU32 bufferType;
2475 NvU32 aperture;
2476 NvU32 kind;
2477 NvU32 pageSize;
2478 NvBool bIsContigous;
2479 NvBool bGlobalBuffer;
2480 NvBool bLocalBuffer;
2481 NvBool bDeviceDescendant;
2482 NvU8 uuid[16];
2483 } NV2080_CTRL_GR_CTX_BUFFER_INFO_v1A_1A;
2484
2485 typedef NV2080_CTRL_GR_CTX_BUFFER_INFO_v1A_1A NV2080_CTRL_GR_CTX_BUFFER_INFO_v;
2486
2487 typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_v1A_1A
2488 {
2489 NvHandle hUserClient;
2490 NvHandle hChannel;
2491 NvU32 bufferCount;
2492 NV2080_CTRL_GR_CTX_BUFFER_INFO_v1A_1A ctxBufferInfo[GR_MAX_RPC_CTX_BUFFER_COUNT];
2493 } NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_v1A_1A;
2494
2495 typedef NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_v1A_1A NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_v;
2496
2497 typedef struct VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07
2498 {
2499 NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_v18_14 fbDynamicBlacklistedPages[MAX_ITERATIONS_DYNAMIC_BLACKLIST];
2500 } VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07;
2501
2502 typedef VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07 VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v;
2503
2504 typedef struct VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D
2505 {
2506 NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03 fbLtcInfoForFbp[MAX_FBPS];
2507 } VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D;
2508
2509 typedef VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D VGPU_FB_GET_LTC_INFO_FOR_FBP_v;
2510
2511 typedef struct NV2080_CTRL_BUS_INFO_v1A_0F
2512 {
2513 NvU32 index;
2514 NvU32 data;
2515 } NV2080_CTRL_BUS_INFO_v1A_0F;
2516
2517 typedef NV2080_CTRL_BUS_INFO_v1A_0F NV2080_CTRL_BUS_INFO_v;
2518
2519 typedef struct NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09
2520 {
2521 NvU32 busInfoListSize;
2522 NV2080_CTRL_BUS_INFO_v1A_0F busInfoList[NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1C_09];
2523 } NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09;
2524
2525 typedef NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09 NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v;
2526
2527 typedef struct NV2080_CTRL_INTERNAL_GR_INFO_v1B_04
2528 {
2529 NvU32 index;
2530 NvU32 data;
2531 } NV2080_CTRL_INTERNAL_GR_INFO_v1B_04;
2532
2533 typedef NV2080_CTRL_INTERNAL_GR_INFO_v1B_04 NV2080_CTRL_INTERNAL_GR_INFO_v;
2534
2535 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO_v24_07
2536 {
2537 NV2080_CTRL_INTERNAL_GR_INFO_v1B_04 infoList[NV0080_CTRL_GR_INFO_MAX_SIZE_24_07];
2538 } NV2080_CTRL_INTERNAL_STATIC_GR_INFO_v24_07;
2539
2540 typedef NV2080_CTRL_INTERNAL_STATIC_GR_INFO_v24_07 NV2080_CTRL_INTERNAL_STATIC_GR_INFO_v;
2541
2542 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07
2543 {
2544 NV2080_CTRL_INTERNAL_STATIC_GR_INFO_v24_07 engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04];
2545 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07;
2546
2547 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07 NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v;
2548
2549 typedef struct GLOBAL_SM_ID_v1F_01
2550 {
2551 NvU16 gpcId;
2552 NvU16 localTpcId;
2553 NvU16 localSmId;
2554 NvU16 globalTpcId;
2555 NvU16 virtualGpcId;
2556 NvU16 migratableTpcId;
2557 } GLOBAL_SM_ID_v1F_01;
2558
2559 typedef GLOBAL_SM_ID_v1F_01 GLOBAL_SM_ID_v;
2560
2561 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_v1F_01
2562 {
2563 GLOBAL_SM_ID_v1F_01 globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03];
2564 NvU16 numSm;
2565 NvU16 numTpc;
2566 } NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_v1F_01;
2567
2568 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_v1F_01 NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_v;
2569
2570 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01
2571 {
2572 NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_v1F_01 globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04];
2573 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01;
2574
2575 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01 NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v;
2576
2577 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO_v1B_05
2578 {
2579 NvU32 ropUnitCount;
2580 NvU32 ropOperationsFactor;
2581 NvU32 ropOperationsCount;
2582 } NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO_v1B_05;
2583
2584 typedef NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO_v;
2585
2586 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05
2587 {
2588 NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO_v1B_05 engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04];
2589 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05;
2590
2591 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v;
2592
2593 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS_v1C_06
2594 {
2595 NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03];
2596 } NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS_v1C_06;
2597
2598 typedef NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS_v1C_06 NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS_v;
2599
2600 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06
2601 {
2602 NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS_v1C_06 enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04];
2603 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06;
2604
2605 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06 NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v;
2606
2607 typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO_v1B_05
2608 {
2609 NvU32 size;
2610 NvU32 alignment;
2611 } NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO_v1B_05;
2612
2613 typedef NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO_v1B_05 NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO_v;
2614
2615 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO_v25_07
2616 {
2617 NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO_v1B_05 engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT_v25_07];
2618 } NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO_v25_07;
2619
2620 typedef NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO_v25_07 NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO_v;
2621
2622 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07
2623 {
2624 NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO_v25_07 engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04];
2625 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07;
2626
2627 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07 NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v;
2628
2629 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_v1B_05
2630 {
2631 NvU8 imla0;
2632 NvU8 fmla16;
2633 NvU8 dp;
2634 NvU8 fmla32;
2635 NvU8 ffma;
2636 NvU8 imla1;
2637 NvU8 imla2;
2638 NvU8 imla3;
2639 NvU8 imla4;
2640 } NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_v1B_05;
2641
2642 typedef NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_v;
2643
2644 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05
2645 {
2646 NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_v1B_05 smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04];
2647 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05;
2648
2649 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v;
2650
2651 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS_v1D_03
2652 {
2653 NvU32 gpcMask;
2654 NvU32 tpcMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03];
2655 NvU32 tpcCount[NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03];
2656 NvU32 physGpcMask;
2657 NvU32 mmuPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03];
2658 NvU32 tpcToPesMap[NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT_v1C_03];
2659 NvU32 numPesPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03];
2660 NvU32 zcullMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03];
2661 } NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS_v1D_03;
2662
2663 typedef NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS_v1D_03 NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS_v;
2664
2665 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03
2666 {
2667 NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS_v1D_03 floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04];
2668 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03;
2669
2670 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v;
2671
2672 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO_v1B_05
2673 {
2674 NvU32 widthAlignPixels;
2675 NvU32 heightAlignPixels;
2676 NvU32 pixelSquaresByAliquots;
2677 NvU32 aliquotTotal;
2678 NvU32 zcullRegionByteMultiplier;
2679 NvU32 zcullRegionHeaderSize;
2680 NvU32 zcullSubregionHeaderSize;
2681 NvU32 subregionCount;
2682 NvU32 subregionWidthAlignPixels;
2683 NvU32 subregionHeightAlignPixels;
2684 } NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO_v1B_05;
2685
2686 typedef NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO_v;
2687
2688 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05
2689 {
2690 NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO_v1B_05 engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04];
2691 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05;
2692
2693 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v;
2694
2695 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_v1B_05
2696 {
2697 NvU32 fecsRecordSize;
2698 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_v1B_05;
2699
2700 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_v;
2701
2702 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05
2703 {
2704 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_v1B_05 fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04];
2705 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05;
2706
2707 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v;
2708
2709 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_v1D_04
2710 {
2711 NvU32 fecsRecordSize;
2712 NvU32 timestampHiTagMask;
2713 NvU8 timestampHiTagShift;
2714 NvU64 timestampVMask NV_ALIGN_BYTES(8);
2715 NvU8 numLowerBitsZeroShift;
2716 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_v1D_04;
2717
2718 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_v1D_04 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_v;
2719
2720 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04
2721 {
2722 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_v1D_04 fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04];
2723 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04;
2724
2725 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v;
2726
2727 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES_v1E_02
2728 {
2729 NvBool bPerSubCtxheaderSupported;
2730 } NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES_v1E_02;
2731
2732 typedef NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES_v1E_02 NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES_v;
2733
2734 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02
2735 {
2736 NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES_v1E_02 pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04];
2737 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02;
2738
2739 typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02 NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v;
2740
2741 typedef struct NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F
2742 {
2743 NvBool ctxsw;
2744 } NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F;
2745
2746 typedef NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v;
2747
2748 typedef struct NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F
2749 {
2750 NvBool ctxsw;
2751 } NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F;
2752
2753 typedef NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v;
2754
2755 typedef struct NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F
2756 {
2757 NvU32 regOpCount;
2758 NVB0CC_REGOPS_MODE mode;
2759 NvBool bPassed;
2760 NvBool bDirect;
2761 NV2080_CTRL_GPU_REG_OP_v03_00 regOps[NVB0CC_REGOPS_MAX_COUNT];
2762 } NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F;
2763
2764 typedef NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v;
2765
2766 typedef struct NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14
2767 {
2768 NvHandle hMemPmaBuffer;
2769 NvU64 pmaBufferOffset NV_ALIGN_BYTES(8);
2770 NvU64 pmaBufferSize NV_ALIGN_BYTES(8);
2771 NvHandle hMemPmaBytesAvailable;
2772 NvU64 pmaBytesAvailableOffset NV_ALIGN_BYTES(8);
2773 NvBool ctxsw;
2774 NvU32 pmaChannelIdx;
2775 NvU64 pmaBufferVA NV_ALIGN_BYTES(8);
2776 } NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14;
2777
2778 typedef NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14 NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v;
2779
2780 typedef struct NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14
2781 {
2782 NvU64 bytesConsumed NV_ALIGN_BYTES(8);
2783 NvBool bUpdateAvailableBytes;
2784 NvBool bWait;
2785 NvU64 bytesAvailable NV_ALIGN_BYTES(8);
2786 NvBool bReturnPut;
2787 NvU64 putPtr NV_ALIGN_BYTES(8);
2788 NvU32 pmaChannelIdx;
2789 } NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14;
2790
2791 typedef NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14 NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v;
2792
2793 typedef struct NV2080_CTRL_FB_INFO_v1A_15
2794 {
2795 NvU32 index;
2796 NvU32 data;
2797 } NV2080_CTRL_FB_INFO_v1A_15;
2798
2799 typedef NV2080_CTRL_FB_INFO_v1A_15 NV2080_CTRL_FB_INFO_v;
2800
2801 typedef struct NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A
2802 {
2803 NvU32 fbInfoListSize;
2804 NV2080_CTRL_FB_INFO_v1A_15 fbInfoList[NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_24_0A];
2805 } NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A;
2806
2807 typedef struct NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00
2808 {
2809 NvU32 fbInfoListSize;
2810 NV2080_CTRL_FB_INFO_v1A_15 fbInfoList[NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_27_00];
2811 } NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00;
2812
2813 typedef NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00 NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v;
2814
2815 typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_v1A_1A
2816 {
2817 NvHandle hUserClient;
2818 NvHandle hChannel;
2819 NvU32 bufferType;
2820 NvU32 firstPage;
2821 NvU32 numPages;
2822 NvU64 physAddrs[NV2080_CTRL_KGR_MAX_BUFFER_PTES] NV_ALIGN_BYTES(8);
2823 NvBool bNoMorePages;
2824 } NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_v1A_1A;
2825
2826 typedef NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_v1A_1A NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_v;
2827
2828 typedef struct NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D
2829 {
2830 NvU8 data[NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D];
2831 } NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D;
2832
2833 typedef NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v;
2834
2835 typedef struct NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D
2836 {
2837 NvU32 swizzId;
2838 NvU64 fbpEnMask NV_ALIGN_BYTES(8);
2839 } NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D;
2840
2841 typedef NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v;
2842
2843 typedef struct NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D
2844 {
2845 NvU32 fbpIndex;
2846 NvU32 ltcEnMask;
2847 } NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D;
2848
2849 typedef NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v;
2850
2851 typedef struct NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D
2852 {
2853 NvU32 fbpIndex;
2854 NvU32 ltsEnMask;
2855 } NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D;
2856
2857 typedef NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v;
2858
2859 typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D
2860 {
2861 NvU32 fbpIndex;
2862 NvU32 fbpaEnMask;
2863 } NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D;
2864
2865 typedef NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v;
2866
2867 typedef struct NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D
2868 {
2869 NvU32 fbpIndex;
2870 NvU32 ropEnMask;
2871 } NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D;
2872
2873 typedef NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v;
2874
2875 typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D
2876 {
2877 NvU32 fbpIndex;
2878 NvU32 swizzId;
2879 NvU32 ltcEnMask;
2880 } NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D;
2881
2882 typedef NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v;
2883
2884 typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D
2885 {
2886 NvU32 fbpIndex;
2887 NvU32 swizzId;
2888 NvU32 ltsEnMask;
2889 } NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D;
2890
2891 typedef NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v;
2892
2893 typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D
2894 {
2895 NvU32 fbpIndex;
2896 NvU32 swizzId;
2897 NvU32 fbpaEnMask;
2898 } NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D;
2899
2900 typedef NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v;
2901
2902 typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D
2903 {
2904 NvU32 fbpIndex;
2905 NvU32 swizzId;
2906 NvU32 ropEnMask;
2907 } NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D;
2908
2909 typedef NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v;
2910
2911 typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D
2912 {
2913 NvU32 fbpIndex;
2914 NvU32 swizzId;
2915 NvU64 fbpaSubpEnMask NV_ALIGN_BYTES(8);
2916 } NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D;
2917
2918 typedef NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v;
2919
2920 typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D
2921 {
2922 NvU32 fbpIndex;
2923 NvU32 fbpaSubpEnMask;
2924 } NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D;
2925
2926 typedef NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v;
2927
2928 typedef struct NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D
2929 {
2930 NvU32 fbpIndex;
2931 NvU32 fbpLogicalIndex;
2932 } NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D;
2933
2934 typedef NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v;
2935
2936 typedef struct NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v26_04
2937 {
2938 NvU32 sysIdx;
2939 NvU32 sysl2LtcEnMask;
2940 } NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v26_04;
2941
2942 typedef NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v26_04 NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v;
2943
2944 typedef struct NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v26_04
2945 {
2946 NvU32 fbpIndex;
2947 NvU32 pacEnMask;
2948 } NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v26_04;
2949
2950 typedef NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v26_04 NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v;
2951
2952 typedef struct NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v26_04
2953 {
2954 NvU32 fbpIndex;
2955 NvU64 logicalLtcEnMask NV_ALIGN_BYTES(8);
2956 } NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v26_04;
2957
2958 typedef NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v26_04 NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v;
2959
2960 typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v26_04
2961 {
2962 NvU32 fbpIndex;
2963 NvU32 swizzId;
2964 NvU64 logicalLtcEnMask NV_ALIGN_BYTES(8);
2965 } NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v26_04;
2966
2967 typedef NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v26_04 NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v;
2968
2969 typedef union NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D
2970 {
2971 NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D inv;
2972 NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D fbp;
2973 NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D ltc;
2974 NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D lts;
2975 NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D fbpa;
2976 NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D rop;
2977 NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D dmLtc;
2978 NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D dmLts;
2979 NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D dmFbpa;
2980 NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D dmRop;
2981 NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D dmFbpaSubp;
2982 NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D fbpaSubp;
2983 NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D fbpLogicalMap;
2984 } NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D;
2985
2986 typedef union NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04
2987 {
2988 NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D inv;
2989 NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D fbp;
2990 NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D ltc;
2991 NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D lts;
2992 NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D fbpa;
2993 NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D rop;
2994 NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D dmLtc;
2995 NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D dmLts;
2996 NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D dmFbpa;
2997 NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D dmRop;
2998 NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D dmFbpaSubp;
2999 NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D fbpaSubp;
3000 NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D fbpLogicalMap;
3001 NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v26_04 sysl2Ltc;
3002 NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v26_04 pac;
3003 NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v26_04 logicalLtc;
3004 NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v26_04 dmLogicalLtc;
3005 } NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04;
3006
3007 typedef NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04 NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v;
3008
3009 typedef struct NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D
3010 {
3011 NvU16 queryType;
3012 NvU8 reserved[2];
3013 NvU32 status;
3014 NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D queryParams;
3015 } NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D;
3016
3017 typedef struct NV2080_CTRL_FB_FS_INFO_QUERY_v26_04
3018 {
3019 NvU16 queryType;
3020 NvU8 reserved[2];
3021 NvU32 status;
3022 NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04 queryParams;
3023 } NV2080_CTRL_FB_FS_INFO_QUERY_v26_04;
3024
3025 typedef NV2080_CTRL_FB_FS_INFO_QUERY_v26_04 NV2080_CTRL_FB_FS_INFO_QUERY_v;
3026
3027 typedef struct NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00
3028 {
3029 NvU16 numQueries;
3030 NvU8 reserved[6];
3031 NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D queries[NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v24_00];
3032 } NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00;
3033
3034 typedef struct NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v26_04
3035 {
3036 NvU16 numQueries;
3037 NvU8 reserved[6];
3038 NV2080_CTRL_FB_FS_INFO_QUERY_v26_04 queries[NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v24_00];
3039 } NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v26_04;
3040
3041 typedef NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v26_04 NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v;
3042
3043 typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D
3044 {
3045 NvU32 gpcCount;
3046 } NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D;
3047
3048 typedef NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v;
3049
3050 typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D
3051 {
3052 NvU32 gpcId;
3053 NvU32 chipletGpcMap;
3054 } NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D;
3055
3056 typedef NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v;
3057
3058 typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D
3059 {
3060 NvU32 gpcId;
3061 NvU32 tpcMask;
3062 } NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D;
3063
3064 typedef NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v;
3065
3066 typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D
3067 {
3068 NvU32 gpcId;
3069 NvU32 ppcMask;
3070 } NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D;
3071
3072 typedef NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v;
3073
3074 typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D
3075 {
3076 NvU32 swizzId;
3077 NvU32 gpcId;
3078 NvU32 chipletGpcMap;
3079 } NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D;
3080
3081 typedef NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v;
3082
3083 typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D
3084 {
3085 NvU32 chipletSyspipeMask;
3086 } NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D;
3087
3088 typedef NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v;
3089
3090 typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D
3091 {
3092 NvU16 swizzId;
3093 NvU16 physSyspipeIdCount;
3094 NvU8 physSyspipeId[NV2080_CTRL_GRMGR_MAX_SMC_IDS_v1A_1D];
3095 } NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D;
3096
3097 typedef NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v;
3098
3099 typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D
3100 {
3101 NvU32 swizzId;
3102 NvU32 grIdx;
3103 NvU32 gpcEnMask;
3104 } NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D;
3105
3106 typedef NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v;
3107
3108 typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D
3109 {
3110 NvU32 syspipeId;
3111 } NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D;
3112
3113 typedef NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v;
3114
3115 typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D
3116 {
3117 NvU32 gpcId;
3118 NvU32 ropMask;
3119 } NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D;
3120
3121 typedef NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v;
3122
3123 typedef union NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D
3124 {
3125 NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D gpcCountData;
3126 NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D chipletGpcMapData;
3127 NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D tpcMaskData;
3128 NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D ppcMaskData;
3129 NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D partitionGpcMapData;
3130 NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D syspipeMaskData;
3131 NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D partitionChipletSyspipeData;
3132 NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D dmGpcMaskData;
3133 NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D partitionSyspipeIdData;
3134 NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D ropMaskData;
3135 } NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D;
3136
3137 typedef NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v;
3138
3139 typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D
3140 {
3141 NvU16 queryType;
3142 NvU8 reserved[2];
3143 NvU32 status;
3144 NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D queryData;
3145 } NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D;
3146
3147 typedef NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v;
3148
3149 typedef struct NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D
3150 {
3151 NvU16 numQueries;
3152 NvU8 reserved[6];
3153 NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D queries[NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D];
3154 } NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D;
3155
3156 typedef NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v;
3157
3158 typedef struct NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E
3159 {
3160 NvBool bImmediate;
3161 } NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E;
3162
3163 typedef NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E NVA06F_CTRL_STOP_CHANNEL_PARAMS_v;
3164
3165 typedef struct NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F
3166 {
3167 NvHandle hChannel;
3168 NvU32 samplingMode;
3169 NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo;
3170 } NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F;
3171
3172 typedef NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v;
3173
3174 typedef struct NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F
3175 {
3176 NvBool bSetMaxFreq;
3177 } NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F;
3178
3179 typedef NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v;
3180
3181 typedef struct PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F
3182 {
3183 NvU32 clientActiveMask;
3184 NvU8 bRegkeyLimitRatedTdp;
3185 } PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F;
3186
3187 typedef PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v;
3188
3189 typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F
3190 {
3191 PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F rm;
3192 NV2080_CTRL_PERF_RATED_TDP_ACTION output;
3193 NV2080_CTRL_PERF_RATED_TDP_ACTION inputs[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS_v1A_1F];
3194 } NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F;
3195
3196 typedef NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v;
3197
3198 typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F
3199 {
3200 NV2080_CTRL_PERF_RATED_TDP_CLIENT client;
3201 NV2080_CTRL_PERF_RATED_TDP_ACTION input;
3202 } NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F;
3203
3204 typedef NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v;
3205
3206 typedef struct NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F
3207 {
3208 NvU32 pmaChannelIdx;
3209 } NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F;
3210
3211 typedef NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v;
3212
3213 typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F
3214 {
3215 NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo;
3216 NvU8 imla0;
3217 NvU8 fmla16;
3218 NvU8 dp;
3219 NvU8 fmla32;
3220 NvU8 ffma;
3221 NvU8 imla1;
3222 NvU8 imla2;
3223 NvU8 imla3;
3224 NvU8 imla4;
3225 } NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F;
3226
3227 typedef NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v;
3228
3229 typedef struct NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23
3230 {
3231 NvU64 base NV_ALIGN_BYTES(8);
3232 NvU64 size NV_ALIGN_BYTES(8);
3233 NvU32 addressSpace;
3234 NvU32 cacheAttrib;
3235 } NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23;
3236
3237 typedef NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23 NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v;
3238
3239 typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02
3240 {
3241 NvU32 smID;
3242 NvBool bSingleStep;
3243 } NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02;
3244
3245 typedef NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02 NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v;
3246
3247 typedef struct NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04
3248 {
3249 NvHandle hChannelGroup;
3250 NV0080_CTRL_GR_TPC_PARTITION_MODE mode;
3251 NvBool bEnableAllTpcs;
3252 NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo;
3253 } NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04;
3254
3255 typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04 NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v;
3256
3257 typedef struct NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08
3258 {
3259 NvU32 pmaChannelIdx;
3260 NvBool bMembytesPollingRequired;
3261 } NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08;
3262
3263 typedef NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08 NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v;
3264
3265 typedef struct NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C
3266 {
3267 NvU32 pmaChannelIdx;
3268 NvU64 pmaBufferVA NV_ALIGN_BYTES(8);
3269 NvU64 pmaBufferSize NV_ALIGN_BYTES(8);
3270 NvU64 membytesVA NV_ALIGN_BYTES(8);
3271 NvU64 hwpmIBPA NV_ALIGN_BYTES(8);
3272 NvU8 hwpmIBAperture;
3273 } NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C;
3274
3275 typedef NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v;
3276
3277 typedef struct NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06
3278 {
3279 NvBool bMode;
3280 } NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06;
3281
3282 typedef NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06 NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v;
3283
3284 typedef struct NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07
3285 {
3286 NvU64 base NV_ALIGN_BYTES(8);
3287 NvU64 size NV_ALIGN_BYTES(8);
3288 NvU64 alignment NV_ALIGN_BYTES(8);
3289 NvU32 addressSpace;
3290 NvU32 cpuCacheAttrib;
3291 } NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07;
3292
3293 typedef NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07 NV2080_CTRL_INTERNAL_MEMDESC_INFO_v;
3294
3295 typedef struct NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07
3296 {
3297 NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07 methodBufferMemdesc[NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES_v1E_07];
3298 NvU64 bar2Addr[NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES_v1E_07] NV_ALIGN_BYTES(8);
3299 NvU32 numValidEntries;
3300 } NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07;
3301
3302 typedef NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07 NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v;
3303
3304 typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v1E_0A
3305 {
3306 NvHandle hChannel;
3307 NvU64 totalBufferSize NV_ALIGN_BYTES(8);
3308 } NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v1E_0A;
3309
3310 typedef NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v1E_0A NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v;
3311
3312 typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v1E_0A
3313 {
3314 NvHandle hUserClient;
3315 NvHandle hChannel;
3316 NvU64 alignment NV_ALIGN_BYTES(8);
3317 NvU64 size NV_ALIGN_BYTES(8);
3318 NvP64 bufferHandle NV_ALIGN_BYTES(8);
3319 NvU64 pageCount NV_ALIGN_BYTES(8);
3320 NvU64 physAddr NV_ALIGN_BYTES(8);
3321 NvU32 aperture;
3322 NvU32 kind;
3323 NvU32 pageSize;
3324 NvBool bIsContigous;
3325 NvBool bDeviceDescendant;
3326 NvU8 uuid[16];
3327 } NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v1E_0A;
3328
3329 typedef NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v1E_0A NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v;
3330
3331 typedef struct NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05
3332 {
3333 NvBool bZbcSurfacesExist;
3334 } NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05;
3335
3336 typedef NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05 NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v;
3337
3338 typedef struct NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C
3339 {
3340 NvU64 offset NV_ALIGN_BYTES(8);
3341 NvU64 totalPfns NV_ALIGN_BYTES(8);
3342 NvU32 pfnArray[NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE];
3343 NvU32 numPfns;
3344 } NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C;
3345
3346 typedef NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C NV00F8_CTRL_DESCRIBE_PARAMS_v;
3347
3348 typedef struct NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C
3349 {
3350 NvU64 totalSize NV_ALIGN_BYTES(8);
3351 NvU64 freeSize NV_ALIGN_BYTES(8);
3352 } NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C;
3353
3354 typedef NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v;
3355
3356 typedef struct ATOMIC_OP_v1F_08
3357 {
3358 NvBool bSupported;
3359 NvU32 attributes;
3360 } ATOMIC_OP_v1F_08;
3361
3362 typedef ATOMIC_OP_v1F_08 ATOMIC_OP_v;
3363
3364 typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08
3365 {
3366 ATOMIC_OP_v1F_08 atomicOp[NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT_v1F_08];
3367 } NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08;
3368
3369 typedef NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08 NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v;
3370
3371 typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02
3372 {
3373 NvU32 gpuId;
3374 NvU8 gpuUuid[VM_UUID_SIZE_v21_02];
3375 NvU32 p2pCaps;
3376 NvU32 p2pOptimalReadCEs;
3377 NvU32 p2pOptimalWriteCEs;
3378 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D];
3379 NvU32 busPeerId;
3380 } NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02;
3381
3382 typedef NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v;
3383
3384 typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02
3385 {
3386 NvBool bAllCaps;
3387 NvBool bUseUuid;
3388 NvU32 peerGpuCount;
3389 NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_v21_02];
3390 } NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02;
3391
3392 typedef NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 NV2080_CTRL_GET_P2P_CAPS_PARAMS_v;
3393
3394 typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03
3395 {
3396 NvU32 connectionType;
3397 NvU32 peerId;
3398 NvU32 bSpaAccessOnly;
3399 NvBool bUseUuid;
3400 NvU32 remoteGpuId;
3401 NvU8 remoteGpuUuid[VM_UUID_SIZE_v21_02];
3402 } NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03;
3403
3404 typedef NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v;
3405
3406 typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03
3407 {
3408 NvU32 connectionType;
3409 NvU32 peerId;
3410 NvBool bUseUuid;
3411 NvU32 remoteGpuId;
3412 NvU8 remoteGpuUuid[VM_UUID_SIZE_v21_02];
3413 } NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03;
3414
3415 typedef NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v;
3416
3417 typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08
3418 {
3419 NvU8 chipletType;
3420 NvU8 chipletIndex;
3421 NvU16 numCredits;
3422 } NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08;
3423
3424 typedef NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v;
3425
3426 typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08
3427 {
3428 NvU8 status;
3429 NvU8 entryIndex;
3430 } NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08;
3431
3432 typedef NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v;
3433
3434 typedef struct NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08
3435 {
3436 NvU32 numCredits;
3437 } NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08;
3438
3439 typedef NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v;
3440
3441 typedef struct NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08
3442 {
3443 NvU8 pmaChannelIdx;
3444 NvU8 numEntries;
3445 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 statusInfo;
3446 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08];
3447 } NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08;
3448
3449 typedef NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v;
3450
3451 typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08
3452 {
3453 NvU8 pmaChannelIdx;
3454 NvU8 numEntries;
3455 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 statusInfo;
3456 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08];
3457 } NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08;
3458
3459 typedef NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08 NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v;
3460
3461 typedef struct NV2080_CTRL_CE_CAPS_v21_0A
3462 {
3463 NvU8 capsTbl[NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A];
3464 } NV2080_CTRL_CE_CAPS_v21_0A;
3465
3466 typedef NV2080_CTRL_CE_CAPS_v21_0A NV2080_CTRL_CE_CAPS_v;
3467
3468 typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A
3469 {
3470 NV2080_CTRL_CE_CAPS_v21_0A ceCaps[NV2080_CTRL_MAX_PCES_v21_0A];
3471 NvU32 present;
3472 } NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A;
3473
3474 typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v;
3475
3476 typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01
3477 {
3478 NvBool bIsLinkUp;
3479 NvU32 nrLinks;
3480 NvU32 linkMask;
3481 NvU32 perLinkBwMBps;
3482 NvU32 remoteType;
3483 } NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01;
3484
3485 typedef NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01 NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v;
3486
3487 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04
3488 {
3489 NvU32 sensorId;
3490 NvU32 limit;
3491 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04;
3492
3493 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v;
3494
3495 typedef union NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04
3496 {
3497 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04 smbpbi;
3498 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04;
3499
3500 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v;
3501
3502 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04
3503 {
3504 NvU8 type ;
3505 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04 data;
3506 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04;
3507
3508 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v;
3509
3510 typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04
3511 {
3512 NvU8 flags;
3513 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 syncData;
3514 } NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04;
3515
3516 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v;
3517
3518 typedef struct VGPU_P2P_CAPABILITY_PARAMS_v25_03
3519 {
3520 NvBool bGpuSupportsFabricProbe;
3521 } VGPU_P2P_CAPABILITY_PARAMS_v25_03;
3522
3523 typedef VGPU_P2P_CAPABILITY_PARAMS_v25_03 VGPU_P2P_CAPABILITY_PARAMS_v;
3524
3525 typedef struct NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04
3526 {
3527 NvU32 value;
3528 } NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04;
3529
3530 typedef NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04 NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v;
3531
3532 typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO_v25_05
3533 {
3534 NvU32 faultId;
3535 NvU32 instanceId;
3536 NvU32 typeEnum;
3537 NvU32 resetId;
3538 NvU32 devicePriBase;
3539 NvU32 isEngine;
3540 NvU32 rlEngId;
3541 NvU32 runlistPriBase;
3542 NvU32 groupId;
3543 } NV2080_CTRL_INTERNAL_DEVICE_INFO_v25_05;
3544
3545 typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO_v27_05
3546 {
3547 NvU32 faultId;
3548 NvU32 instanceId;
3549 NvU32 typeEnum;
3550 NvU32 resetId;
3551 NvU32 devicePriBase;
3552 NvU32 isEngine;
3553 NvU32 rlEngId;
3554 NvU32 runlistPriBase;
3555 NvU32 groupId;
3556 NvU32 ginTargetId;
3557 NvU32 deviceBroadcastPriBase;
3558 } NV2080_CTRL_INTERNAL_DEVICE_INFO_v27_05;
3559
3560 typedef NV2080_CTRL_INTERNAL_DEVICE_INFO_v27_05 NV2080_CTRL_INTERNAL_DEVICE_INFO_v;
3561
3562 typedef struct NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v25_05
3563 {
3564 NvU32 numEntries;
3565 NV2080_CTRL_INTERNAL_DEVICE_INFO_v25_05 deviceInfoTable[NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES_V25_05];
3566 } NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v25_05;
3567
3568 typedef struct NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v27_05
3569 {
3570 NvU32 numEntries;
3571 NV2080_CTRL_INTERNAL_DEVICE_INFO_v27_05 deviceInfoTable[NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES_V25_05];
3572 } NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v27_05;
3573
3574 typedef NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v27_05 NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v;
3575
3576 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06
3577 {
3578 NvBool bOneToOneComptagLineAllocation;
3579 NvBool bUseOneToFourComptagLineAllocation;
3580 NvBool bUseRawModeComptaglineAllocation;
3581 NvBool bDisableCompbitBacking;
3582 NvBool bDisablePostL2Compression;
3583 NvBool bEnabledEccFBPA;
3584 NvBool bL2PreFill;
3585 NvU64 l2CacheSize NV_ALIGN_BYTES(8);
3586 NvBool bFbpaPresent;
3587 NvU32 comprPageSize;
3588 NvU32 comprPageShift;
3589 NvU32 ramType;
3590 NvU32 ltcCount;
3591 NvU32 ltsPerLtcCount;
3592 } NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06;
3593
3594 typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06 NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v;
3595
3596 typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B
3597 {
3598 NvU32 atomicsCaps;
3599 } NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B;
3600
3601 typedef NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v;
3602
3603 typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C
3604 {
3605 NvU32 dataSize;
3606 NvU8 data[512];
3607 } NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C;
3608
3609 typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v;
3610
3611 typedef struct GPU_EXEC_SYSPIPE_INFO_v26_01
3612 {
3613 NvU32 execPartCount;
3614 NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05];
3615 NvU32 syspipeId[NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05];
3616 } GPU_EXEC_SYSPIPE_INFO_v26_01;
3617
3618 typedef GPU_EXEC_SYSPIPE_INFO_v26_01 GPU_EXEC_SYSPIPE_INFO_v;
3619
3620
3621 #endif
3622
3623 #ifdef SDK_UNION_MEMBER_NAME_FUNCTIONS
3624 // Union member index functions for NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle
_get_union_member_index_NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v06_00(NvU32 cmd)3625 uint32_t _get_union_member_index_NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v06_00(NvU32 cmd)
3626 {
3627 switch (cmd)
3628 {
3629 case NV2080_CTRL_CMD_GPU_INITIALIZE_CTX:
3630 return 0; // "InitCtx"
3631
3632 case NV2080_CTRL_CMD_GPU_PROMOTE_CTX:
3633 return 1; // "PromoteCtx"
3634
3635 case NV2080_CTRL_CMD_GPU_EVICT_CTX:
3636 return 2; // "EvictCtx"
3637
3638 case NV2080_CTRL_CMD_DMA_INVALIDATE_TLB:
3639 return 3; // "InvalidateTlb"
3640
3641 default:
3642 return UNION_UNKNOWN_FIELD_PRINT;
3643 }
3644 }
3645
3646
3647
3648
3649 // Union member index functions for vgpuGetEngineUtilization_data
_get_union_member_index_vgpuGetEngineUtilization_data_v1F_0E(NvU32 cmd)3650 uint32_t _get_union_member_index_vgpuGetEngineUtilization_data_v1F_0E(NvU32 cmd)
3651 {
3652 switch (cmd)
3653 {
3654 case NV2080_CTRL_CMD_PERF_GET_PERFMON_SAMPLE:
3655 return 0; // "perfmonSample"
3656
3657 case NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE:
3658 return 1; // "vidPerfmonSample"
3659
3660 case NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE:
3661 return 3; // "getAccountingState"
3662
3663 case NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE:
3664 return 4; // "setAccountingState"
3665
3666 case NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS:
3667 return 5; // "getAccountingPidList"
3668
3669 case NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO:
3670 return 6; // "procAccountingInfo"
3671
3672 case NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA:
3673 return 7; // "clearAccountingInfo"
3674
3675 case NV2080_CTRL_CMD_PERF_GET_PERFMON_SAMPLE_V3:
3676 return 8; // "perfmonSampleV3"
3677
3678 case NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2:
3679 return 9; // "gpumonPerfmonsampleV2"
3680
3681 default:
3682 return UNION_UNKNOWN_FIELD_PRINT;
3683 }
3684 }
3685
3686
3687
3688
3689 // Union member index functions for alloc_object_params
_get_union_member_index_alloc_object_params_v25_08(NvU32 cmd)3690 uint32_t _get_union_member_index_alloc_object_params_v25_08(NvU32 cmd)
3691 {
3692 switch (cmd)
3693 {
3694 case G82_TESLA:
3695 case GT200_TESLA:
3696 case GT214_TESLA:
3697 case NV50_TESLA:
3698 case FERMI_A:
3699 case KEPLER_A:
3700 case KEPLER_B:
3701 case MAXWELL_A:
3702 case MAXWELL_B:
3703 case PASCAL_A:
3704 case PASCAL_B:
3705 case VOLTA_A:
3706 case TURING_A:
3707 case AMPERE_A:
3708 return 0; // "param_NV50_TESLA"
3709
3710 case KEPLER_DMA_COPY_A:
3711 case MAXWELL_DMA_COPY_A:
3712 case PASCAL_DMA_COPY_A:
3713 case VOLTA_DMA_COPY_A:
3714 case TURING_DMA_COPY_A:
3715 case AMPERE_DMA_COPY_A:
3716 return 1; // "param_GT212_DMA_COPY"
3717
3718 case GF100_MSPPP:
3719 return 2; // "param_G98_MSPPP"
3720
3721 case GF100_DISP_SW:
3722 return 3; // "param_GF100_DISP_SW"
3723
3724 case KEPLER_CHANNEL_GROUP_A:
3725 return 4; // "param_KEPLER_CHANNEL_GROUP_A"
3726
3727 case FERMI_CONTEXT_SHARE_A:
3728 return 5; // "param_FERMI_CONTEXT_SHARE_A"
3729
3730 case NVD0B7_VIDEO_ENCODER:
3731 case NVC1B7_VIDEO_ENCODER:
3732 case NVC2B7_VIDEO_ENCODER:
3733 case NVC3B7_VIDEO_ENCODER:
3734 case NVC4B7_VIDEO_ENCODER:
3735 case NVC7B7_VIDEO_ENCODER:
3736 case NVC9B7_VIDEO_ENCODER:
3737 return 6; // "param_NVD0B7_VIDEO_ENCODER"
3738
3739 case FERMI_VASPACE_A:
3740 return 7; // "param_FERMI_VASPACE_A"
3741
3742 case NVA0B0_VIDEO_DECODER:
3743 case NVB0B0_VIDEO_DECODER:
3744 case NVC1B0_VIDEO_DECODER:
3745 case NVC2B0_VIDEO_DECODER:
3746 case NVC3B0_VIDEO_DECODER:
3747 case NV95B1_VIDEO_MSVLD:
3748 return 8; // "param_NVB0B0_VIDEO_DECODER"
3749
3750 case NV95B2_VIDEO_MSPDEC:
3751 return 9; // "param_NV95B2_VIDEO_MSPDEC"
3752
3753 case GT200_DEBUGGER:
3754 return 10; // "param_NV83DE_ALLOC_PARAMETERS"
3755
3756 case NVENC_SW_SESSION:
3757 return 11; // "param_NVENC_SW_SESSION"
3758
3759 case NVC4B0_VIDEO_DECODER:
3760 case NVC6B0_VIDEO_DECODER:
3761 case NVC7B0_VIDEO_DECODER:
3762 case NVB8B0_VIDEO_DECODER:
3763 case NVC9B0_VIDEO_DECODER:
3764 case NVCDB0_VIDEO_DECODER:
3765 return 12; // "param_NVC4B0_VIDEO_DECODER"
3766
3767 case NVFBC_SW_SESSION:
3768 return 13; // "param_NVFBC_SW_SESSION"
3769
3770 case NVC4D1_VIDEO_NVJPG:
3771 case NVB8D1_VIDEO_NVJPG:
3772 case NVC9D1_VIDEO_NVJPG:
3773 case NVCDD1_VIDEO_NVJPG:
3774 return 14; // "param_NV_NVJPG_ALLOCATION_PARAMETERS"
3775
3776 case NV50_P2P:
3777 return 15; // "param_NV503B_ALLOC_PARAMETERS"
3778
3779 case AMPERE_SMC_PARTITION_REF:
3780 return 16; // "param_NVC637_ALLOCATION_PARAMETERS"
3781
3782 case NV01_MEMORY_VIRTUAL:
3783 return 17; // "param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS"
3784
3785 case AMPERE_SMC_EXEC_PARTITION_REF:
3786 return 18; // "param_NVC638_ALLOCATION_PARAMETERS"
3787
3788 case NV50_THIRD_PARTY_P2P:
3789 return 19; // "param_NV503C_ALLOC_PARAMETERS"
3790
3791 case NVC670_DISPLAY:
3792 return 20; // "param_NVC670_ALLOCATION_PARAMETERS"
3793
3794 case NVC67B_WINDOW_IMM_CHANNEL_DMA:
3795 case NVC67D_CORE_CHANNEL_DMA:
3796 case NVC67E_WINDOW_CHANNEL_DMA:
3797 return 21; // "param_NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS"
3798
3799 case MAXWELL_PROFILER_CONTEXT:
3800 return 22; // "param_NVB1CC_ALLOC_PARAMETERS"
3801
3802 case MAXWELL_PROFILER_DEVICE:
3803 return 23; // "param_NVB2CC_ALLOC_PARAMETERS"
3804
3805 case MAXWELL_COMPUTE_A:
3806 case PASCAL_COMPUTE_A:
3807 case VOLTA_COMPUTE_A:
3808 case TURING_COMPUTE_A:
3809 case AMPERE_COMPUTE_A:
3810 case HOPPER_COMPUTE_A:
3811 case MAXWELL_COMPUTE_B:
3812 case PASCAL_COMPUTE_B:
3813 case VOLTA_COMPUTE_B:
3814 case AMPERE_COMPUTE_B:
3815 return 24; // "param_NV_GR_ALLOCATION_PARAMETERS"
3816
3817 case UVM_CHANNEL_RETAINER:
3818 return 25; // "param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS"
3819
3820 case NV_MEMORY_FABRIC:
3821 return 26; // "param_NV00F8_ALLOCATION_PARAMETERS"
3822
3823 case NVC9FA_VIDEO_OFA:
3824 case NVCDFA_VIDEO_OFA:
3825 case NVC6FA_VIDEO_OFA:
3826 case NVC7FA_VIDEO_OFA:
3827 case NVB8FA_VIDEO_OFA:
3828 return 27; // "param_NVC9FA_VIDEO_OFA"
3829
3830 case NV2081_BINAPI:
3831 case NV2082_BINAPI_PRIVILEGED:
3832 return 28; // "param_NV2081_ALLOC_PARAMETERS"
3833
3834 default:
3835 return UNION_UNKNOWN_FIELD_PRINT;
3836 }
3837 }
3838
_get_union_member_index_alloc_object_params_v26_00(NvU32 cmd)3839 uint32_t _get_union_member_index_alloc_object_params_v26_00(NvU32 cmd)
3840 {
3841 switch (cmd)
3842 {
3843 case G82_TESLA:
3844 case GT200_TESLA:
3845 case GT214_TESLA:
3846 case NV50_TESLA:
3847 case FERMI_A:
3848 case KEPLER_A:
3849 case KEPLER_B:
3850 case MAXWELL_A:
3851 case MAXWELL_B:
3852 case PASCAL_A:
3853 case PASCAL_B:
3854 case VOLTA_A:
3855 case TURING_A:
3856 case AMPERE_A:
3857 return 0; // "param_NV50_TESLA"
3858
3859 case KEPLER_DMA_COPY_A:
3860 case MAXWELL_DMA_COPY_A:
3861 case PASCAL_DMA_COPY_A:
3862 case VOLTA_DMA_COPY_A:
3863 case TURING_DMA_COPY_A:
3864 case AMPERE_DMA_COPY_A:
3865 return 1; // "param_GT212_DMA_COPY"
3866
3867 case GF100_MSPPP:
3868 return 2; // "param_G98_MSPPP"
3869
3870 case GF100_DISP_SW:
3871 return 3; // "param_GF100_DISP_SW"
3872
3873 case KEPLER_CHANNEL_GROUP_A:
3874 return 4; // "param_KEPLER_CHANNEL_GROUP_A"
3875
3876 case FERMI_CONTEXT_SHARE_A:
3877 return 5; // "param_FERMI_CONTEXT_SHARE_A"
3878
3879 case NVD0B7_VIDEO_ENCODER:
3880 case NVC1B7_VIDEO_ENCODER:
3881 case NVC2B7_VIDEO_ENCODER:
3882 case NVC3B7_VIDEO_ENCODER:
3883 case NVC4B7_VIDEO_ENCODER:
3884 case NVC7B7_VIDEO_ENCODER:
3885 case NVC9B7_VIDEO_ENCODER:
3886 return 6; // "param_NVD0B7_VIDEO_ENCODER"
3887
3888 case FERMI_VASPACE_A:
3889 return 7; // "param_FERMI_VASPACE_A"
3890
3891 case NVA0B0_VIDEO_DECODER:
3892 case NVB0B0_VIDEO_DECODER:
3893 case NVC1B0_VIDEO_DECODER:
3894 case NVC2B0_VIDEO_DECODER:
3895 case NVC3B0_VIDEO_DECODER:
3896 case NV95B1_VIDEO_MSVLD:
3897 return 8; // "param_NVB0B0_VIDEO_DECODER"
3898
3899 case NV95B2_VIDEO_MSPDEC:
3900 return 9; // "param_NV95B2_VIDEO_MSPDEC"
3901
3902 case GT200_DEBUGGER:
3903 return 10; // "param_NV83DE_ALLOC_PARAMETERS"
3904
3905 case NVENC_SW_SESSION:
3906 return 11; // "param_NVENC_SW_SESSION"
3907
3908 case NVC4B0_VIDEO_DECODER:
3909 case NVC6B0_VIDEO_DECODER:
3910 case NVC7B0_VIDEO_DECODER:
3911 case NVB8B0_VIDEO_DECODER:
3912 case NVC9B0_VIDEO_DECODER:
3913 case NVCDB0_VIDEO_DECODER:
3914 return 12; // "param_NVC4B0_VIDEO_DECODER"
3915
3916 case NVFBC_SW_SESSION:
3917 return 13; // "param_NVFBC_SW_SESSION"
3918
3919 case NVC4D1_VIDEO_NVJPG:
3920 case NVB8D1_VIDEO_NVJPG:
3921 case NVC9D1_VIDEO_NVJPG:
3922 case NVCDD1_VIDEO_NVJPG:
3923 return 14; // "param_NV_NVJPG_ALLOCATION_PARAMETERS"
3924
3925 case NV50_P2P:
3926 return 15; // "param_NV503B_ALLOC_PARAMETERS"
3927
3928 case AMPERE_SMC_PARTITION_REF:
3929 return 16; // "param_NVC637_ALLOCATION_PARAMETERS"
3930
3931 case NV01_MEMORY_VIRTUAL:
3932 return 17; // "param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS"
3933
3934 case AMPERE_SMC_EXEC_PARTITION_REF:
3935 return 18; // "param_NVC638_ALLOCATION_PARAMETERS"
3936
3937 case NV50_THIRD_PARTY_P2P:
3938 return 19; // "param_NV503C_ALLOC_PARAMETERS"
3939
3940 case NVC670_DISPLAY:
3941 return 20; // "param_NVC670_ALLOCATION_PARAMETERS"
3942
3943 case NVC67B_WINDOW_IMM_CHANNEL_DMA:
3944 case NVC67D_CORE_CHANNEL_DMA:
3945 case NVC67E_WINDOW_CHANNEL_DMA:
3946 return 21; // "param_NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS"
3947
3948 case MAXWELL_PROFILER_CONTEXT:
3949 return 22; // "param_NVB1CC_ALLOC_PARAMETERS"
3950
3951 case MAXWELL_PROFILER_DEVICE:
3952 return 23; // "param_NVB2CC_ALLOC_PARAMETERS"
3953
3954 case MAXWELL_COMPUTE_A:
3955 case PASCAL_COMPUTE_A:
3956 case VOLTA_COMPUTE_A:
3957 case TURING_COMPUTE_A:
3958 case AMPERE_COMPUTE_A:
3959 case HOPPER_COMPUTE_A:
3960 case MAXWELL_COMPUTE_B:
3961 case PASCAL_COMPUTE_B:
3962 case VOLTA_COMPUTE_B:
3963 case AMPERE_COMPUTE_B:
3964 return 24; // "param_NV_GR_ALLOCATION_PARAMETERS"
3965
3966 case UVM_CHANNEL_RETAINER:
3967 return 25; // "param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS"
3968
3969 case NV_MEMORY_FABRIC:
3970 return 26; // "param_NV00F8_ALLOCATION_PARAMETERS"
3971
3972 case NVC9FA_VIDEO_OFA:
3973 case NVCDFA_VIDEO_OFA:
3974 case NVC6FA_VIDEO_OFA:
3975 case NVC7FA_VIDEO_OFA:
3976 case NVB8FA_VIDEO_OFA:
3977 return 27; // "param_NVC9FA_VIDEO_OFA"
3978
3979 case NV2081_BINAPI:
3980 case NV2082_BINAPI_PRIVILEGED:
3981 return 28; // "param_NV2081_ALLOC_PARAMETERS"
3982
3983 default:
3984 return UNION_UNKNOWN_FIELD_PRINT;
3985 }
3986 }
3987
_get_union_member_index_alloc_object_params_v27_00(NvU32 cmd)3988 uint32_t _get_union_member_index_alloc_object_params_v27_00(NvU32 cmd)
3989 {
3990 switch (cmd)
3991 {
3992 case G82_TESLA:
3993 case GT200_TESLA:
3994 case GT214_TESLA:
3995 case NV50_TESLA:
3996 case FERMI_A:
3997 case KEPLER_A:
3998 case KEPLER_B:
3999 case MAXWELL_A:
4000 case MAXWELL_B:
4001 case PASCAL_A:
4002 case PASCAL_B:
4003 case VOLTA_A:
4004 case TURING_A:
4005 case AMPERE_A:
4006 return 0; // "param_NV50_TESLA"
4007
4008 case KEPLER_DMA_COPY_A:
4009 case MAXWELL_DMA_COPY_A:
4010 case PASCAL_DMA_COPY_A:
4011 case VOLTA_DMA_COPY_A:
4012 case TURING_DMA_COPY_A:
4013 case AMPERE_DMA_COPY_A:
4014 return 1; // "param_GT212_DMA_COPY"
4015
4016 case GF100_MSPPP:
4017 return 2; // "param_G98_MSPPP"
4018
4019 case GF100_DISP_SW:
4020 return 3; // "param_GF100_DISP_SW"
4021
4022 case KEPLER_CHANNEL_GROUP_A:
4023 return 4; // "param_KEPLER_CHANNEL_GROUP_A"
4024
4025 case FERMI_CONTEXT_SHARE_A:
4026 return 5; // "param_FERMI_CONTEXT_SHARE_A"
4027
4028 case NVD0B7_VIDEO_ENCODER:
4029 case NVC1B7_VIDEO_ENCODER:
4030 case NVC2B7_VIDEO_ENCODER:
4031 case NVC3B7_VIDEO_ENCODER:
4032 case NVC4B7_VIDEO_ENCODER:
4033 case NVC7B7_VIDEO_ENCODER:
4034 case NVC9B7_VIDEO_ENCODER:
4035 return 6; // "param_NVD0B7_VIDEO_ENCODER"
4036
4037 case FERMI_VASPACE_A:
4038 return 7; // "param_FERMI_VASPACE_A"
4039
4040 case NVA0B0_VIDEO_DECODER:
4041 case NVB0B0_VIDEO_DECODER:
4042 case NVC1B0_VIDEO_DECODER:
4043 case NVC2B0_VIDEO_DECODER:
4044 case NVC3B0_VIDEO_DECODER:
4045 case NV95B1_VIDEO_MSVLD:
4046 return 8; // "param_NVB0B0_VIDEO_DECODER"
4047
4048 case NV95B2_VIDEO_MSPDEC:
4049 return 9; // "param_NV95B2_VIDEO_MSPDEC"
4050
4051 case GT200_DEBUGGER:
4052 return 10; // "param_NV83DE_ALLOC_PARAMETERS"
4053
4054 case NVENC_SW_SESSION:
4055 return 11; // "param_NVENC_SW_SESSION"
4056
4057 case NVC4B0_VIDEO_DECODER:
4058 case NVC6B0_VIDEO_DECODER:
4059 case NVC7B0_VIDEO_DECODER:
4060 case NVB8B0_VIDEO_DECODER:
4061 case NVC9B0_VIDEO_DECODER:
4062 case NVCDB0_VIDEO_DECODER:
4063 return 12; // "param_NVC4B0_VIDEO_DECODER"
4064
4065 case NVFBC_SW_SESSION:
4066 return 13; // "param_NVFBC_SW_SESSION"
4067
4068 case NVC4D1_VIDEO_NVJPG:
4069 case NVB8D1_VIDEO_NVJPG:
4070 case NVC9D1_VIDEO_NVJPG:
4071 case NVCDD1_VIDEO_NVJPG:
4072 return 14; // "param_NV_NVJPG_ALLOCATION_PARAMETERS"
4073
4074 case NV50_P2P:
4075 return 15; // "param_NV503B_ALLOC_PARAMETERS"
4076
4077 case AMPERE_SMC_PARTITION_REF:
4078 return 16; // "param_NVC637_ALLOCATION_PARAMETERS"
4079
4080 case NV01_MEMORY_VIRTUAL:
4081 return 17; // "param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS"
4082
4083 case AMPERE_SMC_EXEC_PARTITION_REF:
4084 return 18; // "param_NVC638_ALLOCATION_PARAMETERS"
4085
4086 case NV50_THIRD_PARTY_P2P:
4087 return 19; // "param_NV503C_ALLOC_PARAMETERS"
4088
4089 case NVC670_DISPLAY:
4090 return 20; // "param_NVC670_ALLOCATION_PARAMETERS"
4091
4092 case NVC67B_WINDOW_IMM_CHANNEL_DMA:
4093 case NVC67D_CORE_CHANNEL_DMA:
4094 case NVC67E_WINDOW_CHANNEL_DMA:
4095 return 21; // "param_NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS"
4096
4097 case MAXWELL_PROFILER_CONTEXT:
4098 return 22; // "param_NVB1CC_ALLOC_PARAMETERS"
4099
4100 case MAXWELL_PROFILER_DEVICE:
4101 return 23; // "param_NVB2CC_ALLOC_PARAMETERS"
4102
4103 case MAXWELL_COMPUTE_A:
4104 case PASCAL_COMPUTE_A:
4105 case VOLTA_COMPUTE_A:
4106 case TURING_COMPUTE_A:
4107 case AMPERE_COMPUTE_A:
4108 case HOPPER_COMPUTE_A:
4109 case MAXWELL_COMPUTE_B:
4110 case PASCAL_COMPUTE_B:
4111 case VOLTA_COMPUTE_B:
4112 case AMPERE_COMPUTE_B:
4113 return 24; // "param_NV_GR_ALLOCATION_PARAMETERS"
4114
4115 case UVM_CHANNEL_RETAINER:
4116 return 25; // "param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS"
4117
4118 case NV_MEMORY_FABRIC:
4119 return 26; // "param_NV00F8_ALLOCATION_PARAMETERS"
4120
4121 case NVC9FA_VIDEO_OFA:
4122 case NVCDFA_VIDEO_OFA:
4123 case NVC6FA_VIDEO_OFA:
4124 case NVC7FA_VIDEO_OFA:
4125 case NVB8FA_VIDEO_OFA:
4126 return 27; // "param_NVC9FA_VIDEO_OFA"
4127
4128 case NV2081_BINAPI:
4129 case NV2082_BINAPI_PRIVILEGED:
4130 return 28; // "param_NV2081_ALLOC_PARAMETERS"
4131
4132 default:
4133 return UNION_UNKNOWN_FIELD_PRINT;
4134 }
4135 }
4136
4137
4138
4139
4140 // Union member index functions for NV2080_CTRL_FB_FS_INFO_QUERY_DATA
_get_union_member_index_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D(NvU32 cmd)4141 uint32_t _get_union_member_index_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D(NvU32 cmd)
4142 {
4143 switch (cmd)
4144 {
4145 case NV2080_CTRL_FB_FS_INFO_INVALID_QUERY:
4146 return 0; // "inv"
4147
4148 case NV2080_CTRL_FB_FS_INFO_FBP_MASK:
4149 return 1; // "fbp"
4150
4151 case NV2080_CTRL_FB_FS_INFO_LTC_MASK:
4152 return 2; // "ltc"
4153
4154 case NV2080_CTRL_FB_FS_INFO_LTS_MASK:
4155 return 3; // "lts"
4156
4157 case NV2080_CTRL_FB_FS_INFO_FBPA_MASK:
4158 return 4; // "fbpa"
4159
4160 case NV2080_CTRL_FB_FS_INFO_ROP_MASK:
4161 return 5; // "rop"
4162
4163 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK:
4164 return 6; // "dmLtc"
4165
4166 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK:
4167 return 7; // "dmLts"
4168
4169 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK:
4170 return 8; // "dmFbpa"
4171
4172 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK:
4173 return 9; // "dmRop"
4174
4175 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK:
4176 return 10; // "dmFbpaSubp"
4177
4178 case NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK:
4179 return 11; // "fbpaSubp"
4180
4181 case NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP:
4182 return 12; // "fbpLogicalMap"
4183
4184 default:
4185 return UNION_UNKNOWN_FIELD_PRINT;
4186 }
4187 }
4188
_get_union_member_index_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04(NvU32 cmd)4189 uint32_t _get_union_member_index_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04(NvU32 cmd)
4190 {
4191 switch (cmd)
4192 {
4193 case NV2080_CTRL_FB_FS_INFO_INVALID_QUERY:
4194 return 0; // "inv"
4195
4196 case NV2080_CTRL_FB_FS_INFO_FBP_MASK:
4197 return 1; // "fbp"
4198
4199 case NV2080_CTRL_FB_FS_INFO_LTC_MASK:
4200 return 2; // "ltc"
4201
4202 case NV2080_CTRL_FB_FS_INFO_LTS_MASK:
4203 return 3; // "lts"
4204
4205 case NV2080_CTRL_FB_FS_INFO_FBPA_MASK:
4206 return 4; // "fbpa"
4207
4208 case NV2080_CTRL_FB_FS_INFO_ROP_MASK:
4209 return 5; // "rop"
4210
4211 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK:
4212 return 6; // "dmLtc"
4213
4214 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK:
4215 return 7; // "dmLts"
4216
4217 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK:
4218 return 8; // "dmFbpa"
4219
4220 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK:
4221 return 9; // "dmRop"
4222
4223 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK:
4224 return 10; // "dmFbpaSubp"
4225
4226 case NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK:
4227 return 11; // "fbpaSubp"
4228
4229 case NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP:
4230 return 12; // "fbpLogicalMap"
4231
4232 case NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK:
4233 return 13; // "sysl2Ltc"
4234
4235 case NV2080_CTRL_FB_FS_INFO_PAC_MASK:
4236 return 14; // "pac"
4237
4238 case NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK:
4239 return 15; // "logicalLtc"
4240
4241 case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK:
4242 return 16; // "dmLogicalLtc"
4243
4244 default:
4245 return UNION_UNKNOWN_FIELD_PRINT;
4246 }
4247 }
4248
4249
4250
4251
4252 // Union member index functions for NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA
_get_union_member_index_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D(NvU32 cmd)4253 uint32_t _get_union_member_index_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D(NvU32 cmd)
4254 {
4255 switch (cmd)
4256 {
4257 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT:
4258 return 0; // "gpcCountData"
4259
4260 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP:
4261 return 1; // "chipletGpcMapData"
4262
4263 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK:
4264 return 2; // "tpcMaskData"
4265
4266 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK:
4267 return 3; // "ppcMaskData"
4268
4269 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP:
4270 return 4; // "partitionGpcMapData"
4271
4272 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK:
4273 return 5; // "syspipeMaskData"
4274
4275 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS:
4276 return 6; // "partitionChipletSyspipeData"
4277
4278 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK:
4279 return 7; // "dmGpcMaskData"
4280
4281 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID:
4282 return 8; // "partitionSyspipeIdData"
4283
4284 case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK:
4285 return 9; // "ropMaskData"
4286
4287 default:
4288 return UNION_UNKNOWN_FIELD_PRINT;
4289 }
4290 }
4291
4292
4293
4294
4295 // Union member index functions for NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type
_get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04(NvU32 cmd)4296 uint32_t _get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04(NvU32 cmd)
4297 {
4298 switch (cmd)
4299 {
4300 case NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI:
4301 return 0; // "smbpbi"
4302
4303 default:
4304 return UNION_UNKNOWN_FIELD_PRINT;
4305 }
4306 }
4307
4308
4309
4310
4311
4312 #endif
4313
4314 #ifdef SDK_UNION_MEMBER_NAME_FUNCTIONS_CMD
get_union_member_index_NV5080_CTRL_DEFERRED_API_V2_PARAMS_v06_00_api_bundle(void * msg,NvS32 bytes_remaining,uint32_t * index)4315 static NV_STATUS get_union_member_index_NV5080_CTRL_DEFERRED_API_V2_PARAMS_v06_00_api_bundle(void *msg, NvS32 bytes_remaining, uint32_t* index)
4316 {
4317 NV5080_CTRL_DEFERRED_API_V2_PARAMS_v06_00 *param = msg;
4318
4319 if ((NvS32)(NV_OFFSETOF(NV5080_CTRL_DEFERRED_API_V2_PARAMS_v06_00, cmd) + sizeof(param->cmd)) > bytes_remaining)
4320 return NV_ERR_BUFFER_TOO_SMALL;
4321 *index = _get_union_member_index_NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v06_00(param->cmd);
4322 return NV_OK;
4323 }
get_union_member_index_NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D_queryParams(void * msg,NvS32 bytes_remaining,uint32_t * index)4324 static NV_STATUS get_union_member_index_NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D_queryParams(void *msg, NvS32 bytes_remaining, uint32_t* index)
4325 {
4326 NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D *param = msg;
4327
4328 if ((NvS32)(NV_OFFSETOF(NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D, queryType) + sizeof(param->queryType)) > bytes_remaining)
4329 return NV_ERR_BUFFER_TOO_SMALL;
4330 *index = _get_union_member_index_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D(param->queryType);
4331 return NV_OK;
4332 }
get_union_member_index_NV2080_CTRL_FB_FS_INFO_QUERY_v26_04_queryParams(void * msg,NvS32 bytes_remaining,uint32_t * index)4333 static NV_STATUS get_union_member_index_NV2080_CTRL_FB_FS_INFO_QUERY_v26_04_queryParams(void *msg, NvS32 bytes_remaining, uint32_t* index)
4334 {
4335 NV2080_CTRL_FB_FS_INFO_QUERY_v26_04 *param = msg;
4336
4337 if ((NvS32)(NV_OFFSETOF(NV2080_CTRL_FB_FS_INFO_QUERY_v26_04, queryType) + sizeof(param->queryType)) > bytes_remaining)
4338 return NV_ERR_BUFFER_TOO_SMALL;
4339 *index = _get_union_member_index_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04(param->queryType);
4340 return NV_OK;
4341 }
get_union_member_index_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D_queryData(void * msg,NvS32 bytes_remaining,uint32_t * index)4342 static NV_STATUS get_union_member_index_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D_queryData(void *msg, NvS32 bytes_remaining, uint32_t* index)
4343 {
4344 NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D *param = msg;
4345
4346 if ((NvS32)(NV_OFFSETOF(NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D, queryType) + sizeof(param->queryType)) > bytes_remaining)
4347 return NV_ERR_BUFFER_TOO_SMALL;
4348 *index = _get_union_member_index_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D(param->queryType);
4349 return NV_OK;
4350 }
get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04_data(void * msg,NvS32 bytes_remaining,uint32_t * index)4351 static NV_STATUS get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04_data(void *msg, NvS32 bytes_remaining, uint32_t* index)
4352 {
4353 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 *param = msg;
4354
4355 if ((NvS32)(NV_OFFSETOF(NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04, type) + sizeof(param->type)) > bytes_remaining)
4356 return NV_ERR_BUFFER_TOO_SMALL;
4357 *index = _get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04(param->type);
4358 return NV_OK;
4359 }
4360
4361 #endif
4362
4363 #ifdef SDK_ARRAY_LENGTH_FUNCTIONS
4364
4365 // Array length functions for gpu_exec_reg_ops:
get_array_length_gpu_exec_reg_ops_v12_01_operations(void * msg,NvS32 bytes_remaining,uint32_t * length)4366 static NV_STATUS get_array_length_gpu_exec_reg_ops_v12_01_operations(void *msg, NvS32 bytes_remaining, uint32_t* length)
4367 {
4368 gpu_exec_reg_ops_v12_01 *param = msg;
4369
4370 if ((NvS32)(NV_OFFSETOF(gpu_exec_reg_ops_v12_01, reg_op_params.regOpCount) + sizeof(param->reg_op_params.regOpCount)) > bytes_remaining)
4371 return NV_ERR_BUFFER_TOO_SMALL;
4372 *length = param->reg_op_params.regOpCount;
4373 return NV_OK;
4374 }
4375
4376 // Array length functions for NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS:
get_array_length_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06_smErrorStateArray(void * msg,NvS32 bytes_remaining,uint32_t * length)4377 static NV_STATUS get_array_length_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06_smErrorStateArray(void *msg, NvS32 bytes_remaining, uint32_t* length)
4378 {
4379 NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06 *param = msg;
4380
4381 if ((NvS32)(NV_OFFSETOF(NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06, numSMsToRead) + sizeof(param->numSMsToRead)) > bytes_remaining)
4382 return NV_ERR_BUFFER_TOO_SMALL;
4383 *length = param->numSMsToRead;
4384 return NV_OK;
4385 }
4386
4387 // Array length functions for NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS:
get_array_length_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v15_04_blackList(void * msg,NvS32 bytes_remaining,uint32_t * length)4388 static NV_STATUS get_array_length_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v15_04_blackList(void *msg, NvS32 bytes_remaining, uint32_t* length)
4389 {
4390 NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v15_04 *param = msg;
4391
4392 if ((NvS32)(NV_OFFSETOF(NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v15_04, validEntries) + sizeof(param->validEntries)) > bytes_remaining)
4393 return NV_ERR_BUFFER_TOO_SMALL;
4394 *length = param->validEntries;
4395 return NV_OK;
4396 }
4397
4398 #endif
4399
4400