1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: class/cla0bc.finn 31 // 32 33 #define NVENC_SW_SESSION (0xa0bcU) /* finn: Evaluated from "NVA0BC_ALLOC_PARAMETERS_MESSAGE_ID" */ 34 35 /* 36 * NVENC_SESSION_INFO_REGION_MAX_COUNT_V1 37 * Number of regions. 38 * Currently we have two regions. 39 * +---------+ <== Region 1 Start 40 * | Entry 1 | 41 * | Entry 2 | 42 * | ... | 43 * | Entry N | 44 * +---------+ <== Region 1 End, Region 2 Start. 45 * | Entry 1 | 46 * | Entry 2 | 47 * | ... | 48 * | Entry N | 49 * +---------+ <== Region 2 End 50 * Region 1 : Contains GPU timestamp of each frame when frame was submitted 51 * to encode by UMD. 52 * Region 2 : Two entries in this region for each frame. Start and end GPU 53 * timestamps of when GPU started and ended encoding a frame. 54 */ 55 #define NVENC_SESSION_INFO_REGION_MAX_COUNT_V1 2 56 57 /* 58 * NVENC_SESSION_INFO_ENTRY_V1 59 * This structure represents a single timestamp entry for a frame. 60 * frameId 61 * Frame id of the frame being submitted for encoding by UMD. 62 * reserved 63 * This is a reserved field. Unused. 64 * timestamp 65 * GPU timestamp. 66 */ 67 68 typedef struct NVENC_SESSION_INFO_ENTRY_V1 { 69 NvU32 frameId; 70 NvU32 reserved; 71 NV_DECLARE_ALIGNED(NvU64 timestamp, 8); 72 } NVENC_SESSION_INFO_ENTRY_V1; 73 74 /* 75 * NVENC_SESSION_INFO_REGION_1_ENTRY_V1 76 * This structure represents an entry in Region 1. 77 * submissionTSEntry 78 * Frame id and GPU timestamp of the time when the frame was submitted to 79 * encode by UMD. 80 * 81 * NVENC_SESSION_INFO_REGION_1_ENTRY_SIZE_V1 82 * Size of each entry in region 1. 83 * 84 * NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1 85 * No of entries in region 1. 86 * 87 * NVENC_SESSION_INFO_REGION_1_V1 88 * This structure represents Region 1. 89 * 90 * NVENC_SESSION_INFO_REGION_1_SIZE_V1 91 * Size of region 1. 92 * 93 * NVENC_SESSION_INFO_REGION_1_OFFSET_V1 94 * First region, so offset is 0. 95 */ 96 97 typedef struct NVENC_SESSION_INFO_REGION_1_ENTRY_V1 { 98 NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_ENTRY_V1 submissionTSEntry, 8); 99 } NVENC_SESSION_INFO_REGION_1_ENTRY_V1; 100 101 #define NVENC_SESSION_INFO_REGION_1_ENTRY_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_1_ENTRY_V1) 102 103 #define NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1 256 104 105 typedef struct NVENC_SESSION_INFO_REGION_1_V1 { 106 NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_1_ENTRY_V1 frameInfo[NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1], 8); 107 } NVENC_SESSION_INFO_REGION_1_V1; 108 109 #define NVENC_SESSION_INFO_REGION_1_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_1_V1) 110 111 #define NVENC_SESSION_INFO_REGION_1_OFFSET_V1 0 112 113 /* 114 * NVENC_SESSION_INFO_REGION_2_ENTRY_V1 115 * This structure represents a complete entry in Region 2. 116 * startTSEntry 117 * Frame id and GPU timestamp of the time when frame encoding started. 118 * endTSEntry 119 * Frame id and GPU timestamp of the time when frame encoding ended. 120 * 121 * NVENC_SESSION_INFO_REGION_2_ENTRY_SIZE_V1 122 * Size of each entry in region 2. 123 * 124 * NVENC_SESSION_INFO_REGION_2_MAX_ENTRIES_COUNT_V1 125 * No of entries in region 2. 126 * 127 * NVENC_SESSION_INFO_REGION_2_V1 128 * This structure represents Region 2. 129 * 130 * NVENC_SESSION_INFO_REGION_2_SIZE_V1 131 * Size of region 2. 132 * 133 * NVENC_SESSION_INFO_REGION_2_OFFSET_V1 134 * Offset of region 2 from base. 135 */ 136 137 typedef struct NVENC_SESSION_INFO_REGION_2_ENTRY_V1 { 138 NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_ENTRY_V1 startTSEntry, 8); 139 NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_ENTRY_V1 endTSEntry, 8); 140 } NVENC_SESSION_INFO_REGION_2_ENTRY_V1; 141 142 #define NVENC_SESSION_INFO_REGION_2_ENTRY_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_2_ENTRY_V1) 143 144 #define NVENC_SESSION_INFO_REGION_2_MAX_ENTRIES_COUNT_V1 NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1 145 146 typedef struct NVENC_SESSION_INFO_REGION_2_V1 { 147 NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_2_ENTRY_V1 frameInfo[NVENC_SESSION_INFO_REGION_2_MAX_ENTRIES_COUNT_V1], 8); 148 } NVENC_SESSION_INFO_REGION_2_V1; 149 150 #define NVENC_SESSION_INFO_REGION_2_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_2_V1) 151 152 #define NVENC_SESSION_INFO_REGION_2_OFFSET_V1 (NVENC_SESSION_INFO_REGION_1_OFFSET_V1 + \ 153 NVENC_SESSION_INFO_REGION_1_SIZE_V1) 154 155 /* 156 * NVENC_SESSION_INFO_V1 157 * This structure represents the complete memory allocated to store the per 158 * frame submission-start-end timestamps data. 159 * 160 * NVENC_SESSION_INFO_SIZE_V1 161 * Size of complete memory. 162 */ 163 164 typedef struct NVENC_SESSION_INFO_V1 { 165 NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_1_V1 region1, 8); 166 NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_2_V1 region2, 8); 167 } NVENC_SESSION_INFO_V1; 168 169 #define NVENC_SESSION_INFO_SIZE_V1 sizeof(NVENC_SESSION_INFO_V1) 170 171 /* 172 * NVA0BC_ALLOC_PARAMETERS 173 * 174 * This structure represents NVENC SW session allocation parameters. 175 * 176 * codecType 177 * Codec type to be used to do the encoding. 178 * hResolution 179 * Width of frames to be encoded. 180 * vResolution 181 * Height of frames to be encoded. 182 * version 183 * Adding version to handle any future changes to struct. 184 * In future we can extend this struct to notify RM that UMD needs to send 185 * other data. Versioning will help in identifying the difference in structs. 186 * Values are defined by NVA0BC_ALLOC_PARAMS_VER_xxx. 187 * hMem 188 * Handle to the system memory allocated by UMD. 189 * RM needs to access the memory to get the raw timestamp data and process it. 190 */ 191 192 #define NVA0BC_ALLOC_PARAMETERS_MESSAGE_ID (0xa0bcU) 193 194 typedef struct NVA0BC_ALLOC_PARAMETERS { 195 NvU32 codecType; 196 NvU32 hResolution; 197 NvU32 vResolution; 198 199 NvU32 version; 200 NvHandle hMem; 201 } NVA0BC_ALLOC_PARAMETERS; 202 203 #define NVA0BC_ALLOC_PARAMS_VER_0 0x00000000 204 #define NVA0BC_ALLOC_PARAMS_VER_1 0x00000001 205 206 #define NVA0BC_NVENC_SESSION_CODEC_TYPE_H264 0x000000 207 #define NVA0BC_NVENC_SESSION_CODEC_TYPE_HEVC 0x000001 208 #define NVA0BC_NVENC_SESSION_CODEC_TYPE_AV1 0x000002 209 #define NVA0BC_NVENC_SESSION_CODEC_TYPE_UNKNOWN 0x0000FF 210