1 /*
2 * SPDX-FileCopyrightText: Copyright (c) 2010-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef __NVKMS_TYPES_H__
25 #define __NVKMS_TYPES_H__
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 #include "nvidia-modeset-os-interface.h"
32
33 #include "nvctassert.h"
34 #include "nv_list.h"
35
36 #include <ctrl/ctrl0073/ctrl0073specific.h> /* NV0073_CTRL_SPECIFIC_OR_PROTOCOL_* */
37 #include <ctrl/ctrl0073/ctrl0073system.h> /* NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE */
38 #include <ctrl/ctrl0000/ctrl0000gpu.h> /* NV0000_CTRL_GPU_MAX_ATTACHED_GPUS */
39 #include <ctrl/ctrl0080/ctrl0080unix.h> /* NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO */
40 #include <ctrl/ctrl2080/ctrl2080gpu.h> /* NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_* */
41 #include <ctrl/ctrl30f1.h> /* NV30F1_CTRL_MAX_GPUS_PER_GSYNC */
42 #include <ctrl/ctrl5070/ctrl5070system.h> /* NV5070_CTRL_SYSTEM_CAPS_TBL_SIZE */
43 #include <ctrl/ctrl0073/ctrl0073dfp.h>
44
45 #include "nvkms-api.h"
46 #include "nvkms-prealloc-types.h"
47
48 #include "nvos.h"
49
50 #include "nv_common_utils.h"
51 #include "nv_assert.h"
52 #include "unix_rm_handle.h"
53
54 #include "nvmisc.h"
55
56 #include "nvidia-push-init.h"
57
58 #include "timing/nvtiming.h"
59 #include "timing/nvt_dsc_pps.h"
60 #include "hdmipacket/nvhdmi_frlInterface.h" // HDMI_{SRC,SINK}_CAPS
61
62 #include <stddef.h>
63
64 #if defined(DEBUG) || defined(DEVELOP)
65 #define NVKMS_PROCFS_ENABLE 1
66 #else
67 #define NVKMS_PROCFS_ENABLE 0
68 #endif
69
70 #define NV_DMA_EVO_PUSH_BUFFER_SIZE (4 * 1024)
71 #define NV_DMA_EVO_PUSH_BUFFER_PAD_SIZE (4 * 12)
72 #define NV_DMA_EVO_NOTIFIER_SIZE 4096
73
74 #define NV_NUM_EVO_LUT_ENTRIES 1025
75 /*
76 * Size of the nvdisplay 3 LUT variable segment size header, in LUT entries
77 * (which are 8 bytes each).
78 */
79 #define NV_LUT_VSS_HEADER_SIZE 4
80
81 #define NV_EVO_SUBDEV_STACK_SIZE 10
82
83 #define NV_DP_READ_EDID_RETRIES 18
84 #define NV_DP_REREAD_EDID_DELAY_USEC 500 /* in microseconds */
85
86 #define NV_EVO_SURFACE_ALIGNMENT 0x1000
87
88 /*
89 * Prior to nvdisplay 4.0, the final address for all scanout surfaces must be
90 * 256B-aligned.
91 *
92 * For nvdisplay 4.0, the final address for all scanout surfaces must be
93 * 512B-aligned for GPU, and 1KB-aligned for Tegra.
94 *
95 * NVKMS already uses NV_EVO_SURFACE_ALIGNMENT to force 4KB-alignment for the
96 * base address of each scanout surface. As such, we're forcing 1KB-alignment
97 * for the corresponding ctxdma offsets in order to be compatible with all
98 * display architectures.
99 */
100 #define NV_SURFACE_OFFSET_ALIGNMENT_SHIFT 10
101
102 #define NVKMS_BLOCK_LINEAR_LOG_GOB_WIDTH 6U /* 64 bytes (2^6) */
103 #define NVKMS_BLOCK_LINEAR_GOB_WIDTH ((NvU32)1 << NVKMS_BLOCK_LINEAR_LOG_GOB_WIDTH)
104
105 #define NVKMS_BLOCK_LINEAR_LOG_GOB_HEIGHT 3U /* 8 rows (2^3) */
106 #define NVKMS_BLOCK_LINEAR_GOB_HEIGHT ((NvU32)1 << NVKMS_BLOCK_LINEAR_LOG_GOB_HEIGHT)
107
108 #define NV_INVALID_OR 0xFFFFFFFF
109
110 #define NVKMS_RM_HEAP_ID 0xDCBA
111
112 #define NVKMS_MAX_WINDOWS_PER_DISP 32
113
114 #define NV_SYNCPT_GLOBAL_TABLE_LENGTH 1024
115
116 #define HEAD_MASK_QUERY(_mask, _head) (!!((_mask) & (1 << (_head))))
117 #define HEAD_MASK_SET(_mask, _head) ((_mask) | (1 << (_head)))
118 #define HEAD_MASK_UNSET(_mask, _head) ((_mask) & ~(1 << (_head)))
119
120 #define NVKMS_COMPOSITION_FOR_MATCH_BITS(__colorKeySelect, __match) \
121 for ((__match) = (((__colorKeySelect) == \
122 NVKMS_COMPOSITION_COLOR_KEY_SELECT_DISABLE) ? 1 : 0); \
123 (__match) <= 1; (__match)++)
124
125 typedef struct _NVEvoApiHandlesRec *NVEvoApiHandlesPtr;
126 typedef struct _NVEvoSubDeviceRec *NVSubDeviceEvoPtr;
127 typedef struct _NVEvoDevRec *NVDevEvoPtr;
128 typedef struct _NVDIFRStateEvoRec *NVDIFRStateEvoPtr;
129 typedef struct _NVDmaBufferEvoRec *NVDmaBufferEvoPtr;
130 typedef struct _NVEvoChannel *NVEvoChannelPtr;
131 typedef struct _NVEvoHeadControl *NVEvoHeadControlPtr;
132 typedef struct _NVEvoCapabilities *NVEvoCapabilitiesPtr;
133 typedef struct _NVEvoSubDevHeadStateRec *NVEvoSubDevHeadStatePtr;
134 typedef struct _NVEvoSubDevRec *NVEvoSubDevPtr;
135 typedef struct _NVEvoColorRec *NVEvoColorPtr;
136 typedef struct _NVHwModeViewPortEvo *NVHwModeViewPortEvoPtr;
137 typedef struct _NVHwModeTimingsEvo *NVHwModeTimingsEvoPtr;
138 typedef struct _NVConnectorEvoRec *NVConnectorEvoPtr;
139 typedef struct _NVVblankSyncObjectRec *NVVblankSyncObjectPtr;
140 typedef struct _NVDispHeadStateEvoRec *NVDispHeadStateEvoPtr;
141 typedef struct _NVDispEvoRec *NVDispEvoPtr;
142 typedef struct _NVParsedEdidEvoRec *NVParsedEdidEvoPtr;
143 typedef struct _NVVBlankCallbackRec *NVVBlankCallbackPtr;
144 typedef struct _NVRgLine1CallbackRec *NVRgLine1CallbackPtr;
145 typedef struct _NVDpyEvoRec *NVDpyEvoPtr;
146 typedef struct _NVLutSurfaceEvo *NVLutSurfaceEvoPtr;
147 typedef struct _NVFrameLockEvo *NVFrameLockEvoPtr;
148 typedef struct _NVEvoInfoString *NVEvoInfoStringPtr;
149 typedef struct _NVSurfaceEvoRec NVSurfaceEvoRec, *NVSurfaceEvoPtr;
150 typedef struct _NVDeferredRequestFifoRec *NVDeferredRequestFifoPtr;
151 typedef struct _NVSwapGroupRec *NVSwapGroupPtr;
152 typedef struct _NVEvoModesetUpdateState NVEvoModesetUpdateState;
153 typedef struct _NVLockGroup NVLockGroup;
154 typedef struct _NVVblankSemControl *NVVblankSemControlPtr;
155
156 /*
157 * _NVHs*EvoRec are defined in nvkms-headsurface-priv.h; they are intentionally
158 * opaque outside of the nvkms-headsurface code.
159 */
160 typedef struct _NVHsDeviceEvoRec *NVHsDeviceEvoPtr;
161 typedef struct _NVHsChannelEvoRec *NVHsChannelEvoPtr;
162 typedef struct _NVHsSurfaceRec *NVHsSurfacePtr;
163
164 /* _nv_dplibXXX are defined in dp/nvdp-connector-event-sink.h */
165 typedef struct _nv_dplibconnector NVDPLibConnectorRec, *NVDPLibConnectorPtr;
166 typedef struct _nv_dplibdevice NVDPLibDeviceRec, *NVDPLibDevicePtr;
167 typedef struct __nv_dplibmodesetstate NVDPLibModesetStateRec, *NVDPLibModesetStatePtr;
168
169 /* _nv_dplibtimer is defined in nvdp-timer.hpp */
170 typedef struct _nv_dplibtimer NVDPLibTimerRec, *NVDPLibTimerPtr;
171
172 typedef struct _NVEvoApiHandlesRec {
173 void **pointers; /* Dynamically allocated array of pointers. */
174 NvU32 numPointers; /* Number of elements in pointers array. */
175 NvU32 defaultSize;
176 } NVEvoApiHandlesRec;
177
178 typedef struct _NVSurfaceDescriptor
179 {
180 NvU32 ctxDmaHandle;
181 NvU64 iovaAddress;
182 } NVSurfaceDescriptor;
183
184 typedef struct _NVEvoDma
185 {
186 NvU32 memoryHandle;
187 NVSurfaceDescriptor surfaceDesc;
188
189 NvU64 limit;
190
191 /* Whether this is sysmem, or vidmem accessed through a BAR1 mapping. */
192 NvBool isBar1Mapping;
193
194 struct {
195 NvU8 vrrNotifierNextSlot;
196 } vrrNotifierHead[NV_MAX_HEADS];
197
198 void *subDeviceAddress[NVKMS_MAX_SUBDEVICES];
199 } NVEvoDma, *NVEvoDmaPtr;
200
201 typedef struct _NVDmaBufferEvoRec
202 {
203 NVEvoDma dma;
204
205 NvU32 channel_handle; // handles
206 NvU32 num_channels;
207 void *control[NVKMS_MAX_SUBDEVICES];
208 NvU32 *base; // Push buffer start pointer
209 NvU32 *buffer;// Push buffer current pointer
210 NvU32 *end; // Push buffer end pointer
211 NvU32 offset_max; // Push buffer max offset (in bytes)
212 NvU32 put_offset; // Push buffer last kicked off offset
213 NvU32 fifo_free_count; // fifo free space (in words)
214 NvU32 currentSubDevMask;
215 NVDevEvoPtr pDevEvo;
216 } NVDmaBufferEvoRec;
217
218 /* EVO capabilities */
219 typedef struct {
220 NvBool flipLock;
221 NvBool stereo;
222 NvBool scanLock;
223 } NVEvoLockPinCaps;
224 #define NV_EVO_NUM_LOCK_PIN_CAPS 16
225
226 typedef struct {
227 NvBool supportsInterlaced;
228 NvBool supportsSemiPlanar;
229 NvBool supportsPlanar;
230 NvBool supportsHVFlip;
231 NvBool supportsDSI;
232 } NVEvoMiscCaps;
233
NVEvoScalerTapsToNum(NVEvoScalerTaps taps)234 static inline NvU8 NVEvoScalerTapsToNum(NVEvoScalerTaps taps)
235 {
236 NvU8 numTaps = 1;
237
238 switch (taps) {
239 case NV_EVO_SCALER_8TAPS:
240 numTaps = 8;
241 break;
242 case NV_EVO_SCALER_5TAPS:
243 numTaps = 5;
244 break;
245 case NV_EVO_SCALER_3TAPS:
246 numTaps = 3;
247 break;
248 case NV_EVO_SCALER_2TAPS:
249 numTaps = 2;
250 break;
251 case NV_EVO_SCALER_1TAP:
252 numTaps = 1;
253 break;
254 }
255
256 return numTaps;
257 }
258
259 #define NV_EVO_SCALE_FACTOR_1X (1 << 10)
260 #define NV_EVO_SCALE_FACTOR_2X (2 << 10)
261 #define NV_EVO_SCALE_FACTOR_3X (3 << 10)
262 #define NV_EVO_SCALE_FACTOR_4X (4 << 10)
263
264 typedef struct {
265 NvU32 maxPixelsVTaps;
266 NvU16 maxVDownscaleFactor; /* Scaled by 1024 */
267 NvU16 maxHDownscaleFactor; /* Scaled by 1024 */
268 } NVEvoScalerTapsCaps;
269
270 typedef struct {
271 NvBool present;
272 NVEvoScalerTapsCaps taps[NV_EVO_SCALER_TAPS_MAX + 1];
273 } NVEvoScalerCaps;
274
275 typedef struct {
276 NvBool usable;
277 NvU32 maxPClkKHz;
278 NvBool supportsHDMIYUV420HW;
279 NVEvoScalerCaps scalerCaps;
280 } NVEvoHeadCaps;
281 #define NV_EVO_NUM_HEAD_CAPS 8
282
283 typedef struct {
284 NvBool dualTMDS;
285 NvU32 maxTMDSClkKHz;
286 } NVEvoSorCaps;
287 #define NV_EVO_NUM_SOR_CAPS 8
288
289 typedef struct {
290 NvBool usable;
291 NvBool csc0MatricesPresent;
292 NvBool cscLUTsPresent;
293 NvBool csc1MatricesPresent;
294 NvBool tmoPresent;
295 NVEvoScalerCaps scalerCaps;
296 } NVEvoWindowCaps;
297 #define NV_EVO_NUM_WINDOW_CAPS 32
298
299 typedef NvU64 NVEvoChannelMask;
300
301 #define NV_EVO_CHANNEL_MASK_CORE 0:0
302 #define NV_EVO_CHANNEL_MASK_CORE_ENABLE 1
303 #define NV_EVO_CHANNEL_MASK_CORE_DISABLE 0
304 #define NV_EVO_CHANNEL_MASK_WINDOW_FIELD 32:1
305 #define NV_EVO_CHANNEL_MASK_WINDOW(_n) (1+(_n)):(1+(_n))
306 #define NV_EVO_CHANNEL_MASK_WINDOW__SIZE 32
307 #define NV_EVO_CHANNEL_MASK_WINDOW_ENABLE 1
308 #define NV_EVO_CHANNEL_MASK_WINDOW_DISABLE 0
309 #define NV_EVO_CHANNEL_MASK_CURSOR_FIELD 40:33
310 #define NV_EVO_CHANNEL_MASK_CURSOR(_n) (33+(_n)):(33+(_n))
311 #define NV_EVO_CHANNEL_MASK_CURSOR__SIZE 8
312 #define NV_EVO_CHANNEL_MASK_CURSOR_ENABLE 1
313 #define NV_EVO_CHANNEL_MASK_CURSOR_DISABLE 0
314 #define NV_EVO_CHANNEL_MASK_BASE_FIELD 44:41
315 #define NV_EVO_CHANNEL_MASK_BASE(_n) (41+(_n)):(41+(_n))
316 #define NV_EVO_CHANNEL_MASK_BASE__SIZE 4
317 #define NV_EVO_CHANNEL_MASK_BASE_ENABLE 1
318 #define NV_EVO_CHANNEL_MASK_BASE_DISABLE 0
319 #define NV_EVO_CHANNEL_MASK_OVERLAY_FIELD 48:45
320 #define NV_EVO_CHANNEL_MASK_OVERLAY(_n) (45+(_n)):(45+(_n))
321 #define NV_EVO_CHANNEL_MASK_OVERLAY__SIZE 4
322 #define NV_EVO_CHANNEL_MASK_OVERLAY_ENABLE 1
323 #define NV_EVO_CHANNEL_MASK_OVERLAY_DISABLE 0
324 /* Window Immediate channels get only one bit. */
325 #define NV_EVO_CHANNEL_MASK_WINDOW_IMM 49:49
326 #define NV_EVO_CHANNEL_MASK_WINDOW_IMM_ENABLE 1
327 #define NV_EVO_CHANNEL_MASK_WINDOW_IMM_DISABLE 0
328
329 #define NV_EVO_CHANNEL_MASK_WINDOW_ALL \
330 DRF_SHIFTMASK64(NV_EVO_CHANNEL_MASK_WINDOW_FIELD)
331 #define NV_EVO_CHANNEL_MASK_CURSOR_ALL \
332 DRF_SHIFTMASK64(NV_EVO_CHANNEL_MASK_CURSOR_FIELD)
333 #define NV_EVO_CHANNEL_MASK_BASE_ALL \
334 DRF_SHIFTMASK64(NV_EVO_CHANNEL_MASK_BASE_FIELD)
335 #define NV_EVO_CHANNEL_MASK_OVERLAY_ALL \
336 DRF_SHIFTMASK64(NV_EVO_CHANNEL_MASK_OVERLAY_FIELD)
337
NV_EVO_CHANNEL_MASK_POPCOUNT(NvU64 mask)338 static inline NvU32 NV_EVO_CHANNEL_MASK_POPCOUNT(NvU64 mask)
339 {
340 // It's tempting to use __builtin_popcountll here, but that depends on
341 // intrinsics not available to nvkms in the kernel.
342 return nvPopCount64(mask);
343 }
344
NV_EVO_CHANNEL_MASK_BASE_HEAD_NUMBER(NvU64 mask)345 static inline NvU32 NV_EVO_CHANNEL_MASK_BASE_HEAD_NUMBER(NvU64 mask)
346 {
347 nvAssert(NV_EVO_CHANNEL_MASK_POPCOUNT(mask) == 1);
348 return BIT_IDX_64(DRF_VAL64(_EVO, _CHANNEL_MASK, _BASE_FIELD, mask));
349 }
NV_EVO_CHANNEL_MASK_OVERLAY_HEAD_NUMBER(NvU64 mask)350 static inline NvU32 NV_EVO_CHANNEL_MASK_OVERLAY_HEAD_NUMBER(NvU64 mask)
351 {
352 nvAssert(NV_EVO_CHANNEL_MASK_POPCOUNT(mask) == 1);
353 return BIT_IDX_64(DRF_VAL64(_EVO, _CHANNEL_MASK, _OVERLAY_FIELD, mask));
354 }
NV_EVO_CHANNEL_MASK_WINDOW_NUMBER(NvU64 mask)355 static inline NvU32 NV_EVO_CHANNEL_MASK_WINDOW_NUMBER(NvU64 mask)
356 {
357 nvAssert(NV_EVO_CHANNEL_MASK_POPCOUNT(mask) == 1);
358 return BIT_IDX_64(DRF_VAL64(_EVO, _CHANNEL_MASK, _WINDOW_FIELD, mask));
359 }
360
361 /* EVO structures */
362
363 typedef struct {
364 struct {
365 NVEvoChannelMask channelMask;
366 NVEvoChannelMask noCoreInterlockMask;
367 /* Each channel in this mask was programmed with a "flip lock
368 * qualifying" flip. */
369 NVEvoChannelMask flipLockQualifyingMask;
370 /* Channels set here are transitioning from NULL ctxdma to non-NULL
371 * ctxdma or vice-versa on this update. Only necessary/valid on Turing
372 * (class C5*). */
373 NVEvoChannelMask flipTransitionWAR;
374
375 struct {
376 NvBool vrrTearing;
377 } base[NVKMS_MAX_HEADS_PER_DISP];
378
379 /*
380 * Window immediate channels with pending methods are represented
381 * here by NV_EVO_CHANNEL_MASK_WINDOW(n) for window immediate
382 * channel n.
383 */
384 NVEvoChannelMask winImmChannelMask;
385
386 /*
387 * Each window channel NV_EVO_CHANNEL_MASK_WINDOW(n) needs to
388 * be interlocked with its corresponding window immediate channel n.
389 */
390 NVEvoChannelMask winImmInterlockMask;
391
392 } subdev[NVKMS_MAX_SUBDEVICES];
393
394 } NVEvoUpdateState;
395
396 struct _NVEvoModesetUpdateState {
397 NVEvoUpdateState updateState;
398 NVDpyIdList connectorIds;
399 const NVDPLibModesetStateRec
400 *pDpLibModesetState[NVKMS_MAX_HEADS_PER_DISP];
401 NvBool windowMappingChanged;
402 struct {
403 struct _NVEvoModesetUpdateStateOneLayer {
404 struct nvkms_ref_ptr *ref_ptr;
405 NvBool changed;
406 } layer[NVKMS_MAX_LAYERS_PER_HEAD];
407 } flipOccurredEvent[NVKMS_MAX_HEADS_PER_DISP];
408 };
409
410 typedef struct {
411 struct {
412 NVEvoChannelMask channelMask;
413 } subdev[NVKMS_MAX_SUBDEVICES];
414 } NVEvoIdleChannelState;
415
416 typedef struct {
417 NvU8 validTimeStampBits;
418 NvBool tearingFlips :1;
419 NvBool vrrTearingFlips :1;
420 NvBool perEyeStereoFlips :1;
421 } NVEvoChannelCaps;
422
423 enum NVEvoImmChannel {
424 NV_EVO_IMM_CHANNEL_NONE,
425 NV_EVO_IMM_CHANNEL_PIO,
426 NV_EVO_IMM_CHANNEL_DMA,
427 };
428
429 typedef struct {
430 NvU32 handle;
431 void *control[NVKMS_MAX_SUBDEVICES];
432 } NVEvoPioChannel;
433
434 /*! basic syncpt structure used for pre and post syncpt usage */
435 typedef struct _NVEvoSyncpt {
436 /* syncpt is allocated */
437 NvBool allocated;
438 /*! syncpt id (only useful for post-syncpt) */
439 NvU32 id;
440 /*! bitmask of channels using this syncpt */
441 NVEvoChannelMask channelMask;
442 /*! Surface descriptor for the syncpt */
443 NVSurfaceDescriptor surfaceDesc;
444 /*! handle of syncpt object */
445 NvU32 hSyncpt;
446 /*! stores syncpt max value */
447 NvU32 syncptMaxVal;
448 } NVEvoSyncpt;
449
450 /* Tracks internal state of a vblank sync object. */
451 typedef struct _NVVblankSyncObjectRec {
452 /* Whether the vblank sync object is currently in use by some client. */
453 NvBool inUse;
454
455 /* Whether the vblank sync object is enabled or disabled. */
456 NvBool enabled;
457
458 /*
459 * The index of this Rec inside of the HeadState's vblankSyncObjects array.
460 * Also corresponds with the index of the sync object in hardware.
461 */
462 NvU32 index;
463
464 /*
465 * This syncpoint object should be created as part of
466 * nvRmSetupEvoCoreChannel().
467 */
468 NVEvoSyncpt evoSyncpt;
469 } NVVblankSyncObjectRec;
470
471 /* EVO channel, encompassing multiple subdevices and a single pushbuf */
472 typedef struct _NVEvoChannel {
473 /* Pointer to array of per subdev notifier dma structs */
474 NVEvoDmaPtr notifiersDma;
475
476 NvU32 hwclass;
477 NvU32 instance;
478 NVEvoChannelMask channelMask; /* only one bit should be set */
479
480 NVDmaBufferEvoRec pb;
481
482 NVOS10_EVENT_KERNEL_CALLBACK_EX completionNotifierEventCallback;
483 const struct nvkms_ref_ptr *completionNotifierEventRefPtr;
484 NvU32 completionNotifierEventHandle;
485
486 /*
487 * GV100 timestamped flips need a duplicate update which only changes
488 * TIMESTAMP_MODE and MIN_PRESENT_INTERVAL fields in SET_PRESENT_CONTROL;
489 * to allow updating these fields without changing anything else in
490 * SET_PRESENT_CONTROL, normal updates to SET_PRESENT_CONTROL are cached
491 * here. (bug 1990958)
492 */
493 NvU32 oldPresentControl;
494
495 // On Turing, RM wants to be notified when the tearing mode changes.
496 NvBool oldTearingMode;
497
498 struct {
499 enum NVEvoImmChannel type;
500 union {
501 NVEvoPioChannel *pio;
502 struct _NVEvoChannel *dma;
503 } u;
504 } imm;
505
506 NVEvoChannelCaps caps;
507
508 NVEvoSyncpt postSyncpt;
509
510 struct {
511 NvBool enabled;
512 NvU32 srcMaxLum;
513 NvU32 targetMaxLums[NVKMS_MAX_SUBDEVICES];
514 } tmoParams;
515 } NVEvoChannel;
516
517 typedef enum {
518 NV_EVO_NO_LOCK,
519 NV_EVO_FRAME_LOCK,
520 NV_EVO_RASTER_LOCK,
521 } NVEvoLockMode;
522
523 typedef enum {
524 NV_EVO_LOCK_PIN_ERROR = -1,
525 NV_EVO_LOCK_PIN_INTERNAL_0 = 0,
526 NV_EVO_LOCK_PIN_0 = 0x20,
527 } NVEvoLockPin;
528
529 typedef struct _NVEvoHeadControl {
530 NvBool interlaced;
531 NVEvoLockMode clientLock;
532 NVEvoLockPin clientLockPin;
533 int clientLockoutWindow;
534 NVEvoLockMode serverLock;
535 NVEvoLockPin serverLockPin;
536 NvBool flipLock;
537 NVEvoLockPin flipLockPin;
538 NVEvoLockPin stereoPin;
539
540 NvBool mergeMode;
541 NvBool setLockOffsetX;
542
543 NvU32 stallLockPin;
544 NvBool useStallLockPin;
545 NvBool crashLockUnstallMode;
546
547 /*
548 * Whether or not this GPU is stereo locked. True if all heads are either
549 * frame or raster locked, and all heads are driving non-interlaced modes.
550 */
551 NvBool stereoLocked;
552
553 /*
554 * Whether or not this head is driving a HDMI 3D frame packed mode. Used
555 * in headcontrol only on >=GV100.
556 */
557 NvBool hdmi3D;
558
559 /*
560 * Whether or not this head is driving a mode requiring the HW YUV420
561 * packer. Used in headcontrol only on >=nvdisplay 4.0.
562 */
563 NvBool hwYuv420;
564
565 /* This isn't actually part of HeadControl, but it's convenient */
566 NvU32 lockChainPosition;
567 } NVEvoHeadControl;
568
569 typedef struct _NVEvoCapabilities {
570 NVEvoLockPinCaps pin[NV_EVO_NUM_LOCK_PIN_CAPS];
571 NVEvoMiscCaps misc;
572 NVEvoHeadCaps head[NV_EVO_NUM_HEAD_CAPS];
573 NVEvoSorCaps sor[NV_EVO_NUM_SOR_CAPS];
574 NVEvoWindowCaps window[NV_EVO_NUM_WINDOW_CAPS];
575 } NVEvoCapabilities;
576
577 typedef struct {
578 NVSurfaceEvoPtr pSurfaceEvo;
579 enum NvKmsNIsoFormat format;
580 NvU16 offsetInWords;
581 } NVFlipNIsoSurfaceEvoHwState;
582
583 typedef struct {
584 NVFlipNIsoSurfaceEvoHwState surface;
585 NvBool awaken;
586 } NVFlipCompletionNotifierEvoHwState;
587
588 typedef struct {
589 NvBool usingSyncpt;
590 union {
591 struct {
592 NVFlipNIsoSurfaceEvoHwState acquireSurface;
593 NvU32 acquireValue;
594 NVFlipNIsoSurfaceEvoHwState releaseSurface;
595 NvU32 releaseValue;
596 } semaphores;
597 struct {
598 NvBool isPreSyncptSpecified;
599 NvU32 preSyncpt;
600 NvU32 preValue;
601
602 NvBool isPostSyncptSpecified;
603 NVSurfaceDescriptor surfaceDesc;
604 NvU32 postValue;
605 } syncpts;
606 } u;
607 } NVFlipSyncObjectEvoHwState;
608
609 typedef struct {
610 NVLutSurfaceEvoPtr pLutSurfaceEvo;
611 } NVFlipLutHwState;
612
613 typedef struct {
614 NVSurfaceEvoPtr pSurfaceEvo;
615 NvS16 x, y;
616
617 struct NvKmsCompositionParams cursorCompParams;
618 } NVFlipCursorEvoHwState;
619
620 typedef struct {
621 NVSurfaceEvoPtr pSurfaceEvo[NVKMS_MAX_EYES];
622 NVFlipCompletionNotifierEvoHwState completionNotifier;
623 NVFlipSyncObjectEvoHwState syncObject;
624
625 // Non-zero timeStamp value is only allowed if the channel's
626 // 'timeStampFlipBits' capability is > 0.
627 NvU64 timeStamp;
628 NvU8 minPresentInterval;
629 // True means immediate or tearing flip. False means flip-at-vblank.
630 NvBool tearing;
631 // The tearing mode passed to RM's VRR code via
632 // NV_VRR_TRAP_ARGUMENT_MAX_FPS_TEARING.
633 NvBool vrrTearing;
634 NvBool perEyeStereoFlip;
635
636 struct NvKmsSize sizeIn;
637 struct NvKmsSize sizeOut;
638 struct NvKmsSignedPoint outputPosition;
639
640 NVEvoScalerTaps hTaps;
641 NVEvoScalerTaps vTaps;
642
643 struct NvKmsCscMatrix cscMatrix;
644
645 NVFlipLutHwState inputLut;
646
647 struct NvKmsRRParams rrParams;
648
649 struct NvKmsCompositionParams composition;
650
651 NVFlipLutHwState tmoLut;
652 struct {
653 struct NvKmsHDRStaticMetadata val;
654 NvBool enabled;
655 } hdrStaticMetadata;
656
657 enum NvKmsInputColorSpace colorSpace;
658
659 enum NvKmsInputColorRange colorRange;
660
661 struct {
662 NvBool specified;
663
664 /*
665 * Maximum vertical downscale factor (scaled by 1024)
666 *
667 * For example, if the downscale factor is 1.5, then maxVDownscaleFactor
668 * would be 1.5 x 1024 = 1536.
669 */
670 NvU16 vertical;
671
672 /*
673 * Maximum horizontal downscale factor (scaled by 1024)
674 *
675 * See the example above for vertical.
676 */
677 NvU16 horizontal;
678 } maxDownscaleFactors;
679 } NVFlipChannelEvoHwState;
680
681 enum NvKmsDpyAttributeColorBpcValue {
682 NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_UNKNOWN = 0,
683 NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10 = 10,
684 NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8 = 8,
685 NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6 = 6,
686 };
687
688 typedef struct _NVColorFormatInfoRec {
689 struct {
690 enum NvKmsDpyAttributeColorBpcValue maxBpc;
691 } rgb444, yuv444, yuv422;
692 } NVColorFormatInfoRec;
693
694 typedef struct {
695 struct NvKmsPoint viewPortPointIn;
696 NVFlipCursorEvoHwState cursor;
697 NVFlipChannelEvoHwState layer[NVKMS_MAX_LAYERS_PER_HEAD];
698 struct NvKmsUsageBounds usage;
699 NvBool disableMidFrameAndDWCFWatermark;
700 enum NvKmsOutputTf tf;
701
702 struct {
703 NvBool enabled;
704 enum NvKmsInfoFrameEOTF eotf;
705 struct NvKmsHDRStaticMetadata staticMetadata;
706 } hdrInfoFrame;
707
708 enum NvKmsOutputColorimetry colorimetry;
709
710 NvBool skipLayerPendingFlips[NVKMS_MAX_LAYERS_PER_HEAD];
711
712 struct {
713 NvBool viewPortPointIn : 1;
714 NvBool cursorSurface : 1;
715 NvBool cursorPosition : 1;
716 NvBool tf : 1;
717 NvBool hdrStaticMetadata : 1;
718 NvBool colorimetry : 1;
719
720 NvBool layerPosition[NVKMS_MAX_LAYERS_PER_HEAD];
721 NvBool layerSyncObjects[NVKMS_MAX_LAYERS_PER_HEAD];
722 NvBool layer[NVKMS_MAX_LAYERS_PER_HEAD];
723 } dirty;
724 } NVFlipEvoHwState;
725
726 /*
727 * XXX Default to NVKMS_HDR_INFOFRAME_STATE_TRANSITIONING to send SDR
728 * infoframe for 2 seconds to WAR issue where some displays may remain in HDR
729 * mode after head has been previously shut down.
730 */
731 enum NvKmsHDRInfoFrameState {
732 NVKMS_HDR_INFOFRAME_STATE_TRANSITIONING = 0,
733 NVKMS_HDR_INFOFRAME_STATE_DISABLED = 1,
734 NVKMS_HDR_INFOFRAME_STATE_ENABLED = 2,
735 };
736
737 typedef struct _NVEvoSubDevHeadStateRec {
738 struct NvKmsPoint viewPortPointIn;
739 NVFlipCursorEvoHwState cursor;
740 NVFlipChannelEvoHwState layer[NVKMS_MAX_LAYERS_PER_HEAD];
741 // Current usage bounds programmed into the hardware.
742 struct NvKmsUsageBounds usage;
743 // Usage bounds required after the last scheduled flip completes.
744 struct NvKmsUsageBounds targetUsage;
745 // Preallocated usage bounds that will be required for upcoming flips.
746 struct NvKmsUsageBounds preallocatedUsage;
747
748 // Current state of MidFrameAndDWCFWatermark programmed into the hardware.
749 NvBool disableMidFrameAndDWCFWatermark;
750 //
751 // State of MidFrameAndDWCFWatermark required after the last scheduled
752 // flip completes.
753 //
754 NvBool targetDisableMidFrameAndDWCFWatermark;
755 } NVEvoSubDevHeadStateRec;
756
757 #define NVKMS_HEAD_SURFACE_MAX_BUFFERS 2
758
759 /*
760 * HeadSurface state that applies to a single head, but spans across
761 * all subdevices.
762 */
763 typedef struct {
764 /*
765 * The size of the headSurfaces for this head, across all subdevices.
766 * headSurface might only use a subset of the surfaces on one or more
767 * subdevices in SLI Mosaic.
768 */
769 struct NvKmsSize size;
770 struct NvKmsSize stagingSize;
771
772 /*
773 * The surfaces allocated for use by headSurface on this head.
774 * Surface allocations are broadcast across subdevices, though
775 * headSurface may unicast its rendering to the headSurface
776 * surface allocations on specific subdevices.
777 */
778 struct {
779 NVHsSurfacePtr pSurface;
780 NVHsSurfacePtr pStagingSurface;
781 } surfaces[NVKMS_MAX_EYES][NVKMS_HEAD_SURFACE_MAX_BUFFERS];
782
783 /*
784 * The number of surfaces in the NVKMS_HEAD_SURFACE_MAX_BUFFERS dimension of
785 * the surfaces[][] array. Elements [0,surfaceCount-1] in the surfaces[][]
786 * array will be populated.
787 */
788 NvU32 surfaceCount;
789 } NVHsStateOneHeadAllDisps;
790
791 /* Subdevice-specific, channel-independent state */
792 typedef struct _NVEvoSubDevRec {
793 NvU32 subDeviceInstance;
794
795 NVEvoCapabilities capabilities;
796
797 NVDispEvoPtr pDispEvo;
798
799 NvU32 setSwSpareA[NVKMS_MAX_HEADS_PER_DISP];
800
801 NVEvoSubDevHeadStateRec headState[NVKMS_MAX_HEADS_PER_DISP];
802 NVEvoHeadControl headControl[NVKMS_MAX_HEADS_PER_DISP];
803 NVEvoHeadControl headControlAssy[NVKMS_MAX_HEADS_PER_DISP];
804 void *cursorPio[NVKMS_MAX_HEADS_PER_DISP];
805 NvBool (*scanLockState)(NVDispEvoPtr pDispEvo,
806 NVEvoSubDevPtr pEvoSubDev,
807 NvU32 action,
808 /* NV_INVALID_HEAD-terminated
809 * array of head indices */
810 const NvU32 *pHeads);
811
812 /*
813 * EVO state machine refcounter for the number of SLI or proxy framelock
814 * clients that are connected to this server.
815 */
816 NvU32 frameLockSliProxyClients;
817
818 /*
819 * Since we add all active heads as framelock clients whenever we enable
820 * the second head as a framelock client, there's no need for EVO state
821 * transitions for heads 3 and more. Instead of those state transitions,
822 * we use the frameLockExtraClients ref counter to keep track of heads
823 * 3 and greater being added as framelock clients.
824 *
825 * XXX The state machine currently will naively framelock heads 3 and
826 * greater during this state transition, even if they're not capable
827 * of being framelocked (for example, when they have very different
828 * refresh rates). Bug 976532
829 */
830 NvU32 frameLockExtraClients;
831
832 /*
833 * All of the following except the "armed" versions are set by the EVO
834 * state machine to the desired HW configuration given the current locking
835 * state.
836 * The "armed" versions represent the current hardware configuration, used
837 * to avoid excess hardware updates.
838 */
839 NvU32 frameLockServerMaskArmed;
840 NvU32 frameLockServerMaskAssy;
841 NvU32 frameLockClientMaskArmed;
842 NvU32 frameLockClientMaskAssy;
843 NvU32 frameLockExtRefClkMaskArmed;
844 NvU32 frameLockExtRefClkMaskAssy;
845 NvBool frameLockHouseSync;
846
847 NvU8 flipLockPinSetForFrameLockHeadMask;
848 NvU8 flipLockEnabledForFrameLockHeadMask;
849 NvU8 flipLockPinSetForSliHeadMask;
850 NvU8 flipLockEnabledForSliHeadMask;
851
852 NvU32 flipLockProhibitedHeadMask;
853
854 NvU32 sliRasterLockServerMask;
855 NvU32 sliRasterLockClientMask;
856
857 NVEvoLockPin sliServerLockPin;
858 NVEvoLockPin sliClientLockPin;
859 } NVEvoSubDevRec;
860
861 typedef struct _NVEvoColorRec {
862 NvU16 red;
863 NvU16 green;
864 NvU16 blue;
865 } NVEvoColorRec;
866
867 typedef struct {
868 NvU16 Red;
869 NvU16 Green;
870 NvU16 Blue;
871 NvU16 Unused;
872 } NVEvoLutEntryRec;
873
874 typedef struct {
875 NVEvoLutEntryRec base[NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES];
876 // The output LUT requires 8-bit alignment.
877 NVEvoLutEntryRec output[NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES]
878 __attribute__((aligned(0x100)));
879 } NVEvoLutDataRec;
880
881 typedef struct {
882 NvBool supportsDP13 :1;
883 NvBool supportsHDMI20 :1;
884 NvBool inputLutAppliesToBase :1;
885 NvU8 validNIsoFormatMask;
886 NvU32 maxPitchValue;
887 int maxWidthInBytes;
888 int maxWidthInPixels;
889 int maxHeight;
890 NvU32 maxRasterWidth;
891 NvU32 maxRasterHeight;
892 struct NvKmsCompositionCapabilities cursorCompositionCaps;
893 NvU16 validLayerRRTransforms;
894 struct NvKmsLayerCapabilities layerCaps[NVKMS_MAX_LAYERS_PER_HEAD];
895 NvU8 legacyNotifierFormatSizeBytes[NVKMS_MAX_LAYERS_PER_HEAD];
896 NvU8 dpYCbCr422MaxBpc;
897 NvU8 hdmiYCbCr422MaxBpc;
898 } NVEvoCapsRec;
899
900 typedef struct {
901 NvU32 coreChannelClass;
902 size_t dmaArmedSize;
903 NvU32 dmaArmedOffset;
904 } NVEvoCoreChannelDmaRec;
905
906
907 typedef struct _NVEvoSubDeviceRec {
908 NvU32 handle;
909 NvU32 gpuId;
910 #define NV_INVALID_GPU_LOG_INDEX 0xFF
911 NvU8 gpuLogIndex;
912 char gpuString[NVKMS_GPU_STRING_SIZE];
913
914 NvU32 numEngines;
915 NvU32 *supportedEngines;
916
917 /* Core channel memory mapping for ARM values */
918 void *pCoreDma;
919
920 /* ISO ctxdma programmed by EVO2 hal, into the overlay channel */
921 NvU32 overlayContextDmaIso[NVKMS_MAX_HEADS_PER_DISP];
922 enum NvKmsSurfaceMemoryFormat overlaySurfFormat[NVKMS_MAX_HEADS_PER_DISP];
923
924 /* Per head surface programmed into the core channel */
925 const NVSurfaceEvoRec *pCoreChannelSurface[NVKMS_MAX_HEADS_PER_DISP];
926
927 /* EVO2 only, TRUE if a valid base surface passed to ->Flip() */
928 NvBool isBaseSurfSpecified[NVKMS_MAX_HEADS_PER_DISP];
929 enum NvKmsSurfaceMemoryFormat baseSurfFormat[NVKMS_MAX_HEADS_PER_DISP];
930
931 /* Composition parameters considered for hardware programming by EVO2 hal */
932 struct {
933 NvBool initialized;
934 enum NvKmsCompositionColorKeySelect colorKeySelect;
935 NVColorKey colorKey;
936 } baseComp[NVKMS_MAX_HEADS_PER_DISP], overlayComp[NVKMS_MAX_HEADS_PER_DISP];
937
938 } NVEvoSubDeviceRec;
939
940 enum NvKmsLUTState {
941 NvKmsLUTStateUninitialized = 0,
942 NvKmsLUTStateIdentity = 1,
943 NvKmsLUTStatePQ = 2,
944 };
945
946 /* Device-specific EVO state (subdevice- and channel-independent) */
947 typedef struct _NVEvoDevRec {
948
949 NvU8 gpuLogIndex;
950 NvU32 allocRefCnt; /* number of ALLOC_DEVICE calls */
951 NVListRec devListEntry;
952
953 /* array of gpuIds opened with nvkms_open_gpu() */
954 NvU32 openedGpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS];
955
956 NVUnixRmHandleAllocatorRec handleAllocator;
957 NvU32 deviceId;
958
959 NvU32 deviceHandle;
960 struct NvKmsPerOpenDev *pNvKmsOpenDev;
961
962 struct {
963 NvPushDeviceRec device;
964 NvU32 handlePool[NV_PUSH_DEVICE_HANDLE_POOL_NUM];
965 } nvPush;
966
967 /* SLI Info */
968 struct {
969 NvBool mosaic;
970 struct {
971 NvBool present :1;
972
973 /* Current hardware state */
974 NvBool powered :1;
975
976 /* Software state tracking needs from hardware */
977 NvBool powerNeededForRasterLock :1;
978 } bridge;
979 } sli;
980
981 NvU32 numHeads;
982 NvU32 numWindows; /* NVDisplay only. */
983
984 NvU32 displayHandle;
985
986
987 /*!
988 * modesetOwner points to the pOpenDev of the client that called
989 * NVKMS_IOCTL_GRAB_OWNERSHIP.
990 */
991 const struct NvKmsPerOpenDev *modesetOwner;
992
993 /*!
994 * Indicates whether modeset ownership is changed since
995 * last modeset.
996 */
997 NvBool modesetOwnerChanged;
998
999 /*!
1000 * modesetSubOwner points to the pOpenDev of the client that called
1001 * NVKMS_IOCTL_ACQUIRE_PERMISSIONS with a file descriptor that grants
1002 * NV_KMS_PERMISSIONS_TYPE_SUB_OWNER.
1003 */
1004 const struct NvKmsPerOpenDev *modesetSubOwner;
1005
1006 /*!
1007 * NVEvoDevRec::numSubDevices is the number of GPUs in the SLI
1008 * device. This is the number of NVEvoSubDevPtrs in
1009 * NVEvoDevRec::gpus[] and the number of NVSubDeviceEvoPtr in
1010 * NVEvoDevRec::pSubDevices.
1011 *
1012 * The data structure organization is summarized by the following table:
1013 *
1014 * NVDevEvoRec::numSubDevices (# of pSubDevs)
1015 * | NVDevEvoRec::nDispEvo (# of pDispEvos)
1016 * | | NVDispEvoRec::numSubDevices (# of sd per disp)
1017 * | | |
1018 * no SLI 1 1 1
1019 * SLI Mosaic N N 1
1020 */
1021 NvU32 numSubDevices;
1022 NVSubDeviceEvoPtr pSubDevices[NVKMS_MAX_SUBDEVICES];
1023
1024 NvU32 dispClass;
1025 NvU32 displayCommonHandle;
1026 NvU32 rmCtrlHandle;
1027
1028 unsigned int nDispEvo;
1029 NVDispEvoPtr pDispEvo[NVKMS_MAX_SUBDEVICES];
1030
1031 NVEvoChannelPtr base[NVKMS_MAX_HEADS_PER_DISP];
1032 NVEvoChannelPtr core;
1033 NVEvoChannelPtr overlay[NVKMS_MAX_HEADS_PER_DISP];
1034 NVEvoChannelPtr window[NVKMS_MAX_WINDOWS_PER_DISP];
1035
1036 /* NVDisplay head<->window mapping */
1037 NvU32 headForWindow[NVKMS_MAX_WINDOWS_PER_DISP];
1038
1039 struct {
1040 NVEvoChannelPtr layer[NVKMS_MAX_LAYERS_PER_HEAD];
1041 NvU32 numLayers;
1042 } head[NVKMS_MAX_HEADS_PER_DISP];
1043
1044 /* Pointer to array of subdev structs */
1045 NVEvoSubDevPtr gpus;
1046
1047 NvU32 subDevMaskStack[NV_EVO_SUBDEV_STACK_SIZE];
1048 NvU32 subDevMaskStackDepth;
1049
1050 NvU32 cursorHandle[NVKMS_MAX_HEADS_PER_DISP];
1051
1052 NVDPLibTimerPtr dpTimer;
1053
1054 NvU8 capsBits[NV5070_CTRL_SYSTEM_CAPS_TBL_SIZE];
1055 NvU8 commonCapsBits[NV0073_CTRL_SYSTEM_CAPS_TBL_SIZE];
1056
1057 NVEvoCapsRec caps;
1058
1059 NVEvoCoreChannelDmaRec coreChannelDma;
1060 NvU32 nvkmsGpuVASpace;
1061
1062 NvBool mobile : 1;
1063 NvBool usesTegraDevice : 1;
1064
1065 /*
1066 * IO coherency modes that display supports for ISO and NISO memory
1067 * allocations, respectively.
1068 */
1069 NvKmsDispIOCoherencyModes isoIOCoherencyModes;
1070 NvKmsDispIOCoherencyModes nisoIOCoherencyModes;
1071
1072 /*
1073 * Indicates whether the init_no_update methods that were pushed by the
1074 * hardware during core channel allocation are still pending.
1075 */
1076 NvBool coreInitMethodsPending : 1;
1077 /*
1078 * Indicates that NVKMS restored the console and freeing the core channel
1079 * should leave the display configuration alone.
1080 *
1081 * This should be set to FALSE whenever an update is sent that flips away
1082 * from the framebuffer console.
1083 *
1084 * TODO: Remove this in favor of passing a parameter explicitly to the
1085 * functions that use it.
1086 */
1087 NvBool skipConsoleRestore : 1;
1088 /*
1089 * Indicates that hotplug events that occur while NVKMS is the modeset owner
1090 * should trigger console restore modesets.
1091 */
1092 NvBool handleConsoleHotplugs : 1;
1093 /*
1094 * Cached from NvKmsSetModeRequest::allowHeadSurfaceInNvKms when the
1095 * modeset owner does a modeset. This is needed so that when non-modeset
1096 * owners do a partial modeset they don't override this value.
1097 */
1098 NvBool allowHeadSurfaceInNvKms : 1;
1099
1100 NvBool gc6Allowed : 1;
1101
1102 /*
1103 * Indicates whether NVKMS is driving an SOC display device, or an external
1104 * dGPU device.
1105 */
1106 NvBool isSOCDisplay : 1;
1107
1108 /*
1109 * Indicates whether NVKMS is supporting syncpts.
1110 */
1111 NvBool supportsSyncpts : 1;
1112
1113 /*
1114 * Indicates whether the display device that NVKMS is driving requires all
1115 * memory allocations that display will access to come from sysmem.
1116 *
1117 * For SOC display devices, this should be set to TRUE since the only
1118 * memory aperture that they support is sysmem.
1119 */
1120 NvBool requiresAllAllocationsInSysmem : 1;
1121 /*
1122 * Indicates whether the device that NVKMS is driving supports headSurface
1123 * composition.
1124 *
1125 * For SOC display devices (e.g., Orin), this should be set to FALSE since
1126 * there's currently zero nvgpu support, and no Tegra clients should be
1127 * using headSurface right now.
1128 */
1129 NvBool isHeadSurfaceSupported : 1;
1130
1131 /*
1132 * vblank Sem Control requires support in resman; that support is not
1133 * currently available on Tegra.
1134 */
1135 NvBool supportsVblankSemControl : 1;
1136
1137 nvkms_timer_handle_t *postFlipIMPTimer;
1138 nvkms_timer_handle_t *consoleRestoreTimer;
1139
1140 nvkms_timer_handle_t *lowerDispBandwidthTimer;
1141
1142 NvU32 simulationType;
1143
1144 NvU32 numClasses;
1145 NvU32 *supportedClasses;
1146
1147 struct {
1148 /* name[0] == '\0' for unused registryKeys[] array elements. */
1149 char name[NVKMS_MAX_DEVICE_REGISTRY_KEYNAME_LEN];
1150 NvU32 value;
1151 } registryKeys[NVKMS_MAX_DEVICE_REGISTRY_KEYS];
1152
1153 /* Returns true if the Quadro Sync card connected to this GPU has
1154 * a firmware version incompatible with this GPU.
1155 */
1156 NvBool badFramelockFirmware;
1157
1158 const struct _nv_evo_hal *hal;
1159 const struct _nv_evo_cursor_hal *cursorHal;
1160
1161 /*!
1162 * ref_ptr to the structure.
1163 *
1164 * nvkms_timer_handle_t objects refer to the pDevEvo via references to this,
1165 * so that timers that fire after the pDevEvo has been freed can detect that
1166 * case and do nothing.
1167 */
1168 struct nvkms_ref_ptr *ref_ptr;
1169
1170 struct {
1171 void *handle;
1172 } hdmiLib;
1173
1174 struct {
1175 NvU32 semaphoreHandle;
1176 void *pSemaphores;
1177 NvBool enabled;
1178 NvBool active;
1179 NvU32 flipCounter;
1180 } vrr;
1181
1182 /*
1183 * Information about the framebuffer console returned by
1184 * NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO.
1185 */
1186 NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS vtFbInfo;
1187
1188 /*
1189 * Handle referencing the memory reserved by RM that is used by the kernel
1190 * as the framebuffer console surface.
1191 */
1192 NvKmsSurfaceHandle fbConsoleSurfaceHandle;
1193
1194 NVHsDeviceEvoPtr pHsDevice;
1195
1196 /* The current headSurface configuration. */
1197 NVHsStateOneHeadAllDisps apiHeadSurfaceAllDisps[NVKMS_MAX_HEADS_PER_DISP];
1198
1199 struct NVDevPreallocRec prealloc;
1200
1201 struct {
1202 NvU32 handle;
1203 NVOS10_EVENT_KERNEL_CALLBACK_EX callback;
1204 } nonStallInterrupt;
1205
1206 /*
1207 * Track the LUT with per-head, per-pDisp scope. The LUT itself
1208 * is triple buffered.
1209 *
1210 * RM surface allocations are broadcast in SLI, so LUT is allocated with
1211 * per-device scope. However, writes into the LUT are unicast with
1212 * per-pDisp scope.
1213 *
1214 * The LUT surface in the core channel contains both the base and output
1215 * LUTs.
1216 */
1217 struct {
1218 struct {
1219 NVLutSurfaceEvoPtr LUT[3];
1220 struct {
1221 NvBool waitForPreviousUpdate;
1222 NvBool curBaseLutEnabled;
1223 NvBool curOutputLutEnabled;
1224 NvU8 curLUTIndex;
1225 nvkms_timer_handle_t *updateTimer;
1226 } disp[NVKMS_MAX_SUBDEVICES];
1227 } apiHead[NVKMS_MAX_HEADS_PER_DISP];
1228 NVLutSurfaceEvoPtr defaultLut;
1229 enum NvKmsLUTState defaultBaseLUTState[NVKMS_MAX_SUBDEVICES];
1230 enum NvKmsLUTState defaultOutputLUTState[NVKMS_MAX_SUBDEVICES];
1231
1232 /*
1233 * Track outstanding LUT notifiers. Each notifier can have any number
1234 * of apiHeads waiting on it.
1235 *
1236 * waitingApiHeadMask tracks all apiHeads waiting on a LUT notifier.
1237 * stagedApiHeadMask tracks a set of apiHeads that will be tracked by
1238 * the next LUT notifier kickoff.
1239 *
1240 * notifiers is an array of trackers for specific core
1241 * notifiers. If notifiers[i].waiting is true, then the apiHeads listed
1242 * in notifiers[i].apiHeadMask are waiting on notifiers[i].notifier.
1243 */
1244 struct {
1245 struct {
1246 NvU32 waitingApiHeadMask;
1247 NvU32 stagedApiHeadMask;
1248 struct {
1249 int notifier;
1250 NvU32 apiHeadMask;
1251 NvBool waiting;
1252 } notifiers[NVKMS_MAX_HEADS_PER_DISP];
1253 } sd[NVKMS_MAX_SUBDEVICES];
1254 } notifierState;
1255 } lut;
1256
1257 /*! stores pre-syncpts */
1258 NVEvoSyncpt *preSyncptTable;
1259 NvBool *pAllSyncptUsedInCurrentFlip;
1260
1261 /* DIFR prefetch event handling. */
1262 NVOS10_EVENT_KERNEL_CALLBACK_EX difrPrefetchCallback;
1263 NvU32 difrPrefetchEventHandler;
1264
1265 /* DIFR runtime state. */
1266 NVDIFRStateEvoPtr pDifrState;
1267
1268 NvU32 numApiHeads;
1269
1270 struct {
1271 NvU32 numLayers;
1272 } apiHead[NVKMS_MAX_HEADS_PER_DISP];
1273 } NVDevEvoRec;
1274
1275 /*
1276 * The NVHwModeTimingsEvo structure stores all the values necessary to
1277 * perform a modeset with EVO
1278 */
1279
1280 typedef struct _NVHwModeViewPortEvo {
1281 struct {
1282 /*
1283 * note that EVO centers ViewPortOut within the active raster,
1284 * so xAdjust,yAdjust are signed; to position ViewPortOut at
1285 * 0,0 within active raster:
1286 *
1287 * viewPortOut.xAdjust = (activeRaster.w - viewPortOut.w)/2 * -1;
1288 * viewPortOut.yAdjust = (activeRaster.h - viewPortOut.h)/2 * -1;
1289 */
1290 NvS16 xAdjust;
1291 NvS16 yAdjust;
1292 NvU16 width;
1293 NvU16 height;
1294 } out;
1295
1296 struct {
1297 NvU16 width;
1298 NvU16 height;
1299 } in;
1300
1301 NVEvoScalerTaps hTaps;
1302 NVEvoScalerTaps vTaps;
1303
1304 // These are the window features that may be possible if the required ISO
1305 // bw is available at the time that the feature needs to be enabled. By
1306 // default possibleUsage is set considering that everything is supported
1307 // by the HW and for dGPU, IMP will scale it as needed.
1308 struct NvKmsUsageBounds possibleUsage;
1309
1310 // Guaranteed usage bounds allowed by IMP. These are never assigned to
1311 // NVDpyEvoRec::usage or the hardware directly, but rather are used to
1312 // validate usage bound change requests.
1313 struct NvKmsUsageBounds guaranteedUsage;
1314 } NVHwModeViewPortEvo;
1315
nvIsImageSharpeningAvailable(const NVHwModeViewPortEvo * pViewPort)1316 static inline NvBool nvIsImageSharpeningAvailable(
1317 const NVHwModeViewPortEvo *pViewPort)
1318 {
1319 return (pViewPort->out.width != pViewPort->in.width) ||
1320 (pViewPort->out.height != pViewPort->in.height);
1321 }
1322
1323 enum nvKmsPixelDepth {
1324 NVKMS_PIXEL_DEPTH_18_444,
1325 NVKMS_PIXEL_DEPTH_24_444,
1326 NVKMS_PIXEL_DEPTH_30_444,
1327 NVKMS_PIXEL_DEPTH_20_422,
1328 NVKMS_PIXEL_DEPTH_16_422,
1329 };
1330
1331 enum nvKmsTimingsProtocol {
1332 NVKMS_PROTOCOL_DAC_RGB,
1333
1334 NVKMS_PROTOCOL_SOR_SINGLE_TMDS_A,
1335 NVKMS_PROTOCOL_SOR_SINGLE_TMDS_B,
1336 NVKMS_PROTOCOL_SOR_DUAL_TMDS,
1337 NVKMS_PROTOCOL_SOR_DP_A,
1338 NVKMS_PROTOCOL_SOR_DP_B,
1339 NVKMS_PROTOCOL_SOR_LVDS_CUSTOM,
1340 NVKMS_PROTOCOL_SOR_HDMI_FRL,
1341
1342 NVKMS_PROTOCOL_DSI,
1343
1344 NVKMS_PROTOCOL_PIOR_EXT_TMDS_ENC,
1345 };
1346
1347 enum NVDscInfoEvoType {
1348 NV_DSC_INFO_EVO_TYPE_DISABLED = 0,
1349 NV_DSC_INFO_EVO_TYPE_HDMI = 1,
1350 NV_DSC_INFO_EVO_TYPE_DP = 3,
1351 };
1352
1353 enum NVDscEvoMode {
1354 NV_DSC_EVO_MODE_SINGLE = 0,
1355 NV_DSC_EVO_MODE_DUAL = 1,
1356 };
1357
1358 typedef struct _NVDscInfoEvoRec {
1359 union {
1360 /* DisplayPort Display Stream Compression */
1361 struct {
1362 /*
1363 * The DSC target bits per pixel (bpp) rate value multiplied by 16 that
1364 * is being used by the DSC encoder.
1365 *
1366 * It maps respectively to {pps4[1:0], pps5[7:0]}.
1367 */
1368 NvU32 bitsPerPixelX16;
1369
1370 /*
1371 * The DSC picture parameter set (PPS), which the DSC encoder must
1372 * communicate to the decoder.
1373 */
1374 NvU32 pps[DSC_MAX_PPS_SIZE_DWORD];
1375 enum NVDscEvoMode dscMode;
1376 } dp;
1377
1378 struct {
1379 NvU32 bitsPerPixelX16;
1380 NvU32 pps[HDMI_DSC_MAX_PPS_SIZE_DWORD];
1381 NvU32 dscHActiveBytes;
1382 NvU32 dscHActiveTriBytes;
1383 NvU32 dscHBlankTriBytes;
1384 NvU32 dscTBlankToTTotalRatioX1k;
1385 NvU32 hblankMin;
1386 enum NVDscEvoMode dscMode;
1387 } hdmi;
1388 };
1389
1390 enum NVDscInfoEvoType type;
1391 } NVDscInfoEvoRec;
1392
1393 /*
1394 * This structure defines all of the values necessary to program mode timings
1395 * on EVO hardware.
1396 * NOTE: if you add anything to this, consider adding it to
1397 * RasterLockPossible() in nvkms-evo.c
1398 */
1399 typedef struct _NVHwModeTimingsEvo {
1400 struct NvKmsPoint rasterSize;
1401 struct NvKmsPoint rasterSyncEnd;
1402 struct NvKmsPoint rasterBlankEnd;
1403 struct NvKmsPoint rasterBlankStart;
1404 NvU32 rasterVertBlank2Start;
1405 NvU32 rasterVertBlank2End;
1406
1407 NvU32 pixelClock; /* in kHz */
1408 enum nvKmsTimingsProtocol protocol;
1409 /*
1410 * yuv420Mode reflects whether this mode requires YUV 4:2:0 decimation into
1411 * a half-width output through headsurface (SW YUV420) or >=nvdisplay 4.0 HW
1412 * CSC (HW YUV420).
1413 *
1414 * If a mode requires SW YUV 4:2:0 emulation, the pixelClock and width
1415 * values in NvModeTimings will still be the full width values specified by
1416 * the mode parsed from the EDID (e.g. 3840x2160@60), but the pixelClock
1417 * and width values in NVHwModeTimingsEvo will be the "real" half width
1418 * values programmed in HW and rendered to through a headSurface transform
1419 * (e.g. 1920x2160@60). If a mode requires HW YUV 4:2:0 CSC, the
1420 * pixelClock and width values in both NvModeTimings and NVHwModeTimingsEvo
1421 * will be full width, and the decimation to the half width scanout surface
1422 * is performed in HW. In both cases, only the full width values should
1423 * ever be reported to the client.
1424 */
1425 enum NvYuv420Mode yuv420Mode;
1426 /* *SyncPol is TRUE if negative */
1427 NvBool hSyncPol : 1;
1428 NvBool vSyncPol : 1;
1429 NvBool interlaced : 1;
1430 NvBool doubleScan : 1;
1431 /*
1432 * hdmi3D reflects whether this mode is a HDMI 3D frame packed mode. True
1433 * only if the user selected HDMI 3D stereo mode and the GPU supports it.
1434 * If true, then pixelClock is doubled.
1435 */
1436 NvBool hdmi3D : 1;
1437
1438 struct {
1439 /* The vrr type for which this mode is adjusted. */
1440 enum NvKmsDpyVRRType type;
1441 NvU32 timeoutMicroseconds;
1442 NvBool needsSwFramePacing;
1443 } vrr;
1444
1445 NVHwModeViewPortEvo viewPort;
1446 } NVHwModeTimingsEvo;
1447
nvIsAdaptiveSyncDpyVrrType(enum NvKmsDpyVRRType type)1448 static inline NvBool nvIsAdaptiveSyncDpyVrrType(enum NvKmsDpyVRRType type)
1449 {
1450 return ((type == NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED) ||
1451 (type == NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_NON_DEFAULTLISTED));
1452 }
1453
nvEvoFrametimeUsFromTimings(const NVHwModeTimingsEvo * pTimings)1454 static inline NvU64 nvEvoFrametimeUsFromTimings(const NVHwModeTimingsEvo *pTimings)
1455 {
1456 NvU64 pixelsPerFrame = pTimings->rasterSize.x * pTimings->rasterSize.y;
1457 NvU64 pixelsPerSecond = KHzToHz(pTimings->pixelClock);
1458 NvU64 framesPerSecond = pixelsPerSecond / pixelsPerFrame;
1459
1460 return 1000000ULL / framesPerSecond;
1461 }
1462
nvEvoVisibleWidth(const NVHwModeTimingsEvo * pTimings)1463 static inline NvU16 nvEvoVisibleWidth(const NVHwModeTimingsEvo *pTimings)
1464 {
1465 return pTimings->rasterBlankStart.x - pTimings->rasterBlankEnd.x;
1466 }
1467
nvEvoVisibleHeight(const NVHwModeTimingsEvo * pTimings)1468 static inline NvU16 nvEvoVisibleHeight(const NVHwModeTimingsEvo *pTimings)
1469 {
1470 /* rasterVertBlank2{Start,End} should only be != 0 for interlaced modes. */
1471 nvAssert(pTimings->interlaced ||
1472 ((pTimings->rasterVertBlank2Start == 0) &&
1473 (pTimings->rasterVertBlank2End == 0)));
1474
1475 return pTimings->rasterBlankStart.y - pTimings->rasterBlankEnd.y +
1476 pTimings->rasterVertBlank2Start - pTimings->rasterVertBlank2End;
1477 }
1478
1479 /*
1480 * Calculate BackendSizeHeight, based on this HD or SD quality is
1481 * defined.
1482 */
nvEvoIsHDQualityVideoTimings(const NVHwModeTimingsEvo * pTimings)1483 static inline NvBool nvEvoIsHDQualityVideoTimings(
1484 const NVHwModeTimingsEvo *pTimings)
1485 {
1486 NvU32 height = nvEvoVisibleHeight(pTimings);
1487
1488 // as per windows code, nvva uses < 720.
1489 if (height <= 576) {
1490 // SD quality: 240, 288, 480, 576
1491 return FALSE;
1492 }
1493
1494 // HD quality: 720, 1080
1495 return TRUE;
1496 }
1497
nvEvoViewPortOutHwView(const NVHwModeTimingsEvo * pTimings)1498 static inline struct NvKmsRect nvEvoViewPortOutHwView(
1499 const NVHwModeTimingsEvo *pTimings)
1500 {
1501 const NVHwModeViewPortEvo *pViewPort = &pTimings->viewPort;
1502 const NvU16 hVisible = nvEvoVisibleWidth(pTimings);
1503 const NvU16 vVisible = nvEvoVisibleHeight(pTimings);
1504 struct NvKmsRect viewPortOut = { 0 };
1505
1506 viewPortOut.width = pViewPort->out.width;
1507 viewPortOut.height = pViewPort->out.height;
1508 viewPortOut.x = pViewPort->out.xAdjust +
1509 (hVisible - pViewPort->out.width) / 2;
1510 viewPortOut.y = (pViewPort->out.yAdjust +
1511 (vVisible - pViewPort->out.height) / 2);
1512
1513 return viewPortOut;
1514 }
1515
nvEvoViewPortOutClientView(const NVHwModeTimingsEvo * pTimings)1516 static inline struct NvKmsRect nvEvoViewPortOutClientView(
1517 const NVHwModeTimingsEvo *pTimings)
1518 {
1519 struct NvKmsRect viewPortOut = nvEvoViewPortOutHwView(pTimings);
1520
1521 if (pTimings->doubleScan) {
1522
1523 nvAssert((viewPortOut.x % 2) == 0);
1524 viewPortOut.x /= 2;
1525
1526 nvAssert((viewPortOut.height % 2) == 0);
1527 viewPortOut.height /= 2;
1528 }
1529
1530 return viewPortOut;
1531 }
1532
1533 /*
1534 * The ELD contains a subset of the digital display device's EDID
1535 * information related to audio capabilities. The GPU driver sends the
1536 * ELD to hardware and the audio driver reads it by issuing the ELD
1537 * command verb.
1538 */
1539
1540 #define NV_MAX_AUDIO_DEVICE_ENTRIES \
1541 (NV0073_CTRL_DFP_ELD_AUDIO_CAPS_DEVICE_ENTRY_3 + 1)
1542
1543 typedef enum {
1544 NV_ELD_PRE_MODESET = 0,
1545 NV_ELD_POST_MODESET,
1546 NV_ELD_POWER_ON_RESET,
1547 } NvEldCase;
1548
1549 /* OR indices are per OR-type. The maximum OR index for each type
1550 * on each GPU is:
1551 *
1552 * Pre-GV10X : 8 SORs, 4 PIORs and 4 Dacs;
1553 * GV10X : 8 SORs, 4 PIORs;
1554 * TU10X+ : 8 SORs;
1555 */
1556 #define NV_EVO_MAX_ORS 8
1557
1558 /*
1559 * The scoping of heads, ORs, and dpys relative to connectors can be
1560 * complicated. Here is how objects are scoped for various configurations:
1561 *
1562 * #heads #ORs #dpys #NVConnectorEvoRecs
1563 * DP 1.1 1 1 1 1
1564 * DP-MST n 1 n 1
1565 * DP cloning: 1 1 n 1
1566 * 2-Heads-1-OR: 2 2 1 1
1567 */
1568 typedef struct _NVConnectorEvoRec {
1569 char name[NVKMS_DPY_NAME_SIZE];
1570
1571 NVDispEvoPtr pDispEvo;
1572
1573 NVListRec connectorListEntry;
1574
1575 NvBool detectComplete; /* For sync'ing dpy detection w/ DP lib */
1576 NVDPLibConnectorPtr pDpLibConnector; // DP Lib
1577 NvBool dpSerializerEnabled;
1578
1579 struct {
1580 NvU8 maxLinkBW;
1581 NvU8 maxLaneCount;
1582 NvBool supportsMST;
1583 } dpSerializerCaps;
1584
1585 NVDpyId displayId; // RM Display ID
1586 NvKmsConnectorSignalFormat signalFormat;
1587 NvKmsConnectorType type;
1588 NvU32 typeIndex;
1589 NvU32 legacyType; /* NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_ */
1590 NvU32 legacyTypeIndex;
1591 NvU32 physicalIndex;
1592 NvU32 physicalLocation;
1593
1594 NvU32 dfpInfo; /* DFP info query through NV0073_CTRL_CMD_DFP_GET_INFO */
1595
1596 NVDpyIdList ddcPartnerDpyIdsList;
1597
1598 struct {
1599 NvU32 type;
1600 NvU32 protocol; // NV0073_CTRL_SPECIFIC_OR_PROTOCOL_*
1601 NvU32 location; // NV0073_CTRL_SPECIFIC_OR_LOCATION_*
1602 NvU32 ditherType;
1603 NvU32 ditherAlgo;
1604 /* Hardware heads attached to assigned OR */
1605 NvU32 ownerHeadMask[NV_EVO_MAX_ORS];
1606 /* The mask of secondary ORs assigned to this connector */
1607 NvU32 secondaryMask;
1608 /* The primary OR assigned to this connector */
1609 NvU32 primary;
1610 } or;
1611
1612 NvEldCase audioDevEldCase[NV_MAX_AUDIO_DEVICE_ENTRIES];
1613
1614 NvBool isHdmiEnabled;
1615 } NVConnectorEvoRec;
1616
nvConnectorGetORMaskEvo(const NVConnectorEvoRec * pConnectorEvo)1617 static inline NvU32 nvConnectorGetORMaskEvo(const NVConnectorEvoRec *pConnectorEvo)
1618 {
1619 if (pConnectorEvo->or.primary != NV_INVALID_OR) {
1620 return NVBIT(pConnectorEvo->or.primary) | pConnectorEvo->or.secondaryMask;
1621 }
1622 return 0x0;
1623 }
1624
nvConnectorGetAttachedHeadMaskEvo(const NVConnectorEvoRec * pConnectorEvo)1625 static inline NvU32 nvConnectorGetAttachedHeadMaskEvo(
1626 const NVConnectorEvoRec *pConnectorEvo)
1627 {
1628 NvU32 headMask = 0x0;
1629 NvU32 orIndex;
1630
1631 FOR_EACH_INDEX_IN_MASK(32, orIndex, nvConnectorGetORMaskEvo(pConnectorEvo)) {
1632 headMask |= pConnectorEvo->or.ownerHeadMask[orIndex];
1633 } FOR_EACH_INDEX_IN_MASK_END;
1634
1635 return headMask;
1636 }
1637
1638 static inline
nvIsConnectorActiveEvo(const NVConnectorEvoRec * pConnectorEvo)1639 NvBool nvIsConnectorActiveEvo(const NVConnectorEvoRec *pConnectorEvo)
1640 {
1641 return (pConnectorEvo->or.primary != NV_INVALID_OR) &&
1642 (pConnectorEvo->or.ownerHeadMask[pConnectorEvo->or.primary] != 0x0);
1643 }
1644
1645 typedef struct _NVDpLibIsModePossibleParamsRec {
1646 struct {
1647 NvU32 displayId;
1648 NVDpyIdList dpyIdList;
1649 enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace;
1650 enum NvKmsDpyAttributeColorBpcValue colorBpc;
1651 const struct NvKmsModeValidationParams *pModeValidationParams;
1652 const NVHwModeTimingsEvo *pTimings;
1653 NvBool b2Heads1Or;
1654 NVDscInfoEvoRec *pDscInfo;
1655 } head[NV_MAX_HEADS];
1656 } NVDpLibIsModePossibleParamsRec;
1657
1658 typedef struct _NVDpyAttributeCurrentDitheringConfigRec {
1659 NvBool enabled;
1660 enum NvKmsDpyAttributeCurrentDitheringDepthValue depth;
1661 enum NvKmsDpyAttributeCurrentDitheringModeValue mode;
1662 } NVDpyAttributeCurrentDitheringConfig;
1663
1664 typedef struct __NVAttributesSetEvoRec {
1665
1666 #define NV_EVO_DVC_MIN (-1024)
1667 #define NV_EVO_DVC_MAX 1023
1668 #define NV_EVO_DVC_DEFAULT 0
1669
1670 NvS32 dvc;
1671
1672 /*
1673 * For both colorSpace and colorRange, the value for
1674 * NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_{SPACE,RANGE} sent by the client is
1675 * stored in NVDpyEvoRec::requestedColor(Space, Range}. The structure stores
1676 * the actual color space and color range in use.
1677 *
1678 * nvChooseCurrentColorSpaceAndRangeEvo() chooses the actual color
1679 * space, color bpc, and color range, for a dpy. It sets colorBpc
1680 * to the max bpc supported by the given dpy.
1681 *
1682 * Since YUV444 mode only allows limited color range, changes to the
1683 * current color space may trigger changes to the current color
1684 * range (see nvChooseCurrentColorSpaceAndRangeEvo()).
1685 *
1686 * For SW YUV420 mode, these values are ignored in
1687 * HEAD_SET_PROCAMP and applied in the headSurface composite shader.
1688 */
1689 enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace;
1690 enum NvKmsDpyAttributeColorBpcValue colorBpc;
1691 enum NvKmsDpyAttributeColorRangeValue colorRange;
1692
1693 NVDpyAttributeCurrentDitheringConfig dithering;
1694
1695 #define NV_EVO_IMAGE_SHARPENING_MIN 0
1696 #define NV_EVO_IMAGE_SHARPENING_MAX 255
1697 #define NV_EVO_IMAGE_SHARPENING_DEFAULT 127
1698
1699 struct {
1700 NvBool available;
1701 NvU32 value;
1702 } imageSharpening;
1703
1704 enum NvKmsDpyAttributeDigitalSignalValue digitalSignal;
1705
1706 NvU8 numberOfHardwareHeadsUsed;
1707 } NVAttributesSetEvoRec;
1708
1709 #define NV_EVO_DEFAULT_ATTRIBUTES_SET \
1710 (NVAttributesSetEvoRec) { \
1711 .dvc = NV_EVO_DVC_DEFAULT, \
1712 .colorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB, \
1713 .colorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL, \
1714 .dithering = { \
1715 .enabled = FALSE, \
1716 .mode = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_NONE, \
1717 .depth = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_NONE, \
1718 }, \
1719 .imageSharpening = { \
1720 .value = NV_EVO_IMAGE_SHARPENING_DEFAULT, \
1721 }, \
1722 .numberOfHardwareHeadsUsed = 0, \
1723 }
1724
1725 struct NvKmsVrrFramePacingInfo {
1726 /* Whether sw frame pacing is active. */
1727 NvBool framePacingActive;
1728
1729 /* Memory handle for vidmem buffer */
1730 NvHandle memoryHandle;
1731
1732 /* Shared data to be updated by RM */
1733 NV0073_CTRL_RM_VRR_SHARED_DATA *pData;
1734 };
1735
1736 typedef struct _NVEldEvoRec {
1737 NvU32 size;
1738 NvU8 buffer[NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER];
1739 } NVEldEvoRec;
1740
1741 /*
1742 * This structure stores information about the active per-head audio state.
1743 */
1744 typedef struct _NVDispHeadAudioStateEvoRec {
1745 NvU32 maxFreqSupported;
1746 NVEldEvoRec eld;
1747
1748 NvBool isAudioOverHdmi : 1;
1749 NvBool supported : 1;
1750 NvBool enabled : 1;
1751 } NVDispHeadAudioStateEvoRec;
1752
1753 typedef struct _NVDispHeadInfoFrameStateEvoRec {
1754 NVT_VIDEO_INFOFRAME_CTRL ctrl;
1755 NvBool hdTimings;
1756 } NVDispHeadInfoFrameStateEvoRec;
1757
1758 typedef enum _NVEvoMergeMode {
1759 NV_EVO_MERGE_MODE_DISABLED,
1760 NV_EVO_MERGE_MODE_SETUP,
1761 NV_EVO_MERGE_MODE_PRIMARY,
1762 NV_EVO_MERGE_MODE_SECONDARY,
1763 } NVEvoMergeMode;
1764
1765 /*
1766 * This structure stores information about the active per-head display state.
1767 */
1768 typedef struct _NVDispHeadStateEvoRec {
1769
1770 struct NvKmsVrrFramePacingInfo vrrFramePacingInfo;
1771 NvU32 displayRate;
1772
1773 /*! Cached, to preserve across modesets. */
1774 struct NvKmsModeValidationParams modeValidationParams;
1775
1776 /*
1777 * For Turing and newer, enable display composition bypass mode.
1778 *
1779 * This is intended to be used by console restore to avoid bug 2168873.
1780 */
1781 NvBool bypassComposition : 1;
1782
1783 struct {
1784 NVT_COLOR_FORMAT colorFormat;
1785 NVT_COLORIMETRY colorimetry;
1786 NVT_COLOR_RANGE colorRange;
1787 NvU32 satCos;
1788 } procAmp;
1789
1790 /*
1791 * The activeRmId is the identifier that we use to talk to RM
1792 * about the display device(s) on this head. It is zero except
1793 * when a mode is being driven by this head. For DP MST, it is the
1794 * identifier of the displayport library group to which the driven
1795 * DP device belongs. Otherwise, it is the identifier of the connector
1796 * driven by the head.
1797 */
1798 NvU32 activeRmId;
1799
1800 NVHwModeTimingsEvo timings;
1801 NVConnectorEvoRec *pConnectorEvo; /* NULL if the head is not active */
1802
1803 HDMI_FRL_CONFIG hdmiFrlConfig;
1804 NvU8 hdmiFrlBpc;
1805
1806 NVDscInfoEvoRec dscInfo;
1807
1808 enum nvKmsPixelDepth pixelDepth;
1809
1810 NVDispHeadAudioStateEvoRec audio;
1811
1812 enum NvKmsOutputTf tf;
1813
1814 enum NvKmsOutputColorimetry colorimetry;
1815
1816 struct {
1817 NvBool enabled;
1818 enum NvKmsInfoFrameEOTF eotf;
1819 struct NvKmsHDRStaticMetadata staticMetadata;
1820 } hdrInfoFrameOverride;
1821
1822 struct {
1823 enum NvKmsHDRInfoFrameState state;
1824 enum NvKmsInfoFrameEOTF eotf;
1825 struct NvKmsHDRStaticMetadata staticMetadata;
1826 } hdrInfoFrame;
1827
1828 struct {
1829 NVLutSurfaceEvoPtr pCurrSurface;
1830 NvBool outputLutEnabled : 1;
1831 NvBool baseLutEnabled : 1;
1832 } lut;
1833
1834 /*
1835 * The api head can be mapped onto the N harware heads, a frame presented
1836 * by the api head gets split horizontally into N tiles, 'tilePosition'
1837 * describe the tile presented by this hardware head.
1838 */
1839 NvU8 tilePosition;
1840
1841 NVEvoMergeMode mergeMode;
1842 /*
1843 * XXX[2Heads1OR] Implement per api-head frame pacing and remove
1844 * NVDispEvoRec::mergeModeVrrSecondaryHeadMask.
1845 */
1846 NvU32 mergeModeVrrSecondaryHeadMask;
1847 } NVDispHeadStateEvoRec;
1848
1849 typedef struct _NVDispStereoParamsEvoRec {
1850 enum NvKmsStereoMode mode;
1851 NvBool isAegis;
1852 } NVDispStereoParamsEvoRec;
1853
1854 typedef struct _NVDispFlipOccurredEventDataEvoRec {
1855 NVDispEvoPtr pDispEvo;
1856 NvU32 apiHead;
1857 NvU32 layer;
1858 } NVDispFlipOccurredEventDataEvoRec;
1859
1860 typedef struct _NVDispApiHeadStateEvoRec {
1861 /*
1862 * The mask of hardware heads mapped onto this api head,
1863 * set to zero if the api head is not active.
1864 */
1865 NvU32 hwHeadsMask;
1866
1867 NVDpyIdList activeDpys; /* Empty if the head is not active */
1868 NVAttributesSetEvoRec attributes;
1869
1870 enum NvKmsOutputTf tf;
1871
1872 enum NvKmsOutputColorimetry colorimetry;
1873
1874 NvBool hdrInfoFrameOverride;
1875 NvU32 hdrStaticMetadataLayerMask;
1876
1877 /*
1878 * Hardware timings which are split across hardware heads.
1879 *
1880 * XXX[2Heads1OR] The api-head state does not require to track full
1881 * hardware timings. Replace 'timings' by minimal per api-head hardware
1882 * timings information used in code.
1883 */
1884 NVHwModeTimingsEvo timings;
1885
1886 NVDispStereoParamsEvoRec stereo;
1887
1888 struct NvKmsPoint viewPortPointIn;
1889
1890 NVDispHeadInfoFrameStateEvoRec infoFrame;
1891
1892 /*
1893 * Each head can have up to NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD
1894 * programmable Core semaphores.
1895 *
1896 * The numVblankSyncObjectsCreated will ideally always be equal to
1897 * NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD, but could be lower if errors
1898 * occured during syncpt allocation in nvRMSetupEvoCoreChannel().
1899 */
1900 NvU8 numVblankSyncObjectsCreated;
1901 NVVblankSyncObjectRec vblankSyncObjects[NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD];
1902
1903 struct {
1904 struct nvkms_ref_ptr *ref_ptr;
1905 NVDispFlipOccurredEventDataEvoRec data;
1906 } flipOccurredEvent[NVKMS_MAX_LAYERS_PER_HEAD];
1907
1908 NvU32 rmVBlankCallbackHandle;
1909 NVListRec vblankCallbackList;
1910
1911 NvBool hs10bpcHint : 1;
1912 } NVDispApiHeadStateEvoRec;
1913
1914 typedef struct _NVDispEvoRec {
1915 NvU8 gpuLogIndex;
1916 NVDevEvoPtr pDevEvo;
1917 NvU32 hotplugEventHandle;
1918 NvU32 DPIRQEventHandle;
1919 NVOS10_EVENT_KERNEL_CALLBACK_EX rmHotplugCallback;
1920 NVOS10_EVENT_KERNEL_CALLBACK_EX rmDPIRQCallback;
1921
1922 NVDispHeadStateEvoRec headState[NVKMS_MAX_HEADS_PER_DISP];
1923 NVDispApiHeadStateEvoRec apiHeadState[NVKMS_MAX_HEADS_PER_DISP];
1924
1925 NVDpyIdList vbiosDpyConfig[NVKMS_MAX_HEADS_PER_DISP];
1926
1927 NvU32 isoBandwidthKBPS;
1928 NvU32 dramFloorKBPS;
1929
1930 /*
1931 * The list of physical connector display IDs. This is the union
1932 * of pConnectorEvo->displayId values, which is also the union of
1933 * pDpyEvo->id values for non-MST pDpys.
1934 */
1935 NVDpyIdList connectorIds;
1936
1937 NVListRec connectorList;
1938
1939 NvU32 displayOwner;
1940
1941 NVListRec dpyList;
1942
1943 NVDpyIdList bootDisplays;
1944 NVDpyIdList validDisplays;
1945 NVDpyIdList connectedDisplays;
1946
1947 /*
1948 * displayPortMSTIds is a superset of dynamicDpyIds because not all DP MST
1949 * dpys are dynamic dpys. For example, the DP MST dpys that are driven by
1950 * a DP serializer connector are part of a fixed topology, and are static in
1951 * nature.
1952 */
1953 NVDpyIdList displayPortMSTIds; /* DP MST dpys */
1954 NVDpyIdList dynamicDpyIds;
1955
1956 NVDpyIdList muxDisplays;
1957
1958 struct {
1959 nvkms_timer_handle_t *unstallTimer;
1960 } vrr;
1961
1962 NVFrameLockEvoPtr pFrameLockEvo;
1963 struct {
1964 NVDpyId server;
1965 NVDpyIdList clients;
1966 NvBool syncEnabled; /* GPU is syncing to framelock */
1967 NvU32 connectorIndex;/* NV30F1_GSYNC_CONNECTOR_* */
1968 NvU32 currentServerHead; /* used for disabling */
1969 NvU32 currentClientHeadsMask; /* used for disabling */
1970 NvBool currentHouseSync; /* if state machine thinks house sync
1971 is enabled -- used for disabling */
1972
1973 /* Framelock event-related data */
1974 #define NV_FRAMELOCK_SYNC_LOSS 0
1975 #define NV_FRAMELOCK_SYNC_GAIN 1
1976 #define NV_FRAMELOCK_NUM_EVENTS 2
1977
1978 struct {
1979 NvU32 handle;
1980 NVOS10_EVENT_KERNEL_CALLBACK_EX callback;
1981 } gsyncEvent[NV_FRAMELOCK_NUM_EVENTS];
1982
1983 } framelock;
1984
1985 /* NVDevEvoRec::pHsChannel[] is indexed by the api heads */
1986 NVHsChannelEvoPtr pHsChannel[NVKMS_MAX_HEADS_PER_DISP];
1987
1988 /* NVDevEvoRec::pSwapGroup[] is indexed by the api heads */
1989 NVSwapGroupPtr pSwapGroup[NVKMS_MAX_HEADS_PER_DISP];
1990
1991 /* If cross-GPU rasterlock is possible with the currently-active
1992 * configuration */
1993 NvBool rasterLockPossible;
1994
1995 /*
1996 * This points to an *active* lock group (i.e., a set of 1 or more pDisps
1997 * across which rasterlock -- and possibly fliplock -- is currently
1998 * enabled), or NULL if no lock group is active on this pDisp.
1999 */
2000 NVLockGroup *pLockGroup;
2001
2002 /*!
2003 * ref_ptr to the structure.
2004 *
2005 * nvkms_timer_handle_t objects refer to the pDispEvo via references to
2006 * this, so that timers that fire after the pDispEvo has been freed can
2007 * detect that case and do nothing.
2008 */
2009 struct nvkms_ref_ptr *ref_ptr;
2010
2011 /*
2012 * Indicates that NV_KMS_DISP_ATTRIBUTE_QUERY_DP_AUX_LOG has been queried at
2013 * least once on this device. If set, nvRmDestroyDisplays() will flush any
2014 * remaining AUX log messages to the system log.
2015 */
2016 NvBool dpAuxLoggingEnabled;
2017
2018 struct nvkms_backlight_device *backlightDevice;
2019
2020 NvU32 vrrSetTimeoutEventUsageCount;
2021 NVOS10_EVENT_KERNEL_CALLBACK_EX vrrSetTimeoutCallback;
2022 NvU32 vrrSetTimeoutEventHandle;
2023 } NVDispEvoRec;
2024
GetNextHwHead(NvU32 hwHeadsMask,const NvU32 prevHwHead)2025 static inline NvU32 GetNextHwHead(NvU32 hwHeadsMask, const NvU32 prevHwHead)
2026 {
2027 if ((hwHeadsMask == 0x0) ||
2028 ((prevHwHead != NV_INVALID_HEAD) &&
2029 ((hwHeadsMask &= ~((1 << (prevHwHead + 1)) -1 )) == 0x0))) {
2030 return NV_INVALID_HEAD;
2031 }
2032 return BIT_IDX_32(LOWESTBIT(hwHeadsMask));
2033 }
2034
2035 #define FOR_EACH_EVO_HW_HEAD_IN_MASK(__hwHeadsMask, __hwHead) \
2036 for ((__hwHead) = GetNextHwHead((__hwHeadsMask), NV_INVALID_HEAD); \
2037 (__hwHead) != NV_INVALID_HEAD; \
2038 (__hwHead) = GetNextHwHead((__hwHeadsMask), (__hwHead)))
2039
2040 #define FOR_EACH_EVO_HW_HEAD(__pDispEvo, __apiHead, __hwHead) \
2041 FOR_EACH_EVO_HW_HEAD_IN_MASK((__pDispEvo)->apiHeadState[(__apiHead)].hwHeadsMask, \
2042 (__hwHead))
2043
nvGetPrimaryHwHeadFromMask(const NvU32 hwHeadsMask)2044 static inline NvU32 nvGetPrimaryHwHeadFromMask(const NvU32 hwHeadsMask)
2045 {
2046 return GetNextHwHead(hwHeadsMask, NV_INVALID_HEAD);
2047 }
2048
nvGetPrimaryHwHead(const NVDispEvoRec * pDispEvo,const NvU32 apiHead)2049 static inline NvU32 nvGetPrimaryHwHead(const NVDispEvoRec *pDispEvo,
2050 const NvU32 apiHead)
2051 {
2052 return (apiHead != NV_INVALID_HEAD) ?
2053 nvGetPrimaryHwHeadFromMask(pDispEvo->apiHeadState[apiHead].hwHeadsMask) :
2054 NV_INVALID_HEAD;
2055 }
2056
2057 typedef enum {
2058 NV_EVO_PASSIVE_DP_DONGLE_UNUSED,
2059 NV_EVO_PASSIVE_DP_DONGLE_DP2DVI,
2060 NV_EVO_PASSIVE_DP_DONGLE_DP2HDMI_TYPE_1,
2061 NV_EVO_PASSIVE_DP_DONGLE_DP2HDMI_TYPE_2,
2062 } NVEvoPassiveDpDongleType;
2063
2064 typedef struct NVEdidRec {
2065 NvU8 *buffer;
2066 size_t length;
2067 } NVEdidRec, *NVEdidPtr;
2068
2069 typedef struct _NVParsedEdidEvoRec {
2070 NvBool valid;
2071 NVT_EDID_INFO info;
2072 NVT_EDID_RANGE_LIMIT limits;
2073 char monitorName[NVT_EDID_MONITOR_NAME_STRING_LENGTH];
2074 char serialNumberString[NVT_EDID_LDD_PAYLOAD_SIZE+1];
2075 } NVParsedEdidEvoRec;
2076
2077 typedef void (*NVVBlankCallbackProc)(NVDispEvoRec *pDispEvo,
2078 NVVBlankCallbackPtr pCallbackData);
2079
2080 typedef struct _NVVBlankCallbackRec {
2081 NVListRec vblankCallbackListEntry;
2082 NVVBlankCallbackProc pCallback;
2083 void *pUserData;
2084 NvU32 apiHead;
2085 } NVVBlankCallbackRec;
2086
2087 typedef void (*NVRgLine1CallbackProc)(NVDispEvoRec *pDispEvo,
2088 const NvU32 head,
2089 NVRgLine1CallbackPtr pCallbackData);
2090
2091 typedef struct _NVRgLine1CallbackRec {
2092 NVRgLine1CallbackProc pCallbackProc;
2093 void *pUserData;
2094 } NVRgLine1CallbackRec;
2095
2096 typedef struct _NVDpyAttributeRequestedDitheringConfigRec {
2097 enum NvKmsDpyAttributeRequestedDitheringValue state;
2098 enum NvKmsDpyAttributeRequestedDitheringDepthValue depth;
2099 enum NvKmsDpyAttributeRequestedDitheringModeValue mode;
2100 } NVDpyAttributeRequestedDitheringConfig;
2101
2102 typedef struct _NVDpyEvoRec {
2103 NVListRec dpyListEntry;
2104 NVDpyId id;
2105
2106 char name[NVKMS_DPY_NAME_SIZE];
2107
2108 NvU32 apiHead;
2109
2110 struct _NVDispEvoRec *pDispEvo;
2111 NVConnectorEvoPtr pConnectorEvo;
2112
2113 NvBool hasBacklightBrightness : 1;
2114 NvBool internal : 1;
2115 NvBool allowDVISpecPClkOverride : 1;
2116
2117 /* whether the connected dpy is HDMI capable */
2118 NvBool hdmiCapable : 1;
2119 NvBool isVrHmd : 1;
2120
2121 /*
2122 * Maximum single link and total allowed pixel clock. This is first
2123 * reported by RM through DpyProbeMaxPixelClock, and then potentially
2124 * overridden by the EVO SOR capabilities for HDMI and DVI through
2125 * UpdateMaxPixelClock.
2126 */
2127 NvU32 maxPixelClockKHz;
2128 NvU32 maxSingleLinkPixelClockKHz;
2129
2130 NVEdidRec edid;
2131 NVParsedEdidEvoRec parsedEdid;
2132
2133 NVDpyAttributeRequestedDitheringConfig requestedDithering;
2134
2135 enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace;
2136 enum NvKmsDpyAttributeColorRangeValue requestedColorRange;
2137
2138 NVAttributesSetEvoRec currentAttributes;
2139
2140 nvkms_timer_handle_t *hdrToSdrTransitionTimer;
2141
2142 struct {
2143 char *addressString;
2144 NVDPLibDevicePtr pDpLibDevice; // DP Lib's notion of the device.
2145 NvBool inbandStereoSignaling;
2146
2147 NvU8 laneCount; // NV0073_CTRL_DP_DATA_SET_LANE_COUNT
2148 NvU8 linkRate; // NV0073_CTRL_DP_DATA_SET_LINK_BW
2149 enum NvKmsDpyAttributeDisplayportConnectorTypeValue connectorType;
2150 NvBool sinkIsAudioCapable;
2151
2152 struct {
2153 NvBool valid;
2154 NvU8 buffer[NVKMS_GUID_SIZE];
2155 char str[NVKMS_GUID_STRING_SIZE];
2156 } guid;
2157
2158 /*
2159 * When the DP serializer is in MST mode, this field is used to uniquely
2160 * identify each MST DPY that's connected to the DP serializer.
2161 *
2162 * This field is only valid for DP serializer DPYs, and pDpLibDevice
2163 * must be NULL in this case.
2164 */
2165 NvU8 serializerStreamIndex;
2166 } dp;
2167
2168 struct {
2169 HDMI_SRC_CAPS srcCaps;
2170 HDMI_SINK_CAPS sinkCaps;
2171 } hdmi;
2172
2173 struct {
2174 NvBool ycbcr422Capable;
2175 NvBool ycbcr444Capable;
2176 } colorSpaceCaps;
2177
2178 struct {
2179 NvBool supported : 1;
2180 NvBool requiresModetimingPatching : 1;
2181 NvBool isDLP : 1;
2182 NvBool isAegis : 1;
2183 NvBool requiresVbiAdjustment : 1;
2184 NvU32 subType;
2185 int indexInOverrideTimings;
2186 } stereo3DVision;
2187
2188 struct {
2189 enum NvKmsDpyVRRType type;
2190 NvU32 edidTimeoutMicroseconds;
2191 NvBool needsSwFramePacing;
2192 } vrr;
2193 } NVDpyEvoRec;
2194
nvDpyEvoIsDPMST(const NVDpyEvoRec * pDpyEvo)2195 static inline NvBool nvDpyEvoIsDPMST(const NVDpyEvoRec *pDpyEvo)
2196 {
2197 return nvDpyIdIsInDpyIdList(pDpyEvo->id,
2198 pDpyEvo->pDispEvo->displayPortMSTIds);
2199 }
2200
2201 // Return a pDpy's connector's display ID
nvDpyEvoGetConnectorId(const NVDpyEvoRec * pDpyEvo)2202 static inline NvU32 nvDpyEvoGetConnectorId(const NVDpyEvoRec *pDpyEvo)
2203 {
2204 NvU32 rmDpyId = nvDpyIdToNvU32(pDpyEvo->pConnectorEvo->displayId);
2205
2206 // This function shouldn't be used for DP MST dynamic devices.
2207 nvAssert(!nvDpyEvoIsDPMST(pDpyEvo));
2208 nvAssert(ONEBITSET(rmDpyId));
2209
2210 return rmDpyId;
2211 }
2212
2213 static inline
nvConnectorIsInternal(const NVConnectorEvoRec * pConnectorEvo)2214 NvBool nvConnectorIsInternal(const NVConnectorEvoRec *pConnectorEvo)
2215 {
2216 /* For mobile GPUs check for LVDS or embedded DisplayPort signal flag.
2217 * If found, DFP is internal*/
2218 return (pConnectorEvo->legacyType ==
2219 NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_DFP) &&
2220 (((pConnectorEvo->pDispEvo->pDevEvo->mobile) &&
2221 (FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS, _SIGNAL, _LVDS,
2222 pConnectorEvo->dfpInfo))) ||
2223 (FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS, _SIGNAL, _DSI,
2224 pConnectorEvo->dfpInfo)) ||
2225 (FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS, _EMBEDDED_DISPLAYPORT, _TRUE,
2226 pConnectorEvo->dfpInfo)));
2227 }
2228
NV_EVO_LOCK_PIN(NvU32 n)2229 static inline NvU32 NV_EVO_LOCK_PIN(NvU32 n)
2230 {
2231 return NV_EVO_LOCK_PIN_0 + n;
2232 }
2233
NV_EVO_LOCK_PIN_INTERNAL(NvU32 n)2234 static inline NvU32 NV_EVO_LOCK_PIN_INTERNAL(NvU32 n)
2235 {
2236 return NV_EVO_LOCK_PIN_INTERNAL_0 + n;
2237 }
2238
NV_EVO_LOCK_PIN_IS_INTERNAL(NvU32 n)2239 static inline NvBool NV_EVO_LOCK_PIN_IS_INTERNAL(NvU32 n)
2240 {
2241 ct_assert(NV_IS_UNSIGNED(n) && NV_EVO_LOCK_PIN_INTERNAL_0 == 0);
2242 return n < NV_EVO_LOCK_PIN_0;
2243 }
2244
2245
2246 /*
2247 * Utility macro for looping over all the pConnectorsEvo on a pDispEvo.
2248 */
2249 #define FOR_ALL_EVO_CONNECTORS(_pConnectorEvo, _pDispEvo) \
2250 nvListForEachEntry((_pConnectorEvo), \
2251 &(_pDispEvo)->connectorList, connectorListEntry)
2252
2253 /*
2254 * Utility macro for declaring a for loop to walk over all the
2255 * pDispEvos on a particular pDevEvo.
2256 */
2257 #define FOR_ALL_EVO_DISPLAYS(_pDispEvo, _i, _pDevEvo) \
2258 for ((_i) = 0, \
2259 (_pDispEvo) = (_pDevEvo)->pDispEvo[0]; \
2260 (_pDispEvo); \
2261 (_i)++, (_pDispEvo) = ((_i) < (_pDevEvo)->nDispEvo) ? \
2262 (_pDevEvo)->pDispEvo[(_i)] : NULL)
2263
2264 #define FOR_ALL_EVO_DPYS(_pDpyEvo, _dpyIdList, _pDispEvo) \
2265 nvListForEachEntry((_pDpyEvo), &(_pDispEvo)->dpyList, dpyListEntry) \
2266 if (nvDpyIdIsInDpyIdList((_pDpyEvo)->id, (_dpyIdList)))
2267
2268 #define FOR_ALL_EVO_FRAMELOCKS(_pFrameLockEvo) \
2269 nvListForEachEntry(_pFrameLockEvo, &nvEvoGlobal.frameLockList, \
2270 frameLockListEntry)
2271
2272 #define FOR_ALL_EVO_DEVS(_pDevEvo) \
2273 nvListForEachEntry(_pDevEvo, &nvEvoGlobal.devList, devListEntry)
2274
2275 #define FOR_ALL_DEFERRED_REQUEST_FIFOS_IN_SWAP_GROUP( \
2276 _pSwapGroup, _pDeferredRequestFifo) \
2277 nvListForEachEntry((_pDeferredRequestFifo), \
2278 &(_pSwapGroup)->deferredRequestFifoList, \
2279 swapGroup.deferredRequestFifoListEntry)
2280
2281 #define FOR_EACH_SUBDEV_IN_MASK(_sd, _mask) \
2282 FOR_EACH_INDEX_IN_MASK(32, _sd, _mask)
2283
2284 #define FOR_EACH_SUBDEV_IN_MASK_END \
2285 FOR_EACH_INDEX_IN_MASK_END
2286
nvGetOneArbitraryDpyEvo(NVDpyIdList dpyIdList,const NVDispEvoRec * pDispEvo)2287 static inline NVDpyEvoPtr nvGetOneArbitraryDpyEvo(NVDpyIdList dpyIdList,
2288 const NVDispEvoRec *pDispEvo)
2289 {
2290 NVDpyEvoPtr pDpyEvo;
2291
2292 nvAssert(nvDpyIdListIsASubSetofDpyIdList(dpyIdList,
2293 pDispEvo->validDisplays));
2294
2295 FOR_ALL_EVO_DPYS(pDpyEvo, dpyIdList, pDispEvo) {
2296 return pDpyEvo;
2297 }
2298
2299 return NULL;
2300 }
2301
2302
2303 /*
2304 * Return whether or not the display devices on the connector should
2305 * be handled by the DP library.
2306 */
nvConnectorUsesDPLib(const NVConnectorEvoRec * pConnectorEvo)2307 static inline NvBool nvConnectorUsesDPLib(const NVConnectorEvoRec
2308 *pConnectorEvo)
2309 {
2310 return (pConnectorEvo->pDpLibConnector != NULL);
2311 }
2312
2313 static inline
nvConnectorIsDPSerializer(const NVConnectorEvoRec * pConnectorEvo)2314 NvBool nvConnectorIsDPSerializer(const NVConnectorEvoRec *pConnectorEvo)
2315 {
2316 return (pConnectorEvo->type == NVKMS_CONNECTOR_TYPE_DP_SERIALIZER);
2317 }
2318
2319 /*
2320 * Return whether or not the display device given is handled by the DP
2321 * library.
2322 */
nvDpyUsesDPLib(const NVDpyEvoRec * pDpyEvo)2323 static inline NvBool nvDpyUsesDPLib(const NVDpyEvoRec *pDpyEvo)
2324 {
2325 return nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo);
2326 }
2327
2328 /*
2329 * Return whether this dpy is active. The dpy is active if it is
2330 * driven by a head.
2331 */
nvDpyEvoIsActive(const NVDpyEvoRec * pDpyEvo)2332 static inline NvBool nvDpyEvoIsActive(const NVDpyEvoRec *pDpyEvo)
2333 {
2334 return (pDpyEvo->apiHead != NV_INVALID_HEAD);
2335 }
2336
2337 /*
2338 * Return true if this dpy reports an EDID supporting HDMI 3D and
2339 * isn't connected via active DisplayPort.
2340 */
nvDpyEvoSupportsHdmi3D(const NVDpyEvoRec * pDpyEvo)2341 static inline NvBool nvDpyEvoSupportsHdmi3D(const NVDpyEvoRec *pDpyEvo)
2342 {
2343 return (pDpyEvo->parsedEdid.valid &&
2344 pDpyEvo->parsedEdid.info.HDMI3DSupported &&
2345 !((pDpyEvo->pConnectorEvo->or.protocol ==
2346 NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A) ||
2347 (pDpyEvo->pConnectorEvo->or.protocol ==
2348 NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B)));
2349
2350 }
2351
nvHeadIsActive(const NVDispEvoRec * pDispEvo,const NvU32 head)2352 static inline NvBool nvHeadIsActive(const NVDispEvoRec *pDispEvo,
2353 const NvU32 head)
2354 {
2355 return (head < ARRAY_LEN(pDispEvo->headState)) &&
2356 (pDispEvo->headState[head].pConnectorEvo != NULL);
2357 }
2358
nvApiHeadIsActive(const NVDispEvoRec * pDispEvo,const NvU32 apiHead)2359 static inline NvBool nvApiHeadIsActive(const NVDispEvoRec *pDispEvo,
2360 const NvU32 apiHead)
2361 {
2362 return (apiHead < ARRAY_LEN(pDispEvo->apiHeadState)) &&
2363 (!nvDpyIdListIsEmpty(pDispEvo->apiHeadState[apiHead].activeDpys));
2364 }
2365
2366 /*!
2367 * Return the mask of active heads on this pDispEvo.
2368 */
nvGetActiveHeadMask(const NVDispEvoRec * pDispEvo)2369 static inline NvU32 nvGetActiveHeadMask(const NVDispEvoRec *pDispEvo)
2370 {
2371 NvU32 head;
2372 NvU32 headMask = 0;
2373
2374 for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) {
2375 if (nvHeadIsActive(pDispEvo, head)) {
2376 headMask |= 1 << head;
2377 }
2378 }
2379
2380 return headMask;
2381 }
2382
nvAllHeadsInactive(const NVDevEvoRec * pDevEvo)2383 static inline NvBool nvAllHeadsInactive(const NVDevEvoRec *pDevEvo)
2384 {
2385 NVDispEvoPtr pDispEvo;
2386 NvU32 dispIndex;
2387 NvU32 head;
2388
2389 FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) {
2390 for (head = 0; head < pDevEvo->numHeads; head++) {
2391 if (nvHeadIsActive(pDispEvo, head)) {
2392 return FALSE;
2393 }
2394 }
2395 }
2396
2397 return TRUE;
2398 }
2399
2400 /*
2401 * Return the list of dpys that are currently active on the given disp.
2402 */
nvActiveDpysOnDispEvo(const NVDispEvoRec * pDispEvo)2403 static inline NVDpyIdList nvActiveDpysOnDispEvo(const NVDispEvoRec *pDispEvo)
2404 {
2405 NVDpyIdList dpyIdList = nvEmptyDpyIdList();
2406 NvU32 apiHead;
2407
2408 for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) {
2409 const NVDispApiHeadStateEvoRec *pApiHeadState =
2410 &pDispEvo->apiHeadState[apiHead];
2411
2412 dpyIdList = nvAddDpyIdListToDpyIdList(dpyIdList,
2413 pApiHeadState->activeDpys);
2414 }
2415
2416 return dpyIdList;
2417 }
2418
nvGpuIdOfDispEvo(const NVDispEvoRec * pDispEvo)2419 static inline NvU32 nvGpuIdOfDispEvo(const NVDispEvoRec *pDispEvo)
2420 {
2421 nvAssert(pDispEvo->displayOwner < pDispEvo->pDevEvo->numSubDevices);
2422 return pDispEvo->pDevEvo->pSubDevices[pDispEvo->displayOwner]->gpuId;
2423 }
2424
nvIsEmulationEvo(const NVDevEvoRec * pDevEvo)2425 static inline NvBool nvIsEmulationEvo(const NVDevEvoRec *pDevEvo)
2426 {
2427 return pDevEvo->simulationType !=
2428 NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE;
2429 }
2430
nvIs3DVisionStereoEvo(const enum NvKmsStereoMode stereo)2431 static inline NvBool nvIs3DVisionStereoEvo(const enum NvKmsStereoMode stereo)
2432 {
2433 return (stereo == NVKMS_STEREO_NVIDIA_3D_VISION ||
2434 stereo == NVKMS_STEREO_NVIDIA_3D_VISION_PRO);
2435 }
2436
2437 /*
2438 * Utility macro for iterating over all head bits set in a head bit mask
2439 */
2440 #define FOR_ALL_HEADS(_head, _headMask) \
2441 for((_head) = 0; \
2442 (_headMask) >> (_head); \
2443 (_head)++) \
2444 if ((_headMask) & (1 << (_head)))
2445
2446 typedef struct _NVLutSurfaceEvo {
2447 NVDevEvoPtr pDevEvo;
2448
2449 NvU32 handle;
2450 NvU32 size;
2451
2452 NVSurfaceDescriptor surfaceDesc;
2453
2454 NvU32 allocRefCnt; /* Only used for dynamically allocated LUTs */
2455
2456 NvU64 gpuAddress;
2457 void *subDeviceAddress[NVKMS_MAX_SUBDEVICES];
2458
2459 /* Keep track of prefetched surfaces. */
2460 NvU32 difrLastPrefetchPass;
2461
2462 } NVLutSurfaceEvoRec;
2463
2464 typedef struct _NVFrameLockEvo {
2465 NVListRec frameLockListEntry;
2466
2467 /* array of subdev GPU IDs */
2468 NvU32 nGpuIds;
2469 NvU32 gpuIds[NV30F1_CTRL_MAX_GPUS_PER_GSYNC];
2470
2471 NvU32 gsyncId;
2472 NvU32 device; /* RM device handle for this object */
2473
2474 int fpgaIdAndRevision; /* FPGA revId (including firmware version
2475 * and board ID) */
2476
2477 int firmwareMajorVersion; /* FPGA firmware major version */
2478 int firmwareMinorVersion; /* FPGA firmware minor version */
2479 NvU32 boardId; /* NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_* */
2480 NvU32 caps; /* Various capabilities flags */
2481
2482 NvU32 maxSyncSkew; /* Max sync skew increment */
2483 NvU32 syncSkewResolution; /* In nanoseconds */
2484 NvU32 maxSyncInterval; /* Max sync interval */
2485
2486 NvU32 houseSyncUseable;
2487
2488 /* House sync mode requested by user */
2489 enum NvKmsFrameLockAttributeHouseSyncModeValue houseSyncMode;
2490 NvU32 houseSyncModeValidValues;
2491
2492 NvBool houseSyncAssy; /* Current desired state */
2493 NvBool houseSyncArmed; /* Current hardware state */
2494
2495 NvU8 connectedGpuMask; /* bitmask of GPUs that are connected */
2496 NvU8 syncReadyGpuMask; /* bitmask of GPUs that are syncReady */
2497
2498 NvBool syncReadyLast; /* Previous NV_CTRL_FRAMELOCK_SYNC_READY
2499 * value changed either from nvctrl or
2500 * the RM, used to avoid resending events
2501 * since RM doesn't trigger a SYNC_READY
2502 * event on framelock disable */
2503
2504 NvBool videoModeReadOnly; /* If video mode is read-only */
2505
2506 NvU32 maxMulDivValue; /* Max sync multiply/divide value */
2507
2508 NvBool mulDivSupported; /* Whether this board supports setting a sync
2509 * multiplier/divider; maxMulDivValue is only
2510 * valid if this is true */
2511
2512 /* Current device state */
2513 enum NvKmsFrameLockAttributePolarityValue polarity;
2514 NvU32 syncDelay;
2515 NvU32 syncInterval;
2516 enum NvKmsFrameLockAttributeVideoModeValue videoMode;
2517 NvU8 mulDivValue;
2518 enum NvKmsFrameLockAttributeMulDivModeValue mulDivMode;
2519 NvBool testMode;
2520
2521 NVUnixRmHandleAllocatorRec handleAllocator;
2522
2523 } NVFrameLockEvoRec;
2524
2525 /*!
2526 * The buffer that accumulates a string with information returned to
2527 * the client.
2528 */
2529 typedef struct _NVEvoInfoString {
2530 NvU16 length; /*! strlen(s); excludes the nul terminator */
2531 NvU16 totalLength; /*! number of bytes in the buffer pointed to by 's' */
2532 char *s; /*! pointer to the buffer to be written to */
2533 } NVEvoInfoStringRec;
2534
2535 enum NvHsMapPermissions {
2536 NvHsMapPermissionsNone,
2537 NvHsMapPermissionsReadOnly,
2538 NvHsMapPermissionsReadWrite,
2539 };
2540
2541 #define NV_HS_BAD_GPU_ADDRESS ((NvU64) -1)
2542
2543 #define NVKMS_SURFACE_MEMORY_FORMATS_RGB_PACKED1BPP ( \
2544 NVBIT64(NvKmsSurfaceMemoryFormatI8))
2545
2546 #define NVKMS_SURFACE_MEMORY_FORMATS_RGB_PACKED2BPP ( \
2547 NVBIT64(NvKmsSurfaceMemoryFormatA1R5G5B5) | \
2548 NVBIT64(NvKmsSurfaceMemoryFormatX1R5G5B5) | \
2549 NVBIT64(NvKmsSurfaceMemoryFormatR5G6B5))
2550
2551 #define NVKMS_SURFACE_MEMORY_FORMATS_RGB_PACKED4BPP ( \
2552 NVBIT64(NvKmsSurfaceMemoryFormatA8R8G8B8) | \
2553 NVBIT64(NvKmsSurfaceMemoryFormatX8R8G8B8) | \
2554 NVBIT64(NvKmsSurfaceMemoryFormatA2B10G10R10) | \
2555 NVBIT64(NvKmsSurfaceMemoryFormatX2B10G10R10) | \
2556 NVBIT64(NvKmsSurfaceMemoryFormatA8B8G8R8) | \
2557 NVBIT64(NvKmsSurfaceMemoryFormatX8B8G8R8))
2558
2559 #define NVKMS_SURFACE_MEMORY_FORMATS_RGB_PACKED8BPP ( \
2560 NVBIT64(NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) | \
2561 NVBIT64(NvKmsSurfaceMemoryFormatRF16GF16BF16XF16) | \
2562 NVBIT64(NvKmsSurfaceMemoryFormatR16G16B16A16))
2563
2564 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_PACKED422 ( \
2565 NVBIT64(NvKmsSurfaceMemoryFormatY8_U8__Y8_V8_N422) | \
2566 NVBIT64(NvKmsSurfaceMemoryFormatU8_Y8__V8_Y8_N422))
2567
2568 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_SP420 ( \
2569 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8V8_N420) | \
2570 NVBIT64(NvKmsSurfaceMemoryFormatY8___V8U8_N420))
2571
2572 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_SP422 ( \
2573 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8V8_N422) | \
2574 NVBIT64(NvKmsSurfaceMemoryFormatY8___V8U8_N422))
2575
2576 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_SP444 ( \
2577 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8V8_N444) | \
2578 NVBIT64(NvKmsSurfaceMemoryFormatY8___V8U8_N444))
2579
2580 #define NVKMS_SURFACE_MEMORY_FORMATS_EXT_YUV_SP420 ( \
2581 NVBIT64(NvKmsSurfaceMemoryFormatY10___U10V10_N420) | \
2582 NVBIT64(NvKmsSurfaceMemoryFormatY10___V10U10_N420) | \
2583 NVBIT64(NvKmsSurfaceMemoryFormatY12___U12V12_N420) | \
2584 NVBIT64(NvKmsSurfaceMemoryFormatY12___V12U12_N420))
2585
2586 #define NVKMS_SURFACE_MEMORY_FORMATS_EXT_YUV_SP422 ( \
2587 NVBIT64(NvKmsSurfaceMemoryFormatY10___U10V10_N422) | \
2588 NVBIT64(NvKmsSurfaceMemoryFormatY10___V10U10_N422) | \
2589 NVBIT64(NvKmsSurfaceMemoryFormatY12___U12V12_N422) | \
2590 NVBIT64(NvKmsSurfaceMemoryFormatY12___V12U12_N422))
2591
2592 #define NVKMS_SURFACE_MEMORY_FORMATS_EXT_YUV_SP444 ( \
2593 NVBIT64(NvKmsSurfaceMemoryFormatY10___U10V10_N444) | \
2594 NVBIT64(NvKmsSurfaceMemoryFormatY10___V10U10_N444) | \
2595 NVBIT64(NvKmsSurfaceMemoryFormatY12___U12V12_N444) | \
2596 NVBIT64(NvKmsSurfaceMemoryFormatY12___V12U12_N444))
2597
2598 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_PLANAR444 ( \
2599 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8___V8_N444))
2600
2601 #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_PLANAR420 ( \
2602 NVBIT64(NvKmsSurfaceMemoryFormatY8___U8___V8_N420))
2603
2604 struct _NVSurfaceEvoRec {
2605 /*
2606 * By default, all NVSurfaceEvoRecs will have requireDisplayHardwareAccess
2607 * as TRUE and on chips where ctxDma is supported, a ctxDma is allocated
2608 * and placed in the display engine hash table for each plane.
2609 *
2610 * But, if the client specified the noDisplayHardwareAccess flag,
2611 * requireDisplayHardwareAccess will be FALSE, and ctxDma will be 0 for
2612 * all planes.
2613 *
2614 * requireDisplayHardwareAccess is used to remember what the client
2615 * requested, so that we correctly honor noDisplayHardwareAccess across
2616 * FreeSurfaceCtxDmasForAllOpens() /
2617 * AllocSurfaceCtxDmasForAllOpens() cycles.
2618 */
2619 NvBool requireDisplayHardwareAccess;
2620
2621 struct {
2622 NvU32 rmHandle;
2623 NVSurfaceDescriptor surfaceDesc;
2624 NvU32 pitch;
2625 NvU64 offset;
2626 NvU64 rmObjectSizeInBytes;
2627 } planes[NVKMS_MAX_PLANES_PER_SURFACE];
2628
2629 struct {
2630 const struct NvKmsPerOpenDev *pOpenDev;
2631 NvKmsSurfaceHandle surfaceHandle;
2632 } owner;
2633
2634 NvU32 widthInPixels;
2635 NvU32 heightInPixels;
2636
2637 NvU32 log2GobsPerBlockY;
2638
2639 /*
2640 * GPU virtual address of the surface, in NVKMS's VA space for use by
2641 * headSurface.
2642 */
2643 NvU64 gpuAddress;
2644
2645 /*
2646 * HeadSurface needs a CPU mapping of surfaces containing semaphores.
2647 */
2648 void *cpuAddress[NVKMS_MAX_SUBDEVICES];
2649
2650 enum NvKmsSurfaceMemoryLayout layout;
2651 enum NvKmsSurfaceMemoryFormat format;
2652
2653 NvKmsMemoryIsoType isoType;
2654
2655 /*
2656 * A surface has two reference counts:
2657 *
2658 * - rmRefCnt indicates how many uses of the surface reference
2659 * NVSurfaceEvoRec::planes[]::rmHandle (the surface owner who registered
2660 * the surface, EVO currently displaying the surface, an open
2661 * surface grant file descriptor).
2662 *
2663 * - structRefCnt indicates how many uses of the surface reference
2664 * the NVSurfaceEvoRec. In addition to the rmRefCnt uses, this
2665 * will also count NVKMS clients who acquired the surface
2666 * through GRANT_SURFACE/ACQUIRE_SURFACE.
2667 *
2668 * When a client registers a surface, both reference counts will
2669 * be initialized to 1. The RM surface for each plane will be unduped when
2670 * rmRefCnt reaches zero. The NVSurfaceEvoRec structure will be
2671 * freed when structRefCnt reaches zero.
2672 *
2673 * In most cases, one of the following will be true:
2674 * (rmRefCnt == 0) && (structRefCnt == 0)
2675 * (rmRefCnt != 0) && (structRefCnt != 0)
2676 * The only exception is when the owner of the surface unregisters it while
2677 * other clients still have references to it; in that case, the rmRefCnt
2678 * can drop to zero while structRefCnt is still non-zero.
2679 *
2680 * If rmRefCnt reaches zero before structRefCnt, the surface is
2681 * "orphaned": it still exists in ACQUIRE_SURFACE clients' handle
2682 * namespaces and/or granted FDs, but is not usable in subsequent API
2683 * requests (e.g., to flip, specify cursor image, etc).
2684 *
2685 * Described in a table:
2686 *
2687 * ACTION rmRefCnt structRefCnt
2688 * a) NVKMS_IOCTL_REGISTER_SURFACE =1 =1
2689 * b) flip to surface +1 +1
2690 * c) NVKMS_IOCTL_GRANT_SURFACE(grantFd) n/a +1
2691 * d) NVKMS_IOCTL_ACQUIRE_SURFACE n/a +1
2692 * e) NVKMS_IOCTL_UNREGISTER_SURFACE -1 -1
2693 * f) flip away from surface -1 -1
2694 * g) close(grantFd) n/a -1
2695 * h) NVKMS_IOCTL_RELEASE_SURFACE n/a -1
2696 * i) ..._REGISTER_DEFERRED_REQUEST_FIFO +1 +1
2697 * j) ..._UNREGISTER_DEFERRED_REQUEST_FIFO -1 -1
2698 *
2699 * (e) complements (a)
2700 * (f) complements (b)
2701 * (g) complements (c)
2702 * (h) complements (d)
2703 * (j) complements (i)
2704 */
2705 NvU64 rmRefCnt;
2706 NvU64 structRefCnt;
2707
2708 #if NVKMS_PROCFS_ENABLE
2709 NvBool procFsFlag;
2710 #endif
2711
2712 /*
2713 * Disallow DIFR if display caching is forbidden. This will be set for
2714 * CPU accessible surfaces.
2715 */
2716 NvBool noDisplayCaching;
2717
2718 /* Keep track of prefetched surfaces. */
2719 NvU32 difrLastPrefetchPass;
2720 };
2721
2722 typedef struct _NVDeferredRequestFifoRec {
2723 NVSurfaceEvoPtr pSurfaceEvo;
2724 struct NvKmsDeferredRequestFifo *fifo;
2725
2726 /* A deferred request fifo may be joined to a swapGroup. */
2727 struct {
2728 NVSwapGroupPtr pSwapGroup;
2729 NVListRec deferredRequestFifoListEntry;
2730 NvBool ready;
2731 NvBool perEyeStereo;
2732 NvBool pendingJoined;
2733 NvBool pendingReady;
2734 NvU32 semaphoreIndex;
2735 struct NvKmsPerOpen *pOpenUnicastEvent;
2736 } swapGroup;
2737 } NVDeferredRequestFifoRec;
2738
2739 typedef struct _NVSwapGroupRec {
2740 NVListRec deferredRequestFifoList;
2741 NvBool zombie;
2742 NvBool pendingFlip;
2743 NvU32 nMembers;
2744 NvU32 nMembersReady;
2745 NvU32 nMembersPendingJoined;
2746
2747 NvU16 nClips;
2748 struct NvKmsRect *pClipList;
2749 NvBool swapGroupIsFullscreen;
2750
2751 NvU64 refCnt;
2752 } NVSwapGroupRec;
2753
2754 typedef struct {
2755 NvU32 clientHandle;
2756
2757 NVListRec devList;
2758 NVListRec frameLockList;
2759
2760 #if defined(DEBUG)
2761 NVListRec debugMemoryAllocationList;
2762 #endif
2763
2764 struct NvKmsPerOpen *nvKmsPerOpen;
2765 } NVEvoGlobal;
2766
2767 extern NVEvoGlobal nvEvoGlobal;
2768
2769 /*
2770 * These enums are used during IMP validation:
2771 * - NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE means that no changes will be made to
2772 * the current display bandwidth values.
2773 * - NV_EVO_REALLOCATE_BANDWIDTH_MODE_PRE means that NVKMS will increase the
2774 * current display bandwidth values if required by IMP. This is typically
2775 * specified pre-modeset/flip.
2776 * - NV_EVO_REALLOCATE_BANDWIDTH_MODE_POST means that NVKMS may potentially
2777 * decrease the current display bandwidth values to match the current display
2778 * configuration. This is typically specified post-modeset/flip.
2779 */
2780 typedef enum {
2781 NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE = 0,
2782 NV_EVO_REALLOCATE_BANDWIDTH_MODE_PRE = 1,
2783 NV_EVO_REALLOCATE_BANDWIDTH_MODE_POST = 2,
2784 } NVEvoReallocateBandwidthMode;
2785
2786 typedef struct {
2787 struct {
2788 /* pTimings == NULL => this head is disabled */
2789 const NVHwModeTimingsEvo *pTimings;
2790 NvBool enableDsc;
2791 NvBool b2Heads1Or;
2792 enum nvKmsPixelDepth pixelDepth;
2793 const struct NvKmsUsageBounds *pUsage;
2794 NvU32 displayId;
2795 NvU32 orIndex;
2796 NvU8 orType; /* NV0073_CTRL_SPECIFIC_OR_TYPE_* */
2797 } head[NVKMS_MAX_HEADS_PER_DISP];
2798
2799 NvBool requireBootClocks;
2800 NVEvoReallocateBandwidthMode reallocBandwidth;
2801 } NVEvoIsModePossibleDispInput;
2802
2803 typedef struct {
2804 NvBool possible;
2805 NvU32 minRequiredBandwidthKBPS;
2806 NvU32 floorBandwidthKBPS;
2807 } NVEvoIsModePossibleDispOutput;
2808
2809 /* CRC-query specific defines */
2810 /*!
2811 * Structure that defines information about where a single variable is stored in
2812 * the CRC32NotifierEntry structure
2813 */
2814 typedef struct _CRC32NotifierEntryRec {
2815 NvU32 field_offset; /* Var's offset from start of CRC32Notifier Struct */
2816 NvU32 field_base_bit; /* LSB bit index for variable in entry */
2817 NvU32 field_extent_bit; /* MSB bit index for variable in entry */
2818 struct NvKmsDpyCRC32 *field_frame_values; /* Array to store read field values across frames */
2819 } CRC32NotifierEntryRec;
2820
2821 /*!
2822 * Internally identifies flag read from CRC32Notifier's Status for error-checking
2823 */
2824 enum CRC32NotifierFlagType {
2825 NVEvoCrc32NotifierFlagCount,
2826 NVEvoCrc32NotifierFlagCrcOverflow,
2827 };
2828
2829 /*!
2830 * Structure that defines information about where a single flag is stored in
2831 * the Status of the CRC32NotifierEntry structure
2832 */
2833 typedef struct _CRC32NotifierEntryFlags {
2834 NvU32 flag_base_bit; /* LSB bit index for flag in entry */
2835 NvU32 flag_extent_bit; /* MSB bit index for flag in entry */
2836 enum CRC32NotifierFlagType flag_type; /* Type of error-checking to perform on flag */
2837 } CRC32NotifierEntryFlags;
2838
2839 /*!
2840 * Internal Crc32NotifierRead structure used to collect multiple frames of CRC
2841 * data from a QueryCRC32 call. Arrays should be allocated to match
2842 * entry_count frames.
2843 */
2844 typedef struct _CRC32NotifierCrcOut {
2845 /*!
2846 * Array of CRCs generated from the Compositor hardware
2847 */
2848 struct NvKmsDpyCRC32 *compositorCrc32;
2849
2850 /*!
2851 * CRCs generated from the RG hardware, if head is driving RG/SF.
2852 */
2853 struct NvKmsDpyCRC32 *rasterGeneratorCrc32;
2854
2855 /*!
2856 * Crc values generated from the target SF/OR depending on connector's OR type
2857 */
2858 struct NvKmsDpyCRC32 *outputCrc32;
2859
2860 } CRC32NotifierCrcOut;
2861
2862
2863 typedef const struct _nv_evo_hal {
2864 void (*SetRasterParams) (NVDevEvoPtr pDevEvo, int head,
2865 const NVHwModeTimingsEvo *pTimings,
2866 const NvU8 tilePosition,
2867 const NVDscInfoEvoRec *pDscInfo,
2868 const NVEvoColorRec *pOverscanColor,
2869 NVEvoUpdateState *updateState);
2870 void (*SetProcAmp) (NVDispEvoPtr pDispEvo, const NvU32 head,
2871 NVEvoUpdateState *updateState);
2872 void (*SetHeadControl) (NVDevEvoPtr, int sd, int head,
2873 NVEvoUpdateState *updateState);
2874 void (*SetHeadRefClk) (NVDevEvoPtr, int head, NvBool external,
2875 NVEvoUpdateState *updateState);
2876 void (*HeadSetControlOR) (NVDevEvoPtr pDevEvo,
2877 const int head,
2878 const NVHwModeTimingsEvo *pTimings,
2879 const enum nvKmsPixelDepth pixelDepth,
2880 const NvBool colorSpaceOverride,
2881 NVEvoUpdateState *updateState);
2882 void (*ORSetControl) (NVDevEvoPtr pDevEvo,
2883 const NVConnectorEvoRec *pConnectorEvo,
2884 const enum nvKmsTimingsProtocol protocol,
2885 const NvU32 orIndex,
2886 const NvU32 headMask,
2887 NVEvoUpdateState *updateState);
2888 void (*HeadSetDisplayId) (NVDevEvoPtr pDevEvo,
2889 const NvU32 head, const NvU32 displayId,
2890 NVEvoUpdateState *updateState);
2891 NvBool (*SetUsageBounds) (NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head,
2892 const struct NvKmsUsageBounds *pUsage,
2893 NVEvoUpdateState *updateState);
2894 void (*Update) (NVDevEvoPtr,
2895 const NVEvoUpdateState *updateState,
2896 NvBool releaseElv);
2897 void (*IsModePossible) (NVDispEvoPtr,
2898 const NVEvoIsModePossibleDispInput *,
2899 NVEvoIsModePossibleDispOutput *);
2900 void (*PrePostIMP) (NVDispEvoPtr, NvBool isPre);
2901 void (*SetNotifier) (NVDevEvoRec *pDevEvo,
2902 const NvBool notify,
2903 const NvBool awaken,
2904 const NvU32 notifier,
2905 NVEvoUpdateState *updateState);
2906 NvBool (*GetCapabilities) (NVDevEvoPtr);
2907 void (*Flip) (NVDevEvoPtr pDevEvo,
2908 NVEvoChannelPtr pChannel,
2909 const NVFlipChannelEvoHwState *pHwState,
2910 NVEvoUpdateState *updateState,
2911 NvBool bypassComposition);
2912 void (*FlipTransitionWAR) (NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head,
2913 const NVEvoSubDevHeadStateRec *pSdHeadState,
2914 const NVFlipEvoHwState *pFlipState,
2915 NVEvoUpdateState *updateState);
2916 void (*FillLUTSurface) (NVEvoLutEntryRec *pLUTBuffer,
2917 const NvU16 *red,
2918 const NvU16 *green,
2919 const NvU16 *blue,
2920 int nColorMapEntries, int depth);
2921 void (*SetLUTContextDma) (const NVDispEvoRec *pDispEvo,
2922 const int head,
2923 NVLutSurfaceEvoPtr pLutSurfEvo,
2924 NvBool enableBaseLut,
2925 NvBool enableOutputLut,
2926 NVEvoUpdateState *updateState,
2927 NvBool bypassComposition);
2928 void (*SetOutputScaler) (const NVDispEvoRec *pDispEvo, const NvU32 head,
2929 const NvU32 imageSharpeningValue,
2930 NVEvoUpdateState *updateState);
2931 void (*SetViewportPointIn) (NVDevEvoPtr pDevEvo, const int head,
2932 NvU16 x, NvU16 y,
2933 NVEvoUpdateState *updateState);
2934 void (*SetViewportInOut) (NVDevEvoPtr pDevEvo, const int head,
2935 const NVHwModeViewPortEvo *pViewPortOutMin,
2936 const NVHwModeViewPortEvo *pViewPortOut,
2937 const NVHwModeViewPortEvo *pViewPortOutMax,
2938 NVEvoUpdateState *updateState);
2939 void (*SetCursorImage) (NVDevEvoPtr pDevEvo, const int head,
2940 const NVSurfaceEvoRec *,
2941 NVEvoUpdateState *updateState,
2942 const struct NvKmsCompositionParams *pCursorCompParams);
2943 NvBool (*ValidateCursorSurface)(const NVDevEvoRec *pDevEvo,
2944 const NVSurfaceEvoRec *pSurfaceEvo);
2945 NvBool (*ValidateWindowFormat)(const enum NvKmsSurfaceMemoryFormat format,
2946 const struct NvKmsRect *sourceFetchRect,
2947 NvU32 *hwFormatOut);
2948 void (*InitCompNotifier) (const NVDispEvoRec *pDispEvo, int idx);
2949 NvBool (*IsCompNotifierComplete) (NVDispEvoPtr pDispEvo, int idx);
2950 void (*WaitForCompNotifier) (const NVDispEvoRec *pDispEvo, int idx);
2951 void (*SetDither) (NVDispEvoPtr pDispEvo, const int head,
2952 const NvBool enabled, const NvU32 type,
2953 const NvU32 algo,
2954 NVEvoUpdateState *updateState);
2955 void (*SetStallLock) (NVDispEvoPtr pDispEvo, const int head,
2956 NvBool enable, NVEvoUpdateState *updateState);
2957 void (*SetDisplayRate) (NVDispEvoPtr pDispEvo, const int head,
2958 NvBool enable,
2959 NVEvoUpdateState *updateState,
2960 NvU32 timeoutMicroseconds);
2961 void (*InitChannel) (NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel);
2962 void (*InitDefaultLut) (NVDevEvoPtr pDevEvo);
2963 void (*InitWindowMapping) (const NVDispEvoRec *pDispEvo,
2964 NVEvoModesetUpdateState *pModesetUpdateState);
2965 NvBool (*IsChannelIdle) (NVDevEvoPtr, NVEvoChannelPtr, NvU32 sd,
2966 NvBool *result);
2967 NvBool (*IsChannelMethodPending)(NVDevEvoPtr, NVEvoChannelPtr, NvU32 sd,
2968 NvBool *result);
2969 NvBool (*ForceIdleSatelliteChannel)(NVDevEvoPtr,
2970 const NVEvoIdleChannelState *idleChannelState);
2971 NvBool (*ForceIdleSatelliteChannelIgnoreLock)(NVDevEvoPtr,
2972 const NVEvoIdleChannelState *idleChannelState);
2973
2974 void (*AccelerateChannel)(NVDevEvoPtr pDevEvo,
2975 NVEvoChannelPtr pChannel,
2976 const NvU32 sd,
2977 const NvBool trashPendingMethods,
2978 const NvBool unblockMethodsInExecutation,
2979 NvU32 *pOldAccelerators);
2980
2981 void (*ResetChannelAccelerators)(NVDevEvoPtr pDevEvo,
2982 NVEvoChannelPtr pChannel,
2983 const NvU32 sd,
2984 const NvBool trashPendingMethods,
2985 const NvBool unblockMethodsInExecutation,
2986 NvU32 oldAccelerators);
2987
2988 NvBool (*AllocRmCtrlObject) (NVDevEvoPtr);
2989 void (*FreeRmCtrlObject) (NVDevEvoPtr);
2990 void (*SetImmPointOut) (NVDevEvoPtr, NVEvoChannelPtr, NvU32 sd,
2991 NVEvoUpdateState *updateState,
2992 NvU16 x, NvU16 y);
2993 void (*StartCRC32Capture) (NVDevEvoPtr pDevEvo,
2994 NVEvoDmaPtr pDma,
2995 NVConnectorEvoPtr pConnectorEvo,
2996 const enum nvKmsTimingsProtocol protocol,
2997 const NvU32 orIndex,
2998 NvU32 head,
2999 NvU32 sd,
3000 NVEvoUpdateState *updateState /* out */);
3001 void (*StopCRC32Capture) (NVDevEvoPtr pDevEvo,
3002 NvU32 head,
3003 NVEvoUpdateState *updateState /* out */);
3004 NvBool (*QueryCRC32) (NVDevEvoPtr pDevEvo,
3005 NVEvoDmaPtr pDma,
3006 NvU32 sd,
3007 NvU32 entry_count,
3008 CRC32NotifierCrcOut *crc32 /* out */,
3009 NvU32 *numCRC32 /* out */);
3010 void (*GetScanLine) (const NVDispEvoRec *pDispEvo,
3011 const NvU32 head,
3012 NvU16 *pScanLine,
3013 NvBool *pInBlankingPeriod);
3014 void (*ConfigureVblankSyncObject) (NVDevEvoPtr pDevEvo,
3015 NvU16 rasterLine,
3016 NvU32 head,
3017 NvU32 semaphoreIndex,
3018 const NVSurfaceDescriptor *pSurfaceDesc,
3019 NVEvoUpdateState* pUpdateState);
3020
3021 void (*SetDscParams) (const NVDispEvoRec *pDispEvo,
3022 const NvU32 head,
3023 const NVDscInfoEvoRec *pDscInfo,
3024 const enum nvKmsPixelDepth pixelDepth);
3025
3026 void (*EnableMidFrameAndDWCFWatermark)(NVDevEvoPtr pDevEvo,
3027 NvU32 sd,
3028 NvU32 head,
3029 NvBool enable,
3030 NVEvoUpdateState *pUpdateState);
3031
3032 NvU32 (*GetActiveViewportOffset)(NVDispEvoRec *pDispEvo, NvU32 head);
3033
3034 void (*ClearSurfaceUsage) (NVDevEvoPtr pDevEvo,
3035 NVSurfaceEvoPtr pSurfaceEvo);
3036
3037 NvBool (*ComputeWindowScalingTaps)(const NVDevEvoRec *pDevEvo,
3038 const NVEvoChannel *pChannel,
3039 NVFlipChannelEvoHwState *pHwState);
3040
3041 const NVEvoScalerCaps* (*GetWindowScalingCaps)(const NVDevEvoRec *pDevEvo);
3042
3043 void (*SetMergeMode)(const NVDispEvoRec *pDispEvo,
3044 const NvU32 head,
3045 const NVEvoMergeMode mode,
3046 NVEvoUpdateState* pUpdateState);
3047
3048 NvU32 (*AllocSurfaceDescriptor) (NVDevEvoPtr pDevEvo,
3049 NVSurfaceDescriptor *pSurfaceDesc,
3050 NvU32 memoryHandle,
3051 NvU32 localCtxDmaFlags,
3052 NvU64 limit);
3053
3054 void (*FreeSurfaceDescriptor) (NVDevEvoPtr pDevEvo,
3055 NvU32 deviceHandle,
3056 NVSurfaceDescriptor *pSurfaceDesc);
3057
3058 NvU32 (*BindSurfaceDescriptor) (NVDevEvoPtr pDevEvo,
3059 NVEvoChannelPtr pChannel,
3060 NVSurfaceDescriptor *pSurfaceDesc);
3061
3062 void (*SetTmoLutSurfaceAddress) (NVEvoChannelPtr pChannel,
3063 const NVSurfaceDescriptor *pSurfaceDesc,
3064 NvU32 offset);
3065
3066 void (*SetILUTSurfaceAddress) (NVEvoChannelPtr pChannel,
3067 const NVSurfaceDescriptor *pSurfaceDesc,
3068 NvU32 offset);
3069
3070 void (*SetISOSurfaceAddress) (NVEvoChannelPtr pChannel,
3071 const NVSurfaceDescriptor *pSurfaceDesc,
3072 NvU32 offset,
3073 NvU32 ctxDmaIdx,
3074 NvBool isBlocklinear);
3075
3076 void (*SetCoreNotifierSurfaceAddressAndControl) (NVEvoChannelPtr pChannel,
3077 const NVSurfaceDescriptor *pSurfaceDesc,
3078 NvU32 notifierOffset,
3079 NvU32 ctrlVal);
3080
3081 void (*SetWinNotifierSurfaceAddressAndControl) (NVEvoChannelPtr pChannel,
3082 const NVSurfaceDescriptor *pSurfaceDesc,
3083 NvU32 notifierOffset,
3084 NvU32 ctrlVal);
3085
3086 void (*SetSemaphoreSurfaceAddressAndControl) (NVEvoChannelPtr pChannel,
3087 const NVSurfaceDescriptor *pSurfaceDesc,
3088 NvU32 semaphoreOffset,
3089 NvU32 ctrlVal);
3090
3091 void (*SetAcqSemaphoreSurfaceAddressAndControl) (NVEvoChannelPtr pChannel,
3092 const NVSurfaceDescriptor *pSurfaceDesc,
3093 NvU32 semaphoreOffset,
3094 NvU32 ctrlVal);
3095
3096 struct {
3097 NvU32 supportsNonInterlockedUsageBoundsUpdate :1;
3098 NvU32 supportsDisplayRate :1;
3099 NvU32 supportsFlipLockRGStatus :1;
3100 NvU32 needDefaultLutSurface :1;
3101 NvU32 hasUnorm16OLUT :1;
3102 NvU32 supportsImageSharpening :1;
3103 NvU32 supportsHDMIVRR :1;
3104 NvU32 supportsCoreChannelSurface :1;
3105 NvU32 supportsHDMIFRL :1;
3106 NvU32 supportsSetStorageMemoryLayout :1;
3107 NvU32 supportsIndependentAcqRelSemaphore :1;
3108 NvU32 supportsCoreLut :1;
3109 NvU32 supportsSynchronizedOverlayPositionUpdate :1;
3110 NvU32 supportsVblankSyncObjects :1;
3111 NvU32 requiresScalingTapsInBothDimensions :1;
3112 NvU32 supportsMergeMode :1;
3113 NvU32 supportsHDMI10BPC :1;
3114
3115 NvU32 supportedDitheringModes;
3116 size_t impStructSize;
3117 NVEvoScalerTaps minScalerTaps;
3118 NvU64 xEmulatedSurfaceMemoryFormats;
3119 } caps;
3120 } NVEvoHAL, *NVEvoHALPtr;
3121
3122 typedef const struct _nv_evo_cursor_hal {
3123 NvU32 klass;
3124
3125 void (*MoveCursor) (NVDevEvoPtr, NvU32 sd, NvU32 head,
3126 NvS16 x, NvS16 y);
3127 void (*ReleaseElv) (NVDevEvoPtr, NvU32 sd, NvU32 head);
3128
3129 struct {
3130 NvU16 maxSize;
3131 } caps;
3132 } NVEvoCursorHAL, *NVEvoCursorHALPtr;
3133
3134 NvU32 nvEvoGetHeadSetStoragePitchValue(const NVDevEvoRec *pDevEvo,
3135 enum NvKmsSurfaceMemoryLayout layout,
3136 NvU32 pitch);
3137
3138 NvBool nvEvoGetHeadSetControlCursorValue90(const NVDevEvoRec *pDevEvo,
3139 const NVSurfaceEvoRec *pSurfaceEvo,
3140 NvU32 *pValue);
3141
nvEvoScalingUsageBoundsEqual(const struct NvKmsScalingUsageBounds * a,const struct NvKmsScalingUsageBounds * b)3142 static inline NvBool nvEvoScalingUsageBoundsEqual(
3143 const struct NvKmsScalingUsageBounds *a,
3144 const struct NvKmsScalingUsageBounds *b)
3145 {
3146 return (a->maxVDownscaleFactor == b->maxVDownscaleFactor) &&
3147 (a->maxHDownscaleFactor == b->maxHDownscaleFactor) &&
3148 (a->vTaps == b->vTaps) &&
3149 (a->vUpscalingAllowed == b->vUpscalingAllowed);
3150 }
3151
3152 static inline NvBool
nvEvoLayerUsageBoundsEqual(const struct NvKmsUsageBounds * a,const struct NvKmsUsageBounds * b,const NvU32 layer)3153 nvEvoLayerUsageBoundsEqual(const struct NvKmsUsageBounds *a,
3154 const struct NvKmsUsageBounds *b,
3155 const NvU32 layer)
3156 {
3157 return (a->layer[layer].usable == b->layer[layer].usable) &&
3158 (a->layer[layer].supportedSurfaceMemoryFormats ==
3159 b->layer[layer].supportedSurfaceMemoryFormats) &&
3160 nvEvoScalingUsageBoundsEqual(&a->layer[layer].scaling,
3161 &b->layer[layer].scaling);
3162 }
3163
nvAssignHwHeadsMaskApiHeadState(NVDispApiHeadStateEvoRec * pApiHeadState,const NvU32 hwHeadsMask)3164 static inline void nvAssignHwHeadsMaskApiHeadState(
3165 NVDispApiHeadStateEvoRec *pApiHeadState,
3166 const NvU32 hwHeadsMask)
3167 {
3168 pApiHeadState->hwHeadsMask = hwHeadsMask;
3169 pApiHeadState->attributes.numberOfHardwareHeadsUsed =
3170 nvPopCount32(hwHeadsMask);
3171 }
3172
3173 typedef struct _NVVblankSemControl {
3174 NvU32 dispIndex;
3175 NvU32 hwHead;
3176 NvU64 surfaceOffset;
3177 NVSurfaceEvoRec *pSurfaceEvo;
3178 } NVVblankSemControl;
3179
3180 #ifdef __cplusplus
3181 };
3182 #endif
3183
3184 #endif /* __NVKMS_TYPES_H__ */
3185