1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #ifndef _LINUX_NVME_H
8 #define _LINUX_NVME_H
9
10 #include <linux/bits.h>
11 #include <linux/types.h>
12 #include <linux/uuid.h>
13
14 /* NQN names in commands fields specified one size */
15 #define NVMF_NQN_FIELD_LEN 256
16
17 /* However the max length of a qualified name is another size */
18 #define NVMF_NQN_SIZE 223
19
20 #define NVMF_TRSVCID_SIZE 32
21 #define NVMF_TRADDR_SIZE 256
22 #define NVMF_TSAS_SIZE 256
23
24 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
25
26 #define NVME_NSID_ALL 0xffffffff
27
28 enum nvme_subsys_type {
29 /* Referral to another discovery type target subsystem */
30 NVME_NQN_DISC = 1,
31
32 /* NVME type target subsystem */
33 NVME_NQN_NVME = 2,
34
35 /* Current discovery type target subsystem */
36 NVME_NQN_CURR = 3,
37 };
38
39 enum nvme_ctrl_type {
40 NVME_CTRL_IO = 1, /* I/O controller */
41 NVME_CTRL_DISC = 2, /* Discovery controller */
42 NVME_CTRL_ADMIN = 3, /* Administrative controller */
43 };
44
45 enum nvme_dctype {
46 NVME_DCTYPE_NOT_REPORTED = 0,
47 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */
48 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */
49 };
50
51 /* Address Family codes for Discovery Log Page entry ADRFAM field */
52 enum {
53 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
54 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
55 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
56 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
57 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
58 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
59 NVMF_ADDR_FAMILY_MAX,
60 };
61
62 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
63 enum {
64 NVMF_TRTYPE_RDMA = 1, /* RDMA */
65 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
66 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
67 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
68 NVMF_TRTYPE_MAX,
69 };
70
71 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
72 enum {
73 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
74 NVMF_TREQ_REQUIRED = 1, /* Required */
75 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
76 #define NVME_TREQ_SECURE_CHANNEL_MASK \
77 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
78
79 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
80 };
81
82 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
83 * RDMA_QPTYPE field
84 */
85 enum {
86 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
87 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
88 };
89
90 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
91 * RDMA_QPTYPE field
92 */
93 enum {
94 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
95 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
96 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
97 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
98 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
99 };
100
101 /* RDMA Connection Management Service Type codes for Discovery Log Page
102 * entry TSAS RDMA_CMS field
103 */
104 enum {
105 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
106 };
107
108 /* TSAS SECTYPE for TCP transport */
109 enum {
110 NVMF_TCP_SECTYPE_NONE = 0, /* No Security */
111 NVMF_TCP_SECTYPE_TLS12 = 1, /* TLSv1.2, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
112 NVMF_TCP_SECTYPE_TLS13 = 2, /* TLSv1.3, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
113 };
114
115 #define NVME_AQ_DEPTH 32
116 #define NVME_NR_AEN_COMMANDS 1
117 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
118
119 /*
120 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
121 * NVM-Express 1.2 specification, section 4.1.2.
122 */
123 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
124
125 enum {
126 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
127 NVME_REG_VS = 0x0008, /* Version */
128 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
129 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
130 NVME_REG_CC = 0x0014, /* Controller Configuration */
131 NVME_REG_CSTS = 0x001c, /* Controller Status */
132 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
133 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
134 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
135 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
136 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
137 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
138 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
139 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
140 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
141 * Location
142 */
143 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
144 * Space Control
145 */
146 NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */
147 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
148 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
149 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
150 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
151 * Buffer Size
152 */
153 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
154 * Write Throughput
155 */
156 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
157 };
158
159 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
160 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
161 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
162 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
163 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
164 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
165 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
166 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
167
168 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
169 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
170
171 #define NVME_CRTO_CRIMT(crto) ((crto) >> 16)
172 #define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff)
173
174 enum {
175 NVME_CMBSZ_SQS = 1 << 0,
176 NVME_CMBSZ_CQS = 1 << 1,
177 NVME_CMBSZ_LISTS = 1 << 2,
178 NVME_CMBSZ_RDS = 1 << 3,
179 NVME_CMBSZ_WDS = 1 << 4,
180
181 NVME_CMBSZ_SZ_SHIFT = 12,
182 NVME_CMBSZ_SZ_MASK = 0xfffff,
183
184 NVME_CMBSZ_SZU_SHIFT = 8,
185 NVME_CMBSZ_SZU_MASK = 0xf,
186 };
187
188 /*
189 * Submission and Completion Queue Entry Sizes for the NVM command set.
190 * (In bytes and specified as a power of two (2^n)).
191 */
192 #define NVME_ADM_SQES 6
193 #define NVME_NVM_IOSQES 6
194 #define NVME_NVM_IOCQES 4
195
196 enum {
197 NVME_CC_ENABLE = 1 << 0,
198 NVME_CC_EN_SHIFT = 0,
199 NVME_CC_CSS_SHIFT = 4,
200 NVME_CC_MPS_SHIFT = 7,
201 NVME_CC_AMS_SHIFT = 11,
202 NVME_CC_SHN_SHIFT = 14,
203 NVME_CC_IOSQES_SHIFT = 16,
204 NVME_CC_IOCQES_SHIFT = 20,
205 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
206 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
207 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
208 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
209 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
210 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
211 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
212 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
213 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
214 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
215 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
216 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
217 NVME_CC_CRIME = 1 << 24,
218 };
219
220 enum {
221 NVME_CSTS_RDY = 1 << 0,
222 NVME_CSTS_CFS = 1 << 1,
223 NVME_CSTS_NSSRO = 1 << 4,
224 NVME_CSTS_PP = 1 << 5,
225 NVME_CSTS_SHST_NORMAL = 0 << 2,
226 NVME_CSTS_SHST_OCCUR = 1 << 2,
227 NVME_CSTS_SHST_CMPLT = 2 << 2,
228 NVME_CSTS_SHST_MASK = 3 << 2,
229 };
230
231 enum {
232 NVME_CMBMSC_CRE = 1 << 0,
233 NVME_CMBMSC_CMSE = 1 << 1,
234 };
235
236 enum {
237 NVME_CAP_CSS_NVM = 1 << 0,
238 NVME_CAP_CSS_CSI = 1 << 6,
239 };
240
241 enum {
242 NVME_CAP_CRMS_CRWMS = 1ULL << 59,
243 NVME_CAP_CRMS_CRIMS = 1ULL << 60,
244 };
245
246 struct nvme_id_power_state {
247 __le16 max_power; /* centiwatts */
248 __u8 rsvd2;
249 __u8 flags;
250 __le32 entry_lat; /* microseconds */
251 __le32 exit_lat; /* microseconds */
252 __u8 read_tput;
253 __u8 read_lat;
254 __u8 write_tput;
255 __u8 write_lat;
256 __le16 idle_power;
257 __u8 idle_scale;
258 __u8 rsvd19;
259 __le16 active_power;
260 __u8 active_work_scale;
261 __u8 rsvd23[9];
262 };
263
264 enum {
265 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
266 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
267 };
268
269 enum nvme_ctrl_attr {
270 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
271 NVME_CTRL_ATTR_TBKAS = (1 << 6),
272 NVME_CTRL_ATTR_ELBAS = (1 << 15),
273 };
274
275 struct nvme_id_ctrl {
276 __le16 vid;
277 __le16 ssvid;
278 char sn[20];
279 char mn[40];
280 char fr[8];
281 __u8 rab;
282 __u8 ieee[3];
283 __u8 cmic;
284 __u8 mdts;
285 __le16 cntlid;
286 __le32 ver;
287 __le32 rtd3r;
288 __le32 rtd3e;
289 __le32 oaes;
290 __le32 ctratt;
291 __u8 rsvd100[11];
292 __u8 cntrltype;
293 __u8 fguid[16];
294 __le16 crdt1;
295 __le16 crdt2;
296 __le16 crdt3;
297 __u8 rsvd134[122];
298 __le16 oacs;
299 __u8 acl;
300 __u8 aerl;
301 __u8 frmw;
302 __u8 lpa;
303 __u8 elpe;
304 __u8 npss;
305 __u8 avscc;
306 __u8 apsta;
307 __le16 wctemp;
308 __le16 cctemp;
309 __le16 mtfa;
310 __le32 hmpre;
311 __le32 hmmin;
312 __u8 tnvmcap[16];
313 __u8 unvmcap[16];
314 __le32 rpmbs;
315 __le16 edstt;
316 __u8 dsto;
317 __u8 fwug;
318 __le16 kas;
319 __le16 hctma;
320 __le16 mntmt;
321 __le16 mxtmt;
322 __le32 sanicap;
323 __le32 hmminds;
324 __le16 hmmaxd;
325 __u8 rsvd338[4];
326 __u8 anatt;
327 __u8 anacap;
328 __le32 anagrpmax;
329 __le32 nanagrpid;
330 __u8 rsvd352[160];
331 __u8 sqes;
332 __u8 cqes;
333 __le16 maxcmd;
334 __le32 nn;
335 __le16 oncs;
336 __le16 fuses;
337 __u8 fna;
338 __u8 vwc;
339 __le16 awun;
340 __le16 awupf;
341 __u8 nvscc;
342 __u8 nwpc;
343 __le16 acwu;
344 __u8 rsvd534[2];
345 __le32 sgls;
346 __le32 mnan;
347 __u8 rsvd544[224];
348 char subnqn[256];
349 __u8 rsvd1024[768];
350 __le32 ioccsz;
351 __le32 iorcsz;
352 __le16 icdoff;
353 __u8 ctrattr;
354 __u8 msdbd;
355 __u8 rsvd1804[2];
356 __u8 dctype;
357 __u8 rsvd1807[241];
358 struct nvme_id_power_state psd[32];
359 __u8 vs[1024];
360 };
361
362 enum {
363 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0,
364 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
365 NVME_CTRL_CMIC_ANA = 1 << 3,
366 NVME_CTRL_ONCS_COMPARE = 1 << 0,
367 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
368 NVME_CTRL_ONCS_DSM = 1 << 2,
369 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
370 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
371 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
372 NVME_CTRL_VWC_PRESENT = 1 << 0,
373 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
374 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3,
375 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
376 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
377 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
378 NVME_CTRL_CTRATT_128_ID = 1 << 0,
379 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
380 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
381 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
382 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
383 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
384 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
385 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
386 };
387
388 struct nvme_lbaf {
389 __le16 ms;
390 __u8 ds;
391 __u8 rp;
392 };
393
394 struct nvme_id_ns {
395 __le64 nsze;
396 __le64 ncap;
397 __le64 nuse;
398 __u8 nsfeat;
399 __u8 nlbaf;
400 __u8 flbas;
401 __u8 mc;
402 __u8 dpc;
403 __u8 dps;
404 __u8 nmic;
405 __u8 rescap;
406 __u8 fpi;
407 __u8 dlfeat;
408 __le16 nawun;
409 __le16 nawupf;
410 __le16 nacwu;
411 __le16 nabsn;
412 __le16 nabo;
413 __le16 nabspf;
414 __le16 noiob;
415 __u8 nvmcap[16];
416 __le16 npwg;
417 __le16 npwa;
418 __le16 npdg;
419 __le16 npda;
420 __le16 nows;
421 __u8 rsvd74[18];
422 __le32 anagrpid;
423 __u8 rsvd96[3];
424 __u8 nsattr;
425 __le16 nvmsetid;
426 __le16 endgid;
427 __u8 nguid[16];
428 __u8 eui64[8];
429 struct nvme_lbaf lbaf[64];
430 __u8 vs[3712];
431 };
432
433 /* I/O Command Set Independent Identify Namespace Data Structure */
434 struct nvme_id_ns_cs_indep {
435 __u8 nsfeat;
436 __u8 nmic;
437 __u8 rescap;
438 __u8 fpi;
439 __le32 anagrpid;
440 __u8 nsattr;
441 __u8 rsvd9;
442 __le16 nvmsetid;
443 __le16 endgid;
444 __u8 nstat;
445 __u8 rsvd15[4081];
446 };
447
448 struct nvme_zns_lbafe {
449 __le64 zsze;
450 __u8 zdes;
451 __u8 rsvd9[7];
452 };
453
454 struct nvme_id_ns_zns {
455 __le16 zoc;
456 __le16 ozcs;
457 __le32 mar;
458 __le32 mor;
459 __le32 rrl;
460 __le32 frl;
461 __u8 rsvd20[2796];
462 struct nvme_zns_lbafe lbafe[64];
463 __u8 vs[256];
464 };
465
466 struct nvme_id_ctrl_zns {
467 __u8 zasl;
468 __u8 rsvd1[4095];
469 };
470
471 struct nvme_id_ns_nvm {
472 __le64 lbstm;
473 __u8 pic;
474 __u8 rsvd9[3];
475 __le32 elbaf[64];
476 __u8 rsvd268[3828];
477 };
478
479 enum {
480 NVME_ID_NS_NVM_STS_MASK = 0x7f,
481 NVME_ID_NS_NVM_GUARD_SHIFT = 7,
482 NVME_ID_NS_NVM_GUARD_MASK = 0x3,
483 };
484
nvme_elbaf_sts(__u32 elbaf)485 static inline __u8 nvme_elbaf_sts(__u32 elbaf)
486 {
487 return elbaf & NVME_ID_NS_NVM_STS_MASK;
488 }
489
nvme_elbaf_guard_type(__u32 elbaf)490 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
491 {
492 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
493 }
494
495 struct nvme_id_ctrl_nvm {
496 __u8 vsl;
497 __u8 wzsl;
498 __u8 wusl;
499 __u8 dmrl;
500 __le32 dmrsl;
501 __le64 dmsl;
502 __u8 rsvd16[4080];
503 };
504
505 enum {
506 NVME_ID_CNS_NS = 0x00,
507 NVME_ID_CNS_CTRL = 0x01,
508 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
509 NVME_ID_CNS_NS_DESC_LIST = 0x03,
510 NVME_ID_CNS_CS_NS = 0x05,
511 NVME_ID_CNS_CS_CTRL = 0x06,
512 NVME_ID_CNS_NS_CS_INDEP = 0x08,
513 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
514 NVME_ID_CNS_NS_PRESENT = 0x11,
515 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
516 NVME_ID_CNS_CTRL_LIST = 0x13,
517 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
518 NVME_ID_CNS_NS_GRANULARITY = 0x16,
519 NVME_ID_CNS_UUID_LIST = 0x17,
520 };
521
522 enum {
523 NVME_CSI_NVM = 0,
524 NVME_CSI_ZNS = 2,
525 };
526
527 enum {
528 NVME_DIR_IDENTIFY = 0x00,
529 NVME_DIR_STREAMS = 0x01,
530 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
531 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
532 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
533 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
534 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
535 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
536 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
537 NVME_DIR_ENDIR = 0x01,
538 };
539
540 enum {
541 NVME_NS_FEAT_THIN = 1 << 0,
542 NVME_NS_FEAT_ATOMICS = 1 << 1,
543 NVME_NS_FEAT_IO_OPT = 1 << 4,
544 NVME_NS_ATTR_RO = 1 << 0,
545 NVME_NS_FLBAS_LBA_MASK = 0xf,
546 NVME_NS_FLBAS_LBA_UMASK = 0x60,
547 NVME_NS_FLBAS_LBA_SHIFT = 1,
548 NVME_NS_FLBAS_META_EXT = 0x10,
549 NVME_NS_NMIC_SHARED = 1 << 0,
550 NVME_LBAF_RP_BEST = 0,
551 NVME_LBAF_RP_BETTER = 1,
552 NVME_LBAF_RP_GOOD = 2,
553 NVME_LBAF_RP_DEGRADED = 3,
554 NVME_NS_DPC_PI_LAST = 1 << 4,
555 NVME_NS_DPC_PI_FIRST = 1 << 3,
556 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
557 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
558 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
559 NVME_NS_DPS_PI_FIRST = 1 << 3,
560 NVME_NS_DPS_PI_MASK = 0x7,
561 NVME_NS_DPS_PI_TYPE1 = 1,
562 NVME_NS_DPS_PI_TYPE2 = 2,
563 NVME_NS_DPS_PI_TYPE3 = 3,
564 };
565
566 enum {
567 NVME_NSTAT_NRDY = 1 << 0,
568 };
569
570 enum {
571 NVME_NVM_NS_16B_GUARD = 0,
572 NVME_NVM_NS_32B_GUARD = 1,
573 NVME_NVM_NS_64B_GUARD = 2,
574 };
575
nvme_lbaf_index(__u8 flbas)576 static inline __u8 nvme_lbaf_index(__u8 flbas)
577 {
578 return (flbas & NVME_NS_FLBAS_LBA_MASK) |
579 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
580 }
581
582 /* Identify Namespace Metadata Capabilities (MC): */
583 enum {
584 NVME_MC_EXTENDED_LBA = (1 << 0),
585 NVME_MC_METADATA_PTR = (1 << 1),
586 };
587
588 struct nvme_ns_id_desc {
589 __u8 nidt;
590 __u8 nidl;
591 __le16 reserved;
592 };
593
594 #define NVME_NIDT_EUI64_LEN 8
595 #define NVME_NIDT_NGUID_LEN 16
596 #define NVME_NIDT_UUID_LEN 16
597 #define NVME_NIDT_CSI_LEN 1
598
599 enum {
600 NVME_NIDT_EUI64 = 0x01,
601 NVME_NIDT_NGUID = 0x02,
602 NVME_NIDT_UUID = 0x03,
603 NVME_NIDT_CSI = 0x04,
604 };
605
606 struct nvme_smart_log {
607 __u8 critical_warning;
608 __u8 temperature[2];
609 __u8 avail_spare;
610 __u8 spare_thresh;
611 __u8 percent_used;
612 __u8 endu_grp_crit_warn_sumry;
613 __u8 rsvd7[25];
614 __u8 data_units_read[16];
615 __u8 data_units_written[16];
616 __u8 host_reads[16];
617 __u8 host_writes[16];
618 __u8 ctrl_busy_time[16];
619 __u8 power_cycles[16];
620 __u8 power_on_hours[16];
621 __u8 unsafe_shutdowns[16];
622 __u8 media_errors[16];
623 __u8 num_err_log_entries[16];
624 __le32 warning_temp_time;
625 __le32 critical_comp_time;
626 __le16 temp_sensor[8];
627 __le32 thm_temp1_trans_count;
628 __le32 thm_temp2_trans_count;
629 __le32 thm_temp1_total_time;
630 __le32 thm_temp2_total_time;
631 __u8 rsvd232[280];
632 };
633
634 struct nvme_fw_slot_info_log {
635 __u8 afi;
636 __u8 rsvd1[7];
637 __le64 frs[7];
638 __u8 rsvd64[448];
639 };
640
641 enum {
642 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
643 NVME_CMD_EFFECTS_LBCC = 1 << 1,
644 NVME_CMD_EFFECTS_NCC = 1 << 2,
645 NVME_CMD_EFFECTS_NIC = 1 << 3,
646 NVME_CMD_EFFECTS_CCC = 1 << 4,
647 NVME_CMD_EFFECTS_CSER_MASK = GENMASK(15, 14),
648 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),
649 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
650 NVME_CMD_EFFECTS_SCOPE_MASK = GENMASK(31, 20),
651 };
652
653 struct nvme_effects_log {
654 __le32 acs[256];
655 __le32 iocs[256];
656 __u8 resv[2048];
657 };
658
659 enum nvme_ana_state {
660 NVME_ANA_OPTIMIZED = 0x01,
661 NVME_ANA_NONOPTIMIZED = 0x02,
662 NVME_ANA_INACCESSIBLE = 0x03,
663 NVME_ANA_PERSISTENT_LOSS = 0x04,
664 NVME_ANA_CHANGE = 0x0f,
665 };
666
667 struct nvme_ana_group_desc {
668 __le32 grpid;
669 __le32 nnsids;
670 __le64 chgcnt;
671 __u8 state;
672 __u8 rsvd17[15];
673 __le32 nsids[];
674 };
675
676 /* flag for the log specific field of the ANA log */
677 #define NVME_ANA_LOG_RGO (1 << 0)
678
679 struct nvme_ana_rsp_hdr {
680 __le64 chgcnt;
681 __le16 ngrps;
682 __le16 rsvd10[3];
683 };
684
685 struct nvme_zone_descriptor {
686 __u8 zt;
687 __u8 zs;
688 __u8 za;
689 __u8 rsvd3[5];
690 __le64 zcap;
691 __le64 zslba;
692 __le64 wp;
693 __u8 rsvd32[32];
694 };
695
696 enum {
697 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
698 };
699
700 struct nvme_zone_report {
701 __le64 nr_zones;
702 __u8 resv8[56];
703 struct nvme_zone_descriptor entries[];
704 };
705
706 enum {
707 NVME_SMART_CRIT_SPARE = 1 << 0,
708 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
709 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
710 NVME_SMART_CRIT_MEDIA = 1 << 3,
711 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
712 };
713
714 enum {
715 NVME_AER_ERROR = 0,
716 NVME_AER_SMART = 1,
717 NVME_AER_NOTICE = 2,
718 NVME_AER_CSS = 6,
719 NVME_AER_VS = 7,
720 };
721
722 enum {
723 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
724 };
725
726 enum {
727 NVME_AER_NOTICE_NS_CHANGED = 0x00,
728 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
729 NVME_AER_NOTICE_ANA = 0x03,
730 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
731 };
732
733 enum {
734 NVME_AEN_BIT_NS_ATTR = 8,
735 NVME_AEN_BIT_FW_ACT = 9,
736 NVME_AEN_BIT_ANA_CHANGE = 11,
737 NVME_AEN_BIT_DISC_CHANGE = 31,
738 };
739
740 enum {
741 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
742 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
743 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
744 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
745 };
746
747 struct nvme_lba_range_type {
748 __u8 type;
749 __u8 attributes;
750 __u8 rsvd2[14];
751 __le64 slba;
752 __le64 nlb;
753 __u8 guid[16];
754 __u8 rsvd48[16];
755 };
756
757 enum {
758 NVME_LBART_TYPE_FS = 0x01,
759 NVME_LBART_TYPE_RAID = 0x02,
760 NVME_LBART_TYPE_CACHE = 0x03,
761 NVME_LBART_TYPE_SWAP = 0x04,
762
763 NVME_LBART_ATTRIB_TEMP = 1 << 0,
764 NVME_LBART_ATTRIB_HIDE = 1 << 1,
765 };
766
767 enum nvme_pr_type {
768 NVME_PR_WRITE_EXCLUSIVE = 1,
769 NVME_PR_EXCLUSIVE_ACCESS = 2,
770 NVME_PR_WRITE_EXCLUSIVE_REG_ONLY = 3,
771 NVME_PR_EXCLUSIVE_ACCESS_REG_ONLY = 4,
772 NVME_PR_WRITE_EXCLUSIVE_ALL_REGS = 5,
773 NVME_PR_EXCLUSIVE_ACCESS_ALL_REGS = 6,
774 };
775
776 enum nvme_eds {
777 NVME_EXTENDED_DATA_STRUCT = 0x1,
778 };
779
780 struct nvme_registered_ctrl {
781 __le16 cntlid;
782 __u8 rcsts;
783 __u8 rsvd3[5];
784 __le64 hostid;
785 __le64 rkey;
786 };
787
788 struct nvme_reservation_status {
789 __le32 gen;
790 __u8 rtype;
791 __u8 regctl[2];
792 __u8 resv5[2];
793 __u8 ptpls;
794 __u8 resv10[14];
795 struct nvme_registered_ctrl regctl_ds[];
796 };
797
798 struct nvme_registered_ctrl_ext {
799 __le16 cntlid;
800 __u8 rcsts;
801 __u8 rsvd3[5];
802 __le64 rkey;
803 __u8 hostid[16];
804 __u8 rsvd32[32];
805 };
806
807 struct nvme_reservation_status_ext {
808 __le32 gen;
809 __u8 rtype;
810 __u8 regctl[2];
811 __u8 resv5[2];
812 __u8 ptpls;
813 __u8 resv10[14];
814 __u8 rsvd24[40];
815 struct nvme_registered_ctrl_ext regctl_eds[];
816 };
817
818 /* I/O commands */
819
820 enum nvme_opcode {
821 nvme_cmd_flush = 0x00,
822 nvme_cmd_write = 0x01,
823 nvme_cmd_read = 0x02,
824 nvme_cmd_write_uncor = 0x04,
825 nvme_cmd_compare = 0x05,
826 nvme_cmd_write_zeroes = 0x08,
827 nvme_cmd_dsm = 0x09,
828 nvme_cmd_verify = 0x0c,
829 nvme_cmd_resv_register = 0x0d,
830 nvme_cmd_resv_report = 0x0e,
831 nvme_cmd_resv_acquire = 0x11,
832 nvme_cmd_resv_release = 0x15,
833 nvme_cmd_zone_mgmt_send = 0x79,
834 nvme_cmd_zone_mgmt_recv = 0x7a,
835 nvme_cmd_zone_append = 0x7d,
836 nvme_cmd_vendor_start = 0x80,
837 };
838
839 #define nvme_opcode_name(opcode) { opcode, #opcode }
840 #define show_nvm_opcode_name(val) \
841 __print_symbolic(val, \
842 nvme_opcode_name(nvme_cmd_flush), \
843 nvme_opcode_name(nvme_cmd_write), \
844 nvme_opcode_name(nvme_cmd_read), \
845 nvme_opcode_name(nvme_cmd_write_uncor), \
846 nvme_opcode_name(nvme_cmd_compare), \
847 nvme_opcode_name(nvme_cmd_write_zeroes), \
848 nvme_opcode_name(nvme_cmd_dsm), \
849 nvme_opcode_name(nvme_cmd_verify), \
850 nvme_opcode_name(nvme_cmd_resv_register), \
851 nvme_opcode_name(nvme_cmd_resv_report), \
852 nvme_opcode_name(nvme_cmd_resv_acquire), \
853 nvme_opcode_name(nvme_cmd_resv_release), \
854 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
855 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
856 nvme_opcode_name(nvme_cmd_zone_append))
857
858
859
860 /*
861 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
862 *
863 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
864 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
865 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
866 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
867 * request subtype
868 */
869 enum {
870 NVME_SGL_FMT_ADDRESS = 0x00,
871 NVME_SGL_FMT_OFFSET = 0x01,
872 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
873 NVME_SGL_FMT_INVALIDATE = 0x0f,
874 };
875
876 /*
877 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
878 *
879 * For struct nvme_sgl_desc:
880 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
881 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
882 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
883 *
884 * For struct nvme_keyed_sgl_desc:
885 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
886 *
887 * Transport-specific SGL types:
888 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
889 */
890 enum {
891 NVME_SGL_FMT_DATA_DESC = 0x00,
892 NVME_SGL_FMT_SEG_DESC = 0x02,
893 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
894 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
895 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
896 };
897
898 struct nvme_sgl_desc {
899 __le64 addr;
900 __le32 length;
901 __u8 rsvd[3];
902 __u8 type;
903 };
904
905 struct nvme_keyed_sgl_desc {
906 __le64 addr;
907 __u8 length[3];
908 __u8 key[4];
909 __u8 type;
910 };
911
912 union nvme_data_ptr {
913 struct {
914 __le64 prp1;
915 __le64 prp2;
916 };
917 struct nvme_sgl_desc sgl;
918 struct nvme_keyed_sgl_desc ksgl;
919 };
920
921 /*
922 * Lowest two bits of our flags field (FUSE field in the spec):
923 *
924 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
925 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
926 *
927 * Highest two bits in our flags field (PSDT field in the spec):
928 *
929 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
930 * If used, MPTR contains addr of single physical buffer (byte aligned).
931 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
932 * If used, MPTR contains an address of an SGL segment containing
933 * exactly 1 SGL descriptor (qword aligned).
934 */
935 enum {
936 NVME_CMD_FUSE_FIRST = (1 << 0),
937 NVME_CMD_FUSE_SECOND = (1 << 1),
938
939 NVME_CMD_SGL_METABUF = (1 << 6),
940 NVME_CMD_SGL_METASEG = (1 << 7),
941 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
942 };
943
944 struct nvme_common_command {
945 __u8 opcode;
946 __u8 flags;
947 __u16 command_id;
948 __le32 nsid;
949 __le32 cdw2[2];
950 __le64 metadata;
951 union nvme_data_ptr dptr;
952 struct_group(cdws,
953 __le32 cdw10;
954 __le32 cdw11;
955 __le32 cdw12;
956 __le32 cdw13;
957 __le32 cdw14;
958 __le32 cdw15;
959 );
960 };
961
962 struct nvme_rw_command {
963 __u8 opcode;
964 __u8 flags;
965 __u16 command_id;
966 __le32 nsid;
967 __le32 cdw2;
968 __le32 cdw3;
969 __le64 metadata;
970 union nvme_data_ptr dptr;
971 __le64 slba;
972 __le16 length;
973 __le16 control;
974 __le32 dsmgmt;
975 __le32 reftag;
976 __le16 apptag;
977 __le16 appmask;
978 };
979
980 enum {
981 NVME_RW_LR = 1 << 15,
982 NVME_RW_FUA = 1 << 14,
983 NVME_RW_APPEND_PIREMAP = 1 << 9,
984 NVME_RW_DSM_FREQ_UNSPEC = 0,
985 NVME_RW_DSM_FREQ_TYPICAL = 1,
986 NVME_RW_DSM_FREQ_RARE = 2,
987 NVME_RW_DSM_FREQ_READS = 3,
988 NVME_RW_DSM_FREQ_WRITES = 4,
989 NVME_RW_DSM_FREQ_RW = 5,
990 NVME_RW_DSM_FREQ_ONCE = 6,
991 NVME_RW_DSM_FREQ_PREFETCH = 7,
992 NVME_RW_DSM_FREQ_TEMP = 8,
993 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
994 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
995 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
996 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
997 NVME_RW_DSM_SEQ_REQ = 1 << 6,
998 NVME_RW_DSM_COMPRESSED = 1 << 7,
999 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
1000 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
1001 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
1002 NVME_RW_PRINFO_PRACT = 1 << 13,
1003 NVME_RW_DTYPE_STREAMS = 1 << 4,
1004 NVME_WZ_DEAC = 1 << 9,
1005 };
1006
1007 struct nvme_dsm_cmd {
1008 __u8 opcode;
1009 __u8 flags;
1010 __u16 command_id;
1011 __le32 nsid;
1012 __u64 rsvd2[2];
1013 union nvme_data_ptr dptr;
1014 __le32 nr;
1015 __le32 attributes;
1016 __u32 rsvd12[4];
1017 };
1018
1019 enum {
1020 NVME_DSMGMT_IDR = 1 << 0,
1021 NVME_DSMGMT_IDW = 1 << 1,
1022 NVME_DSMGMT_AD = 1 << 2,
1023 };
1024
1025 #define NVME_DSM_MAX_RANGES 256
1026
1027 struct nvme_dsm_range {
1028 __le32 cattr;
1029 __le32 nlb;
1030 __le64 slba;
1031 };
1032
1033 struct nvme_write_zeroes_cmd {
1034 __u8 opcode;
1035 __u8 flags;
1036 __u16 command_id;
1037 __le32 nsid;
1038 __u64 rsvd2;
1039 __le64 metadata;
1040 union nvme_data_ptr dptr;
1041 __le64 slba;
1042 __le16 length;
1043 __le16 control;
1044 __le32 dsmgmt;
1045 __le32 reftag;
1046 __le16 apptag;
1047 __le16 appmask;
1048 };
1049
1050 enum nvme_zone_mgmt_action {
1051 NVME_ZONE_CLOSE = 0x1,
1052 NVME_ZONE_FINISH = 0x2,
1053 NVME_ZONE_OPEN = 0x3,
1054 NVME_ZONE_RESET = 0x4,
1055 NVME_ZONE_OFFLINE = 0x5,
1056 NVME_ZONE_SET_DESC_EXT = 0x10,
1057 };
1058
1059 struct nvme_zone_mgmt_send_cmd {
1060 __u8 opcode;
1061 __u8 flags;
1062 __u16 command_id;
1063 __le32 nsid;
1064 __le32 cdw2[2];
1065 __le64 metadata;
1066 union nvme_data_ptr dptr;
1067 __le64 slba;
1068 __le32 cdw12;
1069 __u8 zsa;
1070 __u8 select_all;
1071 __u8 rsvd13[2];
1072 __le32 cdw14[2];
1073 };
1074
1075 struct nvme_zone_mgmt_recv_cmd {
1076 __u8 opcode;
1077 __u8 flags;
1078 __u16 command_id;
1079 __le32 nsid;
1080 __le64 rsvd2[2];
1081 union nvme_data_ptr dptr;
1082 __le64 slba;
1083 __le32 numd;
1084 __u8 zra;
1085 __u8 zrasf;
1086 __u8 pr;
1087 __u8 rsvd13;
1088 __le32 cdw14[2];
1089 };
1090
1091 enum {
1092 NVME_ZRA_ZONE_REPORT = 0,
1093 NVME_ZRASF_ZONE_REPORT_ALL = 0,
1094 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
1095 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02,
1096 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03,
1097 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04,
1098 NVME_ZRASF_ZONE_STATE_READONLY = 0x05,
1099 NVME_ZRASF_ZONE_STATE_FULL = 0x06,
1100 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07,
1101 NVME_REPORT_ZONE_PARTIAL = 1,
1102 };
1103
1104 /* Features */
1105
1106 enum {
1107 NVME_TEMP_THRESH_MASK = 0xffff,
1108 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
1109 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
1110 };
1111
1112 struct nvme_feat_auto_pst {
1113 __le64 entries[32];
1114 };
1115
1116 enum {
1117 NVME_HOST_MEM_ENABLE = (1 << 0),
1118 NVME_HOST_MEM_RETURN = (1 << 1),
1119 };
1120
1121 struct nvme_feat_host_behavior {
1122 __u8 acre;
1123 __u8 etdas;
1124 __u8 lbafee;
1125 __u8 resv1[509];
1126 };
1127
1128 enum {
1129 NVME_ENABLE_ACRE = 1,
1130 NVME_ENABLE_LBAFEE = 1,
1131 };
1132
1133 /* Admin commands */
1134
1135 enum nvme_admin_opcode {
1136 nvme_admin_delete_sq = 0x00,
1137 nvme_admin_create_sq = 0x01,
1138 nvme_admin_get_log_page = 0x02,
1139 nvme_admin_delete_cq = 0x04,
1140 nvme_admin_create_cq = 0x05,
1141 nvme_admin_identify = 0x06,
1142 nvme_admin_abort_cmd = 0x08,
1143 nvme_admin_set_features = 0x09,
1144 nvme_admin_get_features = 0x0a,
1145 nvme_admin_async_event = 0x0c,
1146 nvme_admin_ns_mgmt = 0x0d,
1147 nvme_admin_activate_fw = 0x10,
1148 nvme_admin_download_fw = 0x11,
1149 nvme_admin_dev_self_test = 0x14,
1150 nvme_admin_ns_attach = 0x15,
1151 nvme_admin_keep_alive = 0x18,
1152 nvme_admin_directive_send = 0x19,
1153 nvme_admin_directive_recv = 0x1a,
1154 nvme_admin_virtual_mgmt = 0x1c,
1155 nvme_admin_nvme_mi_send = 0x1d,
1156 nvme_admin_nvme_mi_recv = 0x1e,
1157 nvme_admin_dbbuf = 0x7C,
1158 nvme_admin_format_nvm = 0x80,
1159 nvme_admin_security_send = 0x81,
1160 nvme_admin_security_recv = 0x82,
1161 nvme_admin_sanitize_nvm = 0x84,
1162 nvme_admin_get_lba_status = 0x86,
1163 nvme_admin_vendor_start = 0xC0,
1164 };
1165
1166 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1167 #define show_admin_opcode_name(val) \
1168 __print_symbolic(val, \
1169 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1170 nvme_admin_opcode_name(nvme_admin_create_sq), \
1171 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1172 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1173 nvme_admin_opcode_name(nvme_admin_create_cq), \
1174 nvme_admin_opcode_name(nvme_admin_identify), \
1175 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1176 nvme_admin_opcode_name(nvme_admin_set_features), \
1177 nvme_admin_opcode_name(nvme_admin_get_features), \
1178 nvme_admin_opcode_name(nvme_admin_async_event), \
1179 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1180 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1181 nvme_admin_opcode_name(nvme_admin_download_fw), \
1182 nvme_admin_opcode_name(nvme_admin_dev_self_test), \
1183 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1184 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1185 nvme_admin_opcode_name(nvme_admin_directive_send), \
1186 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1187 nvme_admin_opcode_name(nvme_admin_virtual_mgmt), \
1188 nvme_admin_opcode_name(nvme_admin_nvme_mi_send), \
1189 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv), \
1190 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1191 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1192 nvme_admin_opcode_name(nvme_admin_security_send), \
1193 nvme_admin_opcode_name(nvme_admin_security_recv), \
1194 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1195 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1196
1197 enum {
1198 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1199 NVME_CQ_IRQ_ENABLED = (1 << 1),
1200 NVME_SQ_PRIO_URGENT = (0 << 1),
1201 NVME_SQ_PRIO_HIGH = (1 << 1),
1202 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1203 NVME_SQ_PRIO_LOW = (3 << 1),
1204 NVME_FEAT_ARBITRATION = 0x01,
1205 NVME_FEAT_POWER_MGMT = 0x02,
1206 NVME_FEAT_LBA_RANGE = 0x03,
1207 NVME_FEAT_TEMP_THRESH = 0x04,
1208 NVME_FEAT_ERR_RECOVERY = 0x05,
1209 NVME_FEAT_VOLATILE_WC = 0x06,
1210 NVME_FEAT_NUM_QUEUES = 0x07,
1211 NVME_FEAT_IRQ_COALESCE = 0x08,
1212 NVME_FEAT_IRQ_CONFIG = 0x09,
1213 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1214 NVME_FEAT_ASYNC_EVENT = 0x0b,
1215 NVME_FEAT_AUTO_PST = 0x0c,
1216 NVME_FEAT_HOST_MEM_BUF = 0x0d,
1217 NVME_FEAT_TIMESTAMP = 0x0e,
1218 NVME_FEAT_KATO = 0x0f,
1219 NVME_FEAT_HCTM = 0x10,
1220 NVME_FEAT_NOPSC = 0x11,
1221 NVME_FEAT_RRL = 0x12,
1222 NVME_FEAT_PLM_CONFIG = 0x13,
1223 NVME_FEAT_PLM_WINDOW = 0x14,
1224 NVME_FEAT_HOST_BEHAVIOR = 0x16,
1225 NVME_FEAT_SANITIZE = 0x17,
1226 NVME_FEAT_SW_PROGRESS = 0x80,
1227 NVME_FEAT_HOST_ID = 0x81,
1228 NVME_FEAT_RESV_MASK = 0x82,
1229 NVME_FEAT_RESV_PERSIST = 0x83,
1230 NVME_FEAT_WRITE_PROTECT = 0x84,
1231 NVME_FEAT_VENDOR_START = 0xC0,
1232 NVME_FEAT_VENDOR_END = 0xFF,
1233 NVME_LOG_ERROR = 0x01,
1234 NVME_LOG_SMART = 0x02,
1235 NVME_LOG_FW_SLOT = 0x03,
1236 NVME_LOG_CHANGED_NS = 0x04,
1237 NVME_LOG_CMD_EFFECTS = 0x05,
1238 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1239 NVME_LOG_TELEMETRY_HOST = 0x07,
1240 NVME_LOG_TELEMETRY_CTRL = 0x08,
1241 NVME_LOG_ENDURANCE_GROUP = 0x09,
1242 NVME_LOG_ANA = 0x0c,
1243 NVME_LOG_DISC = 0x70,
1244 NVME_LOG_RESERVATION = 0x80,
1245 NVME_FWACT_REPL = (0 << 3),
1246 NVME_FWACT_REPL_ACTV = (1 << 3),
1247 NVME_FWACT_ACTV = (2 << 3),
1248 };
1249
1250 /* NVMe Namespace Write Protect State */
1251 enum {
1252 NVME_NS_NO_WRITE_PROTECT = 0,
1253 NVME_NS_WRITE_PROTECT,
1254 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1255 NVME_NS_WRITE_PROTECT_PERMANENT,
1256 };
1257
1258 #define NVME_MAX_CHANGED_NAMESPACES 1024
1259
1260 struct nvme_identify {
1261 __u8 opcode;
1262 __u8 flags;
1263 __u16 command_id;
1264 __le32 nsid;
1265 __u64 rsvd2[2];
1266 union nvme_data_ptr dptr;
1267 __u8 cns;
1268 __u8 rsvd3;
1269 __le16 ctrlid;
1270 __u8 rsvd11[3];
1271 __u8 csi;
1272 __u32 rsvd12[4];
1273 };
1274
1275 #define NVME_IDENTIFY_DATA_SIZE 4096
1276
1277 struct nvme_features {
1278 __u8 opcode;
1279 __u8 flags;
1280 __u16 command_id;
1281 __le32 nsid;
1282 __u64 rsvd2[2];
1283 union nvme_data_ptr dptr;
1284 __le32 fid;
1285 __le32 dword11;
1286 __le32 dword12;
1287 __le32 dword13;
1288 __le32 dword14;
1289 __le32 dword15;
1290 };
1291
1292 struct nvme_host_mem_buf_desc {
1293 __le64 addr;
1294 __le32 size;
1295 __u32 rsvd;
1296 };
1297
1298 struct nvme_create_cq {
1299 __u8 opcode;
1300 __u8 flags;
1301 __u16 command_id;
1302 __u32 rsvd1[5];
1303 __le64 prp1;
1304 __u64 rsvd8;
1305 __le16 cqid;
1306 __le16 qsize;
1307 __le16 cq_flags;
1308 __le16 irq_vector;
1309 __u32 rsvd12[4];
1310 };
1311
1312 struct nvme_create_sq {
1313 __u8 opcode;
1314 __u8 flags;
1315 __u16 command_id;
1316 __u32 rsvd1[5];
1317 __le64 prp1;
1318 __u64 rsvd8;
1319 __le16 sqid;
1320 __le16 qsize;
1321 __le16 sq_flags;
1322 __le16 cqid;
1323 __u32 rsvd12[4];
1324 };
1325
1326 struct nvme_delete_queue {
1327 __u8 opcode;
1328 __u8 flags;
1329 __u16 command_id;
1330 __u32 rsvd1[9];
1331 __le16 qid;
1332 __u16 rsvd10;
1333 __u32 rsvd11[5];
1334 };
1335
1336 struct nvme_abort_cmd {
1337 __u8 opcode;
1338 __u8 flags;
1339 __u16 command_id;
1340 __u32 rsvd1[9];
1341 __le16 sqid;
1342 __u16 cid;
1343 __u32 rsvd11[5];
1344 };
1345
1346 struct nvme_download_firmware {
1347 __u8 opcode;
1348 __u8 flags;
1349 __u16 command_id;
1350 __u32 rsvd1[5];
1351 union nvme_data_ptr dptr;
1352 __le32 numd;
1353 __le32 offset;
1354 __u32 rsvd12[4];
1355 };
1356
1357 struct nvme_format_cmd {
1358 __u8 opcode;
1359 __u8 flags;
1360 __u16 command_id;
1361 __le32 nsid;
1362 __u64 rsvd2[4];
1363 __le32 cdw10;
1364 __u32 rsvd11[5];
1365 };
1366
1367 struct nvme_get_log_page_command {
1368 __u8 opcode;
1369 __u8 flags;
1370 __u16 command_id;
1371 __le32 nsid;
1372 __u64 rsvd2[2];
1373 union nvme_data_ptr dptr;
1374 __u8 lid;
1375 __u8 lsp; /* upper 4 bits reserved */
1376 __le16 numdl;
1377 __le16 numdu;
1378 __u16 rsvd11;
1379 union {
1380 struct {
1381 __le32 lpol;
1382 __le32 lpou;
1383 };
1384 __le64 lpo;
1385 };
1386 __u8 rsvd14[3];
1387 __u8 csi;
1388 __u32 rsvd15;
1389 };
1390
1391 struct nvme_directive_cmd {
1392 __u8 opcode;
1393 __u8 flags;
1394 __u16 command_id;
1395 __le32 nsid;
1396 __u64 rsvd2[2];
1397 union nvme_data_ptr dptr;
1398 __le32 numd;
1399 __u8 doper;
1400 __u8 dtype;
1401 __le16 dspec;
1402 __u8 endir;
1403 __u8 tdtype;
1404 __u16 rsvd15;
1405
1406 __u32 rsvd16[3];
1407 };
1408
1409 /*
1410 * Fabrics subcommands.
1411 */
1412 enum nvmf_fabrics_opcode {
1413 nvme_fabrics_command = 0x7f,
1414 };
1415
1416 enum nvmf_capsule_command {
1417 nvme_fabrics_type_property_set = 0x00,
1418 nvme_fabrics_type_connect = 0x01,
1419 nvme_fabrics_type_property_get = 0x04,
1420 nvme_fabrics_type_auth_send = 0x05,
1421 nvme_fabrics_type_auth_receive = 0x06,
1422 };
1423
1424 #define nvme_fabrics_type_name(type) { type, #type }
1425 #define show_fabrics_type_name(type) \
1426 __print_symbolic(type, \
1427 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1428 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1429 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1430 nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \
1431 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
1432
1433 /*
1434 * If not fabrics command, fctype will be ignored.
1435 */
1436 #define show_opcode_name(qid, opcode, fctype) \
1437 ((opcode) == nvme_fabrics_command ? \
1438 show_fabrics_type_name(fctype) : \
1439 ((qid) ? \
1440 show_nvm_opcode_name(opcode) : \
1441 show_admin_opcode_name(opcode)))
1442
1443 struct nvmf_common_command {
1444 __u8 opcode;
1445 __u8 resv1;
1446 __u16 command_id;
1447 __u8 fctype;
1448 __u8 resv2[35];
1449 __u8 ts[24];
1450 };
1451
1452 /*
1453 * The legal cntlid range a NVMe Target will provide.
1454 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1455 * Devices based on earlier specs did not have the subsystem concept;
1456 * therefore, those devices had their cntlid value set to 0 as a result.
1457 */
1458 #define NVME_CNTLID_MIN 1
1459 #define NVME_CNTLID_MAX 0xffef
1460 #define NVME_CNTLID_DYNAMIC 0xffff
1461
1462 #define MAX_DISC_LOGS 255
1463
1464 /* Discovery log page entry flags (EFLAGS): */
1465 enum {
1466 NVME_DISC_EFLAGS_EPCSD = (1 << 1),
1467 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0),
1468 };
1469
1470 /* Discovery log page entry */
1471 struct nvmf_disc_rsp_page_entry {
1472 __u8 trtype;
1473 __u8 adrfam;
1474 __u8 subtype;
1475 __u8 treq;
1476 __le16 portid;
1477 __le16 cntlid;
1478 __le16 asqsz;
1479 __le16 eflags;
1480 __u8 resv10[20];
1481 char trsvcid[NVMF_TRSVCID_SIZE];
1482 __u8 resv64[192];
1483 char subnqn[NVMF_NQN_FIELD_LEN];
1484 char traddr[NVMF_TRADDR_SIZE];
1485 union tsas {
1486 char common[NVMF_TSAS_SIZE];
1487 struct rdma {
1488 __u8 qptype;
1489 __u8 prtype;
1490 __u8 cms;
1491 __u8 resv3[5];
1492 __u16 pkey;
1493 __u8 resv10[246];
1494 } rdma;
1495 struct tcp {
1496 __u8 sectype;
1497 } tcp;
1498 } tsas;
1499 };
1500
1501 /* Discovery log page header */
1502 struct nvmf_disc_rsp_page_hdr {
1503 __le64 genctr;
1504 __le64 numrec;
1505 __le16 recfmt;
1506 __u8 resv14[1006];
1507 struct nvmf_disc_rsp_page_entry entries[];
1508 };
1509
1510 enum {
1511 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1512 };
1513
1514 struct nvmf_connect_command {
1515 __u8 opcode;
1516 __u8 resv1;
1517 __u16 command_id;
1518 __u8 fctype;
1519 __u8 resv2[19];
1520 union nvme_data_ptr dptr;
1521 __le16 recfmt;
1522 __le16 qid;
1523 __le16 sqsize;
1524 __u8 cattr;
1525 __u8 resv3;
1526 __le32 kato;
1527 __u8 resv4[12];
1528 };
1529
1530 enum {
1531 NVME_CONNECT_AUTHREQ_ASCR = (1U << 18),
1532 NVME_CONNECT_AUTHREQ_ATR = (1U << 17),
1533 };
1534
1535 struct nvmf_connect_data {
1536 uuid_t hostid;
1537 __le16 cntlid;
1538 char resv4[238];
1539 char subsysnqn[NVMF_NQN_FIELD_LEN];
1540 char hostnqn[NVMF_NQN_FIELD_LEN];
1541 char resv5[256];
1542 };
1543
1544 struct nvmf_property_set_command {
1545 __u8 opcode;
1546 __u8 resv1;
1547 __u16 command_id;
1548 __u8 fctype;
1549 __u8 resv2[35];
1550 __u8 attrib;
1551 __u8 resv3[3];
1552 __le32 offset;
1553 __le64 value;
1554 __u8 resv4[8];
1555 };
1556
1557 struct nvmf_property_get_command {
1558 __u8 opcode;
1559 __u8 resv1;
1560 __u16 command_id;
1561 __u8 fctype;
1562 __u8 resv2[35];
1563 __u8 attrib;
1564 __u8 resv3[3];
1565 __le32 offset;
1566 __u8 resv4[16];
1567 };
1568
1569 struct nvmf_auth_common_command {
1570 __u8 opcode;
1571 __u8 resv1;
1572 __u16 command_id;
1573 __u8 fctype;
1574 __u8 resv2[19];
1575 union nvme_data_ptr dptr;
1576 __u8 resv3;
1577 __u8 spsp0;
1578 __u8 spsp1;
1579 __u8 secp;
1580 __le32 al_tl;
1581 __u8 resv4[16];
1582 };
1583
1584 struct nvmf_auth_send_command {
1585 __u8 opcode;
1586 __u8 resv1;
1587 __u16 command_id;
1588 __u8 fctype;
1589 __u8 resv2[19];
1590 union nvme_data_ptr dptr;
1591 __u8 resv3;
1592 __u8 spsp0;
1593 __u8 spsp1;
1594 __u8 secp;
1595 __le32 tl;
1596 __u8 resv4[16];
1597 };
1598
1599 struct nvmf_auth_receive_command {
1600 __u8 opcode;
1601 __u8 resv1;
1602 __u16 command_id;
1603 __u8 fctype;
1604 __u8 resv2[19];
1605 union nvme_data_ptr dptr;
1606 __u8 resv3;
1607 __u8 spsp0;
1608 __u8 spsp1;
1609 __u8 secp;
1610 __le32 al;
1611 __u8 resv4[16];
1612 };
1613
1614 /* Value for secp */
1615 enum {
1616 NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9,
1617 };
1618
1619 /* Defined value for auth_type */
1620 enum {
1621 NVME_AUTH_COMMON_MESSAGES = 0x00,
1622 NVME_AUTH_DHCHAP_MESSAGES = 0x01,
1623 };
1624
1625 /* Defined messages for auth_id */
1626 enum {
1627 NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00,
1628 NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01,
1629 NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02,
1630 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03,
1631 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04,
1632 NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0,
1633 NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1,
1634 };
1635
1636 struct nvmf_auth_dhchap_protocol_descriptor {
1637 __u8 authid;
1638 __u8 rsvd;
1639 __u8 halen;
1640 __u8 dhlen;
1641 __u8 idlist[60];
1642 };
1643
1644 enum {
1645 NVME_AUTH_DHCHAP_AUTH_ID = 0x01,
1646 };
1647
1648 /* Defined hash functions for DH-HMAC-CHAP authentication */
1649 enum {
1650 NVME_AUTH_HASH_SHA256 = 0x01,
1651 NVME_AUTH_HASH_SHA384 = 0x02,
1652 NVME_AUTH_HASH_SHA512 = 0x03,
1653 NVME_AUTH_HASH_INVALID = 0xff,
1654 };
1655
1656 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1657 enum {
1658 NVME_AUTH_DHGROUP_NULL = 0x00,
1659 NVME_AUTH_DHGROUP_2048 = 0x01,
1660 NVME_AUTH_DHGROUP_3072 = 0x02,
1661 NVME_AUTH_DHGROUP_4096 = 0x03,
1662 NVME_AUTH_DHGROUP_6144 = 0x04,
1663 NVME_AUTH_DHGROUP_8192 = 0x05,
1664 NVME_AUTH_DHGROUP_INVALID = 0xff,
1665 };
1666
1667 union nvmf_auth_protocol {
1668 struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1669 };
1670
1671 struct nvmf_auth_dhchap_negotiate_data {
1672 __u8 auth_type;
1673 __u8 auth_id;
1674 __le16 rsvd;
1675 __le16 t_id;
1676 __u8 sc_c;
1677 __u8 napd;
1678 union nvmf_auth_protocol auth_protocol[];
1679 };
1680
1681 struct nvmf_auth_dhchap_challenge_data {
1682 __u8 auth_type;
1683 __u8 auth_id;
1684 __u16 rsvd1;
1685 __le16 t_id;
1686 __u8 hl;
1687 __u8 rsvd2;
1688 __u8 hashid;
1689 __u8 dhgid;
1690 __le16 dhvlen;
1691 __le32 seqnum;
1692 /* 'hl' bytes of challenge value */
1693 __u8 cval[];
1694 /* followed by 'dhvlen' bytes of DH value */
1695 };
1696
1697 struct nvmf_auth_dhchap_reply_data {
1698 __u8 auth_type;
1699 __u8 auth_id;
1700 __le16 rsvd1;
1701 __le16 t_id;
1702 __u8 hl;
1703 __u8 rsvd2;
1704 __u8 cvalid;
1705 __u8 rsvd3;
1706 __le16 dhvlen;
1707 __le32 seqnum;
1708 /* 'hl' bytes of response data */
1709 __u8 rval[];
1710 /* followed by 'hl' bytes of Challenge value */
1711 /* followed by 'dhvlen' bytes of DH value */
1712 };
1713
1714 enum {
1715 NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
1716 };
1717
1718 struct nvmf_auth_dhchap_success1_data {
1719 __u8 auth_type;
1720 __u8 auth_id;
1721 __le16 rsvd1;
1722 __le16 t_id;
1723 __u8 hl;
1724 __u8 rsvd2;
1725 __u8 rvalid;
1726 __u8 rsvd3[7];
1727 /* 'hl' bytes of response value */
1728 __u8 rval[];
1729 };
1730
1731 struct nvmf_auth_dhchap_success2_data {
1732 __u8 auth_type;
1733 __u8 auth_id;
1734 __le16 rsvd1;
1735 __le16 t_id;
1736 __u8 rsvd2[10];
1737 };
1738
1739 struct nvmf_auth_dhchap_failure_data {
1740 __u8 auth_type;
1741 __u8 auth_id;
1742 __le16 rsvd1;
1743 __le16 t_id;
1744 __u8 rescode;
1745 __u8 rescode_exp;
1746 };
1747
1748 enum {
1749 NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01,
1750 };
1751
1752 enum {
1753 NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01,
1754 NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02,
1755 NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03,
1756 NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04,
1757 NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05,
1758 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06,
1759 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07,
1760 };
1761
1762
1763 struct nvme_dbbuf {
1764 __u8 opcode;
1765 __u8 flags;
1766 __u16 command_id;
1767 __u32 rsvd1[5];
1768 __le64 prp1;
1769 __le64 prp2;
1770 __u32 rsvd12[6];
1771 };
1772
1773 struct streams_directive_params {
1774 __le16 msl;
1775 __le16 nssa;
1776 __le16 nsso;
1777 __u8 rsvd[10];
1778 __le32 sws;
1779 __le16 sgs;
1780 __le16 nsa;
1781 __le16 nso;
1782 __u8 rsvd2[6];
1783 };
1784
1785 struct nvme_command {
1786 union {
1787 struct nvme_common_command common;
1788 struct nvme_rw_command rw;
1789 struct nvme_identify identify;
1790 struct nvme_features features;
1791 struct nvme_create_cq create_cq;
1792 struct nvme_create_sq create_sq;
1793 struct nvme_delete_queue delete_queue;
1794 struct nvme_download_firmware dlfw;
1795 struct nvme_format_cmd format;
1796 struct nvme_dsm_cmd dsm;
1797 struct nvme_write_zeroes_cmd write_zeroes;
1798 struct nvme_zone_mgmt_send_cmd zms;
1799 struct nvme_zone_mgmt_recv_cmd zmr;
1800 struct nvme_abort_cmd abort;
1801 struct nvme_get_log_page_command get_log_page;
1802 struct nvmf_common_command fabrics;
1803 struct nvmf_connect_command connect;
1804 struct nvmf_property_set_command prop_set;
1805 struct nvmf_property_get_command prop_get;
1806 struct nvmf_auth_common_command auth_common;
1807 struct nvmf_auth_send_command auth_send;
1808 struct nvmf_auth_receive_command auth_receive;
1809 struct nvme_dbbuf dbbuf;
1810 struct nvme_directive_cmd directive;
1811 };
1812 };
1813
nvme_is_fabrics(const struct nvme_command * cmd)1814 static inline bool nvme_is_fabrics(const struct nvme_command *cmd)
1815 {
1816 return cmd->common.opcode == nvme_fabrics_command;
1817 }
1818
1819 struct nvme_error_slot {
1820 __le64 error_count;
1821 __le16 sqid;
1822 __le16 cmdid;
1823 __le16 status_field;
1824 __le16 param_error_location;
1825 __le64 lba;
1826 __le32 nsid;
1827 __u8 vs;
1828 __u8 resv[3];
1829 __le64 cs;
1830 __u8 resv2[24];
1831 };
1832
nvme_is_write(const struct nvme_command * cmd)1833 static inline bool nvme_is_write(const struct nvme_command *cmd)
1834 {
1835 /*
1836 * What a mess...
1837 *
1838 * Why can't we simply have a Fabrics In and Fabrics out command?
1839 */
1840 if (unlikely(nvme_is_fabrics(cmd)))
1841 return cmd->fabrics.fctype & 1;
1842 return cmd->common.opcode & 1;
1843 }
1844
1845 enum {
1846 /*
1847 * Generic Command Status:
1848 */
1849 NVME_SC_SUCCESS = 0x0,
1850 NVME_SC_INVALID_OPCODE = 0x1,
1851 NVME_SC_INVALID_FIELD = 0x2,
1852 NVME_SC_CMDID_CONFLICT = 0x3,
1853 NVME_SC_DATA_XFER_ERROR = 0x4,
1854 NVME_SC_POWER_LOSS = 0x5,
1855 NVME_SC_INTERNAL = 0x6,
1856 NVME_SC_ABORT_REQ = 0x7,
1857 NVME_SC_ABORT_QUEUE = 0x8,
1858 NVME_SC_FUSED_FAIL = 0x9,
1859 NVME_SC_FUSED_MISSING = 0xa,
1860 NVME_SC_INVALID_NS = 0xb,
1861 NVME_SC_CMD_SEQ_ERROR = 0xc,
1862 NVME_SC_SGL_INVALID_LAST = 0xd,
1863 NVME_SC_SGL_INVALID_COUNT = 0xe,
1864 NVME_SC_SGL_INVALID_DATA = 0xf,
1865 NVME_SC_SGL_INVALID_METADATA = 0x10,
1866 NVME_SC_SGL_INVALID_TYPE = 0x11,
1867 NVME_SC_CMB_INVALID_USE = 0x12,
1868 NVME_SC_PRP_INVALID_OFFSET = 0x13,
1869 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
1870 NVME_SC_OP_DENIED = 0x15,
1871 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1872 NVME_SC_RESERVED = 0x17,
1873 NVME_SC_HOST_ID_INCONSIST = 0x18,
1874 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
1875 NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
1876 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
1877 NVME_SC_SANITIZE_FAILED = 0x1C,
1878 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1879 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1880 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
1881 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1882 NVME_SC_CMD_INTERRUPTED = 0x21,
1883 NVME_SC_TRANSIENT_TR_ERR = 0x22,
1884 NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
1885 NVME_SC_INVALID_IO_CMD_SET = 0x2C,
1886
1887 NVME_SC_LBA_RANGE = 0x80,
1888 NVME_SC_CAP_EXCEEDED = 0x81,
1889 NVME_SC_NS_NOT_READY = 0x82,
1890 NVME_SC_RESERVATION_CONFLICT = 0x83,
1891 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
1892
1893 /*
1894 * Command Specific Status:
1895 */
1896 NVME_SC_CQ_INVALID = 0x100,
1897 NVME_SC_QID_INVALID = 0x101,
1898 NVME_SC_QUEUE_SIZE = 0x102,
1899 NVME_SC_ABORT_LIMIT = 0x103,
1900 NVME_SC_ABORT_MISSING = 0x104,
1901 NVME_SC_ASYNC_LIMIT = 0x105,
1902 NVME_SC_FIRMWARE_SLOT = 0x106,
1903 NVME_SC_FIRMWARE_IMAGE = 0x107,
1904 NVME_SC_INVALID_VECTOR = 0x108,
1905 NVME_SC_INVALID_LOG_PAGE = 0x109,
1906 NVME_SC_INVALID_FORMAT = 0x10a,
1907 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1908 NVME_SC_INVALID_QUEUE = 0x10c,
1909 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1910 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1911 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1912 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1913 NVME_SC_FW_NEEDS_RESET = 0x111,
1914 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1915 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1916 NVME_SC_OVERLAPPING_RANGE = 0x114,
1917 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1918 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1919 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1920 NVME_SC_NS_IS_PRIVATE = 0x119,
1921 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1922 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1923 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1924 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
1925 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1926 NVME_SC_CTRL_ID_INVALID = 0x11f,
1927 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
1928 NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
1929 NVME_SC_RES_ID_INVALID = 0x122,
1930 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1931 NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
1932 NVME_SC_ANA_ATTACH_FAILED = 0x125,
1933
1934 /*
1935 * I/O Command Set Specific - NVM commands:
1936 */
1937 NVME_SC_BAD_ATTRIBUTES = 0x180,
1938 NVME_SC_INVALID_PI = 0x181,
1939 NVME_SC_READ_ONLY = 0x182,
1940 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1941
1942 /*
1943 * I/O Command Set Specific - Fabrics commands:
1944 */
1945 NVME_SC_CONNECT_FORMAT = 0x180,
1946 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1947 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1948 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1949 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1950
1951 NVME_SC_DISCOVERY_RESTART = 0x190,
1952 NVME_SC_AUTH_REQUIRED = 0x191,
1953
1954 /*
1955 * I/O Command Set Specific - Zoned commands:
1956 */
1957 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1958 NVME_SC_ZONE_FULL = 0x1b9,
1959 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1960 NVME_SC_ZONE_OFFLINE = 0x1bb,
1961 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1962 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1963 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1964 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1965
1966 /*
1967 * Media and Data Integrity Errors:
1968 */
1969 NVME_SC_WRITE_FAULT = 0x280,
1970 NVME_SC_READ_ERROR = 0x281,
1971 NVME_SC_GUARD_CHECK = 0x282,
1972 NVME_SC_APPTAG_CHECK = 0x283,
1973 NVME_SC_REFTAG_CHECK = 0x284,
1974 NVME_SC_COMPARE_FAILED = 0x285,
1975 NVME_SC_ACCESS_DENIED = 0x286,
1976 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1977
1978 /*
1979 * Path-related Errors:
1980 */
1981 NVME_SC_INTERNAL_PATH_ERROR = 0x300,
1982 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1983 NVME_SC_ANA_INACCESSIBLE = 0x302,
1984 NVME_SC_ANA_TRANSITION = 0x303,
1985 NVME_SC_CTRL_PATH_ERROR = 0x360,
1986 NVME_SC_HOST_PATH_ERROR = 0x370,
1987 NVME_SC_HOST_ABORTED_CMD = 0x371,
1988
1989 NVME_SC_CRD = 0x1800,
1990 NVME_SC_MORE = 0x2000,
1991 NVME_SC_DNR = 0x4000,
1992 };
1993
1994 struct nvme_completion {
1995 /*
1996 * Used by Admin and Fabrics commands to return data:
1997 */
1998 union nvme_result {
1999 __le16 u16;
2000 __le32 u32;
2001 __le64 u64;
2002 } result;
2003 __le16 sq_head; /* how much of this queue may be reclaimed */
2004 __le16 sq_id; /* submission queue that generated this entry */
2005 __u16 command_id; /* of the command which completed */
2006 __le16 status; /* did the command fail, and if so, why? */
2007 };
2008
2009 #define NVME_VS(major, minor, tertiary) \
2010 (((major) << 16) | ((minor) << 8) | (tertiary))
2011
2012 #define NVME_MAJOR(ver) ((ver) >> 16)
2013 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
2014 #define NVME_TERTIARY(ver) ((ver) & 0xff)
2015
2016 #endif /* _LINUX_NVME_H */
2017